ath79: drop phy-mask property
[openwrt/openwrt.git] / target / linux / ath79 / dts / ar7161_dlink_dir-825-b1.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "ar7100.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7
8 / {
9 compatible = "dlink,dir-825-b1", "qca,ar7161";
10 model = "D-Link DIR825B1";
11
12 aliases {
13 led-boot = &led_power_orange;
14 led-failsafe = &led_power_orange;
15 led-running = &led_power_blue;
16 led-upgrade = &led_power_orange;
17 };
18
19 extosc: ref {
20 compatible = "fixed-clock";
21 #clock-cells = <0>;
22 clock-output-names = "ref";
23 clock-frequency = <40000000>;
24 };
25
26 leds {
27 compatible = "gpio-leds";
28
29 usb {
30 label = "blue:usb";
31 gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
32 trigger-sources = <&usb_ohci_port>, <&usb_ehci_port>;
33 linux,default-trigger = "usbport";
34 };
35
36 led_power_orange: power_orange {
37 label = "orange:power";
38 gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
39 default-state = "on";
40 };
41
42 led_power_blue: power_blue {
43 label = "blue:power";
44 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
45 };
46
47 wps {
48 label = "blue:wps";
49 gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
50 };
51
52 planet_orange {
53 label = "orange:planet";
54 gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
55 };
56
57 planet_blue {
58 label = "blue:planet";
59 gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
60 };
61 };
62
63 ath9k-leds {
64 compatible = "gpio-leds";
65
66 wlan2g {
67 label = "blue:wlan2g";
68 gpios = <&ath9k0 5 GPIO_ACTIVE_LOW>;
69 linux,default-trigger = "phy0tpt";
70 };
71
72 wlan5g {
73 label = "blue:wlan5g";
74 gpios = <&ath9k1 5 GPIO_ACTIVE_LOW>;
75 linux,default-trigger = "phy1tpt";
76 };
77 };
78
79 keys {
80 compatible = "gpio-keys";
81
82 reset {
83 label = "reset";
84 linux,code = <KEY_RESTART>;
85 gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
86 };
87
88 wps {
89 label = "wps";
90 linux,code = <KEY_WPS_BUTTON>;
91 gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
92 };
93 };
94
95 rtl8366s {
96 compatible = "realtek,rtl8366s";
97 gpio-sda = <&gpio 5 GPIO_ACTIVE_HIGH>;
98 gpio-sck = <&gpio 7 GPIO_ACTIVE_HIGH>;
99 realtek,initvals = <0x06 0x0108>;
100
101 mdio-bus {
102 #address-cells = <1>;
103 #size-cells = <0>;
104 status = "okay";
105
106 phy4: ethernet-phy@4 {
107 reg = <4>;
108 phy-mode = "rgmii";
109 };
110 };
111 };
112 };
113
114 &usb1 {
115 #address-cells = <1>;
116 #size-cells = <0>;
117 status = "okay";
118
119 usb_ohci_port: port@1 {
120 reg = <1>;
121 #trigger-source-cells = <0>;
122 };
123 };
124
125 &usb2 {
126 #address-cells = <1>;
127 #size-cells = <0>;
128 status = "okay";
129
130 usb_ehci_port: port@1 {
131 reg = <1>;
132 #trigger-source-cells = <0>;
133 };
134 };
135
136 &usb_phy {
137 status = "okay";
138 };
139
140 &pcie0 {
141 status = "okay";
142
143 ath9k0: wifi@0,11 {
144 compatible = "pci168c,0029";
145 reg = <0x8800 0 0 0 0>;
146 qca,no-eeprom;
147 #gpio-cells = <2>;
148 gpio-controller;
149 };
150
151 ath9k1: wifi@0,12 {
152 compatible = "pci168c,0029";
153 reg = <0x9000 0 0 0 0>;
154 qca,no-eeprom;
155 #gpio-cells = <2>;
156 gpio-controller;
157 };
158 };
159
160 &pll {
161 clocks = <&extosc>;
162 };
163
164 &spi {
165 status = "okay";
166
167 flash@0 {
168 compatible = "jedec,spi-nor";
169 reg = <0>;
170 spi-max-frequency = <25000000>;
171
172 partitions {
173 compatible = "fixed-partitions";
174 #address-cells = <1>;
175 #size-cells = <1>;
176
177 partition@0 {
178 label = "u-boot";
179 reg = <0x000000 0x040000>;
180 read-only;
181 };
182
183 partition@40000 {
184 label = "config";
185 reg = <0x040000 0x010000>;
186 read-only;
187 };
188
189 partition@50000 {
190 compatible = "denx,uimage";
191 label = "firmware";
192 reg = <0x050000 0x610000>;
193 };
194
195 partition@660000 {
196 label = "caldata";
197 reg = <0x660000 0x010000>;
198 read-only;
199 };
200
201 partition@670000 {
202 label = "unknown";
203 reg = <0x670000 0x190000>;
204 read-only;
205 };
206 };
207 };
208 };
209
210 &eth0 {
211 status = "okay";
212
213 pll-data = <0x11110000 0x00001099 0x00991099>;
214
215 fixed-link {
216 speed = <1000>;
217 full-duplex;
218 };
219 };
220
221 &eth1 {
222 status = "okay";
223
224 pll-data = <0x11110000 0x00001099 0x00991099>;
225
226 phy-handle = <&phy4>;
227 };