ath79: move reference clock node to SoC dtsi
[openwrt/openwrt.git] / target / linux / ath79 / dts / ar7161_siemens_ws-ap3610.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "ar7100.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7
8 / {
9 compatible = "siemens,ws-ap3610", "qca,ar7161";
10 model = "Siemens WS-AP3610";
11
12 aliases {
13 led-boot = &led_power_green;
14 led-failsafe = &led_power_red;
15 led-running = &led_power_green;
16 led-upgrade = &led_power_red;
17 label-mac-device = &eth0;
18 };
19
20 leds {
21 compatible = "gpio-leds";
22
23 led_power_green: led_power_green {
24 label = "green:power";
25 gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
26 };
27
28 led_power_red: led_power_red {
29 label = "red:power";
30 gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
31 };
32
33 led_wlan5_blue {
34 label = "blue:wlan5";
35 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
36 linux,default-trigger = "phy0tpt";
37 };
38
39 led_wlan5_green {
40 label = "green:wlan5";
41 gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
42 };
43
44 led_wlan2_blue {
45 label = "blue:wlan2";
46 gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
47 linux,default-trigger = "phy1tpt";
48 };
49
50 led_wlan2_green {
51 label = "green:wlan2";
52 gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
53 };
54 };
55
56 keys {
57 compatible = "gpio-keys";
58
59 reset {
60 label = "reset";
61 linux,code = <KEY_RESTART>;
62 gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
63 };
64 };
65 };
66
67 &pcie0 {
68 status = "okay";
69 };
70
71 &mdio0 {
72 status = "okay";
73
74 phy0: ethernet-phy@0 {
75 /*
76 * When the compatible-is missing, PHY autodetection
77 * is performed, but the PHY-ID reads all 0xff.
78 *
79 * Linux does not create the device in this case,
80 * and the reset is never even de-asserted.
81 */
82 compatible = "ethernet-phy-id0143.bca2",
83 "ethernet-phy-ieee802.3-c22";
84 reg = <0>;
85
86 resets = <&rst 8>;
87 reset-names = "phy";
88 reset-assert-us = <10000>;
89 reset-deassert-us = <10000>;
90 };
91 };
92
93 &eth0 {
94 status = "okay";
95
96 phy-mode = "rgmii-id";
97 phy-handle = <&phy0>;
98 };
99
100 &spi {
101 status = "okay";
102
103 flash@0 {
104 compatible = "jedec,spi-nor";
105 reg = <0>;
106 spi-max-frequency = <50000000>;
107
108 partitions {
109 compatible = "fixed-partitions";
110 #address-cells = <1>;
111 #size-cells = <1>;
112
113 partition@0 {
114 label = "u-boot";
115 reg = <0x0 0x40000>;
116 read-only;
117 };
118
119 partition@40000 {
120 label = "u-boot-bak";
121 reg = <0x40000 0x40000>;
122 read-only;
123 };
124
125 partition@80000 {
126 compatible = "denx,uimage";
127 label = "firmware";
128 reg = <0x80000 0xe00000>;
129 };
130
131 partition@e80000 {
132 label = "cfg1";
133 reg = <0xe80000 0x40000>;
134 read-only;
135 };
136
137 partition@ec0000 {
138 label = "cfg2";
139 reg = <0xec0000 0x40000>;
140 read-only;
141 };
142
143 partition@f00000 {
144 label = "nvram1";
145 reg = <0xf00000 0x40000>;
146 read-only;
147 };
148
149 partition@f40000 {
150 label = "nvram2";
151 reg = <0xf40000 0x40000>;
152 read-only;
153 };
154
155 partition@f80000 {
156 label = "rsvd1";
157 reg = <0xf80000 0x40000>;
158 read-only;
159 };
160
161 partition@fc0000 {
162 label = "rsvd2";
163 reg = <0xfc0000 0x40000>;
164 read-only;
165 };
166 };
167 };
168 };