ath79: enable UART in SoC DTSI files
[openwrt/openwrt.git] / target / linux / ath79 / dts / ar7240_netgear_wnr612-v2.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "ar7240.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/mtd/partitions/uimage.h>
8
9 / {
10 aliases {
11 led-boot = &led_power;
12 led-failsafe = &led_power;
13 led-running = &led_power;
14 led-upgrade = &led_power;
15 label-mac-device = &eth1;
16 };
17
18 ath9k-keys {
19 compatible = "gpio-keys-polled";
20 poll-interval = <20>;
21
22 reset {
23 label = "reset";
24 linux,code = <KEY_RESTART>;
25 gpios = <&ath9k 7 GPIO_ACTIVE_LOW>;
26 debounce-interval = <60>;
27 };
28 };
29
30 leds {
31 compatible = "gpio-leds";
32
33 pinctrl-names = "default";
34 pinctrl-0 = <&jtag_disable_pins &switch_led_disable_pins &clks_disable_pins>;
35
36 led_power: power {
37 label = "green:power";
38 gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
39 };
40
41 lan1 {
42 label = "green:lan1";
43 gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
44 };
45
46 lan2 {
47 label = "green:lan2";
48 gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
49 };
50
51 wan {
52 label = "green:wan";
53 gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
54 };
55 };
56
57 ath9k-leds {
58 compatible = "gpio-leds";
59
60 wlan {
61 label = "green:wlan";
62 gpios = <&ath9k 1 GPIO_ACTIVE_LOW>;
63 linux,default-trigger = "phy0tpt";
64 };
65 };
66 };
67
68 &spi {
69 status = "okay";
70
71 flash@0 {
72 compatible = "jedec,spi-nor";
73 reg = <0>;
74 spi-max-frequency = <25000000>;
75
76 partitions {
77 compatible = "fixed-partitions";
78 #address-cells = <1>;
79 #size-cells = <1>;
80
81 partition@0 {
82 reg = <0x0 0x40000>;
83 label = "u-boot";
84 read-only;
85 };
86
87 partition@40000 {
88 reg = <0x40000 0x10000>;
89 label = "u-boot-env";
90 };
91
92 partition@50000 {
93 compatible = "openwrt,uimage", "denx,uimage";
94 openwrt,ih-magic = <0x32303631>;
95 openwrt,ih-type = <IH_TYPE_FILESYSTEM>;
96 reg = <0x50000 0x3a0000>;
97 label = "firmware";
98 };
99
100 art: partition@3f0000 {
101 reg = <0x3f0000 0x10000>;
102 label = "art";
103 read-only;
104 };
105 };
106 };
107 };
108
109 &eth0 {
110 mtd-mac-address = <&art 0x0>;
111 };
112
113 &eth1 {
114 status = "okay";
115
116 mtd-mac-address = <&art 0x6>;
117 };
118
119 &pcie {
120 status = "okay";
121
122 ath9k: wifi@0,0 {
123 compatible = "pci168c,002b";
124 reg = <0x0000 0 0 0 0>;
125 mtd-mac-address = <&art 0x0>;
126 mtd-mac-address-increment = <1>;
127 qca,no-eeprom;
128 #gpio-cells = <2>;
129 gpio-controller;
130 };
131 };