target/linux/ath79/dts/ar724x.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include "ath79.dtsi"
   4
   5 / {
   6         compatible = "qca,ar7240";
   7
   8         #address-cells = <1>;
   9         #size-cells = <1>;
  10
  11         chosen {
  12                 bootargs = "console=ttyS0,115200";
  13         };
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "mips,mips24Kc";
  22                         clocks = <&pll ATH79_CLK_CPU>;
  23                         reg = <0>;
  24                 };
  25         };
  26
  27         extosc: ref {
  28                 compatible = "fixed-clock";
  29                 #clock-cells = <0>;
  30                 clock-output-names = "ref";
  31                 clock-frequency = <40000000>;
  32         };
  33
  34         ahb: ahb {
  35                 apb {
  36                         ddr_ctrl: memory-controller@18000000 {
  37                                 compatible = "qca,ar9132-ddr-controller",
  38                                                 "qca,ar7240-ddr-controller";
  39                                 reg = <0x18000000 0x100>;
  40
  41                                 #qca,ddr-wb-channel-cells = <1>;
  42                         };
  43
  44                         uart: uart@18020000 {
  45                                 compatible = "ns16550a";
  46                                 reg = <0x18020000 0x20>;
  47                                 interrupts = <3>;
  48
  49                                 clocks = <&pll ATH79_CLK_AHB>;
  50                                 clock-names = "uart";
  51
  52                                 reg-io-width = <4>;
  53                                 reg-shift = <2>;
  54                                 no-loopback-test;
  55                         };
  56
  57                         gpio: gpio@18040000 {
  58                                 compatible = "qca,ar7240-gpio",
  59                                                 "qca,ar7100-gpio";
  60                                 reg = <0x18040000 0x28>;
  61                                 interrupts = <2>;
  62
  63                                 ngpios = <18>;
  64
  65                                 gpio-controller;
  66                                 #gpio-cells = <2>;
  67
  68                                 interrupt-controller;
  69                                 #interrupt-cells = <2>;
  70                         };
  71
  72                         pinmux: pinmux@18040028 {
  73                                 compatible = "pinctrl-single";
  74
  75                                 reg = <0x18040028 0x8>;
  76
  77                                 pinctrl-single,bit-per-mux;
  78                                 pinctrl-single,register-width = <32>;
  79                                 pinctrl-single,function-mask = <0x1>;
  80                                 #pinctrl-cells = <2>;
  81
  82                                 jtag_disable_pins: pinmux_jtag_disable_pins {
  83                                         pinctrl-single,bits = <0x0 0x1 0x1>;
  84                                 };
  85
  86                                 switch_led_disable_pins: pinmux_switch_led_disable_pins {
  87                                         pinctrl-single,bits = <0x0 0x0 0xf8>;
  88                                 };
  89
  90                                 clks_disable_pins: pinmux_clks_disable_pins {
  91                                         pinctrl-single,bits = <0x0 0x0 0x81f00>;
  92                                 };
  93                         };
  94
  95                         pll: pll-controller@18050000 {
  96                                 compatible = "qca,ar7240-pll", "syscon";
  97                                 reg = <0x18050000 0x3c>;
  98
  99                                 clocks = <&extosc>;
 100                                 clock-names = "ref";
 101
 102                                 #clock-cells = <1>;
 103                                 clock-output-names = "cpu", "ddr", "ahb";
 104                         };
 105
 106                         wdt: wdt@18060008 {
 107                                 compatible = "qca,ar7130-wdt";
 108                                 reg = <0x18060008 0x8>;
 109
 110                                 interrupts = <4>;
 111
 112                                 clocks = <&pll ATH79_CLK_AHB>;
 113                                 clock-names = "wdt";
 114                         };
 115
 116                         rst: reset-controller@1806001c {
 117                                 compatible = "qca,ar7240-reset",
 118                                                 "qca,ar7100-reset";
 119                                 reg = <0x1806001c 0x4>;
 120
 121                                 #reset-cells = <1>;
 122                         };
 123
 124                         pcie: pcie-controller@180c0000 {
 125                                 compatible = "qcom,ar7240-pci";
 126                                 #address-cells = <3>;
 127                                 #size-cells = <2>;
 128                                 bus-range = <0x0 0x0>;
 129                                 reg = <0x180c0000 0x1000>, /* CRP */
 130                                       <0x180f0000 0x100>,  /* CTRL */
 131                                       <0x14000000 0x1000>; /* CFG */
 132                                 reg-names = "crp_base", "ctrl_base", "cfg_base";
 133                                 ranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000        /* pci memory */
 134                                           0x1000000 0 0x00000000 0x0000000 0 0x000001>;         /* io space */
 135                                 interrupt-parent = <&cpuintc>;
 136                                 interrupts = <2>;
 137
 138                                 resets = <&rst 6>, <&rst 7>;
 139                                 reset-names = "hc", "phy";
 140
 141                                 device_type = "pci";
 142
 143                                 interrupt-controller;
 144                                 #interrupt-cells = <1>;
 145
 146                                 interrupt-map-mask = <0 0 0 1>;
 147                                 interrupt-map = <0 0 0 0 &pcie 0>;
 148                                 status = "disabled";
 149                         };
 150                 };
 151
 152                 spi: spi@1f000000 {
 153                         compatible = "qca,ar7240-spi",
 154                                         "qca,ar7100-spi";
 155                         reg = <0x1f000000 0x10>;
 156
 157                         clocks = <&pll ATH79_CLK_AHB>;
 158                         clock-names = "ahb";
 159
 160                         status = "disabled";
 161
 162                         #address-cells = <1>;
 163                         #size-cells = <0>;
 164                 };
 165         };
 166 };
 167
 168 &cpuintc {
 169         qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
 170         qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
 171                                 <&ddr_ctrl 0>, <&ddr_ctrl 1>;
 172 };