ath79: enable UART in SoC DTSI files
[openwrt/openwrt.git] / target / linux / ath79 / dts / ar9342_iodata_etg3-r.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "ar9344.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7
8 / {
9 compatible = "iodata,etg3-r", "qca,ar9344";
10 model = "I-O DATA ETG3-R";
11
12 aliases {
13 led-boot = &led_power;
14 led-failsafe = &led_power;
15 led-running = &led_power;
16 led-upgrade = &led_power;
17 };
18
19 leds {
20 compatible = "gpio-leds";
21
22 led_power: power {
23 label = "green:power";
24 gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
25 default-state = "on";
26 };
27
28 notification {
29 label = "green:notification";
30 gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
31 };
32 };
33
34 keys {
35 compatible = "gpio-keys";
36
37 reset {
38 label = "reset";
39 linux,code = <KEY_RESTART>;
40 gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
41 debounce-interval = <60>;
42 };
43 };
44 };
45
46 &ref {
47 clock-frequency = <40000000>;
48 };
49
50 &spi {
51 status = "okay";
52
53 flash@0 {
54 compatible = "jedec,spi-nor";
55 reg = <0>;
56 spi-max-frequency = <25000000>;
57
58 partitions {
59 compatible = "fixed-partitions";
60 #address-cells = <1>;
61 #size-cells = <1>;
62
63 partition@0 {
64 label = "u-boot";
65 reg = <0x000000 0x040000>;
66 read-only;
67 };
68
69 partition@40000 {
70 label = "u-boot-env";
71 reg = <0x040000 0x010000>;
72 };
73
74 partition@50000 {
75 compatible = "denx,uimage";
76 label = "firmware";
77 reg = <0x050000 0x780000>;
78 };
79
80 partition@7d0000 {
81 label = "Config";
82 reg = <0x07d0000 0x10000>;
83 read-only;
84 };
85
86 partition@7e0000 {
87 label = "Rsv";
88 reg = <0x07e0000 0x10000>;
89 read-only;
90 };
91
92 partition@7f0000 {
93 label = "art";
94 reg = <0x7f0000 0x010000>;
95 read-only;
96 };
97 };
98 };
99 };
100
101 &mdio0 {
102 status = "okay";
103
104 phy0: ethernet-phy@0 {
105 reg = <0>;
106 phy-mode = "rgmii";
107
108 qca,ar8327-initvals = <
109 0x04 0x07600000 /* PORT0 PAD MODE CTRL */
110 0x50 0xffb7ffb7 /* LED_CTRL0 */
111 0x54 0xffb7ffb7 /* LED_CTRL1 */
112 0x58 0xffb7ffb7 /* LED_CTRL2 */
113 0x5c 0x03ffff00 /* LED_CTRL3 */
114 0x7c 0x0000007e /* PORT0_STATUS */
115 >;
116 };
117 };
118
119 &eth0 {
120 status = "okay";
121
122 pll-data = <0x0e000000 0x00000101 0x00001616>;
123
124 phy-mode = "rgmii";
125 phy-handle = <&phy0>;
126
127 gmac-config {
128 device = <&gmac>;
129
130 rgmii-gmac0 = <1>;
131 rxd-delay = <3>;
132 rxdv-delay = <3>;
133 };
134 };