ath79: improve support for D-Link DIR-8x9 A1 series
[openwrt/openwrt.git] / target / linux / ath79 / dts / ar9344_devolo_dlan_wifi.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "ar9344.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7
8 / {
9 aliases {
10 led-boot = &led_dlan_red;
11 led-failsafe = &led_dlan_red;
12 led-running = &led_dlan_white;
13 led-upgrade = &led_dlan_red;
14 };
15
16 leds {
17 compatible = "gpio-leds";
18
19 wlan {
20 label = "white:wlan";
21 gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
22 linux,default-trigger = "phy1tpt";
23 };
24
25 led_dlan_white: dlan_white {
26 label = "white:dlan";
27 gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
28 };
29
30 led_dlan_red: dlan_red {
31 label = "red:dlan";
32 gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
33 panic-indicator;
34 };
35 };
36
37 keys {
38 compatible = "gpio-keys";
39
40 reset {
41 label = "Reset button";
42 linux,code = <KEY_RESTART>;
43 gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
44 debounce-interval = <60>;
45 };
46
47 wifi {
48 label = "WIFI button";
49 linux,code = <KEY_RFKILL>;
50 gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
51 debounce-interval = <60>;
52 };
53
54 dlan {
55 label = "DLAN button";
56 linux,code = <BTN_0>;
57 gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
58 debounce-interval = <60>;
59 };
60 };
61 };
62
63 &gpio {
64 wlan_power {
65 gpio-hog;
66 line-name = "WLAN power";
67 gpios = <&gpio 21 GPIO_ACTIVE_HIGH>;
68 output-high;
69 };
70 };
71
72 &spi {
73 status = "okay";
74
75 flash@0 {
76 compatible = "jedec,spi-nor";
77 reg = <0>;
78 spi-max-frequency = <25000000>;
79
80 partitions {
81 compatible = "fixed-partitions";
82 #address-cells = <1>;
83 #size-cells = <1>;
84
85 uboot: partition@0 {
86 label = "u-boot";
87 reg = <0x0 0x40000>;
88 read-only;
89 };
90
91 partition@40000 {
92 label = "u-boot-env";
93 reg = <0x40000 0x10000>;
94 read-only;
95 };
96
97 partition@50000 {
98 label = "Config1";
99 reg = <0x50000 0x10000>;
100 read-only;
101 };
102
103 partition@60000 {
104 label = "Config2";
105 reg = <0x60000 0x10000>;
106 read-only;
107 };
108
109 partition@70000 {
110 compatible = "denx,uimage";
111 label = "firmware";
112 reg = <0x70000 0xf80000>;
113 };
114
115 art: partition@ff0000 {
116 label = "art";
117 reg = <0xff0000 0x10000>;
118 read-only;
119 };
120 };
121 };
122 };
123
124 &ref {
125 clock-frequency = <40000000>;
126 };
127
128 &eth0 {
129 status = "okay";
130
131 pll-data = <0x02000000 0x00000101 0x00001616>;
132
133 nvmem-cells = <&macaddr_art_1002>;
134 nvmem-cell-names = "mac-address";
135 mac-address-increment = <2>;
136
137 phy-mode = "rgmii";
138 phy-handle = <&phy0>;
139 };
140
141 &wmac {
142 status = "okay";
143
144 mtd-cal-data = <&art 0x1000>;
145 };
146
147 &pcie {
148 status = "okay";
149
150 wifi@0,0 {
151 compatible = "qcom,ath10k";
152 reg = <0 0 0 0 0>;
153 };
154 };
155
156 &mdio0 {
157 status = "okay";
158
159 phy0: ethernet-phy@0 {
160 reg = <0>;
161 phy-mode = "rgmii";
162
163 qca,ar8327-initvals = <
164 /* PORT0: RGMII, MAC0/6 exchange, tx_delay 01, No rx_delay */
165 0x04 0x06400000
166 0x08 0x00000000 /* PORT5 PAD MODE CTRL */
167 0x0c 0x00000000 /* PORT6 PAD MODE CTRL */
168 0x7c 0x0000007e /* PORT0_STATUS */
169 >;
170 };
171 };
172
173 &art {
174 compatible = "nvmem-cells";
175 #address-cells = <1>;
176 #size-cells = <1>;
177
178 macaddr_art_1002: macaddr@1002 {
179 reg = <0x1002 0x6>;
180 };
181 };