ath79: enable UART in SoC DTSI files
[openwrt/openwrt.git] / target / linux / ath79 / dts / ar9344_qxwlan_e750x.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "ar9344.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7
8 / {
9 aliases {
10 label-mac-device = &eth0;
11 led-boot = &led_system;
12 led-failsafe = &led_system;
13 led-running = &led_system;
14 led-upgrade = &led_system;
15 };
16
17 keys {
18 compatible = "gpio-keys";
19
20 reset {
21 label = "reset";
22 linux,code = <KEY_RESTART>;
23 gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
24 debounce-interval = <60>;
25 };
26 };
27
28 leds: leds {
29 compatible = "gpio-leds";
30
31 led_system: system {
32 label = "green:system";
33 gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
34 default-state = "on";
35 };
36
37 sig1 {
38 label = "green:sig1";
39 gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
40 };
41
42 sig2 {
43 label = "green:sig2";
44 gpios = <&gpio 20 GPIO_ACTIVE_LOW>;
45 };
46
47 wlan {
48 label = "green:wlan";
49 gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
50 linux,default-trigger = "phy0tpt";
51 };
52 };
53 };
54
55 &pcie {
56 status = "okay";
57 };
58
59 &spi {
60 status = "okay";
61
62 flash@0 {
63 compatible = "jedec,spi-nor";
64 reg = <0>;
65 spi-max-frequency = <25000000>;
66
67 partitions: partitions {
68 compatible = "fixed-partitions";
69 #address-cells = <1>;
70 #size-cells = <1>;
71
72 partition@0 {
73 label = "u-boot";
74 reg = <0x000000 0x040000>;
75 read-only;
76 };
77
78 partition@40000 {
79 label = "u-boot-env";
80 reg = <0x040000 0x010000>;
81 read-only;
82 };
83
84 pridata: partition@50000 {
85 label = "pri-data";
86 reg = <0x050000 0x010000>;
87 read-only;
88 };
89
90 art: partition@60000 {
91 label = "art";
92 reg = <0x060000 0x010000>;
93 read-only;
94 };
95 };
96 };
97 };
98
99 &ref {
100 clock-frequency = <40000000>;
101 };
102
103 &wmac {
104 status = "okay";
105
106 mtd-cal-data = <&art 0x1000>;
107 };