target/linux/ath79/dts/ar9344_wd_mynet-n750.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include "ar9344.dtsi"
   4
   5 #include <dt-bindings/gpio/gpio.h>
   6 #include <dt-bindings/input/input.h>
   7
   8 / {
   9         model = "Western Digital My Net N750";
  10         compatible = "wd,mynet-n750", "qca,ar9344";
  11
  12         chosen {
  13                 bootargs = "console=ttyS0,115200n8";
  14         };
  15
  16         aliases {
  17                 led-boot = &led_power;
  18                 led-failsafe = &led_power;
  19                 led-running = &led_power;
  20                 led-upgrade = &led_power;
  21         };
  22
  23         leds {
  24                 compatible = "gpio-leds";
  25
  26                 wifi {
  27                         label = "blue:wireless";
  28                         gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
  29                 };
  30
  31                 internet {
  32                         label = "blue:internet";
  33                         gpios = <&gpio 12 GPIO_ACTIVE_HIGH>;
  34                 };
  35
  36                 wps {
  37                         label = "blue:wps";
  38                         gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
  39                 };
  40
  41                 led_power: power {
  42                         label = "blue:power";
  43                         gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
  44                 };
  45         };
  46
  47         keys {
  48                 compatible = "gpio-keys";
  49
  50                 reset {
  51                         linux,code = <KEY_RESTART>;
  52                         gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
  53                 };
  54
  55                 wps {
  56                         linux,code = <KEY_WPS_BUTTON>;
  57                         gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
  58                 };
  59         };
  60 };
  61
  62 &ref {
  63         clock-frequency = <40000000>;
  64 };
  65
  66 &uart {
  67         status = "okay";
  68 };
  69
  70 &gpio {
  71         gpio_ext_lna0 {
  72                 gpio-hog;
  73                 gpios = <15 0>;
  74                 output-high;
  75                 line-name = "mynet-n750:ext:lna0";
  76         };
  77
  78         gpio_ext_lna1 {
  79                 gpio-hog;
  80                 gpios = <18 0>;
  81                 output-high;
  82                 line-name = "mynet-n750:ext:lna1";
  83         };
  84 };
  85
  86 &spi {
  87         status = "okay";
  88
  89         num-cs = <1>;
  90
  91         flash@0 {
  92                 compatible = "jedec,spi-nor";
  93                 reg = <0>;
  94                 spi-max-frequency = <25000000>;
  95
  96                 partitions {
  97                         compatible = "fixed-partitions";
  98                         #address-cells = <1>;
  99                         #size-cells = <1>;
 100
 101                         partition@0 {
 102                                 label = "bootloader";
 103                                 reg = <0x000000 0x40000>;
 104                                 read-only;
 105                         };
 106
 107                         partition@40000 {
 108                                 label = "bdcfg";
 109                                 reg = <0x040000 0x10000>;
 110                                 read-only;
 111                         };
 112
 113                         partition@50000 {
 114                                 label = "devdata";
 115                                 reg = <0x050000 0x10000>;
 116                                 read-only;
 117                         };
 118
 119                         partition@60000 {
 120                                 label = "devconf";
 121                                 reg = <0x060000 0x10000>;
 122                                 read-only;
 123                         };
 124
 125                         partition@70000 {
 126                                 compatible = "seama";
 127                                 label = "firmware";
 128                                 reg = <0x070000 0xf80000>;
 129                         };
 130
 131                         art: partition@ff0000 {
 132                                 label = "art";
 133                                 reg = <0xff0000 0x010000>;
 134                                 read-only;
 135                         };
 136                 };
 137         };
 138 };
 139
 140 &usb {
 141         #address-cells = <1>;
 142         #size-cells = <0>;
 143         status = "okay";
 144
 145         port@1 {
 146                 #address-cells = <1>;
 147                 #size-cells = <0>;
 148                 reg = <1>;
 149                 #trigger-source-cells = <0>;
 150
 151                 hub_port1: port@1 {
 152                         reg = <1>;
 153                         #trigger-source-cells = <0>;
 154                 };
 155
 156                 hub_port2: port@2 {
 157                         reg = <2>;
 158                         #trigger-source-cells = <0>;
 159                 };
 160         };
 161 };
 162
 163 &usb_phy {
 164         status = "okay";
 165 };
 166
 167 &pcie {
 168         status = "okay";
 169
 170         wifi@0,0 {
 171                 compatible = "pci168c,0033";
 172                 reg = <0x0000 0 0 0 0>;
 173                 qca,no-eeprom;
 174         };
 175 };
 176
 177 &wmac {
 178         status = "okay";
 179
 180         qca,no-eeprom;
 181 };
 182
 183 &mdio0 {
 184         status = "okay";
 185
 186         phy-mask = <0>;
 187
 188         switch0@1f {
 189                 compatible = "qca,ar8327";
 190                 reg = <0x1f>;
 191
 192                 qca,ar8327-initvals = <
 193                         0x04 0x07600000 /* PORT0 PAD MODE CTRL */
 194                         0x10 0x80000080 /* POWER_ON_STRAP */
 195                         0x50 0xc737c737 /* LED_CTRL0 */
 196                         0x54 0x00000000 /* LED_CTRL1 */
 197                         0x58 0x00000000 /* LED_CTRL2 */
 198                         0x5c 0x0030c300 /* LED_CTRL3 */
 199                         0x7c 0x0000007e /* PORT0_STATUS */
 200                         >;
 201         };
 202 };
 203
 204 &eth0 {
 205         status = "okay";
 206
 207         /* default for ar934x, except for 1000M */
 208         pll-data = <0x06000000 0x00000101 0x00001616>;
 209
 210         phy-mode = "rgmii";
 211         fixed-link {
 212                 speed = <1000>;
 213                 full-duplex;
 214         };
 215 };