ath79: enable UART in SoC DTSI files
[openwrt/openwrt.git] / target / linux / ath79 / dts / qca9531_comfast_cf-e560ac.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "qca953x.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7
8 / {
9 compatible = "comfast,cf-e560ac", "qca,qca9531";
10 model = "COMFAST CF-E560AC";
11
12 aliases {
13 serial0 = &uart;
14 label-mac-device = &eth1;
15 led-boot = &led_system;
16 led-failsafe = &led_system;
17 led-upgrade = &led_system;
18 };
19
20 keys {
21 compatible = "gpio-keys";
22
23 reset {
24 label = "reset";
25 linux,code = <KEY_RESTART>;
26 gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
27 debounce-interval = <60>;
28 };
29 };
30
31 leds {
32 compatible = "gpio-leds";
33
34 pinctrl-names = "default";
35 pinctrl-0 = <&jtag_disable_pins>;
36
37 lan1 {
38 label = "blue:lan1";
39 gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
40 };
41
42 lan2 {
43 label = "blue:lan2";
44 gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
45 };
46
47 lan3 {
48 label = "blue:lan3";
49 gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
50 };
51
52 lan4 {
53 label = "blue:lan4";
54 gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
55 };
56
57 led_system: system {
58 label = "blue:system";
59 gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
60 };
61
62 wan {
63 label = "blue:wan";
64 gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
65 };
66
67 wlan {
68 label = "blue:wlan";
69 gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
70 linux,default-trigger = "phy0tpt";
71 };
72 };
73
74 watchdog {
75 compatible = "linux,wdt-gpio";
76 gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
77 hw_algo = "toggle";
78 hw_margin_ms = <1200>;
79 always-running;
80 };
81 };
82
83 &spi {
84 status = "okay";
85
86 flash@0 {
87 compatible = "jedec,spi-nor";
88 reg = <0>;
89 spi-max-frequency = <25000000>;
90
91 partitions {
92 compatible = "fixed-partitions";
93 #address-cells = <1>;
94 #size-cells = <1>;
95
96 partition@0 {
97 label = "u-boot";
98 reg = <0x000000 0x010000>;
99 read-only;
100 };
101
102 art: partition@10000 {
103 label = "art";
104 reg = <0x010000 0x010000>;
105 read-only;
106 };
107
108 partition@20000 {
109 compatible = "denx,uimage";
110 label = "firmware";
111 reg = <0x020000 0xfc0000>;
112 };
113
114 partition@fe0000 {
115 label = "configs";
116 reg = <0xfe0000 0x010000>;
117 read-only;
118 };
119
120 partition@ff0000 {
121 label = "nvram";
122 reg = <0xff0000 0x010000>;
123 read-only;
124 };
125 };
126 };
127 };
128
129 &pcie0 {
130 status = "okay";
131 };
132
133 &usb_phy {
134 status = "okay";
135 };
136
137 &usb0 {
138 #address-cells = <1>;
139 #size-cells = <0>;
140 status = "okay";
141
142 port@1 {
143 reg = <1>;
144 #trigger-source-cells = <0>;
145 };
146 };
147
148 &eth0 {
149 status = "okay";
150
151 phy-handle = <&swphy4>;
152
153 mtd-mac-address = <&art 0x0>;
154 mtd-mac-address-increment = <1>;
155 };
156
157 &eth1 {
158 mtd-mac-address = <&art 0x0>;
159 };
160
161 &wmac {
162 status = "okay";
163
164 mtd-cal-data = <&art 0x1000>;
165 mtd-mac-address = <&art 0x0>;
166 mtd-mac-address-increment = <10>;
167 };