ath79: enable UART in SoC DTSI files
[openwrt/openwrt.git] / target / linux / ath79 / dts / qca9558_tplink_rex5x.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "qca955x.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7
8 / {
9 aliases {
10 led-boot = &led_power;
11 led-failsafe = &led_power;
12 led-running = &led_power;
13 led-upgrade = &led_power;
14 mdio-gpio0 = &mdio2;
15 label-mac-device = &eth0;
16 };
17
18 leds {
19 compatible = "gpio-leds";
20
21 led_power: power {
22 label = "blue:power";
23 gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
24 };
25
26 wlan2g {
27 label = "blue:wlan2g";
28 gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
29 linux,default-trigger = "phy1tpt";
30 };
31
32 wlan5g {
33 label = "blue:wlan5g";
34 gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
35 linux,default-trigger = "phy0tpt";
36 };
37
38 lan_link {
39 label = "green:lan_link";
40 gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
41 };
42
43 lan_data {
44 label = "green:lan_data";
45 gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
46 };
47
48 wps_blue {
49 label = "blue:wps";
50 gpios = <&gpio 21 GPIO_ACTIVE_HIGH>;
51 };
52
53 wps_red {
54 label = "red:wps";
55 gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
56 };
57 };
58
59 keys {
60 compatible = "gpio-keys";
61
62 reset {
63 label = "Reset button";
64 linux,code = <KEY_RESTART>;
65 gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
66 debounce-interval = <60>;
67 };
68
69 leds {
70 label = "LED control button";
71 linux,code = <BTN_0>;
72 gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
73 debounce-interval = <60>;
74 };
75
76 wps {
77 label = "WPS button";
78 linux,code = <KEY_WPS_BUTTON>;
79 gpios = <&gpio 20 GPIO_ACTIVE_LOW>;
80 debounce-interval = <60>;
81 };
82 };
83
84 mdio2: mdio {
85 compatible = "virtual,mdio-gpio";
86
87 gpios = <&gpio 3 GPIO_ACTIVE_HIGH>, /* MDC */
88 <&gpio 1 GPIO_ACTIVE_HIGH>; /* MDIO */
89 #address-cells = <1>;
90 #size-cells = <0>;
91
92 phy4: ethernet-phy@4 {
93 reg = <4>;
94 reset-gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
95 };
96 };
97 };
98
99 &pcie0 {
100 status = "okay";
101 };
102
103 &spi {
104 status = "okay";
105
106 flash@0 {
107 compatible = "jedec,spi-nor";
108 reg = <0>;
109 spi-max-frequency = <25000000>;
110
111 partitions {
112 compatible = "fixed-partitions";
113 #address-cells = <1>;
114 #size-cells = <1>;
115
116 partition@0 {
117 label = "u-boot";
118 reg = <0x000000 0x020000>;
119 read-only;
120 };
121
122 partition@20000 {
123 compatible = "tplink,firmware";
124 label = "firmware";
125 reg = <0x020000 0x5e0000>;
126 };
127
128 partition@600000 {
129 label = "partition-table";
130 reg = <0x600000 0x010000>;
131 read-only;
132 };
133
134 info: partition@610000 {
135 label = "info";
136 reg = <0x610000 0x020000>;
137 read-only;
138 };
139
140 partition@630000 {
141 label = "config";
142 reg = <0x630000 0x1c0000>;
143 read-only;
144 };
145
146 art: partition@7f0000 {
147 label = "art";
148 reg = <0x7f0000 0x010000>;
149 read-only;
150 };
151 };
152 };
153 };
154
155 &eth0 {
156 status = "okay";
157
158 phy-handle = <&phy4>;
159 pll-data = <0xa6000000 0x00000101 0x00001616>;
160
161 mtd-mac-address = <&info 0x8>;
162 };
163
164 &wmac {
165 status = "okay";
166
167 mtd-cal-data = <&art 0x1000>;
168 mtd-mac-address = <&info 0x8>;
169 mtd-mac-address-increment = <(-1)>;
170 };