ath79: enable UART in SoC DTSI files
[openwrt/openwrt.git] / target / linux / ath79 / dts / qca9558_trendnet_tew-823dru.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "qca955x.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7
8 / {
9 compatible = "trendnet,tew-823dru", "qca,qca9558";
10 model = "TRENDNET TEW-823DRU";
11
12 aliases {
13 led-boot = &led_power_green;
14 led-failsafe = &led_power_green;
15 led-running = &led_power_green;
16 led-upgrade = &led_power_green;
17 };
18
19 leds {
20 compatible = "gpio-leds";
21
22 power_orange {
23 label = "orange:power";
24 gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
25 };
26
27 led_power_green: power_green {
28 label = "green:power";
29 gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
30 };
31
32 planet_green {
33 label = "green:planet";
34 gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
35 };
36
37 planet_orange {
38 label = "orange:planet";
39 gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
40 };
41 };
42
43 keys {
44 compatible = "gpio-keys";
45
46 reset {
47 label = "Reset button";
48 linux,code = <KEY_RESTART>;
49 gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
50 debounce-interval = <60>;
51 };
52
53 wps {
54 label = "WPS button";
55 linux,code = <KEY_WPS_BUTTON>;
56 gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
57 debounce-interval = <60>;
58 };
59 };
60 };
61
62 &pcie0 {
63 status = "okay";
64 };
65
66 &pcie1 {
67 status = "okay";
68 };
69
70 &usb_phy0 {
71 status = "okay";
72 };
73
74 &usb0 {
75 #address-cells = <1>;
76 #size-cells = <0>;
77 status = "okay";
78
79 hub_port0: port@1 {
80 reg = <1>;
81 #trigger-source-cells = <0>;
82 };
83 };
84
85 &usb_phy1 {
86 status = "okay";
87 };
88
89 &usb1 {
90 #address-cells = <1>;
91 #size-cells = <0>;
92 status = "okay";
93
94 hub_port1: port@1 {
95 reg = <1>;
96 #trigger-source-cells = <0>;
97 };
98 };
99
100 &spi {
101 status = "okay";
102
103 flash@0 {
104 compatible = "jedec,spi-nor";
105 reg = <0>;
106 spi-max-frequency = <25000000>;
107
108 partitions {
109 compatible = "fixed-partitions";
110 #address-cells = <1>;
111 #size-cells = <1>;
112
113 partition@0 {
114 label = "u-boot";
115 reg = <0x000000 0x030000>;
116 read-only;
117 };
118
119 partition@30000 {
120 label = "nvram";
121 reg = <0x030000 0x010000>;
122 read-only;
123 };
124
125 partition@40000 {
126 compatible = "denx,uimage";
127 label = "firmware";
128 reg = <0x040000 0xef0000>;
129 };
130
131 partition@f30000 {
132 label = "lang";
133 reg = <0xf30000 0x030000>;
134 read-only;
135 };
136
137 partition@f60000 {
138 label = "my-dlink";
139 reg = <0xf60000 0x080000>;
140 read-only;
141 };
142
143 partition@fe0000 {
144 label = "mac";
145 reg = <0xfe0000 0x010000>;
146 read-only;
147 };
148
149 art: partition@ff0000 {
150 label = "art";
151 reg = <0xff0000 0x010000>;
152 read-only;
153 };
154 };
155 };
156 };
157
158 &mdio0 {
159 status = "okay";
160
161 phy0: ethernet-phy@0 {
162 reg = <0>;
163 qca,ar8327-initvals = <
164 0x04 0x00080080 /* PORT0 PAD MODE CTRL */
165 0x0c 0x07600000 /* PORT6 PAD MODE CTRL */
166 0x10 0x81000080 /* POWER_ON_STRAP */
167 0x7c 0x0000007e /* PORT0_STATUS */
168 0x94 0x0000007e /* PORT6 STATUS */
169 >;
170 };
171 };
172
173 &eth0 {
174 status = "okay";
175
176 phy-handle = <&phy0>;
177 pll-data = <0x56000000 0x00000101 0x00001616>;
178
179 gmac-config {
180 device = <&gmac>;
181 rgmii-enabled = <1>;
182 };
183 };
184
185 &eth1 {
186 status = "okay";
187
188 pll-data = <0x03000101 0x00000101 0x00001616>;
189
190 fixed-link {
191 speed = <1000>;
192 full-duplex;
193 };
194 };
195
196 &wmac {
197 status = "okay";
198
199 mtd-cal-data = <&art 0x1000>;
200 };