ath79: enable UART in SoC DTSI files
[openwrt/openwrt.git] / target / linux / ath79 / dts / qca9563_yuncore_xd4200.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "qca956x.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7
8 / {
9 aliases {
10 label-mac-device = &eth0;
11 };
12
13 keys {
14 compatible = "gpio-keys";
15
16 reset {
17 linux,code = <KEY_RESTART>;
18 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
19 debounce-interval = <60>;
20 };
21 };
22 };
23
24 &eth0 {
25 status = "okay";
26
27 pll-data = <0x03000101 0x00000101 0x00001919>;
28
29 mtd-mac-address = <&art 0x0>;
30 phy-mode = "sgmii";
31 phy-handle = <&phy0>;
32 };
33
34 &mdio0 {
35 status = "okay";
36
37 phy-mask = <0>;
38
39 phy0: ethernet-phy@0 {
40 reg = <0>;
41 phy-mode = "sgmii";
42
43 qca,ar8327-initvals = <
44 0x04 0x00080080 /* PORT0 PAD MODE CTRL */
45 0x10 0x81000080 /* POWER_ON_STRAP */
46 0x50 0xcf37cf37 /* LED_CTRL0 */
47 0x54 0xcf37cf37 /* LED_CTRL1 */
48 0x58 0xcf37cf37 /* LED_CTRL2 */
49 0x5c 0x0000c300 /* LED_CTRL3 */
50 0x7c 0x0000007e /* PORT0_STATUS */
51 >;
52 };
53 };
54
55 &pcie {
56 status = "okay";
57
58 wifi@0,0 {
59 compatible = "pci168c,0056";
60 reg = <0x0000 0 0 0 0>;
61 };
62 };
63
64 &spi {
65 status = "okay";
66
67 flash@0 {
68 compatible = "jedec,spi-nor";
69 reg = <0>;
70 spi-max-frequency = <25000000>;
71
72 partitions {
73 compatible = "fixed-partitions";
74 #address-cells = <1>;
75 #size-cells = <1>;
76
77 partition@0 {
78 label = "u-boot";
79 reg = <0x000000 0x040000>;
80 read-only;
81 };
82
83 partition@40000 {
84 label = "u-boot-env";
85 reg = <0x040000 0x010000>;
86 };
87
88 partition@50000 {
89 compatible = "denx,uimage";
90 label = "firmware";
91 reg = <0x050000 0xfa0000>;
92 };
93
94 art: partition@ff0000 {
95 label = "art";
96 reg = <0xff0000 0x010000>;
97 read-only;
98 };
99 };
100 };
101 };
102
103 &wmac {
104 status = "okay";
105
106 mtd-cal-data = <&art 0x1000>;
107 };