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ath79: add new OF only target for QCA MIPS silicon
[openwrt/openwrt.git] / target / linux / ath79 / files / drivers / net / ethernet / atheros / ag71xx / ag71xx_ar7240.c
1 /*
2 * Driver for the built-in ethernet switch of the Atheros AR7240 SoC
3 * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (c) 2010 Felix Fietkau <nbd@nbd.name>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 */
11
12 #include <linux/etherdevice.h>
13 #include <linux/list.h>
14 #include <linux/netdevice.h>
15 #include <linux/phy.h>
16 #include <linux/mii.h>
17 #include <linux/bitops.h>
18 #include <linux/switch.h>
19 #include "ag71xx.h"
20
21 #define BITM(_count) (BIT(_count) - 1)
22 #define BITS(_shift, _count) (BITM(_count) << _shift)
23
24 #define AR7240_REG_MASK_CTRL 0x00
25 #define AR7240_MASK_CTRL_REVISION_M BITM(8)
26 #define AR7240_MASK_CTRL_VERSION_M BITM(8)
27 #define AR7240_MASK_CTRL_VERSION_S 8
28 #define AR7240_MASK_CTRL_VERSION_AR7240 0x01
29 #define AR7240_MASK_CTRL_VERSION_AR934X 0x02
30 #define AR7240_MASK_CTRL_SOFT_RESET BIT(31)
31
32 #define AR7240_REG_MAC_ADDR0 0x20
33 #define AR7240_REG_MAC_ADDR1 0x24
34
35 #define AR7240_REG_FLOOD_MASK 0x2c
36 #define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26)
37
38 #define AR7240_REG_GLOBAL_CTRL 0x30
39 #define AR7240_GLOBAL_CTRL_MTU_M BITM(11)
40 #define AR9340_GLOBAL_CTRL_MTU_M BITM(14)
41
42 #define AR7240_REG_VTU 0x0040
43 #define AR7240_VTU_OP BITM(3)
44 #define AR7240_VTU_OP_NOOP 0x0
45 #define AR7240_VTU_OP_FLUSH 0x1
46 #define AR7240_VTU_OP_LOAD 0x2
47 #define AR7240_VTU_OP_PURGE 0x3
48 #define AR7240_VTU_OP_REMOVE_PORT 0x4
49 #define AR7240_VTU_ACTIVE BIT(3)
50 #define AR7240_VTU_FULL BIT(4)
51 #define AR7240_VTU_PORT BITS(8, 4)
52 #define AR7240_VTU_PORT_S 8
53 #define AR7240_VTU_VID BITS(16, 12)
54 #define AR7240_VTU_VID_S 16
55 #define AR7240_VTU_PRIO BITS(28, 3)
56 #define AR7240_VTU_PRIO_S 28
57 #define AR7240_VTU_PRIO_EN BIT(31)
58
59 #define AR7240_REG_VTU_DATA 0x0044
60 #define AR7240_VTUDATA_MEMBER BITS(0, 10)
61 #define AR7240_VTUDATA_VALID BIT(11)
62
63 #define AR7240_REG_ATU 0x50
64 #define AR7240_ATU_FLUSH_ALL 0x1
65
66 #define AR7240_REG_AT_CTRL 0x5c
67 #define AR7240_AT_CTRL_AGE_TIME BITS(0, 15)
68 #define AR7240_AT_CTRL_AGE_EN BIT(17)
69 #define AR7240_AT_CTRL_LEARN_CHANGE BIT(18)
70 #define AR7240_AT_CTRL_RESERVED BIT(19)
71 #define AR7240_AT_CTRL_ARP_EN BIT(20)
72
73 #define AR7240_REG_TAG_PRIORITY 0x70
74
75 #define AR7240_REG_SERVICE_TAG 0x74
76 #define AR7240_SERVICE_TAG_M BITM(16)
77
78 #define AR7240_REG_CPU_PORT 0x78
79 #define AR7240_MIRROR_PORT_S 4
80 #define AR7240_MIRROR_PORT_M BITM(4)
81 #define AR7240_CPU_PORT_EN BIT(8)
82
83 #define AR7240_REG_MIB_FUNCTION0 0x80
84 #define AR7240_MIB_TIMER_M BITM(16)
85 #define AR7240_MIB_AT_HALF_EN BIT(16)
86 #define AR7240_MIB_BUSY BIT(17)
87 #define AR7240_MIB_FUNC_S 24
88 #define AR7240_MIB_FUNC_M BITM(3)
89 #define AR7240_MIB_FUNC_NO_OP 0x0
90 #define AR7240_MIB_FUNC_FLUSH 0x1
91 #define AR7240_MIB_FUNC_CAPTURE 0x3
92
93 #define AR7240_REG_MDIO_CTRL 0x98
94 #define AR7240_MDIO_CTRL_DATA_M BITM(16)
95 #define AR7240_MDIO_CTRL_REG_ADDR_S 16
96 #define AR7240_MDIO_CTRL_PHY_ADDR_S 21
97 #define AR7240_MDIO_CTRL_CMD_WRITE 0
98 #define AR7240_MDIO_CTRL_CMD_READ BIT(27)
99 #define AR7240_MDIO_CTRL_MASTER_EN BIT(30)
100 #define AR7240_MDIO_CTRL_BUSY BIT(31)
101
102 #define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
103
104 #define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00)
105 #define AR7240_PORT_STATUS_SPEED_S 0
106 #define AR7240_PORT_STATUS_SPEED_M BITM(2)
107 #define AR7240_PORT_STATUS_SPEED_10 0
108 #define AR7240_PORT_STATUS_SPEED_100 1
109 #define AR7240_PORT_STATUS_SPEED_1000 2
110 #define AR7240_PORT_STATUS_TXMAC BIT(2)
111 #define AR7240_PORT_STATUS_RXMAC BIT(3)
112 #define AR7240_PORT_STATUS_TXFLOW BIT(4)
113 #define AR7240_PORT_STATUS_RXFLOW BIT(5)
114 #define AR7240_PORT_STATUS_DUPLEX BIT(6)
115 #define AR7240_PORT_STATUS_LINK_UP BIT(8)
116 #define AR7240_PORT_STATUS_LINK_AUTO BIT(9)
117 #define AR7240_PORT_STATUS_LINK_PAUSE BIT(10)
118
119 #define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04)
120 #define AR7240_PORT_CTRL_STATE_M BITM(3)
121 #define AR7240_PORT_CTRL_STATE_DISABLED 0
122 #define AR7240_PORT_CTRL_STATE_BLOCK 1
123 #define AR7240_PORT_CTRL_STATE_LISTEN 2
124 #define AR7240_PORT_CTRL_STATE_LEARN 3
125 #define AR7240_PORT_CTRL_STATE_FORWARD 4
126 #define AR7240_PORT_CTRL_LEARN_LOCK BIT(7)
127 #define AR7240_PORT_CTRL_VLAN_MODE_S 8
128 #define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0
129 #define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1
130 #define AR7240_PORT_CTRL_VLAN_MODE_ADD 2
131 #define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3
132 #define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10)
133 #define AR7240_PORT_CTRL_HEADER BIT(11)
134 #define AR7240_PORT_CTRL_MAC_LOOP BIT(12)
135 #define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13)
136 #define AR7240_PORT_CTRL_LEARN BIT(14)
137 #define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15)
138 #define AR7240_PORT_CTRL_MIRROR_TX BIT(16)
139 #define AR7240_PORT_CTRL_MIRROR_RX BIT(17)
140
141 #define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08)
142
143 #define AR7240_PORT_VLAN_DEFAULT_ID_S 0
144 #define AR7240_PORT_VLAN_DEST_PORTS_S 16
145 #define AR7240_PORT_VLAN_MODE_S 30
146 #define AR7240_PORT_VLAN_MODE_PORT_ONLY 0
147 #define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1
148 #define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2
149 #define AR7240_PORT_VLAN_MODE_SECURE 3
150
151
152 #define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100)
153
154 #define AR7240_STATS_RXBROAD 0x00
155 #define AR7240_STATS_RXPAUSE 0x04
156 #define AR7240_STATS_RXMULTI 0x08
157 #define AR7240_STATS_RXFCSERR 0x0c
158 #define AR7240_STATS_RXALIGNERR 0x10
159 #define AR7240_STATS_RXRUNT 0x14
160 #define AR7240_STATS_RXFRAGMENT 0x18
161 #define AR7240_STATS_RX64BYTE 0x1c
162 #define AR7240_STATS_RX128BYTE 0x20
163 #define AR7240_STATS_RX256BYTE 0x24
164 #define AR7240_STATS_RX512BYTE 0x28
165 #define AR7240_STATS_RX1024BYTE 0x2c
166 #define AR7240_STATS_RX1518BYTE 0x30
167 #define AR7240_STATS_RXMAXBYTE 0x34
168 #define AR7240_STATS_RXTOOLONG 0x38
169 #define AR7240_STATS_RXGOODBYTE 0x3c
170 #define AR7240_STATS_RXBADBYTE 0x44
171 #define AR7240_STATS_RXOVERFLOW 0x4c
172 #define AR7240_STATS_FILTERED 0x50
173 #define AR7240_STATS_TXBROAD 0x54
174 #define AR7240_STATS_TXPAUSE 0x58
175 #define AR7240_STATS_TXMULTI 0x5c
176 #define AR7240_STATS_TXUNDERRUN 0x60
177 #define AR7240_STATS_TX64BYTE 0x64
178 #define AR7240_STATS_TX128BYTE 0x68
179 #define AR7240_STATS_TX256BYTE 0x6c
180 #define AR7240_STATS_TX512BYTE 0x70
181 #define AR7240_STATS_TX1024BYTE 0x74
182 #define AR7240_STATS_TX1518BYTE 0x78
183 #define AR7240_STATS_TXMAXBYTE 0x7c
184 #define AR7240_STATS_TXOVERSIZE 0x80
185 #define AR7240_STATS_TXBYTE 0x84
186 #define AR7240_STATS_TXCOLLISION 0x8c
187 #define AR7240_STATS_TXABORTCOL 0x90
188 #define AR7240_STATS_TXMULTICOL 0x94
189 #define AR7240_STATS_TXSINGLECOL 0x98
190 #define AR7240_STATS_TXEXCDEFER 0x9c
191 #define AR7240_STATS_TXDEFER 0xa0
192 #define AR7240_STATS_TXLATECOL 0xa4
193
194 #define AR7240_PORT_CPU 0
195 #define AR7240_NUM_PORTS 6
196 #define AR7240_NUM_PHYS 5
197
198 #define AR7240_PHY_ID1 0x004d
199 #define AR7240_PHY_ID2 0xd041
200
201 #define AR934X_PHY_ID1 0x004d
202 #define AR934X_PHY_ID2 0xd042
203
204 #define AR7240_MAX_VLANS 16
205
206 #define AR934X_REG_OPER_MODE0 0x04
207 #define AR934X_OPER_MODE0_MAC_GMII_EN BIT(6)
208 #define AR934X_OPER_MODE0_PHY_MII_EN BIT(10)
209
210 #define AR934X_REG_OPER_MODE1 0x08
211 #define AR934X_REG_OPER_MODE1_PHY4_MII_EN BIT(28)
212
213 #define AR934X_REG_FLOOD_MASK 0x2c
214 #define AR934X_FLOOD_MASK_MC_DP(_p) BIT(16 + (_p))
215 #define AR934X_FLOOD_MASK_BC_DP(_p) BIT(25 + (_p))
216
217 #define AR934X_REG_QM_CTRL 0x3c
218 #define AR934X_QM_CTRL_ARP_EN BIT(15)
219
220 #define AR934X_REG_AT_CTRL 0x5c
221 #define AR934X_AT_CTRL_AGE_TIME BITS(0, 15)
222 #define AR934X_AT_CTRL_AGE_EN BIT(17)
223 #define AR934X_AT_CTRL_LEARN_CHANGE BIT(18)
224
225 #define AR934X_MIB_ENABLE BIT(30)
226
227 #define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
228
229 #define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08)
230 #define AR934X_PORT_VLAN1_DEFAULT_SVID_S 0
231 #define AR934X_PORT_VLAN1_FORCE_DEFAULT_VID_EN BIT(12)
232 #define AR934X_PORT_VLAN1_PORT_TLS_MODE BIT(13)
233 #define AR934X_PORT_VLAN1_PORT_VLAN_PROP_EN BIT(14)
234 #define AR934X_PORT_VLAN1_PORT_CLONE_EN BIT(15)
235 #define AR934X_PORT_VLAN1_DEFAULT_CVID_S 16
236 #define AR934X_PORT_VLAN1_FORCE_PORT_VLAN_EN BIT(28)
237 #define AR934X_PORT_VLAN1_ING_PORT_PRI_S 29
238
239 #define AR934X_REG_PORT_VLAN2(_port) (AR934X_REG_PORT_BASE((_port)) + 0x0c)
240 #define AR934X_PORT_VLAN2_PORT_VID_MEM_S 16
241 #define AR934X_PORT_VLAN2_8021Q_MODE_S 30
242 #define AR934X_PORT_VLAN2_8021Q_MODE_PORT_ONLY 0
243 #define AR934X_PORT_VLAN2_8021Q_MODE_PORT_FALLBACK 1
244 #define AR934X_PORT_VLAN2_8021Q_MODE_VLAN_ONLY 2
245 #define AR934X_PORT_VLAN2_8021Q_MODE_SECURE 3
246
247 #define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
248
249 struct ar7240sw_port_stat {
250 unsigned long rx_broadcast;
251 unsigned long rx_pause;
252 unsigned long rx_multicast;
253 unsigned long rx_fcs_error;
254 unsigned long rx_align_error;
255 unsigned long rx_runt;
256 unsigned long rx_fragments;
257 unsigned long rx_64byte;
258 unsigned long rx_128byte;
259 unsigned long rx_256byte;
260 unsigned long rx_512byte;
261 unsigned long rx_1024byte;
262 unsigned long rx_1518byte;
263 unsigned long rx_maxbyte;
264 unsigned long rx_toolong;
265 unsigned long rx_good_byte;
266 unsigned long rx_bad_byte;
267 unsigned long rx_overflow;
268 unsigned long filtered;
269
270 unsigned long tx_broadcast;
271 unsigned long tx_pause;
272 unsigned long tx_multicast;
273 unsigned long tx_underrun;
274 unsigned long tx_64byte;
275 unsigned long tx_128byte;
276 unsigned long tx_256byte;
277 unsigned long tx_512byte;
278 unsigned long tx_1024byte;
279 unsigned long tx_1518byte;
280 unsigned long tx_maxbyte;
281 unsigned long tx_oversize;
282 unsigned long tx_byte;
283 unsigned long tx_collision;
284 unsigned long tx_abortcol;
285 unsigned long tx_multicol;
286 unsigned long tx_singlecol;
287 unsigned long tx_excdefer;
288 unsigned long tx_defer;
289 unsigned long tx_xlatecol;
290 };
291
292 struct ar7240sw {
293 struct mii_bus *mii_bus;
294 struct ag71xx_switch_platform_data *swdata;
295 struct switch_dev swdev;
296 int num_ports;
297 u8 ver;
298 bool vlan;
299 u16 vlan_id[AR7240_MAX_VLANS];
300 u8 vlan_table[AR7240_MAX_VLANS];
301 u8 vlan_tagged;
302 u16 pvid[AR7240_NUM_PORTS];
303 char buf[80];
304
305 rwlock_t stats_lock;
306 struct ar7240sw_port_stat port_stats[AR7240_NUM_PORTS];
307 };
308
309 struct ar7240sw_hw_stat {
310 char string[ETH_GSTRING_LEN];
311 int sizeof_stat;
312 int reg;
313 };
314
315 static DEFINE_MUTEX(reg_mutex);
316
317 static inline int sw_is_ar7240(struct ar7240sw *as)
318 {
319 return as->ver == AR7240_MASK_CTRL_VERSION_AR7240;
320 }
321
322 static inline int sw_is_ar934x(struct ar7240sw *as)
323 {
324 return as->ver == AR7240_MASK_CTRL_VERSION_AR934X;
325 }
326
327 static inline u32 ar7240sw_port_mask(struct ar7240sw *as, int port)
328 {
329 return BIT(port);
330 }
331
332 static inline u32 ar7240sw_port_mask_all(struct ar7240sw *as)
333 {
334 return BIT(as->swdev.ports) - 1;
335 }
336
337 static inline u32 ar7240sw_port_mask_but(struct ar7240sw *as, int port)
338 {
339 return ar7240sw_port_mask_all(as) & ~BIT(port);
340 }
341
342 static inline u16 mk_phy_addr(u32 reg)
343 {
344 return 0x17 & ((reg >> 4) | 0x10);
345 }
346
347 static inline u16 mk_phy_reg(u32 reg)
348 {
349 return (reg << 1) & 0x1e;
350 }
351
352 static inline u16 mk_high_addr(u32 reg)
353 {
354 return (reg >> 7) & 0x1ff;
355 }
356
357 static u32 __ar7240sw_reg_read(struct mii_bus *mii, u32 reg)
358 {
359 unsigned long flags;
360 u16 phy_addr;
361 u16 phy_reg;
362 u32 hi, lo;
363
364 reg = (reg & 0xfffffffc) >> 2;
365 phy_addr = mk_phy_addr(reg);
366 phy_reg = mk_phy_reg(reg);
367
368 local_irq_save(flags);
369 ag71xx_mdio_mii_write(mii, 0x1f, 0x10, mk_high_addr(reg));
370 lo = (u32) ag71xx_mdio_mii_read(mii, phy_addr, phy_reg);
371 hi = (u32) ag71xx_mdio_mii_read(mii, phy_addr, phy_reg + 1);
372 local_irq_restore(flags);
373
374 return (hi << 16) | lo;
375 }
376
377 static void __ar7240sw_reg_write(struct mii_bus *mii, u32 reg, u32 val)
378 {
379 unsigned long flags;
380 u16 phy_addr;
381 u16 phy_reg;
382
383 reg = (reg & 0xfffffffc) >> 2;
384 phy_addr = mk_phy_addr(reg);
385 phy_reg = mk_phy_reg(reg);
386
387 local_irq_save(flags);
388 ag71xx_mdio_mii_write(mii, 0x1f, 0x10, mk_high_addr(reg));
389 ag71xx_mdio_mii_write(mii, phy_addr, phy_reg + 1, (val >> 16));
390 ag71xx_mdio_mii_write(mii, phy_addr, phy_reg, (val & 0xffff));
391 local_irq_restore(flags);
392 }
393
394 static u32 ar7240sw_reg_read(struct mii_bus *mii, u32 reg_addr)
395 {
396 u32 ret;
397
398 mutex_lock(&reg_mutex);
399 ret = __ar7240sw_reg_read(mii, reg_addr);
400 mutex_unlock(&reg_mutex);
401
402 return ret;
403 }
404
405 static void ar7240sw_reg_write(struct mii_bus *mii, u32 reg_addr, u32 reg_val)
406 {
407 mutex_lock(&reg_mutex);
408 __ar7240sw_reg_write(mii, reg_addr, reg_val);
409 mutex_unlock(&reg_mutex);
410 }
411
412 static u32 ar7240sw_reg_rmw(struct mii_bus *mii, u32 reg, u32 mask, u32 val)
413 {
414 u32 t;
415
416 mutex_lock(&reg_mutex);
417 t = __ar7240sw_reg_read(mii, reg);
418 t &= ~mask;
419 t |= val;
420 __ar7240sw_reg_write(mii, reg, t);
421 mutex_unlock(&reg_mutex);
422
423 return t;
424 }
425
426 static void ar7240sw_reg_set(struct mii_bus *mii, u32 reg, u32 val)
427 {
428 u32 t;
429
430 mutex_lock(&reg_mutex);
431 t = __ar7240sw_reg_read(mii, reg);
432 t |= val;
433 __ar7240sw_reg_write(mii, reg, t);
434 mutex_unlock(&reg_mutex);
435 }
436
437 static int __ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
438 unsigned timeout)
439 {
440 int i;
441
442 for (i = 0; i < timeout; i++) {
443 u32 t;
444
445 t = __ar7240sw_reg_read(mii, reg);
446 if ((t & mask) == val)
447 return 0;
448
449 usleep_range(1000, 2000);
450 }
451
452 return -ETIMEDOUT;
453 }
454
455 static int ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
456 unsigned timeout)
457 {
458 int ret;
459
460 mutex_lock(&reg_mutex);
461 ret = __ar7240sw_reg_wait(mii, reg, mask, val, timeout);
462 mutex_unlock(&reg_mutex);
463 return ret;
464 }
465
466 int ar7240sw_phy_read(struct mii_bus *mii, int phy_addr, int reg_addr)
467 {
468 u32 t, val = 0xffff;
469 int err;
470
471 if (phy_addr >= AR7240_NUM_PHYS)
472 return 0xffff;
473
474 mutex_lock(&reg_mutex);
475 t = (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
476 (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
477 AR7240_MDIO_CTRL_MASTER_EN |
478 AR7240_MDIO_CTRL_BUSY |
479 AR7240_MDIO_CTRL_CMD_READ;
480
481 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
482 err = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
483 AR7240_MDIO_CTRL_BUSY, 0, 5);
484 if (!err)
485 val = __ar7240sw_reg_read(mii, AR7240_REG_MDIO_CTRL);
486 mutex_unlock(&reg_mutex);
487
488 return val & AR7240_MDIO_CTRL_DATA_M;
489 }
490
491 int ar7240sw_phy_write(struct mii_bus *mii, int phy_addr, int reg_addr,
492 u16 reg_val)
493 {
494 u32 t;
495 int ret;
496
497 if (phy_addr >= AR7240_NUM_PHYS)
498 return -EINVAL;
499
500 mutex_lock(&reg_mutex);
501 t = (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
502 (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
503 AR7240_MDIO_CTRL_MASTER_EN |
504 AR7240_MDIO_CTRL_BUSY |
505 AR7240_MDIO_CTRL_CMD_WRITE |
506 reg_val;
507
508 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
509 ret = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
510 AR7240_MDIO_CTRL_BUSY, 0, 5);
511 mutex_unlock(&reg_mutex);
512
513 return ret;
514 }
515
516 static int ar7240sw_capture_stats(struct ar7240sw *as)
517 {
518 struct mii_bus *mii = as->mii_bus;
519 int port;
520 int ret;
521
522 write_lock(&as->stats_lock);
523
524 /* Capture the hardware statistics for all ports */
525 ar7240sw_reg_rmw(mii, AR7240_REG_MIB_FUNCTION0,
526 (AR7240_MIB_FUNC_M << AR7240_MIB_FUNC_S),
527 (AR7240_MIB_FUNC_CAPTURE << AR7240_MIB_FUNC_S));
528
529 /* Wait for the capturing to complete. */
530 ret = ar7240sw_reg_wait(mii, AR7240_REG_MIB_FUNCTION0,
531 AR7240_MIB_BUSY, 0, 10);
532
533 if (ret)
534 goto unlock;
535
536 for (port = 0; port < AR7240_NUM_PORTS; port++) {
537 unsigned int base;
538 struct ar7240sw_port_stat *stats;
539
540 base = AR7240_REG_STATS_BASE(port);
541 stats = &as->port_stats[port];
542
543 #define READ_STAT(_r) ar7240sw_reg_read(mii, base + AR7240_STATS_ ## _r)
544
545 stats->rx_good_byte += READ_STAT(RXGOODBYTE);
546 stats->tx_byte += READ_STAT(TXBYTE);
547
548 #undef READ_STAT
549 }
550
551 ret = 0;
552
553 unlock:
554 write_unlock(&as->stats_lock);
555 return ret;
556 }
557
558 static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port)
559 {
560 ar7240sw_reg_write(as->mii_bus, AR7240_REG_PORT_CTRL(port),
561 AR7240_PORT_CTRL_STATE_DISABLED);
562 }
563
564 static void ar7240sw_setup(struct ar7240sw *as)
565 {
566 struct mii_bus *mii = as->mii_bus;
567
568 /* Enable CPU port, and disable mirror port */
569 ar7240sw_reg_write(mii, AR7240_REG_CPU_PORT,
570 AR7240_CPU_PORT_EN |
571 (15 << AR7240_MIRROR_PORT_S));
572
573 /* Setup TAG priority mapping */
574 ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50);
575
576 if (sw_is_ar934x(as)) {
577 /* Enable aging, MAC replacing */
578 ar7240sw_reg_write(mii, AR934X_REG_AT_CTRL,
579 0x2b /* 5 min age time */ |
580 AR934X_AT_CTRL_AGE_EN |
581 AR934X_AT_CTRL_LEARN_CHANGE);
582 /* Enable ARP frame acknowledge */
583 ar7240sw_reg_set(mii, AR934X_REG_QM_CTRL,
584 AR934X_QM_CTRL_ARP_EN);
585 /* Enable Broadcast/Multicast frames transmitted to the CPU */
586 ar7240sw_reg_set(mii, AR934X_REG_FLOOD_MASK,
587 AR934X_FLOOD_MASK_BC_DP(0) |
588 AR934X_FLOOD_MASK_MC_DP(0));
589
590 /* setup MTU */
591 ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL,
592 AR9340_GLOBAL_CTRL_MTU_M,
593 AR9340_GLOBAL_CTRL_MTU_M);
594
595 /* Enable MIB counters */
596 ar7240sw_reg_set(mii, AR7240_REG_MIB_FUNCTION0,
597 AR934X_MIB_ENABLE);
598
599 } else {
600 /* Enable ARP frame acknowledge, aging, MAC replacing */
601 ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL,
602 AR7240_AT_CTRL_RESERVED |
603 0x2b /* 5 min age time */ |
604 AR7240_AT_CTRL_AGE_EN |
605 AR7240_AT_CTRL_ARP_EN |
606 AR7240_AT_CTRL_LEARN_CHANGE);
607 /* Enable Broadcast frames transmitted to the CPU */
608 ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK,
609 AR7240_FLOOD_MASK_BROAD_TO_CPU);
610
611 /* setup MTU */
612 ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL,
613 AR7240_GLOBAL_CTRL_MTU_M,
614 AR7240_GLOBAL_CTRL_MTU_M);
615 }
616
617 /* setup Service TAG */
618 ar7240sw_reg_rmw(mii, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, 0);
619 }
620
621 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
622 static int
623 ar7240sw_phy_poll_reset(struct mii_bus *bus)
624 {
625 const unsigned int sleep_msecs = 20;
626 int ret, elapsed, i;
627
628 for (elapsed = sleep_msecs; elapsed <= 600;
629 elapsed += sleep_msecs) {
630 msleep(sleep_msecs);
631 for (i = 0; i < AR7240_NUM_PHYS; i++) {
632 ret = ar7240sw_phy_read(bus, i, MII_BMCR);
633 if (ret < 0)
634 return ret;
635 if (ret & BMCR_RESET)
636 break;
637 if (i == AR7240_NUM_PHYS - 1) {
638 usleep_range(1000, 2000);
639 return 0;
640 }
641 }
642 }
643 return -ETIMEDOUT;
644 }
645
646 static int ar7240sw_reset(struct ar7240sw *as)
647 {
648 struct mii_bus *mii = as->mii_bus;
649 int ret;
650 int i;
651
652 /* Set all ports to disabled state. */
653 for (i = 0; i < AR7240_NUM_PORTS; i++)
654 ar7240sw_disable_port(as, i);
655
656 /* Wait for transmit queues to drain. */
657 usleep_range(2000, 3000);
658
659 /* Reset the switch. */
660 ar7240sw_reg_write(mii, AR7240_REG_MASK_CTRL,
661 AR7240_MASK_CTRL_SOFT_RESET);
662
663 ret = ar7240sw_reg_wait(mii, AR7240_REG_MASK_CTRL,
664 AR7240_MASK_CTRL_SOFT_RESET, 0, 1000);
665
666 /* setup PHYs */
667 for (i = 0; i < AR7240_NUM_PHYS; i++) {
668 ar7240sw_phy_write(mii, i, MII_ADVERTISE,
669 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
670 ADVERTISE_PAUSE_ASYM);
671 ar7240sw_phy_write(mii, i, MII_BMCR,
672 BMCR_RESET | BMCR_ANENABLE);
673 }
674 ret = ar7240sw_phy_poll_reset(mii);
675 if (ret)
676 return ret;
677
678 ar7240sw_setup(as);
679 return ret;
680 }
681
682 static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask)
683 {
684 struct mii_bus *mii = as->mii_bus;
685 u32 ctrl;
686 u32 vid, mode;
687
688 ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN |
689 AR7240_PORT_CTRL_SINGLE_VLAN;
690
691 if (port == AR7240_PORT_CPU) {
692 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
693 AR7240_PORT_STATUS_SPEED_1000 |
694 AR7240_PORT_STATUS_TXFLOW |
695 AR7240_PORT_STATUS_RXFLOW |
696 AR7240_PORT_STATUS_TXMAC |
697 AR7240_PORT_STATUS_RXMAC |
698 AR7240_PORT_STATUS_DUPLEX);
699 } else {
700 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
701 AR7240_PORT_STATUS_LINK_AUTO);
702 }
703
704 /* Set the default VID for this port */
705 if (as->vlan) {
706 vid = as->vlan_id[as->pvid[port]];
707 mode = AR7240_PORT_VLAN_MODE_SECURE;
708 } else {
709 vid = port;
710 mode = AR7240_PORT_VLAN_MODE_PORT_ONLY;
711 }
712
713 if (as->vlan) {
714 if (as->vlan_tagged & BIT(port))
715 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_ADD <<
716 AR7240_PORT_CTRL_VLAN_MODE_S;
717 else
718 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_STRIP <<
719 AR7240_PORT_CTRL_VLAN_MODE_S;
720 } else {
721 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_KEEP <<
722 AR7240_PORT_CTRL_VLAN_MODE_S;
723 }
724
725 if (!portmask) {
726 if (port == AR7240_PORT_CPU)
727 portmask = ar7240sw_port_mask_but(as, AR7240_PORT_CPU);
728 else
729 portmask = ar7240sw_port_mask(as, AR7240_PORT_CPU);
730 }
731
732 /* allow the port to talk to all other ports, but exclude its
733 * own ID to prevent frames from being reflected back to the
734 * port that they came from */
735 portmask &= ar7240sw_port_mask_but(as, port);
736
737 ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl);
738 if (sw_is_ar934x(as)) {
739 u32 vlan1, vlan2;
740
741 vlan1 = (vid << AR934X_PORT_VLAN1_DEFAULT_CVID_S);
742 vlan2 = (portmask << AR934X_PORT_VLAN2_PORT_VID_MEM_S) |
743 (mode << AR934X_PORT_VLAN2_8021Q_MODE_S);
744 ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN1(port), vlan1);
745 ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN2(port), vlan2);
746 } else {
747 u32 vlan;
748
749 vlan = vid | (mode << AR7240_PORT_VLAN_MODE_S) |
750 (portmask << AR7240_PORT_VLAN_DEST_PORTS_S);
751
752 ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan);
753 }
754 }
755
756 static int ar7240_set_addr(struct ar7240sw *as, u8 *addr)
757 {
758 struct mii_bus *mii = as->mii_bus;
759 u32 t;
760
761 t = (addr[4] << 8) | addr[5];
762 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR0, t);
763
764 t = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
765 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR1, t);
766
767 return 0;
768 }
769
770 static int
771 ar7240_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
772 struct switch_val *val)
773 {
774 struct ar7240sw *as = sw_to_ar7240(dev);
775 as->vlan_id[val->port_vlan] = val->value.i;
776 return 0;
777 }
778
779 static int
780 ar7240_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
781 struct switch_val *val)
782 {
783 struct ar7240sw *as = sw_to_ar7240(dev);
784 val->value.i = as->vlan_id[val->port_vlan];
785 return 0;
786 }
787
788 static int
789 ar7240_set_pvid(struct switch_dev *dev, int port, int vlan)
790 {
791 struct ar7240sw *as = sw_to_ar7240(dev);
792
793 /* make sure no invalid PVIDs get set */
794
795 if (vlan >= dev->vlans)
796 return -EINVAL;
797
798 as->pvid[port] = vlan;
799 return 0;
800 }
801
802 static int
803 ar7240_get_pvid(struct switch_dev *dev, int port, int *vlan)
804 {
805 struct ar7240sw *as = sw_to_ar7240(dev);
806 *vlan = as->pvid[port];
807 return 0;
808 }
809
810 static int
811 ar7240_get_ports(struct switch_dev *dev, struct switch_val *val)
812 {
813 struct ar7240sw *as = sw_to_ar7240(dev);
814 u8 ports = as->vlan_table[val->port_vlan];
815 int i;
816
817 val->len = 0;
818 for (i = 0; i < as->swdev.ports; i++) {
819 struct switch_port *p;
820
821 if (!(ports & (1 << i)))
822 continue;
823
824 p = &val->value.ports[val->len++];
825 p->id = i;
826 if (as->vlan_tagged & (1 << i))
827 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
828 else
829 p->flags = 0;
830 }
831 return 0;
832 }
833
834 static int
835 ar7240_set_ports(struct switch_dev *dev, struct switch_val *val)
836 {
837 struct ar7240sw *as = sw_to_ar7240(dev);
838 u8 *vt = &as->vlan_table[val->port_vlan];
839 int i, j;
840
841 *vt = 0;
842 for (i = 0; i < val->len; i++) {
843 struct switch_port *p = &val->value.ports[i];
844
845 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED))
846 as->vlan_tagged |= (1 << p->id);
847 else {
848 as->vlan_tagged &= ~(1 << p->id);
849 as->pvid[p->id] = val->port_vlan;
850
851 /* make sure that an untagged port does not
852 * appear in other vlans */
853 for (j = 0; j < AR7240_MAX_VLANS; j++) {
854 if (j == val->port_vlan)
855 continue;
856 as->vlan_table[j] &= ~(1 << p->id);
857 }
858 }
859
860 *vt |= 1 << p->id;
861 }
862 return 0;
863 }
864
865 static int
866 ar7240_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
867 struct switch_val *val)
868 {
869 struct ar7240sw *as = sw_to_ar7240(dev);
870 as->vlan = !!val->value.i;
871 return 0;
872 }
873
874 static int
875 ar7240_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
876 struct switch_val *val)
877 {
878 struct ar7240sw *as = sw_to_ar7240(dev);
879 val->value.i = as->vlan;
880 return 0;
881 }
882
883 static void
884 ar7240_vtu_op(struct ar7240sw *as, u32 op, u32 val)
885 {
886 struct mii_bus *mii = as->mii_bus;
887
888 if (ar7240sw_reg_wait(mii, AR7240_REG_VTU, AR7240_VTU_ACTIVE, 0, 5))
889 return;
890
891 if ((op & AR7240_VTU_OP) == AR7240_VTU_OP_LOAD) {
892 val &= AR7240_VTUDATA_MEMBER;
893 val |= AR7240_VTUDATA_VALID;
894 ar7240sw_reg_write(mii, AR7240_REG_VTU_DATA, val);
895 }
896 op |= AR7240_VTU_ACTIVE;
897 ar7240sw_reg_write(mii, AR7240_REG_VTU, op);
898 }
899
900 static int
901 ar7240_hw_apply(struct switch_dev *dev)
902 {
903 struct ar7240sw *as = sw_to_ar7240(dev);
904 u8 portmask[AR7240_NUM_PORTS];
905 int i, j;
906
907 /* flush all vlan translation unit entries */
908 ar7240_vtu_op(as, AR7240_VTU_OP_FLUSH, 0);
909
910 memset(portmask, 0, sizeof(portmask));
911 if (as->vlan) {
912 /* calculate the port destination masks and load vlans
913 * into the vlan translation unit */
914 for (j = 0; j < AR7240_MAX_VLANS; j++) {
915 u8 vp = as->vlan_table[j];
916
917 if (!vp)
918 continue;
919
920 for (i = 0; i < as->swdev.ports; i++) {
921 u8 mask = (1 << i);
922 if (vp & mask)
923 portmask[i] |= vp & ~mask;
924 }
925
926 ar7240_vtu_op(as,
927 AR7240_VTU_OP_LOAD |
928 (as->vlan_id[j] << AR7240_VTU_VID_S),
929 as->vlan_table[j]);
930 }
931 } else {
932 /* vlan disabled:
933 * isolate all ports, but connect them to the cpu port */
934 for (i = 0; i < as->swdev.ports; i++) {
935 if (i == AR7240_PORT_CPU)
936 continue;
937
938 portmask[i] = 1 << AR7240_PORT_CPU;
939 portmask[AR7240_PORT_CPU] |= (1 << i);
940 }
941 }
942
943 /* update the port destination mask registers and tag settings */
944 for (i = 0; i < as->swdev.ports; i++)
945 ar7240sw_setup_port(as, i, portmask[i]);
946
947 return 0;
948 }
949
950 static int
951 ar7240_reset_switch(struct switch_dev *dev)
952 {
953 struct ar7240sw *as = sw_to_ar7240(dev);
954 ar7240sw_reset(as);
955 return 0;
956 }
957
958 static int
959 ar7240_get_port_link(struct switch_dev *dev, int port,
960 struct switch_port_link *link)
961 {
962 struct ar7240sw *as = sw_to_ar7240(dev);
963 struct mii_bus *mii = as->mii_bus;
964 u32 status;
965
966 if (port >= AR7240_NUM_PORTS)
967 return -EINVAL;
968
969 status = ar7240sw_reg_read(mii, AR7240_REG_PORT_STATUS(port));
970 link->aneg = !!(status & AR7240_PORT_STATUS_LINK_AUTO);
971 if (link->aneg) {
972 link->link = !!(status & AR7240_PORT_STATUS_LINK_UP);
973 if (!link->link)
974 return 0;
975 } else {
976 link->link = true;
977 }
978
979 link->duplex = !!(status & AR7240_PORT_STATUS_DUPLEX);
980 link->tx_flow = !!(status & AR7240_PORT_STATUS_TXFLOW);
981 link->rx_flow = !!(status & AR7240_PORT_STATUS_RXFLOW);
982 switch (status & AR7240_PORT_STATUS_SPEED_M) {
983 case AR7240_PORT_STATUS_SPEED_10:
984 link->speed = SWITCH_PORT_SPEED_10;
985 break;
986 case AR7240_PORT_STATUS_SPEED_100:
987 link->speed = SWITCH_PORT_SPEED_100;
988 break;
989 case AR7240_PORT_STATUS_SPEED_1000:
990 link->speed = SWITCH_PORT_SPEED_1000;
991 break;
992 }
993
994 return 0;
995 }
996
997 static int
998 ar7240_get_port_stats(struct switch_dev *dev, int port,
999 struct switch_port_stats *stats)
1000 {
1001 struct ar7240sw *as = sw_to_ar7240(dev);
1002
1003 if (port >= AR7240_NUM_PORTS)
1004 return -EINVAL;
1005
1006 ar7240sw_capture_stats(as);
1007
1008 read_lock(&as->stats_lock);
1009 stats->rx_bytes = as->port_stats[port].rx_good_byte;
1010 stats->tx_bytes = as->port_stats[port].tx_byte;
1011 read_unlock(&as->stats_lock);
1012
1013 return 0;
1014 }
1015
1016 static int
1017 ar7240_set_mirror_monitor_port(struct switch_dev *dev,
1018 const struct switch_attr *attr,
1019 struct switch_val *val)
1020 {
1021 struct ar7240sw *as = sw_to_ar7240(dev);
1022 struct mii_bus *mii = as->mii_bus;
1023
1024 int port = val->value.i;
1025
1026 if (port > 15)
1027 return -EINVAL;
1028
1029 ar7240sw_reg_rmw(mii, AR7240_REG_CPU_PORT,
1030 AR7240_MIRROR_PORT_M << AR7240_MIRROR_PORT_S,
1031 port << AR7240_MIRROR_PORT_S);
1032
1033 return 0;
1034 }
1035
1036 static int
1037 ar7240_get_mirror_monitor_port(struct switch_dev *dev,
1038 const struct switch_attr *attr,
1039 struct switch_val *val)
1040 {
1041 struct ar7240sw *as = sw_to_ar7240(dev);
1042 struct mii_bus *mii = as->mii_bus;
1043
1044 u32 ret;
1045
1046 ret = ar7240sw_reg_read(mii, AR7240_REG_CPU_PORT);
1047 val->value.i = (ret >> AR7240_MIRROR_PORT_S) & AR7240_MIRROR_PORT_M;
1048
1049 return 0;
1050 }
1051
1052 static int
1053 ar7240_set_mirror_rx(struct switch_dev *dev, const struct switch_attr *attr,
1054 struct switch_val *val)
1055 {
1056 struct ar7240sw *as = sw_to_ar7240(dev);
1057 struct mii_bus *mii = as->mii_bus;
1058
1059 int port = val->port_vlan;
1060
1061 if (port >= dev->ports)
1062 return -EINVAL;
1063
1064 if (val && val->value.i == 1)
1065 ar7240sw_reg_set(mii, AR7240_REG_PORT_CTRL(port),
1066 AR7240_PORT_CTRL_MIRROR_RX);
1067 else
1068 ar7240sw_reg_rmw(mii, AR7240_REG_PORT_CTRL(port),
1069 AR7240_PORT_CTRL_MIRROR_RX, 0);
1070
1071 return 0;
1072 }
1073
1074 static int
1075 ar7240_get_mirror_rx(struct switch_dev *dev, const struct switch_attr *attr,
1076 struct switch_val *val)
1077 {
1078 struct ar7240sw *as = sw_to_ar7240(dev);
1079 struct mii_bus *mii = as->mii_bus;
1080
1081 u32 ctrl;
1082
1083 int port = val->port_vlan;
1084
1085 if (port >= dev->ports)
1086 return -EINVAL;
1087
1088 ctrl = ar7240sw_reg_read(mii, AR7240_REG_PORT_CTRL(port));
1089
1090 if ((ctrl & AR7240_PORT_CTRL_MIRROR_RX) == AR7240_PORT_CTRL_MIRROR_RX)
1091 val->value.i = 1;
1092 else
1093 val->value.i = 0;
1094
1095 return 0;
1096 }
1097
1098 static int
1099 ar7240_set_mirror_tx(struct switch_dev *dev, const struct switch_attr *attr,
1100 struct switch_val *val)
1101 {
1102 struct ar7240sw *as = sw_to_ar7240(dev);
1103 struct mii_bus *mii = as->mii_bus;
1104
1105 int port = val->port_vlan;
1106
1107 if (port >= dev->ports)
1108 return -EINVAL;
1109
1110 if (val && val->value.i == 1)
1111 ar7240sw_reg_set(mii, AR7240_REG_PORT_CTRL(port),
1112 AR7240_PORT_CTRL_MIRROR_TX);
1113 else
1114 ar7240sw_reg_rmw(mii, AR7240_REG_PORT_CTRL(port),
1115 AR7240_PORT_CTRL_MIRROR_TX, 0);
1116
1117 return 0;
1118 }
1119
1120 static int
1121 ar7240_get_mirror_tx(struct switch_dev *dev, const struct switch_attr *attr,
1122 struct switch_val *val)
1123 {
1124 struct ar7240sw *as = sw_to_ar7240(dev);
1125 struct mii_bus *mii = as->mii_bus;
1126
1127 u32 ctrl;
1128
1129 int port = val->port_vlan;
1130
1131 if (port >= dev->ports)
1132 return -EINVAL;
1133
1134 ctrl = ar7240sw_reg_read(mii, AR7240_REG_PORT_CTRL(port));
1135
1136 if ((ctrl & AR7240_PORT_CTRL_MIRROR_TX) == AR7240_PORT_CTRL_MIRROR_TX)
1137 val->value.i = 1;
1138 else
1139 val->value.i = 0;
1140
1141 return 0;
1142 }
1143
1144 static struct switch_attr ar7240_globals[] = {
1145 {
1146 .type = SWITCH_TYPE_INT,
1147 .name = "enable_vlan",
1148 .description = "Enable VLAN mode",
1149 .set = ar7240_set_vlan,
1150 .get = ar7240_get_vlan,
1151 .max = 1
1152 },
1153 {
1154 .type = SWITCH_TYPE_INT,
1155 .name = "mirror_monitor_port",
1156 .description = "Mirror monitor port",
1157 .set = ar7240_set_mirror_monitor_port,
1158 .get = ar7240_get_mirror_monitor_port,
1159 .max = 15
1160 },
1161 };
1162
1163 static struct switch_attr ar7240_port[] = {
1164 {
1165 .type = SWITCH_TYPE_INT,
1166 .name = "enable_mirror_rx",
1167 .description = "Enable mirroring of RX packets",
1168 .set = ar7240_set_mirror_rx,
1169 .get = ar7240_get_mirror_rx,
1170 .max = 1
1171 },
1172 {
1173 .type = SWITCH_TYPE_INT,
1174 .name = "enable_mirror_tx",
1175 .description = "Enable mirroring of TX packets",
1176 .set = ar7240_set_mirror_tx,
1177 .get = ar7240_get_mirror_tx,
1178 .max = 1
1179 },
1180 };
1181
1182 static struct switch_attr ar7240_vlan[] = {
1183 {
1184 .type = SWITCH_TYPE_INT,
1185 .name = "vid",
1186 .description = "VLAN ID",
1187 .set = ar7240_set_vid,
1188 .get = ar7240_get_vid,
1189 .max = 4094,
1190 },
1191 };
1192
1193 static const struct switch_dev_ops ar7240_ops = {
1194 .attr_global = {
1195 .attr = ar7240_globals,
1196 .n_attr = ARRAY_SIZE(ar7240_globals),
1197 },
1198 .attr_port = {
1199 .attr = ar7240_port,
1200 .n_attr = ARRAY_SIZE(ar7240_port),
1201 },
1202 .attr_vlan = {
1203 .attr = ar7240_vlan,
1204 .n_attr = ARRAY_SIZE(ar7240_vlan),
1205 },
1206 .get_port_pvid = ar7240_get_pvid,
1207 .set_port_pvid = ar7240_set_pvid,
1208 .get_vlan_ports = ar7240_get_ports,
1209 .set_vlan_ports = ar7240_set_ports,
1210 .apply_config = ar7240_hw_apply,
1211 .reset_switch = ar7240_reset_switch,
1212 .get_port_link = ar7240_get_port_link,
1213 .get_port_stats = ar7240_get_port_stats,
1214 };
1215
1216 static struct ar7240sw *
1217 ar7240_probe(struct ag71xx *ag, struct device_node *np)
1218 {
1219 struct mii_bus *mii = ag->mii_bus;
1220 struct ar7240sw *as;
1221 struct switch_dev *swdev;
1222 u32 ctrl;
1223 u16 phy_id1;
1224 u16 phy_id2;
1225 int i;
1226
1227 phy_id1 = ar7240sw_phy_read(mii, 0, MII_PHYSID1);
1228 phy_id2 = ar7240sw_phy_read(mii, 0, MII_PHYSID2);
1229 if ((phy_id1 != AR7240_PHY_ID1 || phy_id2 != AR7240_PHY_ID2) &&
1230 (phy_id1 != AR934X_PHY_ID1 || phy_id2 != AR934X_PHY_ID2)) {
1231 pr_err("%s: unknown phy id '%04x:%04x'\n",
1232 dev_name(&mii->dev), phy_id1, phy_id2);
1233 return NULL;
1234 }
1235
1236 as = kzalloc(sizeof(*as), GFP_KERNEL);
1237 if (!as)
1238 return NULL;
1239
1240 as->mii_bus = mii;
1241
1242 swdev = &as->swdev;
1243
1244 ctrl = ar7240sw_reg_read(mii, AR7240_REG_MASK_CTRL);
1245 as->ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) &
1246 AR7240_MASK_CTRL_VERSION_M;
1247
1248 if (sw_is_ar7240(as)) {
1249 swdev->name = "AR7240/AR9330 built-in switch";
1250 swdev->ports = AR7240_NUM_PORTS - 1;
1251 } else if (sw_is_ar934x(as)) {
1252 swdev->name = "AR934X built-in switch";
1253
1254 if (ag->phy_if_mode == PHY_INTERFACE_MODE_GMII) {
1255 ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
1256 AR934X_OPER_MODE0_MAC_GMII_EN);
1257 } else if (ag->phy_if_mode == PHY_INTERFACE_MODE_MII) {
1258 ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
1259 AR934X_OPER_MODE0_PHY_MII_EN);
1260 } else {
1261 pr_err("%s: invalid PHY interface mode\n",
1262 dev_name(&mii->dev));
1263 goto err_free;
1264 }
1265
1266 if (of_property_read_bool(np, "phy4-mii-enable")) {
1267 ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE1,
1268 AR934X_REG_OPER_MODE1_PHY4_MII_EN);
1269 swdev->ports = AR7240_NUM_PORTS - 1;
1270 } else {
1271 swdev->ports = AR7240_NUM_PORTS;
1272 }
1273 } else {
1274 pr_err("%s: unsupported chip, ctrl=%08x\n",
1275 dev_name(&mii->dev), ctrl);
1276 goto err_free;
1277 }
1278
1279 swdev->cpu_port = AR7240_PORT_CPU;
1280 swdev->vlans = AR7240_MAX_VLANS;
1281 swdev->ops = &ar7240_ops;
1282
1283 if (register_switch(&as->swdev, ag->dev) < 0)
1284 goto err_free;
1285
1286 pr_info("%s: Found an %s\n", dev_name(&mii->dev), swdev->name);
1287
1288 /* initialize defaults */
1289 for (i = 0; i < AR7240_MAX_VLANS; i++)
1290 as->vlan_id[i] = i;
1291
1292 as->vlan_table[0] = ar7240sw_port_mask_all(as);
1293
1294 return as;
1295
1296 err_free:
1297 kfree(as);
1298 return NULL;
1299 }
1300
1301 void ag71xx_ar7240_start(struct ag71xx *ag)
1302 {
1303 struct ar7240sw *as = ag->phy_priv;
1304
1305 if (!as)
1306 return;
1307
1308 ar7240sw_reset(as);
1309
1310 ar7240_set_addr(as, ag->dev->dev_addr);
1311 ar7240_hw_apply(&as->swdev);
1312 }
1313
1314 int ag71xx_ar7240_init(struct ag71xx *ag, struct device_node *np)
1315 {
1316 struct ar7240sw *as;
1317
1318 as = ar7240_probe(ag, np);
1319 if (!as)
1320 return -ENODEV;
1321
1322 ag->phy_priv = as;
1323 ar7240sw_reset(as);
1324
1325 rwlock_init(&as->stats_lock);
1326
1327 return 0;
1328 }
1329
1330 void ag71xx_ar7240_cleanup(struct ag71xx *ag)
1331 {
1332 struct ar7240sw *as = ag->phy_priv;
1333
1334 if (!as)
1335 return;
1336
1337 unregister_switch(&as->swdev);
1338 kfree(as);
1339 ag->phy_priv = NULL;
1340 }
OpenWrt Source Repository