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[openwrt/openwrt.git] / target / linux / ath79 / files / drivers / net / ethernet / atheros / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include <linux/sizes.h>
15 #include <linux/of_net.h>
16 #include <linux/of_address.h>
17 #include <linux/of_platform.h>
18 #include "ag71xx.h"
19
20 #define AG71XX_DEFAULT_MSG_ENABLE \
21 (NETIF_MSG_DRV \
22 | NETIF_MSG_PROBE \
23 | NETIF_MSG_LINK \
24 | NETIF_MSG_TIMER \
25 | NETIF_MSG_IFDOWN \
26 | NETIF_MSG_IFUP \
27 | NETIF_MSG_RX_ERR \
28 | NETIF_MSG_TX_ERR)
29
30 static int ag71xx_msg_level = -1;
31
32 module_param_named(msg_level, ag71xx_msg_level, int, 0);
33 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
34
35 #define ETH_SWITCH_HEADER_LEN 2
36
37 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush);
38
39 static inline unsigned int ag71xx_max_frame_len(unsigned int mtu)
40 {
41 return ETH_SWITCH_HEADER_LEN + ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN;
42 }
43
44 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
45 {
46 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
47 ag->dev->name,
48 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
49 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
50 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
51
52 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
53 ag->dev->name,
54 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
55 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
56 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
57 }
58
59 static void ag71xx_dump_regs(struct ag71xx *ag)
60 {
61 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
62 ag->dev->name,
63 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
64 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
65 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
66 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
67 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
68 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
69 ag->dev->name,
70 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
71 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
72 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
73 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
74 ag->dev->name,
75 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
76 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
77 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
78 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
79 ag->dev->name,
80 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
81 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
82 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
83 }
84
85 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
86 {
87 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
88 ag->dev->name, label, intr,
89 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
90 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
91 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
92 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
93 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
94 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
95 }
96
97 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
98 {
99 struct ag71xx_ring *ring = &ag->tx_ring;
100 struct net_device *dev = ag->dev;
101 int ring_mask = BIT(ring->order) - 1;
102 u32 bytes_compl = 0, pkts_compl = 0;
103
104 while (ring->curr != ring->dirty) {
105 struct ag71xx_desc *desc;
106 u32 i = ring->dirty & ring_mask;
107
108 desc = ag71xx_ring_desc(ring, i);
109 if (!ag71xx_desc_empty(desc)) {
110 desc->ctrl = 0;
111 dev->stats.tx_errors++;
112 }
113
114 if (ring->buf[i].skb) {
115 bytes_compl += ring->buf[i].len;
116 pkts_compl++;
117 dev_kfree_skb_any(ring->buf[i].skb);
118 }
119 ring->buf[i].skb = NULL;
120 ring->dirty++;
121 }
122
123 /* flush descriptors */
124 wmb();
125
126 netdev_completed_queue(dev, pkts_compl, bytes_compl);
127 }
128
129 static void ag71xx_ring_tx_init(struct ag71xx *ag)
130 {
131 struct ag71xx_ring *ring = &ag->tx_ring;
132 int ring_size = BIT(ring->order);
133 int ring_mask = BIT(ring->order) - 1;
134 int i;
135
136 for (i = 0; i < ring_size; i++) {
137 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
138
139 desc->next = (u32) (ring->descs_dma +
140 AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
141
142 desc->ctrl = DESC_EMPTY;
143 ring->buf[i].skb = NULL;
144 }
145
146 /* flush descriptors */
147 wmb();
148
149 ring->curr = 0;
150 ring->dirty = 0;
151 netdev_reset_queue(ag->dev);
152 }
153
154 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
155 {
156 struct ag71xx_ring *ring = &ag->rx_ring;
157 int ring_size = BIT(ring->order);
158 int i;
159
160 if (!ring->buf)
161 return;
162
163 for (i = 0; i < ring_size; i++)
164 if (ring->buf[i].rx_buf) {
165 dma_unmap_single(&ag->pdev->dev, ring->buf[i].dma_addr,
166 ag->rx_buf_size, DMA_FROM_DEVICE);
167 skb_free_frag(ring->buf[i].rx_buf);
168 }
169 }
170
171 static int ag71xx_buffer_size(struct ag71xx *ag)
172 {
173 return ag->rx_buf_size +
174 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
175 }
176
177 static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf,
178 int offset,
179 void *(*alloc)(unsigned int size))
180 {
181 struct ag71xx_ring *ring = &ag->rx_ring;
182 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, buf - &ring->buf[0]);
183 void *data;
184
185 data = alloc(ag71xx_buffer_size(ag));
186 if (!data)
187 return false;
188
189 buf->rx_buf = data;
190 buf->dma_addr = dma_map_single(&ag->pdev->dev, data, ag->rx_buf_size,
191 DMA_FROM_DEVICE);
192 desc->data = (u32) buf->dma_addr + offset;
193 return true;
194 }
195
196 static int ag71xx_ring_rx_init(struct ag71xx *ag)
197 {
198 struct ag71xx_ring *ring = &ag->rx_ring;
199 int ring_size = BIT(ring->order);
200 int ring_mask = BIT(ring->order) - 1;
201 unsigned int i;
202 int ret;
203
204 ret = 0;
205 for (i = 0; i < ring_size; i++) {
206 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
207
208 desc->next = (u32) (ring->descs_dma +
209 AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
210
211 DBG("ag71xx: RX desc at %p, next is %08x\n",
212 desc, desc->next);
213 }
214
215 for (i = 0; i < ring_size; i++) {
216 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
217
218 if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], ag->rx_buf_offset,
219 netdev_alloc_frag)) {
220 ret = -ENOMEM;
221 break;
222 }
223
224 desc->ctrl = DESC_EMPTY;
225 }
226
227 /* flush descriptors */
228 wmb();
229
230 ring->curr = 0;
231 ring->dirty = 0;
232
233 return ret;
234 }
235
236 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
237 {
238 struct ag71xx_ring *ring = &ag->rx_ring;
239 int ring_mask = BIT(ring->order) - 1;
240 unsigned int count;
241 int offset = ag->rx_buf_offset;
242
243 count = 0;
244 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
245 struct ag71xx_desc *desc;
246 unsigned int i;
247
248 i = ring->dirty & ring_mask;
249 desc = ag71xx_ring_desc(ring, i);
250
251 if (!ring->buf[i].rx_buf &&
252 !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset,
253 napi_alloc_frag))
254 break;
255
256 desc->ctrl = DESC_EMPTY;
257 count++;
258 }
259
260 /* flush descriptors */
261 wmb();
262
263 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
264
265 return count;
266 }
267
268 static int ag71xx_rings_init(struct ag71xx *ag)
269 {
270 struct ag71xx_ring *tx = &ag->tx_ring;
271 struct ag71xx_ring *rx = &ag->rx_ring;
272 int ring_size = BIT(tx->order) + BIT(rx->order);
273 int tx_size = BIT(tx->order);
274
275 tx->buf = kzalloc(ring_size * sizeof(*tx->buf), GFP_KERNEL);
276 if (!tx->buf)
277 return -ENOMEM;
278
279 tx->descs_cpu = dma_alloc_coherent(&ag->pdev->dev, ring_size * AG71XX_DESC_SIZE,
280 &tx->descs_dma, GFP_KERNEL);
281 if (!tx->descs_cpu) {
282 kfree(tx->buf);
283 tx->buf = NULL;
284 return -ENOMEM;
285 }
286
287 rx->buf = &tx->buf[tx_size];
288 rx->descs_cpu = ((void *)tx->descs_cpu) + tx_size * AG71XX_DESC_SIZE;
289 rx->descs_dma = tx->descs_dma + tx_size * AG71XX_DESC_SIZE;
290
291 ag71xx_ring_tx_init(ag);
292 return ag71xx_ring_rx_init(ag);
293 }
294
295 static void ag71xx_rings_free(struct ag71xx *ag)
296 {
297 struct ag71xx_ring *tx = &ag->tx_ring;
298 struct ag71xx_ring *rx = &ag->rx_ring;
299 int ring_size = BIT(tx->order) + BIT(rx->order);
300
301 if (tx->descs_cpu)
302 dma_free_coherent(&ag->pdev->dev, ring_size * AG71XX_DESC_SIZE,
303 tx->descs_cpu, tx->descs_dma);
304
305 kfree(tx->buf);
306
307 tx->descs_cpu = NULL;
308 rx->descs_cpu = NULL;
309 tx->buf = NULL;
310 rx->buf = NULL;
311 }
312
313 static void ag71xx_rings_cleanup(struct ag71xx *ag)
314 {
315 ag71xx_ring_rx_clean(ag);
316 ag71xx_ring_tx_clean(ag);
317 ag71xx_rings_free(ag);
318
319 netdev_reset_queue(ag->dev);
320 }
321
322 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
323 {
324 switch (ag->speed) {
325 case SPEED_1000:
326 return "1000";
327 case SPEED_100:
328 return "100";
329 case SPEED_10:
330 return "10";
331 }
332
333 return "?";
334 }
335
336 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
337 {
338 u32 t;
339
340 t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
341 | (((u32) mac[3]) << 8) | ((u32) mac[2]);
342
343 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
344
345 t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
346 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
347 }
348
349 static void ag71xx_dma_reset(struct ag71xx *ag)
350 {
351 u32 val;
352 int i;
353
354 ag71xx_dump_dma_regs(ag);
355
356 /* stop RX and TX */
357 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
358 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
359
360 /*
361 * give the hardware some time to really stop all rx/tx activity
362 * clearing the descriptors too early causes random memory corruption
363 */
364 mdelay(1);
365
366 /* clear descriptor addresses */
367 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
368 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
369
370 /* clear pending RX/TX interrupts */
371 for (i = 0; i < 256; i++) {
372 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
373 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
374 }
375
376 /* clear pending errors */
377 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
378 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
379
380 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
381 if (val)
382 pr_alert("%s: unable to clear DMA Rx status: %08x\n",
383 ag->dev->name, val);
384
385 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
386
387 /* mask out reserved bits */
388 val &= ~0xff000000;
389
390 if (val)
391 pr_alert("%s: unable to clear DMA Tx status: %08x\n",
392 ag->dev->name, val);
393
394 ag71xx_dump_dma_regs(ag);
395 }
396
397 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
398 MAC_CFG1_SRX | MAC_CFG1_STX)
399
400 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
401
402 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
403 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
404 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
405 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
406 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
407 FIFO_CFG4_VT)
408
409 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
410 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
411 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
412 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
413 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
414 FIFO_CFG5_17 | FIFO_CFG5_SF)
415
416 static void ag71xx_hw_stop(struct ag71xx *ag)
417 {
418 /* disable all interrupts and stop the rx/tx engine */
419 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
420 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
421 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
422 }
423
424 static void ag71xx_hw_setup(struct ag71xx *ag)
425 {
426 struct device_node *np = ag->pdev->dev.of_node;
427 u32 init = MAC_CFG1_INIT;
428
429 /* setup MAC configuration registers */
430 if (of_property_read_bool(np, "flow-control"))
431 init |= MAC_CFG1_TFC | MAC_CFG1_RFC;
432 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, init);
433
434 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
435 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
436
437 /* setup max frame length to zero */
438 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0);
439
440 /* setup FIFO configuration registers */
441 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
442 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, ag->fifodata[0]);
443 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, ag->fifodata[1]);
444 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
445 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
446 }
447
448 static void ag71xx_hw_init(struct ag71xx *ag)
449 {
450 ag71xx_hw_stop(ag);
451
452 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
453 udelay(20);
454
455 reset_control_assert(ag->mac_reset);
456 if (ag->mdio_reset)
457 reset_control_assert(ag->mdio_reset);
458 msleep(100);
459 reset_control_deassert(ag->mac_reset);
460 if (ag->mdio_reset)
461 reset_control_deassert(ag->mdio_reset);
462 msleep(200);
463
464 ag71xx_hw_setup(ag);
465
466 ag71xx_dma_reset(ag);
467 }
468
469 static void ag71xx_fast_reset(struct ag71xx *ag)
470 {
471 struct net_device *dev = ag->dev;
472 u32 rx_ds;
473 u32 mii_reg;
474
475 ag71xx_hw_stop(ag);
476 wmb();
477
478 mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
479 rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
480
481 ag71xx_tx_packets(ag, true);
482
483 reset_control_assert(ag->mac_reset);
484 udelay(10);
485 reset_control_deassert(ag->mac_reset);
486 udelay(10);
487
488 ag71xx_dma_reset(ag);
489 ag71xx_hw_setup(ag);
490 ag->tx_ring.curr = 0;
491 ag->tx_ring.dirty = 0;
492 netdev_reset_queue(ag->dev);
493
494 /* setup max frame length */
495 ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
496 ag71xx_max_frame_len(ag->dev->mtu));
497
498 ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
499 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
500 ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
501
502 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
503 }
504
505 static void ag71xx_hw_start(struct ag71xx *ag)
506 {
507 /* start RX engine */
508 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
509
510 /* enable interrupts */
511 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
512
513 netif_wake_queue(ag->dev);
514 }
515
516 static void ath79_set_pllval(struct ag71xx *ag)
517 {
518 u32 pll_reg = ag->pllreg[1];
519 u32 pll_val;
520
521 if (!ag->pllregmap)
522 return;
523
524 switch (ag->speed) {
525 case SPEED_10:
526 pll_val = ag->plldata[2];
527 break;
528 case SPEED_100:
529 pll_val = ag->plldata[1];
530 break;
531 case SPEED_1000:
532 pll_val = ag->plldata[0];
533 break;
534 default:
535 BUG();
536 }
537
538 if (pll_val)
539 regmap_write(ag->pllregmap, pll_reg, pll_val);
540 }
541
542 static void ath79_set_pll(struct ag71xx *ag)
543 {
544 u32 pll_cfg = ag->pllreg[0];
545 u32 pll_shift = ag->pllreg[2];
546
547 if (!ag->pllregmap)
548 return;
549
550 regmap_update_bits(ag->pllregmap, pll_cfg, 3 << pll_shift, 2 << pll_shift);
551 udelay(100);
552
553 ath79_set_pllval(ag);
554
555 regmap_update_bits(ag->pllregmap, pll_cfg, 3 << pll_shift, 3 << pll_shift);
556 udelay(100);
557
558 regmap_update_bits(ag->pllregmap, pll_cfg, 3 << pll_shift, 0);
559 udelay(100);
560 }
561
562 static void ag71xx_bit_set(void __iomem *reg, u32 bit)
563 {
564 u32 val;
565
566 val = __raw_readl(reg) | bit;
567 __raw_writel(val, reg);
568 __raw_readl(reg);
569 }
570
571 static void ag71xx_bit_clear(void __iomem *reg, u32 bit)
572 {
573 u32 val;
574
575 val = __raw_readl(reg) & ~bit;
576 __raw_writel(val, reg);
577 __raw_readl(reg);
578 }
579
580 static void ag71xx_sgmii_serdes_init_qca956x(struct device_node *np)
581 {
582 struct device_node *np_dev;
583 void __iomem *gmac_base;
584 u32 serdes_cal;
585 u32 t;
586
587 np = of_get_child_by_name(np, "gmac-config");
588 if (!np)
589 return;
590
591 if (of_property_read_u32(np, "serdes-cal", &serdes_cal))
592 /* By default, use middle value for resistor calibration */
593 serdes_cal = 0x7;
594
595 np_dev = of_parse_phandle(np, "device", 0);
596 if (!np_dev)
597 goto out;
598
599 gmac_base = of_iomap(np_dev, 0);
600 if (!gmac_base) {
601 pr_err("%pOF: can't map GMAC registers\n", np_dev);
602 goto err_iomap;
603 }
604
605 pr_debug("%pOF: fixup SERDES calibration to value %i\n",
606 np_dev, serdes_cal);
607 t = __raw_readl(gmac_base + QCA956X_GMAC_REG_SGMII_SERDES);
608 t &= ~(QCA956X_SGMII_SERDES_RES_CALIBRATION_MASK
609 << QCA956X_SGMII_SERDES_RES_CALIBRATION_SHIFT);
610 t |= (serdes_cal & QCA956X_SGMII_SERDES_RES_CALIBRATION_MASK)
611 << QCA956X_SGMII_SERDES_RES_CALIBRATION_SHIFT;
612 __raw_writel(t, gmac_base + QCA956X_GMAC_REG_SGMII_SERDES);
613
614 ath79_pll_wr(QCA956X_PLL_ETH_SGMII_SERDES_REG,
615 QCA956X_PLL_ETH_SGMII_SERDES_LOCK_DETECT
616 | QCA956X_PLL_ETH_SGMII_SERDES_EN_PLL);
617
618 t = __raw_readl(gmac_base + QCA956X_GMAC_REG_SGMII_SERDES);
619
620 /* missing in QCA u-boot code, clear before setting */
621 t &= ~(QCA956X_SGMII_SERDES_CDR_BW_MASK
622 << QCA956X_SGMII_SERDES_CDR_BW_SHIFT |
623 QCA956X_SGMII_SERDES_TX_DR_CTRL_MASK
624 << QCA956X_SGMII_SERDES_TX_DR_CTRL_SHIFT |
625 QCA956X_SGMII_SERDES_VCO_REG_MASK
626 << QCA956X_SGMII_SERDES_VCO_REG_SHIFT);
627
628 t |= (3 << QCA956X_SGMII_SERDES_CDR_BW_SHIFT) |
629 (1 << QCA956X_SGMII_SERDES_TX_DR_CTRL_SHIFT) |
630 QCA956X_SGMII_SERDES_PLL_BW |
631 QCA956X_SGMII_SERDES_EN_SIGNAL_DETECT |
632 QCA956X_SGMII_SERDES_FIBER_SDO |
633 (3 << QCA956X_SGMII_SERDES_VCO_REG_SHIFT);
634
635 __raw_writel(t, gmac_base + QCA956X_GMAC_REG_SGMII_SERDES);
636
637 ath79_device_reset_clear(QCA956X_RESET_SGMII_ANALOG);
638 ath79_device_reset_clear(QCA956X_RESET_SGMII);
639
640 while (!(__raw_readl(gmac_base + QCA956X_GMAC_REG_SGMII_SERDES)
641 & QCA956X_SGMII_SERDES_LOCK_DETECT_STATUS))
642 ;
643
644 iounmap(gmac_base);
645 err_iomap:
646 of_node_put(np_dev);
647 out:
648 of_node_put(np);
649 }
650
651 static void ag71xx_sgmii_init_qca955x(struct device_node *np)
652 {
653 struct device_node *np_dev;
654 void __iomem *gmac_base;
655 u32 mr_an_status;
656 u32 sgmii_status;
657 u8 tries = 0;
658 int err = 0;
659
660 np = of_get_child_by_name(np, "gmac-config");
661 if (!np)
662 return;
663
664 np_dev = of_parse_phandle(np, "device", 0);
665 if (!np_dev)
666 goto out;
667
668 gmac_base = of_iomap(np_dev, 0);
669 if (!gmac_base) {
670 pr_err("%pOF: can't map GMAC registers\n", np_dev);
671 err = -ENOMEM;
672 goto err_iomap;
673 }
674
675 mr_an_status = __raw_readl(gmac_base + QCA955X_GMAC_REG_MR_AN_STATUS);
676 if (!(mr_an_status & QCA955X_MR_AN_STATUS_AN_ABILITY))
677 goto sgmii_out;
678
679 /* SGMII reset sequence */
680 __raw_writel(QCA955X_SGMII_RESET_RX_CLK_N_RESET,
681 gmac_base + QCA955X_GMAC_REG_SGMII_RESET);
682 __raw_readl(gmac_base + QCA955X_GMAC_REG_SGMII_RESET);
683 udelay(10);
684
685 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
686 QCA955X_SGMII_RESET_HW_RX_125M_N);
687 udelay(10);
688
689 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
690 QCA955X_SGMII_RESET_RX_125M_N);
691 udelay(10);
692
693 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
694 QCA955X_SGMII_RESET_TX_125M_N);
695 udelay(10);
696
697 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
698 QCA955X_SGMII_RESET_RX_CLK_N);
699 udelay(10);
700
701 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
702 QCA955X_SGMII_RESET_TX_CLK_N);
703 udelay(10);
704
705 /*
706 * The following is what QCA has to say about what happens here:
707 *
708 * Across resets SGMII link status goes to weird state.
709 * If SGMII_DEBUG register reads other than 0x1f or 0x10,
710 * we are for sure in a bad state.
711 *
712 * Issue a PHY reset in MR_AN_CONTROL to keep going.
713 */
714 do {
715 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_MR_AN_CONTROL,
716 QCA955X_MR_AN_CONTROL_PHY_RESET |
717 QCA955X_MR_AN_CONTROL_AN_ENABLE);
718 udelay(200);
719 ag71xx_bit_clear(gmac_base + QCA955X_GMAC_REG_MR_AN_CONTROL,
720 QCA955X_MR_AN_CONTROL_PHY_RESET);
721 mdelay(300);
722 sgmii_status = __raw_readl(gmac_base + QCA955X_GMAC_REG_SGMII_DEBUG) &
723 QCA955X_SGMII_DEBUG_TX_STATE_MASK;
724
725 if (tries++ >= 20) {
726 pr_err("ag71xx: max retries for SGMII fixup exceeded\n");
727 break;
728 }
729 } while (!(sgmii_status == 0xf || sgmii_status == 0x10));
730
731 sgmii_out:
732 iounmap(gmac_base);
733 err_iomap:
734 of_node_put(np_dev);
735 out:
736 of_node_put(np);
737 }
738
739 static void ag71xx_mux_select_sgmii_qca956x(struct device_node *np)
740 {
741 struct device_node *np_dev;
742 void __iomem *gmac_base;
743 u32 t;
744
745 np = of_get_child_by_name(np, "gmac-config");
746 if (!np)
747 return;
748
749 np_dev = of_parse_phandle(np, "device", 0);
750 if (!np_dev)
751 goto out;
752
753 gmac_base = of_iomap(np_dev, 0);
754 if (!gmac_base) {
755 pr_err("%pOF: can't map GMAC registers\n", np_dev);
756 goto err_iomap;
757 }
758
759 t = __raw_readl(gmac_base + QCA956X_GMAC_REG_ETH_CFG);
760 t |= QCA956X_ETH_CFG_GE0_SGMII;
761 __raw_writel(t, gmac_base + QCA956X_GMAC_REG_ETH_CFG);
762
763 iounmap(gmac_base);
764 err_iomap:
765 of_node_put(np_dev);
766 out:
767 of_node_put(np);
768 }
769
770 static void ath79_mii_ctrl_set_if(struct ag71xx *ag, unsigned int mii_if)
771 {
772 u32 t;
773
774 t = __raw_readl(ag->mii_base);
775 t &= ~(AR71XX_MII_CTRL_IF_MASK);
776 t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
777 __raw_writel(t, ag->mii_base);
778 }
779
780 static void ath79_mii0_ctrl_set_if(struct ag71xx *ag)
781 {
782 unsigned int mii_if;
783
784 switch (ag->phy_if_mode) {
785 case PHY_INTERFACE_MODE_MII:
786 mii_if = AR71XX_MII0_CTRL_IF_MII;
787 break;
788 case PHY_INTERFACE_MODE_GMII:
789 mii_if = AR71XX_MII0_CTRL_IF_GMII;
790 break;
791 case PHY_INTERFACE_MODE_RGMII:
792 case PHY_INTERFACE_MODE_RGMII_ID:
793 case PHY_INTERFACE_MODE_RGMII_RXID:
794 case PHY_INTERFACE_MODE_RGMII_TXID:
795 mii_if = AR71XX_MII0_CTRL_IF_RGMII;
796 break;
797 case PHY_INTERFACE_MODE_RMII:
798 mii_if = AR71XX_MII0_CTRL_IF_RMII;
799 break;
800 default:
801 WARN(1, "Impossible PHY mode defined.\n");
802 return;
803 }
804
805 ath79_mii_ctrl_set_if(ag, mii_if);
806 }
807
808 static void ath79_mii1_ctrl_set_if(struct ag71xx *ag)
809 {
810 unsigned int mii_if;
811
812 switch (ag->phy_if_mode) {
813 case PHY_INTERFACE_MODE_RMII:
814 mii_if = AR71XX_MII1_CTRL_IF_RMII;
815 break;
816 case PHY_INTERFACE_MODE_RGMII:
817 case PHY_INTERFACE_MODE_RGMII_ID:
818 case PHY_INTERFACE_MODE_RGMII_RXID:
819 case PHY_INTERFACE_MODE_RGMII_TXID:
820 mii_if = AR71XX_MII1_CTRL_IF_RGMII;
821 break;
822 default:
823 WARN(1, "Impossible PHY mode defined.\n");
824 return;
825 }
826
827 ath79_mii_ctrl_set_if(ag, mii_if);
828 }
829
830 static void ath79_mii_ctrl_set_speed(struct ag71xx *ag)
831 {
832 unsigned int mii_speed;
833 u32 t;
834
835 if (!ag->mii_base)
836 return;
837
838 switch (ag->speed) {
839 case SPEED_10:
840 mii_speed = AR71XX_MII_CTRL_SPEED_10;
841 break;
842 case SPEED_100:
843 mii_speed = AR71XX_MII_CTRL_SPEED_100;
844 break;
845 case SPEED_1000:
846 mii_speed = AR71XX_MII_CTRL_SPEED_1000;
847 break;
848 default:
849 BUG();
850 }
851
852 t = __raw_readl(ag->mii_base);
853 t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
854 t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
855 __raw_writel(t, ag->mii_base);
856 }
857
858 static void
859 __ag71xx_link_adjust(struct ag71xx *ag, bool update)
860 {
861 struct device_node *np = ag->pdev->dev.of_node;
862 u32 cfg2;
863 u32 ifctl;
864 u32 fifo5;
865
866 if (!ag->link && update) {
867 ag71xx_hw_stop(ag);
868 netif_carrier_off(ag->dev);
869 if (netif_msg_link(ag))
870 pr_info("%s: link down\n", ag->dev->name);
871 return;
872 }
873
874 if (!of_device_is_compatible(np, "qca,ar9130-eth") &&
875 !of_device_is_compatible(np, "qca,ar7100-eth"))
876 ag71xx_fast_reset(ag);
877
878 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
879 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
880 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
881
882 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
883 ifctl &= ~(MAC_IFCTL_SPEED);
884
885 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
886 fifo5 &= ~FIFO_CFG5_BM;
887
888 switch (ag->speed) {
889 case SPEED_1000:
890 cfg2 |= MAC_CFG2_IF_1000;
891 fifo5 |= FIFO_CFG5_BM;
892 break;
893 case SPEED_100:
894 cfg2 |= MAC_CFG2_IF_10_100;
895 ifctl |= MAC_IFCTL_SPEED;
896 break;
897 case SPEED_10:
898 cfg2 |= MAC_CFG2_IF_10_100;
899 break;
900 default:
901 BUG();
902 return;
903 }
904
905 if (ag->tx_ring.desc_split) {
906 ag->fifodata[2] &= 0xffff;
907 ag->fifodata[2] |= ((2048 - ag->tx_ring.desc_split) / 4) << 16;
908 }
909
910 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, ag->fifodata[2]);
911
912 if (update) {
913 if (of_device_is_compatible(np, "qca,ar7100-eth") ||
914 of_device_is_compatible(np, "qca,ar9130-eth")) {
915 ath79_set_pll(ag);
916 ath79_mii_ctrl_set_speed(ag);
917 } else if (of_device_is_compatible(np, "qca,ar7242-eth") ||
918 of_device_is_compatible(np, "qca,ar9340-eth") ||
919 of_device_is_compatible(np, "qca,qca9550-eth") ||
920 of_device_is_compatible(np, "qca,qca9560-eth")) {
921 ath79_set_pllval(ag);
922 if (of_property_read_bool(np, "qca955x-sgmii-fixup"))
923 ag71xx_sgmii_init_qca955x(np);
924 }
925 }
926
927 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
928 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
929 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
930
931 if (of_device_is_compatible(np, "qca,qca9530-eth") ||
932 of_device_is_compatible(np, "qca,qca9560-eth")) {
933 /*
934 * The rx ring buffer can stall on small packets on QCA953x and
935 * QCA956x. Disabling the inline checksum engine fixes the stall.
936 * The wr, rr functions cannot be used since this hidden register
937 * is outside of the normal ag71xx register block.
938 */
939 void __iomem *dam = ioremap_nocache(0xb90001bc, 0x4);
940 if (dam) {
941 __raw_writel(__raw_readl(dam) & ~BIT(27), dam);
942 (void)__raw_readl(dam);
943 iounmap(dam);
944 }
945 }
946
947 ag71xx_hw_start(ag);
948
949 netif_carrier_on(ag->dev);
950 if (update && netif_msg_link(ag))
951 pr_info("%s: link up (%sMbps/%s duplex)\n",
952 ag->dev->name,
953 ag71xx_speed_str(ag),
954 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
955
956 ag71xx_dump_regs(ag);
957 }
958
959 void ag71xx_link_adjust(struct ag71xx *ag)
960 {
961 __ag71xx_link_adjust(ag, true);
962 }
963
964 static int ag71xx_hw_enable(struct ag71xx *ag)
965 {
966 int ret;
967
968 ret = ag71xx_rings_init(ag);
969 if (ret)
970 return ret;
971
972 napi_enable(&ag->napi);
973 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
974 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
975 netif_start_queue(ag->dev);
976
977 return 0;
978 }
979
980 static void ag71xx_hw_disable(struct ag71xx *ag)
981 {
982 netif_stop_queue(ag->dev);
983
984 ag71xx_hw_stop(ag);
985 ag71xx_dma_reset(ag);
986
987 napi_disable(&ag->napi);
988 del_timer_sync(&ag->oom_timer);
989
990 ag71xx_rings_cleanup(ag);
991 }
992
993 static int ag71xx_open(struct net_device *dev)
994 {
995 struct ag71xx *ag = netdev_priv(dev);
996 unsigned int max_frame_len;
997 int ret;
998
999 netif_carrier_off(dev);
1000 max_frame_len = ag71xx_max_frame_len(dev->mtu);
1001 ag->rx_buf_size = SKB_DATA_ALIGN(max_frame_len + NET_SKB_PAD + NET_IP_ALIGN);
1002
1003 /* setup max frame length */
1004 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len);
1005 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
1006
1007 ret = ag71xx_hw_enable(ag);
1008 if (ret)
1009 goto err;
1010
1011 phy_start(ag->phy_dev);
1012
1013 return 0;
1014
1015 err:
1016 ag71xx_rings_cleanup(ag);
1017 return ret;
1018 }
1019
1020 static int ag71xx_stop(struct net_device *dev)
1021 {
1022 unsigned long flags;
1023 struct ag71xx *ag = netdev_priv(dev);
1024
1025 netif_carrier_off(dev);
1026 phy_stop(ag->phy_dev);
1027
1028 spin_lock_irqsave(&ag->lock, flags);
1029 if (ag->link) {
1030 ag->link = 0;
1031 ag71xx_link_adjust(ag);
1032 }
1033 spin_unlock_irqrestore(&ag->lock, flags);
1034
1035 ag71xx_hw_disable(ag);
1036
1037 return 0;
1038 }
1039
1040 static int ag71xx_fill_dma_desc(struct ag71xx_ring *ring, u32 addr, int len)
1041 {
1042 int i;
1043 struct ag71xx_desc *desc;
1044 int ring_mask = BIT(ring->order) - 1;
1045 int ndesc = 0;
1046 int split = ring->desc_split;
1047
1048 if (!split)
1049 split = len;
1050
1051 while (len > 0) {
1052 unsigned int cur_len = len;
1053
1054 i = (ring->curr + ndesc) & ring_mask;
1055 desc = ag71xx_ring_desc(ring, i);
1056
1057 if (!ag71xx_desc_empty(desc))
1058 return -1;
1059
1060 if (cur_len > split) {
1061 cur_len = split;
1062
1063 /*
1064 * TX will hang if DMA transfers <= 4 bytes,
1065 * make sure next segment is more than 4 bytes long.
1066 */
1067 if (len <= split + 4)
1068 cur_len -= 4;
1069 }
1070
1071 desc->data = addr;
1072 addr += cur_len;
1073 len -= cur_len;
1074
1075 if (len > 0)
1076 cur_len |= DESC_MORE;
1077
1078 /* prevent early tx attempt of this descriptor */
1079 if (!ndesc)
1080 cur_len |= DESC_EMPTY;
1081
1082 desc->ctrl = cur_len;
1083 ndesc++;
1084 }
1085
1086 return ndesc;
1087 }
1088
1089 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
1090 struct net_device *dev)
1091 {
1092 struct ag71xx *ag = netdev_priv(dev);
1093 struct ag71xx_ring *ring = &ag->tx_ring;
1094 int ring_mask = BIT(ring->order) - 1;
1095 int ring_size = BIT(ring->order);
1096 struct ag71xx_desc *desc;
1097 dma_addr_t dma_addr;
1098 int i, n, ring_min;
1099
1100 if (skb->len <= 4) {
1101 DBG("%s: packet len is too small\n", ag->dev->name);
1102 goto err_drop;
1103 }
1104
1105 dma_addr = dma_map_single(&ag->pdev->dev, skb->data, skb->len,
1106 DMA_TO_DEVICE);
1107
1108 i = ring->curr & ring_mask;
1109 desc = ag71xx_ring_desc(ring, i);
1110
1111 /* setup descriptor fields */
1112 n = ag71xx_fill_dma_desc(ring, (u32) dma_addr, skb->len & ag->desc_pktlen_mask);
1113 if (n < 0)
1114 goto err_drop_unmap;
1115
1116 i = (ring->curr + n - 1) & ring_mask;
1117 ring->buf[i].len = skb->len;
1118 ring->buf[i].skb = skb;
1119
1120 netdev_sent_queue(dev, skb->len);
1121
1122 skb_tx_timestamp(skb);
1123
1124 desc->ctrl &= ~DESC_EMPTY;
1125 ring->curr += n;
1126
1127 /* flush descriptor */
1128 wmb();
1129
1130 ring_min = 2;
1131 if (ring->desc_split)
1132 ring_min *= AG71XX_TX_RING_DS_PER_PKT;
1133
1134 if (ring->curr - ring->dirty >= ring_size - ring_min) {
1135 DBG("%s: tx queue full\n", dev->name);
1136 netif_stop_queue(dev);
1137 }
1138
1139 DBG("%s: packet injected into TX queue\n", ag->dev->name);
1140
1141 /* enable TX engine */
1142 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
1143
1144 return NETDEV_TX_OK;
1145
1146 err_drop_unmap:
1147 dma_unmap_single(&ag->pdev->dev, dma_addr, skb->len, DMA_TO_DEVICE);
1148
1149 err_drop:
1150 dev->stats.tx_dropped++;
1151
1152 dev_kfree_skb(skb);
1153 return NETDEV_TX_OK;
1154 }
1155
1156 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1157 {
1158 struct ag71xx *ag = netdev_priv(dev);
1159
1160
1161 switch (cmd) {
1162 case SIOCSIFHWADDR:
1163 if (copy_from_user
1164 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
1165 return -EFAULT;
1166 return 0;
1167
1168 case SIOCGIFHWADDR:
1169 if (copy_to_user
1170 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
1171 return -EFAULT;
1172 return 0;
1173
1174 case SIOCGMIIPHY:
1175 case SIOCGMIIREG:
1176 case SIOCSMIIREG:
1177 if (ag->phy_dev == NULL)
1178 break;
1179
1180 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
1181
1182 default:
1183 break;
1184 }
1185
1186 return -EOPNOTSUPP;
1187 }
1188
1189 static void ag71xx_oom_timer_handler(struct timer_list *t)
1190 {
1191 struct ag71xx *ag = from_timer(ag, t, oom_timer);
1192
1193 napi_schedule(&ag->napi);
1194 }
1195
1196 static void ag71xx_tx_timeout(struct net_device *dev)
1197 {
1198 struct ag71xx *ag = netdev_priv(dev);
1199
1200 if (netif_msg_tx_err(ag))
1201 pr_info("%s: tx timeout\n", ag->dev->name);
1202
1203 schedule_delayed_work(&ag->restart_work, 1);
1204 }
1205
1206 static void ag71xx_restart_work_func(struct work_struct *work)
1207 {
1208 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work.work);
1209
1210 rtnl_lock();
1211 ag71xx_hw_disable(ag);
1212 ag71xx_hw_enable(ag);
1213 if (ag->link)
1214 __ag71xx_link_adjust(ag, false);
1215 rtnl_unlock();
1216 }
1217
1218 static bool ag71xx_check_dma_stuck(struct ag71xx *ag)
1219 {
1220 unsigned long timestamp;
1221 u32 rx_sm, tx_sm, rx_fd;
1222
1223 timestamp = netdev_get_tx_queue(ag->dev, 0)->trans_start;
1224 if (likely(time_before(jiffies, timestamp + HZ/10)))
1225 return false;
1226
1227 if (!netif_carrier_ok(ag->dev))
1228 return false;
1229
1230 rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
1231 if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
1232 return true;
1233
1234 tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
1235 rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
1236 if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
1237 ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
1238 return true;
1239
1240 return false;
1241 }
1242
1243 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush)
1244 {
1245 struct ag71xx_ring *ring = &ag->tx_ring;
1246 bool dma_stuck = false;
1247 int ring_mask = BIT(ring->order) - 1;
1248 int ring_size = BIT(ring->order);
1249 int sent = 0;
1250 int bytes_compl = 0;
1251 int n = 0;
1252
1253 DBG("%s: processing TX ring\n", ag->dev->name);
1254
1255 while (ring->dirty + n != ring->curr) {
1256 unsigned int i = (ring->dirty + n) & ring_mask;
1257 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
1258 struct sk_buff *skb = ring->buf[i].skb;
1259
1260 if (!flush && !ag71xx_desc_empty(desc)) {
1261 if (ag->tx_hang_workaround &&
1262 ag71xx_check_dma_stuck(ag)) {
1263 schedule_delayed_work(&ag->restart_work, HZ / 2);
1264 dma_stuck = true;
1265 }
1266 break;
1267 }
1268
1269 if (flush)
1270 desc->ctrl |= DESC_EMPTY;
1271
1272 n++;
1273 if (!skb)
1274 continue;
1275
1276 dev_kfree_skb_any(skb);
1277 ring->buf[i].skb = NULL;
1278
1279 bytes_compl += ring->buf[i].len;
1280
1281 sent++;
1282 ring->dirty += n;
1283
1284 while (n > 0) {
1285 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
1286 n--;
1287 }
1288 }
1289
1290 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
1291
1292 if (!sent)
1293 return 0;
1294
1295 ag->dev->stats.tx_bytes += bytes_compl;
1296 ag->dev->stats.tx_packets += sent;
1297
1298 netdev_completed_queue(ag->dev, sent, bytes_compl);
1299 if ((ring->curr - ring->dirty) < (ring_size * 3) / 4)
1300 netif_wake_queue(ag->dev);
1301
1302 if (!dma_stuck)
1303 cancel_delayed_work(&ag->restart_work);
1304
1305 return sent;
1306 }
1307
1308 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
1309 {
1310 struct net_device *dev = ag->dev;
1311 struct ag71xx_ring *ring = &ag->rx_ring;
1312 unsigned int pktlen_mask = ag->desc_pktlen_mask;
1313 unsigned int offset = ag->rx_buf_offset;
1314 int ring_mask = BIT(ring->order) - 1;
1315 int ring_size = BIT(ring->order);
1316 struct list_head rx_list;
1317 struct sk_buff *next;
1318 struct sk_buff *skb;
1319 int done = 0;
1320
1321 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
1322 dev->name, limit, ring->curr, ring->dirty);
1323 INIT_LIST_HEAD(&rx_list);
1324
1325 while (done < limit) {
1326 unsigned int i = ring->curr & ring_mask;
1327 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
1328 int pktlen;
1329 int err = 0;
1330
1331 if (ag71xx_desc_empty(desc))
1332 break;
1333
1334 if ((ring->dirty + ring_size) == ring->curr) {
1335 ag71xx_assert(0);
1336 break;
1337 }
1338
1339 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
1340
1341 pktlen = desc->ctrl & pktlen_mask;
1342 pktlen -= ETH_FCS_LEN;
1343
1344 dma_unmap_single(&ag->pdev->dev, ring->buf[i].dma_addr,
1345 ag->rx_buf_size, DMA_FROM_DEVICE);
1346
1347 dev->stats.rx_packets++;
1348 dev->stats.rx_bytes += pktlen;
1349
1350 skb = build_skb(ring->buf[i].rx_buf, ag71xx_buffer_size(ag));
1351 if (!skb) {
1352 skb_free_frag(ring->buf[i].rx_buf);
1353 goto next;
1354 }
1355
1356 skb_reserve(skb, offset);
1357 skb_put(skb, pktlen);
1358
1359 if (err) {
1360 dev->stats.rx_dropped++;
1361 kfree_skb(skb);
1362 } else {
1363 skb->dev = dev;
1364 skb->ip_summed = CHECKSUM_NONE;
1365 list_add_tail(&skb->list, &rx_list);
1366 }
1367
1368 next:
1369 ring->buf[i].rx_buf = NULL;
1370 done++;
1371
1372 ring->curr++;
1373 }
1374
1375 ag71xx_ring_rx_refill(ag);
1376
1377 list_for_each_entry_safe(skb, next, &rx_list, list)
1378 skb->protocol = eth_type_trans(skb, dev);
1379 netif_receive_skb_list(&rx_list);
1380
1381 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
1382 dev->name, ring->curr, ring->dirty, done);
1383
1384 return done;
1385 }
1386
1387 static int ag71xx_poll(struct napi_struct *napi, int limit)
1388 {
1389 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
1390 struct net_device *dev = ag->dev;
1391 struct ag71xx_ring *rx_ring = &ag->rx_ring;
1392 int rx_ring_size = BIT(rx_ring->order);
1393 unsigned long flags;
1394 u32 status;
1395 int tx_done;
1396 int rx_done;
1397
1398 tx_done = ag71xx_tx_packets(ag, false);
1399
1400 DBG("%s: processing RX ring\n", dev->name);
1401 rx_done = ag71xx_rx_packets(ag, limit);
1402
1403 ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
1404
1405 if (rx_ring->buf[rx_ring->dirty % rx_ring_size].rx_buf == NULL)
1406 goto oom;
1407
1408 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
1409 if (unlikely(status & RX_STATUS_OF)) {
1410 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
1411 dev->stats.rx_fifo_errors++;
1412
1413 /* restart RX */
1414 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
1415 }
1416
1417 if (rx_done < limit) {
1418 if (status & RX_STATUS_PR)
1419 goto more;
1420
1421 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
1422 if (status & TX_STATUS_PS)
1423 goto more;
1424
1425 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
1426 dev->name, rx_done, tx_done, limit);
1427
1428 napi_complete(napi);
1429
1430 /* enable interrupts */
1431 spin_lock_irqsave(&ag->lock, flags);
1432 ag71xx_int_enable(ag, AG71XX_INT_POLL);
1433 spin_unlock_irqrestore(&ag->lock, flags);
1434 return rx_done;
1435 }
1436
1437 more:
1438 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
1439 dev->name, rx_done, tx_done, limit);
1440 return limit;
1441
1442 oom:
1443 if (netif_msg_rx_err(ag))
1444 pr_info("%s: out of memory\n", dev->name);
1445
1446 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
1447 napi_complete(napi);
1448 return 0;
1449 }
1450
1451 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
1452 {
1453 struct net_device *dev = dev_id;
1454 struct ag71xx *ag = netdev_priv(dev);
1455 u32 status;
1456
1457 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
1458 ag71xx_dump_intr(ag, "raw", status);
1459
1460 if (unlikely(!status))
1461 return IRQ_NONE;
1462
1463 if (unlikely(status & AG71XX_INT_ERR)) {
1464 if (status & AG71XX_INT_TX_BE) {
1465 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
1466 dev_err(&dev->dev, "TX BUS error\n");
1467 }
1468 if (status & AG71XX_INT_RX_BE) {
1469 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
1470 dev_err(&dev->dev, "RX BUS error\n");
1471 }
1472 }
1473
1474 if (likely(status & AG71XX_INT_POLL)) {
1475 ag71xx_int_disable(ag, AG71XX_INT_POLL);
1476 DBG("%s: enable polling mode\n", dev->name);
1477 napi_schedule(&ag->napi);
1478 }
1479
1480 ag71xx_debugfs_update_int_stats(ag, status);
1481
1482 return IRQ_HANDLED;
1483 }
1484
1485 static int ag71xx_change_mtu(struct net_device *dev, int new_mtu)
1486 {
1487 struct ag71xx *ag = netdev_priv(dev);
1488
1489 dev->mtu = new_mtu;
1490 ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
1491 ag71xx_max_frame_len(dev->mtu));
1492
1493 return 0;
1494 }
1495
1496 static const struct net_device_ops ag71xx_netdev_ops = {
1497 .ndo_open = ag71xx_open,
1498 .ndo_stop = ag71xx_stop,
1499 .ndo_start_xmit = ag71xx_hard_start_xmit,
1500 .ndo_do_ioctl = ag71xx_do_ioctl,
1501 .ndo_tx_timeout = ag71xx_tx_timeout,
1502 .ndo_change_mtu = ag71xx_change_mtu,
1503 .ndo_set_mac_address = eth_mac_addr,
1504 .ndo_validate_addr = eth_validate_addr,
1505 };
1506
1507 static int ag71xx_probe(struct platform_device *pdev)
1508 {
1509 struct device_node *np = pdev->dev.of_node;
1510 struct net_device *dev;
1511 struct resource *res;
1512 struct ag71xx *ag;
1513 const void *mac_addr;
1514 u32 max_frame_len;
1515 int tx_size, err;
1516
1517 if (!np)
1518 return -ENODEV;
1519
1520 dev = devm_alloc_etherdev(&pdev->dev, sizeof(*ag));
1521 if (!dev)
1522 return -ENOMEM;
1523
1524 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1525 if (!res)
1526 return -EINVAL;
1527
1528 if (of_property_read_bool(np, "qca956x-serdes-fixup")) {
1529 ag71xx_sgmii_serdes_init_qca956x(np);
1530 ag71xx_sgmii_init_qca955x(np);
1531 }
1532
1533 err = ag71xx_setup_gmac(np);
1534 if (err)
1535 return err;
1536
1537 SET_NETDEV_DEV(dev, &pdev->dev);
1538
1539 ag = netdev_priv(dev);
1540 ag->pdev = pdev;
1541 ag->dev = dev;
1542 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1543 AG71XX_DEFAULT_MSG_ENABLE);
1544 spin_lock_init(&ag->lock);
1545
1546 ag->mac_reset = devm_reset_control_get_exclusive(&pdev->dev, "mac");
1547 if (IS_ERR(ag->mac_reset)) {
1548 dev_err(&pdev->dev, "missing mac reset\n");
1549 return PTR_ERR(ag->mac_reset);
1550 }
1551
1552 ag->mdio_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "mdio");
1553
1554 if (of_property_read_u32_array(np, "fifo-data", ag->fifodata, 3)) {
1555 if (of_device_is_compatible(np, "qca,ar9130-eth") ||
1556 of_device_is_compatible(np, "qca,ar7100-eth")) {
1557 ag->fifodata[0] = 0x0fff0000;
1558 ag->fifodata[1] = 0x00001fff;
1559 } else {
1560 ag->fifodata[0] = 0x0010ffff;
1561 ag->fifodata[1] = 0x015500aa;
1562 ag->fifodata[2] = 0x01f00140;
1563 }
1564 if (of_device_is_compatible(np, "qca,ar9130-eth"))
1565 ag->fifodata[2] = 0x00780fff;
1566 else if (of_device_is_compatible(np, "qca,ar7100-eth"))
1567 ag->fifodata[2] = 0x008001ff;
1568 }
1569
1570 if (of_property_read_u32_array(np, "pll-data", ag->plldata, 3))
1571 dev_dbg(&pdev->dev, "failed to read pll-data property\n");
1572
1573 if (of_property_read_u32_array(np, "pll-reg", ag->pllreg, 3))
1574 dev_dbg(&pdev->dev, "failed to read pll-reg property\n");
1575
1576 ag->pllregmap = syscon_regmap_lookup_by_phandle(np, "pll-handle");
1577 if (IS_ERR(ag->pllregmap)) {
1578 dev_dbg(&pdev->dev, "failed to read pll-handle property\n");
1579 ag->pllregmap = NULL;
1580 }
1581
1582 ag->mac_base = devm_ioremap_nocache(&pdev->dev, res->start,
1583 res->end - res->start + 1);
1584 if (!ag->mac_base)
1585 return -ENOMEM;
1586
1587 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1588 if (res) {
1589 ag->mii_base = devm_ioremap_nocache(&pdev->dev, res->start,
1590 res->end - res->start + 1);
1591 if (!ag->mii_base)
1592 return -ENOMEM;
1593 }
1594
1595 dev->irq = platform_get_irq(pdev, 0);
1596 err = devm_request_irq(&pdev->dev, dev->irq, ag71xx_interrupt,
1597 0x0, dev_name(&pdev->dev), dev);
1598 if (err) {
1599 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1600 return err;
1601 }
1602
1603 dev->netdev_ops = &ag71xx_netdev_ops;
1604 dev->ethtool_ops = &ag71xx_ethtool_ops;
1605
1606 INIT_DELAYED_WORK(&ag->restart_work, ag71xx_restart_work_func);
1607
1608 timer_setup(&ag->oom_timer, ag71xx_oom_timer_handler, 0);
1609
1610 tx_size = AG71XX_TX_RING_SIZE_DEFAULT;
1611 ag->rx_ring.order = ag71xx_ring_size_order(AG71XX_RX_RING_SIZE_DEFAULT);
1612
1613 if (of_device_is_compatible(np, "qca,ar9340-eth") ||
1614 of_device_is_compatible(np, "qca,qca9530-eth") ||
1615 of_device_is_compatible(np, "qca,qca9550-eth") ||
1616 of_device_is_compatible(np, "qca,qca9560-eth"))
1617 ag->desc_pktlen_mask = SZ_16K - 1;
1618 else
1619 ag->desc_pktlen_mask = SZ_4K - 1;
1620
1621 if (ag->desc_pktlen_mask == SZ_16K - 1 &&
1622 !of_device_is_compatible(np, "qca,qca9550-eth") &&
1623 !of_device_is_compatible(np, "qca,qca9560-eth"))
1624 max_frame_len = ag->desc_pktlen_mask;
1625 else
1626 max_frame_len = 1540;
1627
1628 dev->min_mtu = 68;
1629 dev->max_mtu = max_frame_len - ag71xx_max_frame_len(0);
1630
1631 if (of_device_is_compatible(np, "qca,ar7240-eth") ||
1632 of_device_is_compatible(np, "qca,ar7241-eth") ||
1633 of_device_is_compatible(np, "qca,ar7242-eth") ||
1634 of_device_is_compatible(np, "qca,ar9330-eth") ||
1635 of_device_is_compatible(np, "qca,ar9340-eth") ||
1636 of_device_is_compatible(np, "qca,qca9530-eth") ||
1637 of_device_is_compatible(np, "qca,qca9550-eth") ||
1638 of_device_is_compatible(np, "qca,qca9560-eth"))
1639 ag->tx_hang_workaround = 1;
1640
1641 ag->rx_buf_offset = NET_SKB_PAD;
1642 if (!of_device_is_compatible(np, "qca,ar7100-eth") &&
1643 !of_device_is_compatible(np, "qca,ar9130-eth"))
1644 ag->rx_buf_offset += NET_IP_ALIGN;
1645
1646 if (of_device_is_compatible(np, "qca,ar7100-eth")) {
1647 ag->tx_ring.desc_split = AG71XX_TX_RING_SPLIT;
1648 tx_size *= AG71XX_TX_RING_DS_PER_PKT;
1649 }
1650 ag->tx_ring.order = ag71xx_ring_size_order(tx_size);
1651
1652 ag->stop_desc = dmam_alloc_coherent(&pdev->dev,
1653 sizeof(struct ag71xx_desc),
1654 &ag->stop_desc_dma, GFP_KERNEL);
1655 if (!ag->stop_desc)
1656 return -ENOMEM;
1657
1658 ag->stop_desc->data = 0;
1659 ag->stop_desc->ctrl = 0;
1660 ag->stop_desc->next = (u32) ag->stop_desc_dma;
1661
1662 mac_addr = of_get_mac_address(np);
1663 if (IS_ERR_OR_NULL(mac_addr) || !is_valid_ether_addr(mac_addr)) {
1664 dev_err(&pdev->dev, "invalid MAC address, using random address\n");
1665 eth_random_addr(dev->dev_addr);
1666 } else {
1667 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
1668 }
1669
1670 ag->phy_if_mode = of_get_phy_mode(np);
1671 if (ag->phy_if_mode < 0) {
1672 dev_err(&pdev->dev, "missing phy-mode property in DT\n");
1673 return ag->phy_if_mode;
1674 }
1675
1676 if (of_device_is_compatible(np, "qca,qca9560-eth") &&
1677 ag->phy_if_mode == PHY_INTERFACE_MODE_SGMII)
1678 ag71xx_mux_select_sgmii_qca956x(np);
1679
1680 if (of_property_read_u32(np, "qca,mac-idx", &ag->mac_idx))
1681 ag->mac_idx = -1;
1682 if (ag->mii_base)
1683 switch (ag->mac_idx) {
1684 case 0:
1685 ath79_mii0_ctrl_set_if(ag);
1686 break;
1687 case 1:
1688 ath79_mii1_ctrl_set_if(ag);
1689 break;
1690 default:
1691 break;
1692 }
1693
1694 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1695
1696 ag71xx_dump_regs(ag);
1697
1698 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, 0);
1699
1700 ag71xx_hw_init(ag);
1701
1702 ag71xx_dump_regs(ag);
1703
1704 /*
1705 * populate current node to register mdio-bus as a subdevice.
1706 * the mdio bus works independently on ar7241 and later chips
1707 * and we need to load mdio1 before gmac0, which can be done
1708 * by adding a "simple-mfd" compatible to gmac node. The
1709 * following code checks OF_POPULATED_BUS flag before populating
1710 * to avoid duplicated population.
1711 */
1712 if (!of_node_check_flag(np, OF_POPULATED_BUS)) {
1713 err = of_platform_populate(np, NULL, NULL, &pdev->dev);
1714 if (err)
1715 return err;
1716 }
1717
1718 err = ag71xx_phy_connect(ag);
1719 if (err)
1720 return err;
1721
1722 err = ag71xx_debugfs_init(ag);
1723 if (err)
1724 goto err_phy_disconnect;
1725
1726 platform_set_drvdata(pdev, dev);
1727
1728 err = register_netdev(dev);
1729 if (err) {
1730 dev_err(&pdev->dev, "unable to register net device\n");
1731 platform_set_drvdata(pdev, NULL);
1732 ag71xx_debugfs_exit(ag);
1733 goto err_phy_disconnect;
1734 }
1735
1736 pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d, mode: %s\n",
1737 dev->name, (unsigned long) ag->mac_base, dev->irq,
1738 phy_modes(ag->phy_if_mode));
1739
1740 return 0;
1741
1742 err_phy_disconnect:
1743 ag71xx_phy_disconnect(ag);
1744 return err;
1745 }
1746
1747 static int ag71xx_remove(struct platform_device *pdev)
1748 {
1749 struct net_device *dev = platform_get_drvdata(pdev);
1750 struct ag71xx *ag;
1751
1752 if (!dev)
1753 return 0;
1754
1755 ag = netdev_priv(dev);
1756 ag71xx_debugfs_exit(ag);
1757 ag71xx_phy_disconnect(ag);
1758 unregister_netdev(dev);
1759 platform_set_drvdata(pdev, NULL);
1760 return 0;
1761 }
1762
1763 static const struct of_device_id ag71xx_match[] = {
1764 { .compatible = "qca,ar7100-eth" },
1765 { .compatible = "qca,ar7240-eth" },
1766 { .compatible = "qca,ar7241-eth" },
1767 { .compatible = "qca,ar7242-eth" },
1768 { .compatible = "qca,ar9130-eth" },
1769 { .compatible = "qca,ar9330-eth" },
1770 { .compatible = "qca,ar9340-eth" },
1771 { .compatible = "qca,qca9530-eth" },
1772 { .compatible = "qca,qca9550-eth" },
1773 { .compatible = "qca,qca9560-eth" },
1774 {}
1775 };
1776
1777 static struct platform_driver ag71xx_driver = {
1778 .probe = ag71xx_probe,
1779 .remove = ag71xx_remove,
1780 .driver = {
1781 .name = AG71XX_DRV_NAME,
1782 .of_match_table = ag71xx_match,
1783 }
1784 };
1785
1786 static int __init ag71xx_module_init(void)
1787 {
1788 int ret;
1789
1790 ret = ag71xx_debugfs_root_init();
1791 if (ret)
1792 goto err_out;
1793
1794 ret = platform_driver_register(&ag71xx_driver);
1795 if (ret)
1796 goto err_debugfs_exit;
1797
1798 return 0;
1799
1800 err_debugfs_exit:
1801 ag71xx_debugfs_root_exit();
1802 err_out:
1803 return ret;
1804 }
1805
1806 static void __exit ag71xx_module_exit(void)
1807 {
1808 platform_driver_unregister(&ag71xx_driver);
1809 ag71xx_debugfs_root_exit();
1810 }
1811
1812 module_init(ag71xx_module_init);
1813 module_exit(ag71xx_module_exit);
1814
1815 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1816 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1817 MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
1818 MODULE_LICENSE("GPL v2");
1819 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
OpenWrt Source Repository