projects / openwrt / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
ath79: force SGMII SerDes mode to MAC operation
[openwrt/openwrt.git] / target / linux / ath79 / files / drivers / net / ethernet / atheros / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include <linux/sizes.h>
15 #include <linux/of_net.h>
16 #include <linux/of_address.h>
17 #include <linux/of_platform.h>
18 #include "ag71xx.h"
19
20 #define AG71XX_DEFAULT_MSG_ENABLE \
21 (NETIF_MSG_DRV \
22 | NETIF_MSG_PROBE \
23 | NETIF_MSG_LINK \
24 | NETIF_MSG_TIMER \
25 | NETIF_MSG_IFDOWN \
26 | NETIF_MSG_IFUP \
27 | NETIF_MSG_RX_ERR \
28 | NETIF_MSG_TX_ERR)
29
30 static int ag71xx_msg_level = -1;
31
32 module_param_named(msg_level, ag71xx_msg_level, int, 0);
33 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
34
35 #define ETH_SWITCH_HEADER_LEN 2
36
37 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush);
38
39 static inline unsigned int ag71xx_max_frame_len(unsigned int mtu)
40 {
41 return ETH_SWITCH_HEADER_LEN + ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN;
42 }
43
44 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
45 {
46 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
47 ag->dev->name,
48 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
49 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
50 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
51
52 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
53 ag->dev->name,
54 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
55 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
56 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
57 }
58
59 static void ag71xx_dump_regs(struct ag71xx *ag)
60 {
61 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
62 ag->dev->name,
63 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
64 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
65 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
66 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
67 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
68 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
69 ag->dev->name,
70 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
71 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
72 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
73 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
74 ag->dev->name,
75 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
76 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
77 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
78 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
79 ag->dev->name,
80 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
81 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
82 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
83 }
84
85 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
86 {
87 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
88 ag->dev->name, label, intr,
89 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
90 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
91 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
92 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
93 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
94 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
95 }
96
97 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
98 {
99 struct ag71xx_ring *ring = &ag->tx_ring;
100 struct net_device *dev = ag->dev;
101 int ring_mask = BIT(ring->order) - 1;
102 u32 bytes_compl = 0, pkts_compl = 0;
103
104 while (ring->curr != ring->dirty) {
105 struct ag71xx_desc *desc;
106 u32 i = ring->dirty & ring_mask;
107
108 desc = ag71xx_ring_desc(ring, i);
109 if (!ag71xx_desc_empty(desc)) {
110 desc->ctrl = 0;
111 dev->stats.tx_errors++;
112 }
113
114 if (ring->buf[i].skb) {
115 bytes_compl += ring->buf[i].len;
116 pkts_compl++;
117 dev_kfree_skb_any(ring->buf[i].skb);
118 }
119 ring->buf[i].skb = NULL;
120 ring->dirty++;
121 }
122
123 /* flush descriptors */
124 wmb();
125
126 netdev_completed_queue(dev, pkts_compl, bytes_compl);
127 }
128
129 static void ag71xx_ring_tx_init(struct ag71xx *ag)
130 {
131 struct ag71xx_ring *ring = &ag->tx_ring;
132 int ring_size = BIT(ring->order);
133 int ring_mask = BIT(ring->order) - 1;
134 int i;
135
136 for (i = 0; i < ring_size; i++) {
137 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
138
139 desc->next = (u32) (ring->descs_dma +
140 AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
141
142 desc->ctrl = DESC_EMPTY;
143 ring->buf[i].skb = NULL;
144 }
145
146 /* flush descriptors */
147 wmb();
148
149 ring->curr = 0;
150 ring->dirty = 0;
151 netdev_reset_queue(ag->dev);
152 }
153
154 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
155 {
156 struct ag71xx_ring *ring = &ag->rx_ring;
157 int ring_size = BIT(ring->order);
158 int i;
159
160 if (!ring->buf)
161 return;
162
163 for (i = 0; i < ring_size; i++)
164 if (ring->buf[i].rx_buf) {
165 dma_unmap_single(&ag->pdev->dev, ring->buf[i].dma_addr,
166 ag->rx_buf_size, DMA_FROM_DEVICE);
167 skb_free_frag(ring->buf[i].rx_buf);
168 }
169 }
170
171 static int ag71xx_buffer_size(struct ag71xx *ag)
172 {
173 return ag->rx_buf_size +
174 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
175 }
176
177 static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf,
178 int offset,
179 void *(*alloc)(unsigned int size))
180 {
181 struct ag71xx_ring *ring = &ag->rx_ring;
182 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, buf - &ring->buf[0]);
183 void *data;
184
185 data = alloc(ag71xx_buffer_size(ag));
186 if (!data)
187 return false;
188
189 buf->rx_buf = data;
190 buf->dma_addr = dma_map_single(&ag->pdev->dev, data, ag->rx_buf_size,
191 DMA_FROM_DEVICE);
192 desc->data = (u32) buf->dma_addr + offset;
193 return true;
194 }
195
196 static int ag71xx_ring_rx_init(struct ag71xx *ag)
197 {
198 struct ag71xx_ring *ring = &ag->rx_ring;
199 int ring_size = BIT(ring->order);
200 int ring_mask = BIT(ring->order) - 1;
201 unsigned int i;
202 int ret;
203
204 ret = 0;
205 for (i = 0; i < ring_size; i++) {
206 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
207
208 desc->next = (u32) (ring->descs_dma +
209 AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
210
211 DBG("ag71xx: RX desc at %p, next is %08x\n",
212 desc, desc->next);
213 }
214
215 for (i = 0; i < ring_size; i++) {
216 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
217
218 if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], ag->rx_buf_offset,
219 netdev_alloc_frag)) {
220 ret = -ENOMEM;
221 break;
222 }
223
224 desc->ctrl = DESC_EMPTY;
225 }
226
227 /* flush descriptors */
228 wmb();
229
230 ring->curr = 0;
231 ring->dirty = 0;
232
233 return ret;
234 }
235
236 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
237 {
238 struct ag71xx_ring *ring = &ag->rx_ring;
239 int ring_mask = BIT(ring->order) - 1;
240 unsigned int count;
241 int offset = ag->rx_buf_offset;
242
243 count = 0;
244 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
245 struct ag71xx_desc *desc;
246 unsigned int i;
247
248 i = ring->dirty & ring_mask;
249 desc = ag71xx_ring_desc(ring, i);
250
251 if (!ring->buf[i].rx_buf &&
252 !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset,
253 napi_alloc_frag))
254 break;
255
256 desc->ctrl = DESC_EMPTY;
257 count++;
258 }
259
260 /* flush descriptors */
261 wmb();
262
263 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
264
265 return count;
266 }
267
268 static int ag71xx_rings_init(struct ag71xx *ag)
269 {
270 struct ag71xx_ring *tx = &ag->tx_ring;
271 struct ag71xx_ring *rx = &ag->rx_ring;
272 int ring_size = BIT(tx->order) + BIT(rx->order);
273 int tx_size = BIT(tx->order);
274
275 tx->buf = kzalloc(ring_size * sizeof(*tx->buf), GFP_KERNEL);
276 if (!tx->buf)
277 return -ENOMEM;
278
279 tx->descs_cpu = dma_alloc_coherent(&ag->pdev->dev, ring_size * AG71XX_DESC_SIZE,
280 &tx->descs_dma, GFP_KERNEL);
281 if (!tx->descs_cpu) {
282 kfree(tx->buf);
283 tx->buf = NULL;
284 return -ENOMEM;
285 }
286
287 rx->buf = &tx->buf[tx_size];
288 rx->descs_cpu = ((void *)tx->descs_cpu) + tx_size * AG71XX_DESC_SIZE;
289 rx->descs_dma = tx->descs_dma + tx_size * AG71XX_DESC_SIZE;
290
291 ag71xx_ring_tx_init(ag);
292 return ag71xx_ring_rx_init(ag);
293 }
294
295 static void ag71xx_rings_free(struct ag71xx *ag)
296 {
297 struct ag71xx_ring *tx = &ag->tx_ring;
298 struct ag71xx_ring *rx = &ag->rx_ring;
299 int ring_size = BIT(tx->order) + BIT(rx->order);
300
301 if (tx->descs_cpu)
302 dma_free_coherent(&ag->pdev->dev, ring_size * AG71XX_DESC_SIZE,
303 tx->descs_cpu, tx->descs_dma);
304
305 kfree(tx->buf);
306
307 tx->descs_cpu = NULL;
308 rx->descs_cpu = NULL;
309 tx->buf = NULL;
310 rx->buf = NULL;
311 }
312
313 static void ag71xx_rings_cleanup(struct ag71xx *ag)
314 {
315 ag71xx_ring_rx_clean(ag);
316 ag71xx_ring_tx_clean(ag);
317 ag71xx_rings_free(ag);
318
319 netdev_reset_queue(ag->dev);
320 }
321
322 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
323 {
324 switch (ag->speed) {
325 case SPEED_1000:
326 return "1000";
327 case SPEED_100:
328 return "100";
329 case SPEED_10:
330 return "10";
331 }
332
333 return "?";
334 }
335
336 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
337 {
338 u32 t;
339
340 t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
341 | (((u32) mac[3]) << 8) | ((u32) mac[2]);
342
343 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
344
345 t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
346 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
347 }
348
349 static void ag71xx_dma_reset(struct ag71xx *ag)
350 {
351 u32 val;
352 int i;
353
354 ag71xx_dump_dma_regs(ag);
355
356 /* stop RX and TX */
357 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
358 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
359
360 /*
361 * give the hardware some time to really stop all rx/tx activity
362 * clearing the descriptors too early causes random memory corruption
363 */
364 mdelay(1);
365
366 /* clear descriptor addresses */
367 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
368 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
369
370 /* clear pending RX/TX interrupts */
371 for (i = 0; i < 256; i++) {
372 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
373 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
374 }
375
376 /* clear pending errors */
377 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
378 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
379
380 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
381 if (val)
382 pr_alert("%s: unable to clear DMA Rx status: %08x\n",
383 ag->dev->name, val);
384
385 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
386
387 /* mask out reserved bits */
388 val &= ~0xff000000;
389
390 if (val)
391 pr_alert("%s: unable to clear DMA Tx status: %08x\n",
392 ag->dev->name, val);
393
394 ag71xx_dump_dma_regs(ag);
395 }
396
397 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
398 MAC_CFG1_SRX | MAC_CFG1_STX)
399
400 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
401
402 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
403 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
404 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
405 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
406 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
407 FIFO_CFG4_VT)
408
409 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
410 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
411 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
412 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
413 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
414 FIFO_CFG5_17 | FIFO_CFG5_SF)
415
416 static void ag71xx_hw_stop(struct ag71xx *ag)
417 {
418 /* disable all interrupts and stop the rx/tx engine */
419 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
420 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
421 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
422 }
423
424 static void ag71xx_hw_setup(struct ag71xx *ag)
425 {
426 struct device_node *np = ag->pdev->dev.of_node;
427 u32 init = MAC_CFG1_INIT;
428
429 /* setup MAC configuration registers */
430 if (of_property_read_bool(np, "flow-control"))
431 init |= MAC_CFG1_TFC | MAC_CFG1_RFC;
432 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, init);
433
434 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
435 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
436
437 /* setup max frame length to zero */
438 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0);
439
440 /* setup FIFO configuration registers */
441 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
442 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, ag->fifodata[0]);
443 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, ag->fifodata[1]);
444 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
445 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
446 }
447
448 static void ag71xx_hw_init(struct ag71xx *ag)
449 {
450 ag71xx_hw_stop(ag);
451
452 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
453 udelay(20);
454
455 reset_control_assert(ag->mac_reset);
456 if (ag->mdio_reset)
457 reset_control_assert(ag->mdio_reset);
458 msleep(100);
459 reset_control_deassert(ag->mac_reset);
460 if (ag->mdio_reset)
461 reset_control_deassert(ag->mdio_reset);
462 msleep(200);
463
464 ag71xx_hw_setup(ag);
465
466 ag71xx_dma_reset(ag);
467 }
468
469 static void ag71xx_fast_reset(struct ag71xx *ag)
470 {
471 struct net_device *dev = ag->dev;
472 u32 rx_ds;
473 u32 mii_reg;
474
475 ag71xx_hw_stop(ag);
476 wmb();
477
478 mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
479 rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
480
481 ag71xx_tx_packets(ag, true);
482
483 reset_control_assert(ag->mac_reset);
484 udelay(10);
485 reset_control_deassert(ag->mac_reset);
486 udelay(10);
487
488 ag71xx_dma_reset(ag);
489 ag71xx_hw_setup(ag);
490 ag->tx_ring.curr = 0;
491 ag->tx_ring.dirty = 0;
492 netdev_reset_queue(ag->dev);
493
494 /* setup max frame length */
495 ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
496 ag71xx_max_frame_len(ag->dev->mtu));
497
498 ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
499 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
500 ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
501
502 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
503 }
504
505 static void ag71xx_hw_start(struct ag71xx *ag)
506 {
507 /* start RX engine */
508 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
509
510 /* enable interrupts */
511 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
512
513 netif_wake_queue(ag->dev);
514 }
515
516 static void ath79_set_pllval(struct ag71xx *ag)
517 {
518 u32 pll_reg = ag->pllreg[1];
519 u32 pll_val;
520
521 if (!ag->pllregmap)
522 return;
523
524 switch (ag->speed) {
525 case SPEED_10:
526 pll_val = ag->plldata[2];
527 break;
528 case SPEED_100:
529 pll_val = ag->plldata[1];
530 break;
531 case SPEED_1000:
532 pll_val = ag->plldata[0];
533 break;
534 default:
535 BUG();
536 }
537
538 if (pll_val)
539 regmap_write(ag->pllregmap, pll_reg, pll_val);
540 }
541
542 static void ath79_set_pll(struct ag71xx *ag)
543 {
544 u32 pll_cfg = ag->pllreg[0];
545 u32 pll_shift = ag->pllreg[2];
546
547 if (!ag->pllregmap)
548 return;
549
550 regmap_update_bits(ag->pllregmap, pll_cfg, 3 << pll_shift, 2 << pll_shift);
551 udelay(100);
552
553 ath79_set_pllval(ag);
554
555 regmap_update_bits(ag->pllregmap, pll_cfg, 3 << pll_shift, 3 << pll_shift);
556 udelay(100);
557
558 regmap_update_bits(ag->pllregmap, pll_cfg, 3 << pll_shift, 0);
559 udelay(100);
560 }
561
562 static void ag71xx_bit_set(void __iomem *reg, u32 bit)
563 {
564 u32 val;
565
566 val = __raw_readl(reg) | bit;
567 __raw_writel(val, reg);
568 __raw_readl(reg);
569 }
570
571 static void ag71xx_bit_clear(void __iomem *reg, u32 bit)
572 {
573 u32 val;
574
575 val = __raw_readl(reg) & ~bit;
576 __raw_writel(val, reg);
577 __raw_readl(reg);
578 }
579
580 static void ag71xx_sgmii_serdes_init_qca956x(struct device_node *np)
581 {
582 struct device_node *np_dev;
583 void __iomem *gmac_base;
584 u32 serdes_cal;
585 u32 t;
586
587 np = of_get_child_by_name(np, "gmac-config");
588 if (!np)
589 return;
590
591 if (of_property_read_u32(np, "serdes-cal", &serdes_cal))
592 /* By default, use middle value for resistor calibration */
593 serdes_cal = 0x7;
594
595 np_dev = of_parse_phandle(np, "device", 0);
596 if (!np_dev)
597 goto out;
598
599 gmac_base = of_iomap(np_dev, 0);
600 if (!gmac_base) {
601 pr_err("%pOF: can't map GMAC registers\n", np_dev);
602 goto err_iomap;
603 }
604
605 t = __raw_readl(gmac_base + QCA956X_GMAC_REG_SGMII_CONFIG);
606 t &= ~(QCA956X_SGMII_CONFIG_MODE_CTRL_MASK << QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT);
607 t |= QCA956X_SGMII_CONFIG_MODE_CTRL_SGMII_MAC;
608 __raw_writel(t, gmac_base + QCA956X_GMAC_REG_SGMII_CONFIG);
609
610 pr_debug("%pOF: fixup SERDES calibration to value %i\n",
611 np_dev, serdes_cal);
612 t = __raw_readl(gmac_base + QCA956X_GMAC_REG_SGMII_SERDES);
613 t &= ~(QCA956X_SGMII_SERDES_RES_CALIBRATION_MASK
614 << QCA956X_SGMII_SERDES_RES_CALIBRATION_SHIFT);
615 t |= (serdes_cal & QCA956X_SGMII_SERDES_RES_CALIBRATION_MASK)
616 << QCA956X_SGMII_SERDES_RES_CALIBRATION_SHIFT;
617 __raw_writel(t, gmac_base + QCA956X_GMAC_REG_SGMII_SERDES);
618
619 ath79_pll_wr(QCA956X_PLL_ETH_SGMII_SERDES_REG,
620 QCA956X_PLL_ETH_SGMII_SERDES_LOCK_DETECT
621 | QCA956X_PLL_ETH_SGMII_SERDES_EN_PLL);
622
623 t = __raw_readl(gmac_base + QCA956X_GMAC_REG_SGMII_SERDES);
624
625 /* missing in QCA u-boot code, clear before setting */
626 t &= ~(QCA956X_SGMII_SERDES_CDR_BW_MASK
627 << QCA956X_SGMII_SERDES_CDR_BW_SHIFT |
628 QCA956X_SGMII_SERDES_TX_DR_CTRL_MASK
629 << QCA956X_SGMII_SERDES_TX_DR_CTRL_SHIFT |
630 QCA956X_SGMII_SERDES_VCO_REG_MASK
631 << QCA956X_SGMII_SERDES_VCO_REG_SHIFT);
632
633 t |= (3 << QCA956X_SGMII_SERDES_CDR_BW_SHIFT) |
634 (1 << QCA956X_SGMII_SERDES_TX_DR_CTRL_SHIFT) |
635 QCA956X_SGMII_SERDES_PLL_BW |
636 QCA956X_SGMII_SERDES_EN_SIGNAL_DETECT |
637 QCA956X_SGMII_SERDES_FIBER_SDO |
638 (3 << QCA956X_SGMII_SERDES_VCO_REG_SHIFT);
639
640 __raw_writel(t, gmac_base + QCA956X_GMAC_REG_SGMII_SERDES);
641
642 ath79_device_reset_clear(QCA956X_RESET_SGMII_ANALOG);
643 ath79_device_reset_clear(QCA956X_RESET_SGMII);
644
645 while (!(__raw_readl(gmac_base + QCA956X_GMAC_REG_SGMII_SERDES)
646 & QCA956X_SGMII_SERDES_LOCK_DETECT_STATUS))
647 ;
648
649 iounmap(gmac_base);
650 err_iomap:
651 of_node_put(np_dev);
652 out:
653 of_node_put(np);
654 }
655
656 static void ag71xx_sgmii_init_qca955x(struct device_node *np)
657 {
658 struct device_node *np_dev;
659 void __iomem *gmac_base;
660 u32 mr_an_status;
661 u32 sgmii_status;
662 u8 tries = 0;
663 int err = 0;
664
665 np = of_get_child_by_name(np, "gmac-config");
666 if (!np)
667 return;
668
669 np_dev = of_parse_phandle(np, "device", 0);
670 if (!np_dev)
671 goto out;
672
673 gmac_base = of_iomap(np_dev, 0);
674 if (!gmac_base) {
675 pr_err("%pOF: can't map GMAC registers\n", np_dev);
676 err = -ENOMEM;
677 goto err_iomap;
678 }
679
680 mr_an_status = __raw_readl(gmac_base + QCA955X_GMAC_REG_MR_AN_STATUS);
681 if (!(mr_an_status & QCA955X_MR_AN_STATUS_AN_ABILITY))
682 goto sgmii_out;
683
684 /* SGMII reset sequence */
685 __raw_writel(QCA955X_SGMII_RESET_RX_CLK_N_RESET,
686 gmac_base + QCA955X_GMAC_REG_SGMII_RESET);
687 __raw_readl(gmac_base + QCA955X_GMAC_REG_SGMII_RESET);
688 udelay(10);
689
690 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
691 QCA955X_SGMII_RESET_HW_RX_125M_N);
692 udelay(10);
693
694 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
695 QCA955X_SGMII_RESET_RX_125M_N);
696 udelay(10);
697
698 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
699 QCA955X_SGMII_RESET_TX_125M_N);
700 udelay(10);
701
702 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
703 QCA955X_SGMII_RESET_RX_CLK_N);
704 udelay(10);
705
706 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
707 QCA955X_SGMII_RESET_TX_CLK_N);
708 udelay(10);
709
710 /*
711 * The following is what QCA has to say about what happens here:
712 *
713 * Across resets SGMII link status goes to weird state.
714 * If SGMII_DEBUG register reads other than 0x1f or 0x10,
715 * we are for sure in a bad state.
716 *
717 * Issue a PHY reset in MR_AN_CONTROL to keep going.
718 */
719 do {
720 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_MR_AN_CONTROL,
721 QCA955X_MR_AN_CONTROL_PHY_RESET |
722 QCA955X_MR_AN_CONTROL_AN_ENABLE);
723 udelay(200);
724 ag71xx_bit_clear(gmac_base + QCA955X_GMAC_REG_MR_AN_CONTROL,
725 QCA955X_MR_AN_CONTROL_PHY_RESET);
726 mdelay(300);
727 sgmii_status = __raw_readl(gmac_base + QCA955X_GMAC_REG_SGMII_DEBUG) &
728 QCA955X_SGMII_DEBUG_TX_STATE_MASK;
729
730 if (tries++ >= 20) {
731 pr_err("ag71xx: max retries for SGMII fixup exceeded\n");
732 break;
733 }
734 } while (!(sgmii_status == 0xf || sgmii_status == 0x10));
735
736 sgmii_out:
737 iounmap(gmac_base);
738 err_iomap:
739 of_node_put(np_dev);
740 out:
741 of_node_put(np);
742 }
743
744 static void ag71xx_mux_select_sgmii_qca956x(struct device_node *np)
745 {
746 struct device_node *np_dev;
747 void __iomem *gmac_base;
748 u32 t;
749
750 np = of_get_child_by_name(np, "gmac-config");
751 if (!np)
752 return;
753
754 np_dev = of_parse_phandle(np, "device", 0);
755 if (!np_dev)
756 goto out;
757
758 gmac_base = of_iomap(np_dev, 0);
759 if (!gmac_base) {
760 pr_err("%pOF: can't map GMAC registers\n", np_dev);
761 goto err_iomap;
762 }
763
764 t = __raw_readl(gmac_base + QCA956X_GMAC_REG_ETH_CFG);
765 t |= QCA956X_ETH_CFG_GE0_SGMII;
766 __raw_writel(t, gmac_base + QCA956X_GMAC_REG_ETH_CFG);
767
768 iounmap(gmac_base);
769 err_iomap:
770 of_node_put(np_dev);
771 out:
772 of_node_put(np);
773 }
774
775 static void ath79_mii_ctrl_set_if(struct ag71xx *ag, unsigned int mii_if)
776 {
777 u32 t;
778
779 t = __raw_readl(ag->mii_base);
780 t &= ~(AR71XX_MII_CTRL_IF_MASK);
781 t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
782 __raw_writel(t, ag->mii_base);
783 }
784
785 static void ath79_mii0_ctrl_set_if(struct ag71xx *ag)
786 {
787 unsigned int mii_if;
788
789 switch (ag->phy_if_mode) {
790 case PHY_INTERFACE_MODE_MII:
791 mii_if = AR71XX_MII0_CTRL_IF_MII;
792 break;
793 case PHY_INTERFACE_MODE_GMII:
794 mii_if = AR71XX_MII0_CTRL_IF_GMII;
795 break;
796 case PHY_INTERFACE_MODE_RGMII:
797 case PHY_INTERFACE_MODE_RGMII_ID:
798 case PHY_INTERFACE_MODE_RGMII_RXID:
799 case PHY_INTERFACE_MODE_RGMII_TXID:
800 mii_if = AR71XX_MII0_CTRL_IF_RGMII;
801 break;
802 case PHY_INTERFACE_MODE_RMII:
803 mii_if = AR71XX_MII0_CTRL_IF_RMII;
804 break;
805 default:
806 WARN(1, "Impossible PHY mode defined.\n");
807 return;
808 }
809
810 ath79_mii_ctrl_set_if(ag, mii_if);
811 }
812
813 static void ath79_mii1_ctrl_set_if(struct ag71xx *ag)
814 {
815 unsigned int mii_if;
816
817 switch (ag->phy_if_mode) {
818 case PHY_INTERFACE_MODE_RMII:
819 mii_if = AR71XX_MII1_CTRL_IF_RMII;
820 break;
821 case PHY_INTERFACE_MODE_RGMII:
822 case PHY_INTERFACE_MODE_RGMII_ID:
823 case PHY_INTERFACE_MODE_RGMII_RXID:
824 case PHY_INTERFACE_MODE_RGMII_TXID:
825 mii_if = AR71XX_MII1_CTRL_IF_RGMII;
826 break;
827 default:
828 WARN(1, "Impossible PHY mode defined.\n");
829 return;
830 }
831
832 ath79_mii_ctrl_set_if(ag, mii_if);
833 }
834
835 static void ath79_mii_ctrl_set_speed(struct ag71xx *ag)
836 {
837 unsigned int mii_speed;
838 u32 t;
839
840 if (!ag->mii_base)
841 return;
842
843 switch (ag->speed) {
844 case SPEED_10:
845 mii_speed = AR71XX_MII_CTRL_SPEED_10;
846 break;
847 case SPEED_100:
848 mii_speed = AR71XX_MII_CTRL_SPEED_100;
849 break;
850 case SPEED_1000:
851 mii_speed = AR71XX_MII_CTRL_SPEED_1000;
852 break;
853 default:
854 BUG();
855 }
856
857 t = __raw_readl(ag->mii_base);
858 t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
859 t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
860 __raw_writel(t, ag->mii_base);
861 }
862
863 static void
864 __ag71xx_link_adjust(struct ag71xx *ag, bool update)
865 {
866 struct device_node *np = ag->pdev->dev.of_node;
867 u32 cfg2;
868 u32 ifctl;
869 u32 fifo5;
870
871 if (!ag->link && update) {
872 ag71xx_hw_stop(ag);
873 netif_carrier_off(ag->dev);
874 if (netif_msg_link(ag))
875 pr_info("%s: link down\n", ag->dev->name);
876 return;
877 }
878
879 if (!of_device_is_compatible(np, "qca,ar9130-eth") &&
880 !of_device_is_compatible(np, "qca,ar7100-eth"))
881 ag71xx_fast_reset(ag);
882
883 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
884 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
885 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
886
887 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
888 ifctl &= ~(MAC_IFCTL_SPEED);
889
890 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
891 fifo5 &= ~FIFO_CFG5_BM;
892
893 switch (ag->speed) {
894 case SPEED_1000:
895 cfg2 |= MAC_CFG2_IF_1000;
896 fifo5 |= FIFO_CFG5_BM;
897 break;
898 case SPEED_100:
899 cfg2 |= MAC_CFG2_IF_10_100;
900 ifctl |= MAC_IFCTL_SPEED;
901 break;
902 case SPEED_10:
903 cfg2 |= MAC_CFG2_IF_10_100;
904 break;
905 default:
906 BUG();
907 return;
908 }
909
910 if (ag->tx_ring.desc_split) {
911 ag->fifodata[2] &= 0xffff;
912 ag->fifodata[2] |= ((2048 - ag->tx_ring.desc_split) / 4) << 16;
913 }
914
915 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, ag->fifodata[2]);
916
917 if (update) {
918 if (of_device_is_compatible(np, "qca,ar7100-eth") ||
919 of_device_is_compatible(np, "qca,ar9130-eth")) {
920 ath79_set_pll(ag);
921 ath79_mii_ctrl_set_speed(ag);
922 } else if (of_device_is_compatible(np, "qca,ar7242-eth") ||
923 of_device_is_compatible(np, "qca,ar9340-eth") ||
924 of_device_is_compatible(np, "qca,qca9550-eth") ||
925 of_device_is_compatible(np, "qca,qca9560-eth")) {
926 ath79_set_pllval(ag);
927 if (of_property_read_bool(np, "qca955x-sgmii-fixup"))
928 ag71xx_sgmii_init_qca955x(np);
929 }
930 }
931
932 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
933 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
934 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
935
936 if (of_device_is_compatible(np, "qca,qca9530-eth") ||
937 of_device_is_compatible(np, "qca,qca9560-eth")) {
938 /*
939 * The rx ring buffer can stall on small packets on QCA953x and
940 * QCA956x. Disabling the inline checksum engine fixes the stall.
941 * The wr, rr functions cannot be used since this hidden register
942 * is outside of the normal ag71xx register block.
943 */
944 void __iomem *dam = ioremap_nocache(0xb90001bc, 0x4);
945 if (dam) {
946 __raw_writel(__raw_readl(dam) & ~BIT(27), dam);
947 (void)__raw_readl(dam);
948 iounmap(dam);
949 }
950 }
951
952 ag71xx_hw_start(ag);
953
954 netif_carrier_on(ag->dev);
955 if (update && netif_msg_link(ag))
956 pr_info("%s: link up (%sMbps/%s duplex)\n",
957 ag->dev->name,
958 ag71xx_speed_str(ag),
959 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
960
961 ag71xx_dump_regs(ag);
962 }
963
964 void ag71xx_link_adjust(struct ag71xx *ag)
965 {
966 __ag71xx_link_adjust(ag, true);
967 }
968
969 static int ag71xx_hw_enable(struct ag71xx *ag)
970 {
971 int ret;
972
973 ret = ag71xx_rings_init(ag);
974 if (ret)
975 return ret;
976
977 napi_enable(&ag->napi);
978 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
979 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
980 netif_start_queue(ag->dev);
981
982 return 0;
983 }
984
985 static void ag71xx_hw_disable(struct ag71xx *ag)
986 {
987 netif_stop_queue(ag->dev);
988
989 ag71xx_hw_stop(ag);
990 ag71xx_dma_reset(ag);
991
992 napi_disable(&ag->napi);
993 del_timer_sync(&ag->oom_timer);
994
995 ag71xx_rings_cleanup(ag);
996 }
997
998 static int ag71xx_open(struct net_device *dev)
999 {
1000 struct ag71xx *ag = netdev_priv(dev);
1001 unsigned int max_frame_len;
1002 int ret;
1003
1004 netif_carrier_off(dev);
1005 max_frame_len = ag71xx_max_frame_len(dev->mtu);
1006 ag->rx_buf_size = SKB_DATA_ALIGN(max_frame_len + NET_SKB_PAD + NET_IP_ALIGN);
1007
1008 /* setup max frame length */
1009 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len);
1010 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
1011
1012 ret = ag71xx_hw_enable(ag);
1013 if (ret)
1014 goto err;
1015
1016 phy_start(ag->phy_dev);
1017
1018 return 0;
1019
1020 err:
1021 ag71xx_rings_cleanup(ag);
1022 return ret;
1023 }
1024
1025 static int ag71xx_stop(struct net_device *dev)
1026 {
1027 unsigned long flags;
1028 struct ag71xx *ag = netdev_priv(dev);
1029
1030 netif_carrier_off(dev);
1031 phy_stop(ag->phy_dev);
1032
1033 spin_lock_irqsave(&ag->lock, flags);
1034 if (ag->link) {
1035 ag->link = 0;
1036 ag71xx_link_adjust(ag);
1037 }
1038 spin_unlock_irqrestore(&ag->lock, flags);
1039
1040 ag71xx_hw_disable(ag);
1041
1042 return 0;
1043 }
1044
1045 static int ag71xx_fill_dma_desc(struct ag71xx_ring *ring, u32 addr, int len)
1046 {
1047 int i;
1048 struct ag71xx_desc *desc;
1049 int ring_mask = BIT(ring->order) - 1;
1050 int ndesc = 0;
1051 int split = ring->desc_split;
1052
1053 if (!split)
1054 split = len;
1055
1056 while (len > 0) {
1057 unsigned int cur_len = len;
1058
1059 i = (ring->curr + ndesc) & ring_mask;
1060 desc = ag71xx_ring_desc(ring, i);
1061
1062 if (!ag71xx_desc_empty(desc))
1063 return -1;
1064
1065 if (cur_len > split) {
1066 cur_len = split;
1067
1068 /*
1069 * TX will hang if DMA transfers <= 4 bytes,
1070 * make sure next segment is more than 4 bytes long.
1071 */
1072 if (len <= split + 4)
1073 cur_len -= 4;
1074 }
1075
1076 desc->data = addr;
1077 addr += cur_len;
1078 len -= cur_len;
1079
1080 if (len > 0)
1081 cur_len |= DESC_MORE;
1082
1083 /* prevent early tx attempt of this descriptor */
1084 if (!ndesc)
1085 cur_len |= DESC_EMPTY;
1086
1087 desc->ctrl = cur_len;
1088 ndesc++;
1089 }
1090
1091 return ndesc;
1092 }
1093
1094 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
1095 struct net_device *dev)
1096 {
1097 struct ag71xx *ag = netdev_priv(dev);
1098 struct ag71xx_ring *ring = &ag->tx_ring;
1099 int ring_mask = BIT(ring->order) - 1;
1100 int ring_size = BIT(ring->order);
1101 struct ag71xx_desc *desc;
1102 dma_addr_t dma_addr;
1103 int i, n, ring_min;
1104
1105 if (skb->len <= 4) {
1106 DBG("%s: packet len is too small\n", ag->dev->name);
1107 goto err_drop;
1108 }
1109
1110 dma_addr = dma_map_single(&ag->pdev->dev, skb->data, skb->len,
1111 DMA_TO_DEVICE);
1112
1113 i = ring->curr & ring_mask;
1114 desc = ag71xx_ring_desc(ring, i);
1115
1116 /* setup descriptor fields */
1117 n = ag71xx_fill_dma_desc(ring, (u32) dma_addr, skb->len & ag->desc_pktlen_mask);
1118 if (n < 0)
1119 goto err_drop_unmap;
1120
1121 i = (ring->curr + n - 1) & ring_mask;
1122 ring->buf[i].len = skb->len;
1123 ring->buf[i].skb = skb;
1124
1125 netdev_sent_queue(dev, skb->len);
1126
1127 skb_tx_timestamp(skb);
1128
1129 desc->ctrl &= ~DESC_EMPTY;
1130 ring->curr += n;
1131
1132 /* flush descriptor */
1133 wmb();
1134
1135 ring_min = 2;
1136 if (ring->desc_split)
1137 ring_min *= AG71XX_TX_RING_DS_PER_PKT;
1138
1139 if (ring->curr - ring->dirty >= ring_size - ring_min) {
1140 DBG("%s: tx queue full\n", dev->name);
1141 netif_stop_queue(dev);
1142 }
1143
1144 DBG("%s: packet injected into TX queue\n", ag->dev->name);
1145
1146 /* enable TX engine */
1147 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
1148
1149 return NETDEV_TX_OK;
1150
1151 err_drop_unmap:
1152 dma_unmap_single(&ag->pdev->dev, dma_addr, skb->len, DMA_TO_DEVICE);
1153
1154 err_drop:
1155 dev->stats.tx_dropped++;
1156
1157 dev_kfree_skb(skb);
1158 return NETDEV_TX_OK;
1159 }
1160
1161 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1162 {
1163 struct ag71xx *ag = netdev_priv(dev);
1164
1165
1166 switch (cmd) {
1167 case SIOCSIFHWADDR:
1168 if (copy_from_user
1169 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
1170 return -EFAULT;
1171 return 0;
1172
1173 case SIOCGIFHWADDR:
1174 if (copy_to_user
1175 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
1176 return -EFAULT;
1177 return 0;
1178
1179 case SIOCGMIIPHY:
1180 case SIOCGMIIREG:
1181 case SIOCSMIIREG:
1182 if (ag->phy_dev == NULL)
1183 break;
1184
1185 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
1186
1187 default:
1188 break;
1189 }
1190
1191 return -EOPNOTSUPP;
1192 }
1193
1194 static void ag71xx_oom_timer_handler(struct timer_list *t)
1195 {
1196 struct ag71xx *ag = from_timer(ag, t, oom_timer);
1197
1198 napi_schedule(&ag->napi);
1199 }
1200
1201 static void ag71xx_tx_timeout(struct net_device *dev)
1202 {
1203 struct ag71xx *ag = netdev_priv(dev);
1204
1205 if (netif_msg_tx_err(ag))
1206 pr_info("%s: tx timeout\n", ag->dev->name);
1207
1208 schedule_delayed_work(&ag->restart_work, 1);
1209 }
1210
1211 static void ag71xx_restart_work_func(struct work_struct *work)
1212 {
1213 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work.work);
1214
1215 rtnl_lock();
1216 ag71xx_hw_disable(ag);
1217 ag71xx_hw_enable(ag);
1218 if (ag->link)
1219 __ag71xx_link_adjust(ag, false);
1220 rtnl_unlock();
1221 }
1222
1223 static bool ag71xx_check_dma_stuck(struct ag71xx *ag)
1224 {
1225 unsigned long timestamp;
1226 u32 rx_sm, tx_sm, rx_fd;
1227
1228 timestamp = netdev_get_tx_queue(ag->dev, 0)->trans_start;
1229 if (likely(time_before(jiffies, timestamp + HZ/10)))
1230 return false;
1231
1232 if (!netif_carrier_ok(ag->dev))
1233 return false;
1234
1235 rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
1236 if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
1237 return true;
1238
1239 tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
1240 rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
1241 if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
1242 ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
1243 return true;
1244
1245 return false;
1246 }
1247
1248 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush)
1249 {
1250 struct ag71xx_ring *ring = &ag->tx_ring;
1251 bool dma_stuck = false;
1252 int ring_mask = BIT(ring->order) - 1;
1253 int ring_size = BIT(ring->order);
1254 int sent = 0;
1255 int bytes_compl = 0;
1256 int n = 0;
1257
1258 DBG("%s: processing TX ring\n", ag->dev->name);
1259
1260 while (ring->dirty + n != ring->curr) {
1261 unsigned int i = (ring->dirty + n) & ring_mask;
1262 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
1263 struct sk_buff *skb = ring->buf[i].skb;
1264
1265 if (!flush && !ag71xx_desc_empty(desc)) {
1266 if (ag->tx_hang_workaround &&
1267 ag71xx_check_dma_stuck(ag)) {
1268 schedule_delayed_work(&ag->restart_work, HZ / 2);
1269 dma_stuck = true;
1270 }
1271 break;
1272 }
1273
1274 if (flush)
1275 desc->ctrl |= DESC_EMPTY;
1276
1277 n++;
1278 if (!skb)
1279 continue;
1280
1281 dev_kfree_skb_any(skb);
1282 ring->buf[i].skb = NULL;
1283
1284 bytes_compl += ring->buf[i].len;
1285
1286 sent++;
1287 ring->dirty += n;
1288
1289 while (n > 0) {
1290 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
1291 n--;
1292 }
1293 }
1294
1295 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
1296
1297 if (!sent)
1298 return 0;
1299
1300 ag->dev->stats.tx_bytes += bytes_compl;
1301 ag->dev->stats.tx_packets += sent;
1302
1303 netdev_completed_queue(ag->dev, sent, bytes_compl);
1304 if ((ring->curr - ring->dirty) < (ring_size * 3) / 4)
1305 netif_wake_queue(ag->dev);
1306
1307 if (!dma_stuck)
1308 cancel_delayed_work(&ag->restart_work);
1309
1310 return sent;
1311 }
1312
1313 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
1314 {
1315 struct net_device *dev = ag->dev;
1316 struct ag71xx_ring *ring = &ag->rx_ring;
1317 unsigned int pktlen_mask = ag->desc_pktlen_mask;
1318 unsigned int offset = ag->rx_buf_offset;
1319 int ring_mask = BIT(ring->order) - 1;
1320 int ring_size = BIT(ring->order);
1321 struct list_head rx_list;
1322 struct sk_buff *next;
1323 struct sk_buff *skb;
1324 int done = 0;
1325
1326 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
1327 dev->name, limit, ring->curr, ring->dirty);
1328 INIT_LIST_HEAD(&rx_list);
1329
1330 while (done < limit) {
1331 unsigned int i = ring->curr & ring_mask;
1332 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
1333 int pktlen;
1334 int err = 0;
1335
1336 if (ag71xx_desc_empty(desc))
1337 break;
1338
1339 if ((ring->dirty + ring_size) == ring->curr) {
1340 ag71xx_assert(0);
1341 break;
1342 }
1343
1344 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
1345
1346 pktlen = desc->ctrl & pktlen_mask;
1347 pktlen -= ETH_FCS_LEN;
1348
1349 dma_unmap_single(&ag->pdev->dev, ring->buf[i].dma_addr,
1350 ag->rx_buf_size, DMA_FROM_DEVICE);
1351
1352 dev->stats.rx_packets++;
1353 dev->stats.rx_bytes += pktlen;
1354
1355 skb = build_skb(ring->buf[i].rx_buf, ag71xx_buffer_size(ag));
1356 if (!skb) {
1357 skb_free_frag(ring->buf[i].rx_buf);
1358 goto next;
1359 }
1360
1361 skb_reserve(skb, offset);
1362 skb_put(skb, pktlen);
1363
1364 if (err) {
1365 dev->stats.rx_dropped++;
1366 kfree_skb(skb);
1367 } else {
1368 skb->dev = dev;
1369 skb->ip_summed = CHECKSUM_NONE;
1370 list_add_tail(&skb->list, &rx_list);
1371 }
1372
1373 next:
1374 ring->buf[i].rx_buf = NULL;
1375 done++;
1376
1377 ring->curr++;
1378 }
1379
1380 ag71xx_ring_rx_refill(ag);
1381
1382 list_for_each_entry_safe(skb, next, &rx_list, list)
1383 skb->protocol = eth_type_trans(skb, dev);
1384 netif_receive_skb_list(&rx_list);
1385
1386 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
1387 dev->name, ring->curr, ring->dirty, done);
1388
1389 return done;
1390 }
1391
1392 static int ag71xx_poll(struct napi_struct *napi, int limit)
1393 {
1394 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
1395 struct net_device *dev = ag->dev;
1396 struct ag71xx_ring *rx_ring = &ag->rx_ring;
1397 int rx_ring_size = BIT(rx_ring->order);
1398 unsigned long flags;
1399 u32 status;
1400 int tx_done;
1401 int rx_done;
1402
1403 tx_done = ag71xx_tx_packets(ag, false);
1404
1405 DBG("%s: processing RX ring\n", dev->name);
1406 rx_done = ag71xx_rx_packets(ag, limit);
1407
1408 ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
1409
1410 if (rx_ring->buf[rx_ring->dirty % rx_ring_size].rx_buf == NULL)
1411 goto oom;
1412
1413 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
1414 if (unlikely(status & RX_STATUS_OF)) {
1415 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
1416 dev->stats.rx_fifo_errors++;
1417
1418 /* restart RX */
1419 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
1420 }
1421
1422 if (rx_done < limit) {
1423 if (status & RX_STATUS_PR)
1424 goto more;
1425
1426 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
1427 if (status & TX_STATUS_PS)
1428 goto more;
1429
1430 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
1431 dev->name, rx_done, tx_done, limit);
1432
1433 napi_complete(napi);
1434
1435 /* enable interrupts */
1436 spin_lock_irqsave(&ag->lock, flags);
1437 ag71xx_int_enable(ag, AG71XX_INT_POLL);
1438 spin_unlock_irqrestore(&ag->lock, flags);
1439 return rx_done;
1440 }
1441
1442 more:
1443 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
1444 dev->name, rx_done, tx_done, limit);
1445 return limit;
1446
1447 oom:
1448 if (netif_msg_rx_err(ag))
1449 pr_info("%s: out of memory\n", dev->name);
1450
1451 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
1452 napi_complete(napi);
1453 return 0;
1454 }
1455
1456 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
1457 {
1458 struct net_device *dev = dev_id;
1459 struct ag71xx *ag = netdev_priv(dev);
1460 u32 status;
1461
1462 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
1463 ag71xx_dump_intr(ag, "raw", status);
1464
1465 if (unlikely(!status))
1466 return IRQ_NONE;
1467
1468 if (unlikely(status & AG71XX_INT_ERR)) {
1469 if (status & AG71XX_INT_TX_BE) {
1470 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
1471 dev_err(&dev->dev, "TX BUS error\n");
1472 }
1473 if (status & AG71XX_INT_RX_BE) {
1474 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
1475 dev_err(&dev->dev, "RX BUS error\n");
1476 }
1477 }
1478
1479 if (likely(status & AG71XX_INT_POLL)) {
1480 ag71xx_int_disable(ag, AG71XX_INT_POLL);
1481 DBG("%s: enable polling mode\n", dev->name);
1482 napi_schedule(&ag->napi);
1483 }
1484
1485 ag71xx_debugfs_update_int_stats(ag, status);
1486
1487 return IRQ_HANDLED;
1488 }
1489
1490 static int ag71xx_change_mtu(struct net_device *dev, int new_mtu)
1491 {
1492 struct ag71xx *ag = netdev_priv(dev);
1493
1494 dev->mtu = new_mtu;
1495 ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
1496 ag71xx_max_frame_len(dev->mtu));
1497
1498 return 0;
1499 }
1500
1501 static const struct net_device_ops ag71xx_netdev_ops = {
1502 .ndo_open = ag71xx_open,
1503 .ndo_stop = ag71xx_stop,
1504 .ndo_start_xmit = ag71xx_hard_start_xmit,
1505 .ndo_do_ioctl = ag71xx_do_ioctl,
1506 .ndo_tx_timeout = ag71xx_tx_timeout,
1507 .ndo_change_mtu = ag71xx_change_mtu,
1508 .ndo_set_mac_address = eth_mac_addr,
1509 .ndo_validate_addr = eth_validate_addr,
1510 };
1511
1512 static int ag71xx_probe(struct platform_device *pdev)
1513 {
1514 struct device_node *np = pdev->dev.of_node;
1515 struct net_device *dev;
1516 struct resource *res;
1517 struct ag71xx *ag;
1518 const void *mac_addr;
1519 u32 max_frame_len;
1520 int tx_size, err;
1521
1522 if (!np)
1523 return -ENODEV;
1524
1525 dev = devm_alloc_etherdev(&pdev->dev, sizeof(*ag));
1526 if (!dev)
1527 return -ENOMEM;
1528
1529 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1530 if (!res)
1531 return -EINVAL;
1532
1533 if (of_property_read_bool(np, "qca956x-serdes-fixup")) {
1534 ag71xx_sgmii_serdes_init_qca956x(np);
1535 ag71xx_sgmii_init_qca955x(np);
1536 }
1537
1538 err = ag71xx_setup_gmac(np);
1539 if (err)
1540 return err;
1541
1542 SET_NETDEV_DEV(dev, &pdev->dev);
1543
1544 ag = netdev_priv(dev);
1545 ag->pdev = pdev;
1546 ag->dev = dev;
1547 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1548 AG71XX_DEFAULT_MSG_ENABLE);
1549 spin_lock_init(&ag->lock);
1550
1551 ag->mac_reset = devm_reset_control_get_exclusive(&pdev->dev, "mac");
1552 if (IS_ERR(ag->mac_reset)) {
1553 dev_err(&pdev->dev, "missing mac reset\n");
1554 return PTR_ERR(ag->mac_reset);
1555 }
1556
1557 ag->mdio_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "mdio");
1558
1559 if (of_property_read_u32_array(np, "fifo-data", ag->fifodata, 3)) {
1560 if (of_device_is_compatible(np, "qca,ar9130-eth") ||
1561 of_device_is_compatible(np, "qca,ar7100-eth")) {
1562 ag->fifodata[0] = 0x0fff0000;
1563 ag->fifodata[1] = 0x00001fff;
1564 } else {
1565 ag->fifodata[0] = 0x0010ffff;
1566 ag->fifodata[1] = 0x015500aa;
1567 ag->fifodata[2] = 0x01f00140;
1568 }
1569 if (of_device_is_compatible(np, "qca,ar9130-eth"))
1570 ag->fifodata[2] = 0x00780fff;
1571 else if (of_device_is_compatible(np, "qca,ar7100-eth"))
1572 ag->fifodata[2] = 0x008001ff;
1573 }
1574
1575 if (of_property_read_u32_array(np, "pll-data", ag->plldata, 3))
1576 dev_dbg(&pdev->dev, "failed to read pll-data property\n");
1577
1578 if (of_property_read_u32_array(np, "pll-reg", ag->pllreg, 3))
1579 dev_dbg(&pdev->dev, "failed to read pll-reg property\n");
1580
1581 ag->pllregmap = syscon_regmap_lookup_by_phandle(np, "pll-handle");
1582 if (IS_ERR(ag->pllregmap)) {
1583 dev_dbg(&pdev->dev, "failed to read pll-handle property\n");
1584 ag->pllregmap = NULL;
1585 }
1586
1587 ag->mac_base = devm_ioremap_nocache(&pdev->dev, res->start,
1588 res->end - res->start + 1);
1589 if (!ag->mac_base)
1590 return -ENOMEM;
1591
1592 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1593 if (res) {
1594 ag->mii_base = devm_ioremap_nocache(&pdev->dev, res->start,
1595 res->end - res->start + 1);
1596 if (!ag->mii_base)
1597 return -ENOMEM;
1598 }
1599
1600 dev->irq = platform_get_irq(pdev, 0);
1601 err = devm_request_irq(&pdev->dev, dev->irq, ag71xx_interrupt,
1602 0x0, dev_name(&pdev->dev), dev);
1603 if (err) {
1604 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1605 return err;
1606 }
1607
1608 dev->netdev_ops = &ag71xx_netdev_ops;
1609 dev->ethtool_ops = &ag71xx_ethtool_ops;
1610
1611 INIT_DELAYED_WORK(&ag->restart_work, ag71xx_restart_work_func);
1612
1613 timer_setup(&ag->oom_timer, ag71xx_oom_timer_handler, 0);
1614
1615 tx_size = AG71XX_TX_RING_SIZE_DEFAULT;
1616 ag->rx_ring.order = ag71xx_ring_size_order(AG71XX_RX_RING_SIZE_DEFAULT);
1617
1618 if (of_device_is_compatible(np, "qca,ar9340-eth") ||
1619 of_device_is_compatible(np, "qca,qca9530-eth") ||
1620 of_device_is_compatible(np, "qca,qca9550-eth") ||
1621 of_device_is_compatible(np, "qca,qca9560-eth"))
1622 ag->desc_pktlen_mask = SZ_16K - 1;
1623 else
1624 ag->desc_pktlen_mask = SZ_4K - 1;
1625
1626 if (ag->desc_pktlen_mask == SZ_16K - 1 &&
1627 !of_device_is_compatible(np, "qca,qca9550-eth") &&
1628 !of_device_is_compatible(np, "qca,qca9560-eth"))
1629 max_frame_len = ag->desc_pktlen_mask;
1630 else
1631 max_frame_len = 1540;
1632
1633 dev->min_mtu = 68;
1634 dev->max_mtu = max_frame_len - ag71xx_max_frame_len(0);
1635
1636 if (of_device_is_compatible(np, "qca,ar7240-eth") ||
1637 of_device_is_compatible(np, "qca,ar7241-eth") ||
1638 of_device_is_compatible(np, "qca,ar7242-eth") ||
1639 of_device_is_compatible(np, "qca,ar9330-eth") ||
1640 of_device_is_compatible(np, "qca,ar9340-eth") ||
1641 of_device_is_compatible(np, "qca,qca9530-eth") ||
1642 of_device_is_compatible(np, "qca,qca9550-eth") ||
1643 of_device_is_compatible(np, "qca,qca9560-eth"))
1644 ag->tx_hang_workaround = 1;
1645
1646 ag->rx_buf_offset = NET_SKB_PAD;
1647 if (!of_device_is_compatible(np, "qca,ar7100-eth") &&
1648 !of_device_is_compatible(np, "qca,ar9130-eth"))
1649 ag->rx_buf_offset += NET_IP_ALIGN;
1650
1651 if (of_device_is_compatible(np, "qca,ar7100-eth")) {
1652 ag->tx_ring.desc_split = AG71XX_TX_RING_SPLIT;
1653 tx_size *= AG71XX_TX_RING_DS_PER_PKT;
1654 }
1655 ag->tx_ring.order = ag71xx_ring_size_order(tx_size);
1656
1657 ag->stop_desc = dmam_alloc_coherent(&pdev->dev,
1658 sizeof(struct ag71xx_desc),
1659 &ag->stop_desc_dma, GFP_KERNEL);
1660 if (!ag->stop_desc)
1661 return -ENOMEM;
1662
1663 ag->stop_desc->data = 0;
1664 ag->stop_desc->ctrl = 0;
1665 ag->stop_desc->next = (u32) ag->stop_desc_dma;
1666
1667 mac_addr = of_get_mac_address(np);
1668 if (IS_ERR_OR_NULL(mac_addr) || !is_valid_ether_addr(mac_addr)) {
1669 dev_err(&pdev->dev, "invalid MAC address, using random address\n");
1670 eth_random_addr(dev->dev_addr);
1671 } else {
1672 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
1673 }
1674
1675 ag->phy_if_mode = of_get_phy_mode(np);
1676 if (ag->phy_if_mode < 0) {
1677 dev_err(&pdev->dev, "missing phy-mode property in DT\n");
1678 return ag->phy_if_mode;
1679 }
1680
1681 if (of_device_is_compatible(np, "qca,qca9560-eth") &&
1682 ag->phy_if_mode == PHY_INTERFACE_MODE_SGMII)
1683 ag71xx_mux_select_sgmii_qca956x(np);
1684
1685 if (of_property_read_u32(np, "qca,mac-idx", &ag->mac_idx))
1686 ag->mac_idx = -1;
1687 if (ag->mii_base)
1688 switch (ag->mac_idx) {
1689 case 0:
1690 ath79_mii0_ctrl_set_if(ag);
1691 break;
1692 case 1:
1693 ath79_mii1_ctrl_set_if(ag);
1694 break;
1695 default:
1696 break;
1697 }
1698
1699 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1700
1701 ag71xx_dump_regs(ag);
1702
1703 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, 0);
1704
1705 ag71xx_hw_init(ag);
1706
1707 ag71xx_dump_regs(ag);
1708
1709 /*
1710 * populate current node to register mdio-bus as a subdevice.
1711 * the mdio bus works independently on ar7241 and later chips
1712 * and we need to load mdio1 before gmac0, which can be done
1713 * by adding a "simple-mfd" compatible to gmac node. The
1714 * following code checks OF_POPULATED_BUS flag before populating
1715 * to avoid duplicated population.
1716 */
1717 if (!of_node_check_flag(np, OF_POPULATED_BUS)) {
1718 err = of_platform_populate(np, NULL, NULL, &pdev->dev);
1719 if (err)
1720 return err;
1721 }
1722
1723 err = ag71xx_phy_connect(ag);
1724 if (err)
1725 return err;
1726
1727 err = ag71xx_debugfs_init(ag);
1728 if (err)
1729 goto err_phy_disconnect;
1730
1731 platform_set_drvdata(pdev, dev);
1732
1733 err = register_netdev(dev);
1734 if (err) {
1735 dev_err(&pdev->dev, "unable to register net device\n");
1736 platform_set_drvdata(pdev, NULL);
1737 ag71xx_debugfs_exit(ag);
1738 goto err_phy_disconnect;
1739 }
1740
1741 pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d, mode: %s\n",
1742 dev->name, (unsigned long) ag->mac_base, dev->irq,
1743 phy_modes(ag->phy_if_mode));
1744
1745 return 0;
1746
1747 err_phy_disconnect:
1748 ag71xx_phy_disconnect(ag);
1749 return err;
1750 }
1751
1752 static int ag71xx_remove(struct platform_device *pdev)
1753 {
1754 struct net_device *dev = platform_get_drvdata(pdev);
1755 struct ag71xx *ag;
1756
1757 if (!dev)
1758 return 0;
1759
1760 ag = netdev_priv(dev);
1761 ag71xx_debugfs_exit(ag);
1762 ag71xx_phy_disconnect(ag);
1763 unregister_netdev(dev);
1764 platform_set_drvdata(pdev, NULL);
1765 return 0;
1766 }
1767
1768 static const struct of_device_id ag71xx_match[] = {
1769 { .compatible = "qca,ar7100-eth" },
1770 { .compatible = "qca,ar7240-eth" },
1771 { .compatible = "qca,ar7241-eth" },
1772 { .compatible = "qca,ar7242-eth" },
1773 { .compatible = "qca,ar9130-eth" },
1774 { .compatible = "qca,ar9330-eth" },
1775 { .compatible = "qca,ar9340-eth" },
1776 { .compatible = "qca,qca9530-eth" },
1777 { .compatible = "qca,qca9550-eth" },
1778 { .compatible = "qca,qca9560-eth" },
1779 {}
1780 };
1781
1782 static struct platform_driver ag71xx_driver = {
1783 .probe = ag71xx_probe,
1784 .remove = ag71xx_remove,
1785 .driver = {
1786 .name = AG71XX_DRV_NAME,
1787 .of_match_table = ag71xx_match,
1788 }
1789 };
1790
1791 static int __init ag71xx_module_init(void)
1792 {
1793 int ret;
1794
1795 ret = ag71xx_debugfs_root_init();
1796 if (ret)
1797 goto err_out;
1798
1799 ret = platform_driver_register(&ag71xx_driver);
1800 if (ret)
1801 goto err_debugfs_exit;
1802
1803 return 0;
1804
1805 err_debugfs_exit:
1806 ag71xx_debugfs_root_exit();
1807 err_out:
1808 return ret;
1809 }
1810
1811 static void __exit ag71xx_module_exit(void)
1812 {
1813 platform_driver_unregister(&ag71xx_driver);
1814 ag71xx_debugfs_root_exit();
1815 }
1816
1817 module_init(ag71xx_module_init);
1818 module_exit(ag71xx_module_exit);
1819
1820 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1821 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1822 MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
1823 MODULE_LICENSE("GPL v2");
1824 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
OpenWrt Source Repository