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ath79: ag71xx: Remove ar7240_set_addr and ag71xx_ar7240_start
[openwrt/openwrt.git] / target / linux / ath79 / files / drivers / net / ethernet / atheros / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include <linux/sizes.h>
15 #include <linux/of_net.h>
16 #include <linux/of_address.h>
17 #include "ag71xx.h"
18
19 #define AG71XX_DEFAULT_MSG_ENABLE \
20 (NETIF_MSG_DRV \
21 | NETIF_MSG_PROBE \
22 | NETIF_MSG_LINK \
23 | NETIF_MSG_TIMER \
24 | NETIF_MSG_IFDOWN \
25 | NETIF_MSG_IFUP \
26 | NETIF_MSG_RX_ERR \
27 | NETIF_MSG_TX_ERR)
28
29 static int ag71xx_msg_level = -1;
30
31 module_param_named(msg_level, ag71xx_msg_level, int, 0);
32 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
33
34 #define ETH_SWITCH_HEADER_LEN 2
35
36 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush);
37
38 static inline unsigned int ag71xx_max_frame_len(unsigned int mtu)
39 {
40 return ETH_SWITCH_HEADER_LEN + ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN;
41 }
42
43 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
44 {
45 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
46 ag->dev->name,
47 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
48 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
49 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
50
51 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
52 ag->dev->name,
53 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
54 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
55 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
56 }
57
58 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
59 {
60 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
61 ag->dev->name, label, intr,
62 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
63 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
64 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
65 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
66 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
67 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
68 }
69
70 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
71 {
72 struct ag71xx_ring *ring = &ag->tx_ring;
73 struct net_device *dev = ag->dev;
74 int ring_mask = BIT(ring->order) - 1;
75 u32 bytes_compl = 0, pkts_compl = 0;
76
77 while (ring->curr != ring->dirty) {
78 struct ag71xx_desc *desc;
79 u32 i = ring->dirty & ring_mask;
80
81 desc = ag71xx_ring_desc(ring, i);
82 if (!ag71xx_desc_empty(desc)) {
83 desc->ctrl = 0;
84 dev->stats.tx_errors++;
85 }
86
87 if (ring->buf[i].skb) {
88 bytes_compl += ring->buf[i].len;
89 pkts_compl++;
90 dev_kfree_skb_any(ring->buf[i].skb);
91 }
92 ring->buf[i].skb = NULL;
93 ring->dirty++;
94 }
95
96 /* flush descriptors */
97 wmb();
98
99 netdev_completed_queue(dev, pkts_compl, bytes_compl);
100 }
101
102 static void ag71xx_ring_tx_init(struct ag71xx *ag)
103 {
104 struct ag71xx_ring *ring = &ag->tx_ring;
105 int ring_size = BIT(ring->order);
106 int ring_mask = ring_size - 1;
107 int i;
108
109 for (i = 0; i < ring_size; i++) {
110 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
111
112 desc->next = (u32) (ring->descs_dma +
113 AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
114
115 desc->ctrl = DESC_EMPTY;
116 ring->buf[i].skb = NULL;
117 }
118
119 /* flush descriptors */
120 wmb();
121
122 ring->curr = 0;
123 ring->dirty = 0;
124 netdev_reset_queue(ag->dev);
125 }
126
127 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
128 {
129 struct ag71xx_ring *ring = &ag->rx_ring;
130 int ring_size = BIT(ring->order);
131 int i;
132
133 if (!ring->buf)
134 return;
135
136 for (i = 0; i < ring_size; i++)
137 if (ring->buf[i].rx_buf) {
138 dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
139 ag->rx_buf_size, DMA_FROM_DEVICE);
140 skb_free_frag(ring->buf[i].rx_buf);
141 }
142 }
143
144 static int ag71xx_buffer_size(struct ag71xx *ag)
145 {
146 return ag->rx_buf_size +
147 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
148 }
149
150 static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf,
151 int offset,
152 void *(*alloc)(unsigned int size))
153 {
154 struct ag71xx_ring *ring = &ag->rx_ring;
155 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, buf - &ring->buf[0]);
156 void *data;
157
158 data = alloc(ag71xx_buffer_size(ag));
159 if (!data)
160 return false;
161
162 buf->rx_buf = data;
163 buf->dma_addr = dma_map_single(&ag->dev->dev, data, ag->rx_buf_size,
164 DMA_FROM_DEVICE);
165 desc->data = (u32) buf->dma_addr + offset;
166 return true;
167 }
168
169 static int ag71xx_ring_rx_init(struct ag71xx *ag)
170 {
171 struct ag71xx_ring *ring = &ag->rx_ring;
172 int ring_size = BIT(ring->order);
173 int ring_mask = BIT(ring->order) - 1;
174 unsigned int i;
175 int ret;
176
177 ret = 0;
178 for (i = 0; i < ring_size; i++) {
179 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
180
181 desc->next = (u32) (ring->descs_dma +
182 AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
183
184 DBG("ag71xx: RX desc at %p, next is %08x\n",
185 desc, desc->next);
186 }
187
188 for (i = 0; i < ring_size; i++) {
189 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
190
191 if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], ag->rx_buf_offset,
192 netdev_alloc_frag)) {
193 ret = -ENOMEM;
194 break;
195 }
196
197 desc->ctrl = DESC_EMPTY;
198 }
199
200 /* flush descriptors */
201 wmb();
202
203 ring->curr = 0;
204 ring->dirty = 0;
205
206 return ret;
207 }
208
209 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
210 {
211 struct ag71xx_ring *ring = &ag->rx_ring;
212 int ring_mask = BIT(ring->order) - 1;
213 unsigned int count;
214 int offset = ag->rx_buf_offset;
215
216 count = 0;
217 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
218 struct ag71xx_desc *desc;
219 unsigned int i;
220
221 i = ring->dirty & ring_mask;
222 desc = ag71xx_ring_desc(ring, i);
223
224 if (!ring->buf[i].rx_buf &&
225 !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset,
226 napi_alloc_frag))
227 break;
228
229 desc->ctrl = DESC_EMPTY;
230 count++;
231 }
232
233 /* flush descriptors */
234 wmb();
235
236 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
237
238 return count;
239 }
240
241 static int ag71xx_rings_init(struct ag71xx *ag)
242 {
243 struct ag71xx_ring *tx = &ag->tx_ring;
244 struct ag71xx_ring *rx = &ag->rx_ring;
245 int ring_size = BIT(tx->order) + BIT(rx->order);
246 int tx_size = BIT(tx->order);
247
248 tx->buf = kzalloc(ring_size * sizeof(*tx->buf), GFP_KERNEL);
249 if (!tx->buf)
250 return -ENOMEM;
251
252 tx->descs_cpu = dma_alloc_coherent(NULL, ring_size * AG71XX_DESC_SIZE,
253 &tx->descs_dma, GFP_ATOMIC);
254 if (!tx->descs_cpu) {
255 kfree(tx->buf);
256 tx->buf = NULL;
257 return -ENOMEM;
258 }
259
260 rx->buf = &tx->buf[BIT(tx->order)];
261 rx->descs_cpu = ((void *)tx->descs_cpu) + tx_size * AG71XX_DESC_SIZE;
262 rx->descs_dma = tx->descs_dma + tx_size * AG71XX_DESC_SIZE;
263
264 ag71xx_ring_tx_init(ag);
265 return ag71xx_ring_rx_init(ag);
266 }
267
268 static void ag71xx_rings_free(struct ag71xx *ag)
269 {
270 struct ag71xx_ring *tx = &ag->tx_ring;
271 struct ag71xx_ring *rx = &ag->rx_ring;
272 int ring_size = BIT(tx->order) + BIT(rx->order);
273
274 if (tx->descs_cpu)
275 dma_free_coherent(NULL, ring_size * AG71XX_DESC_SIZE,
276 tx->descs_cpu, tx->descs_dma);
277
278 kfree(tx->buf);
279
280 tx->descs_cpu = NULL;
281 rx->descs_cpu = NULL;
282 tx->buf = NULL;
283 rx->buf = NULL;
284 }
285
286 static void ag71xx_rings_cleanup(struct ag71xx *ag)
287 {
288 ag71xx_ring_rx_clean(ag);
289 ag71xx_ring_tx_clean(ag);
290 ag71xx_rings_free(ag);
291
292 netdev_reset_queue(ag->dev);
293 }
294
295 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
296 {
297 switch (ag->speed) {
298 case SPEED_1000:
299 return "1000";
300 case SPEED_100:
301 return "100";
302 case SPEED_10:
303 return "10";
304 }
305
306 return "?";
307 }
308
309 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
310 {
311 u32 t;
312
313 t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
314 | (((u32) mac[3]) << 8) | ((u32) mac[2]);
315
316 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
317
318 t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
319 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
320 }
321
322 static void ag71xx_dma_reset(struct ag71xx *ag)
323 {
324 u32 val;
325 int i;
326
327 ag71xx_dump_dma_regs(ag);
328
329 /* stop RX and TX */
330 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
331 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
332
333 /*
334 * give the hardware some time to really stop all rx/tx activity
335 * clearing the descriptors too early causes random memory corruption
336 */
337 mdelay(1);
338
339 /* clear descriptor addresses */
340 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
341 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
342
343 /* clear pending RX/TX interrupts */
344 for (i = 0; i < 256; i++) {
345 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
346 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
347 }
348
349 /* clear pending errors */
350 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
351 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
352
353 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
354 if (val)
355 pr_alert("%s: unable to clear DMA Rx status: %08x\n",
356 ag->dev->name, val);
357
358 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
359
360 /* mask out reserved bits */
361 val &= ~0xff000000;
362
363 if (val)
364 pr_alert("%s: unable to clear DMA Tx status: %08x\n",
365 ag->dev->name, val);
366
367 ag71xx_dump_dma_regs(ag);
368 }
369
370 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
371 MAC_CFG1_SRX | MAC_CFG1_STX)
372
373 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
374
375 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
376 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
377 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
378 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
379 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
380 FIFO_CFG4_VT)
381
382 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
383 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
384 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
385 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
386 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
387 FIFO_CFG5_17 | FIFO_CFG5_SF)
388
389 static void ag71xx_hw_stop(struct ag71xx *ag)
390 {
391 /* disable all interrupts and stop the rx/tx engine */
392 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
393 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
394 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
395 }
396
397 static void ag71xx_hw_setup(struct ag71xx *ag)
398 {
399 struct device_node *np = ag->pdev->dev.of_node;
400 u32 init = MAC_CFG1_INIT;
401
402 /* setup MAC configuration registers */
403 if (of_property_read_bool(np, "flow-control"))
404 init |= MAC_CFG1_TFC | MAC_CFG1_RFC;
405 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, init);
406
407 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
408 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
409
410 /* setup max frame length to zero */
411 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0);
412
413 /* setup FIFO configuration registers */
414 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
415 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, ag->fifodata[0]);
416 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, ag->fifodata[1]);
417 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
418 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
419 }
420
421 static void ag71xx_hw_init(struct ag71xx *ag)
422 {
423 ag71xx_hw_stop(ag);
424
425 if (ag->phy_reset) {
426 reset_control_assert(ag->phy_reset);
427 msleep(50);
428 reset_control_deassert(ag->phy_reset);
429 msleep(200);
430 }
431
432 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
433 udelay(20);
434
435 reset_control_assert(ag->mac_reset);
436 msleep(100);
437 reset_control_deassert(ag->mac_reset);
438 msleep(200);
439
440 ag71xx_hw_setup(ag);
441
442 ag71xx_dma_reset(ag);
443 }
444
445 static void ag71xx_fast_reset(struct ag71xx *ag)
446 {
447 struct net_device *dev = ag->dev;
448 u32 rx_ds;
449 u32 mii_reg;
450
451 ag71xx_hw_stop(ag);
452 wmb();
453
454 mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
455 rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
456
457 ag71xx_tx_packets(ag, true);
458
459 reset_control_assert(ag->mac_reset);
460 udelay(10);
461 reset_control_deassert(ag->mac_reset);
462 udelay(10);
463
464 ag71xx_dma_reset(ag);
465 ag71xx_hw_setup(ag);
466 ag->tx_ring.curr = 0;
467 ag->tx_ring.dirty = 0;
468 netdev_reset_queue(ag->dev);
469
470 /* setup max frame length */
471 ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
472 ag71xx_max_frame_len(ag->dev->mtu));
473
474 ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
475 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
476 ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
477
478 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
479 }
480
481 static void ag71xx_hw_start(struct ag71xx *ag)
482 {
483 /* start RX engine */
484 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
485
486 /* enable interrupts */
487 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
488
489 netif_wake_queue(ag->dev);
490 }
491
492 static void ath79_set_pllval(struct ag71xx *ag)
493 {
494 u32 pll_reg = ag->pllreg[1];
495 u32 pll_val;
496
497 if (!ag->pllregmap)
498 return;
499
500 switch (ag->speed) {
501 case SPEED_10:
502 pll_val = ag->plldata[2];
503 break;
504 case SPEED_100:
505 pll_val = ag->plldata[1];
506 break;
507 case SPEED_1000:
508 pll_val = ag->plldata[0];
509 break;
510 default:
511 BUG();
512 }
513
514 if (pll_val)
515 regmap_write(ag->pllregmap, pll_reg, pll_val);
516 }
517
518 static void ath79_set_pll(struct ag71xx *ag)
519 {
520 u32 pll_cfg = ag->pllreg[0];
521 u32 pll_shift = ag->pllreg[2];
522
523 if (!ag->pllregmap)
524 return;
525
526 regmap_update_bits(ag->pllregmap, pll_cfg, 3 << pll_shift, 2 << pll_shift);
527 udelay(100);
528
529 ath79_set_pllval(ag);
530
531 regmap_update_bits(ag->pllregmap, pll_cfg, 3 << pll_shift, 3 << pll_shift);
532 udelay(100);
533
534 regmap_update_bits(ag->pllregmap, pll_cfg, 3 << pll_shift, 0);
535 udelay(100);
536 }
537
538 static void ath79_mii_ctrl_set_speed(struct ag71xx *ag)
539 {
540 unsigned int mii_speed;
541 u32 t;
542
543 if (!ag->mii_base)
544 return;
545
546 switch (ag->speed) {
547 case SPEED_10:
548 mii_speed = AR71XX_MII_CTRL_SPEED_10;
549 break;
550 case SPEED_100:
551 mii_speed = AR71XX_MII_CTRL_SPEED_100;
552 break;
553 case SPEED_1000:
554 mii_speed = AR71XX_MII_CTRL_SPEED_1000;
555 break;
556 default:
557 BUG();
558 }
559
560 t = __raw_readl(ag->mii_base);
561 t &= ~(AR71XX_MII_CTRL_IF_MASK);
562 t |= (mii_speed & AR71XX_MII_CTRL_IF_MASK);
563 __raw_writel(t, ag->mii_base);
564 }
565
566 static void
567 __ag71xx_link_adjust(struct ag71xx *ag, bool update)
568 {
569 struct device_node *np = ag->pdev->dev.of_node;
570 u32 cfg2;
571 u32 ifctl;
572 u32 fifo5;
573
574 if (!ag->link && update) {
575 ag71xx_hw_stop(ag);
576 netif_carrier_off(ag->dev);
577 if (netif_msg_link(ag))
578 pr_info("%s: link down\n", ag->dev->name);
579 return;
580 }
581
582 if (!of_device_is_compatible(np, "qca,ar9130-eth") &&
583 !of_device_is_compatible(np, "qca,ar7100-eth"))
584 ag71xx_fast_reset(ag);
585
586 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
587 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
588 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
589
590 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
591 ifctl &= ~(MAC_IFCTL_SPEED);
592
593 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
594 fifo5 &= ~FIFO_CFG5_BM;
595
596 switch (ag->speed) {
597 case SPEED_1000:
598 cfg2 |= MAC_CFG2_IF_1000;
599 fifo5 |= FIFO_CFG5_BM;
600 break;
601 case SPEED_100:
602 cfg2 |= MAC_CFG2_IF_10_100;
603 ifctl |= MAC_IFCTL_SPEED;
604 break;
605 case SPEED_10:
606 cfg2 |= MAC_CFG2_IF_10_100;
607 break;
608 default:
609 BUG();
610 return;
611 }
612
613 if (ag->tx_ring.desc_split) {
614 ag->fifodata[2] &= 0xffff;
615 ag->fifodata[2] |= ((2048 - ag->tx_ring.desc_split) / 4) << 16;
616 }
617
618 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, ag->fifodata[2]);
619
620 if (update) {
621 if (of_device_is_compatible(np, "qca,ar7100-eth") ||
622 of_device_is_compatible(np, "qca,ar9130-eth")) {
623 ath79_set_pll(ag);
624 ath79_mii_ctrl_set_speed(ag);
625 } else if (of_device_is_compatible(np, "qca,ar7242-eth") ||
626 of_device_is_compatible(np, "qca,ar9340-eth") ||
627 of_device_is_compatible(np, "qca,qca9550-eth") ||
628 of_device_is_compatible(np, "qca,qca9560-eth")) {
629 ath79_set_pllval(ag);
630 }
631 }
632
633 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
634 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
635 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
636
637 if (of_device_is_compatible(np, "qca,qca9530-eth") ||
638 of_device_is_compatible(np, "qca,qca9560-eth")) {
639 /*
640 * The rx ring buffer can stall on small packets on QCA953x and
641 * QCA956x. Disabling the inline checksum engine fixes the stall.
642 * The wr, rr functions cannot be used since this hidden register
643 * is outside of the normal ag71xx register block.
644 */
645 void __iomem *dam = ioremap_nocache(0xb90001bc, 0x4);
646 if (dam) {
647 __raw_writel(__raw_readl(dam) & ~BIT(27), dam);
648 (void)__raw_readl(dam);
649 iounmap(dam);
650 }
651 }
652
653 ag71xx_hw_start(ag);
654
655 netif_carrier_on(ag->dev);
656 if (update && netif_msg_link(ag))
657 pr_info("%s: link up (%sMbps/%s duplex)\n",
658 ag->dev->name,
659 ag71xx_speed_str(ag),
660 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
661
662 DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
663 ag->dev->name,
664 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
665 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
666 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
667
668 DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
669 ag->dev->name,
670 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
671 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
672 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
673
674 DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x\n",
675 ag->dev->name,
676 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
677 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL));
678 }
679
680 void ag71xx_link_adjust(struct ag71xx *ag)
681 {
682 __ag71xx_link_adjust(ag, true);
683 }
684
685 static int ag71xx_hw_enable(struct ag71xx *ag)
686 {
687 int ret;
688
689 ret = ag71xx_rings_init(ag);
690 if (ret)
691 return ret;
692
693 napi_enable(&ag->napi);
694 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
695 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
696 netif_start_queue(ag->dev);
697
698 return 0;
699 }
700
701 static void ag71xx_hw_disable(struct ag71xx *ag)
702 {
703 unsigned long flags;
704
705 spin_lock_irqsave(&ag->lock, flags);
706
707 netif_stop_queue(ag->dev);
708
709 ag71xx_hw_stop(ag);
710 ag71xx_dma_reset(ag);
711
712 napi_disable(&ag->napi);
713 del_timer_sync(&ag->oom_timer);
714
715 spin_unlock_irqrestore(&ag->lock, flags);
716
717 ag71xx_rings_cleanup(ag);
718 }
719
720 static int ag71xx_open(struct net_device *dev)
721 {
722 struct ag71xx *ag = netdev_priv(dev);
723 unsigned int max_frame_len;
724 int ret;
725
726 netif_carrier_off(dev);
727 max_frame_len = ag71xx_max_frame_len(dev->mtu);
728 ag->rx_buf_size = SKB_DATA_ALIGN(max_frame_len + NET_SKB_PAD + NET_IP_ALIGN);
729
730 /* setup max frame length */
731 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len);
732 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
733
734 ret = ag71xx_hw_enable(ag);
735 if (ret)
736 goto err;
737
738 phy_start(ag->phy_dev);
739
740 return 0;
741
742 err:
743 ag71xx_rings_cleanup(ag);
744 return ret;
745 }
746
747 static int ag71xx_stop(struct net_device *dev)
748 {
749 struct ag71xx *ag = netdev_priv(dev);
750
751 netif_carrier_off(dev);
752 phy_stop(ag->phy_dev);
753 ag71xx_hw_disable(ag);
754
755 return 0;
756 }
757
758 static int ag71xx_fill_dma_desc(struct ag71xx_ring *ring, u32 addr, int len)
759 {
760 int i;
761 struct ag71xx_desc *desc;
762 int ring_mask = BIT(ring->order) - 1;
763 int ndesc = 0;
764 int split = ring->desc_split;
765
766 if (!split)
767 split = len;
768
769 while (len > 0) {
770 unsigned int cur_len = len;
771
772 i = (ring->curr + ndesc) & ring_mask;
773 desc = ag71xx_ring_desc(ring, i);
774
775 if (!ag71xx_desc_empty(desc))
776 return -1;
777
778 if (cur_len > split) {
779 cur_len = split;
780
781 /*
782 * TX will hang if DMA transfers <= 4 bytes,
783 * make sure next segment is more than 4 bytes long.
784 */
785 if (len <= split + 4)
786 cur_len -= 4;
787 }
788
789 desc->data = addr;
790 addr += cur_len;
791 len -= cur_len;
792
793 if (len > 0)
794 cur_len |= DESC_MORE;
795
796 /* prevent early tx attempt of this descriptor */
797 if (!ndesc)
798 cur_len |= DESC_EMPTY;
799
800 desc->ctrl = cur_len;
801 ndesc++;
802 }
803
804 return ndesc;
805 }
806
807 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
808 struct net_device *dev)
809 {
810 struct ag71xx *ag = netdev_priv(dev);
811 struct ag71xx_ring *ring = &ag->tx_ring;
812 int ring_mask = BIT(ring->order) - 1;
813 int ring_size = BIT(ring->order);
814 struct ag71xx_desc *desc;
815 dma_addr_t dma_addr;
816 int i, n, ring_min;
817
818 if (skb->len <= 4) {
819 DBG("%s: packet len is too small\n", ag->dev->name);
820 goto err_drop;
821 }
822
823 dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
824 DMA_TO_DEVICE);
825
826 i = ring->curr & ring_mask;
827 desc = ag71xx_ring_desc(ring, i);
828
829 /* setup descriptor fields */
830 n = ag71xx_fill_dma_desc(ring, (u32) dma_addr, skb->len & ag->desc_pktlen_mask);
831 if (n < 0)
832 goto err_drop_unmap;
833
834 i = (ring->curr + n - 1) & ring_mask;
835 ring->buf[i].len = skb->len;
836 ring->buf[i].skb = skb;
837
838 netdev_sent_queue(dev, skb->len);
839
840 skb_tx_timestamp(skb);
841
842 desc->ctrl &= ~DESC_EMPTY;
843 ring->curr += n;
844
845 /* flush descriptor */
846 wmb();
847
848 ring_min = 2;
849 if (ring->desc_split)
850 ring_min *= AG71XX_TX_RING_DS_PER_PKT;
851
852 if (ring->curr - ring->dirty >= ring_size - ring_min) {
853 DBG("%s: tx queue full\n", dev->name);
854 netif_stop_queue(dev);
855 }
856
857 DBG("%s: packet injected into TX queue\n", ag->dev->name);
858
859 /* enable TX engine */
860 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
861
862 return NETDEV_TX_OK;
863
864 err_drop_unmap:
865 dma_unmap_single(&dev->dev, dma_addr, skb->len, DMA_TO_DEVICE);
866
867 err_drop:
868 dev->stats.tx_dropped++;
869
870 dev_kfree_skb(skb);
871 return NETDEV_TX_OK;
872 }
873
874 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
875 {
876 struct ag71xx *ag = netdev_priv(dev);
877 int ret;
878
879 switch (cmd) {
880 case SIOCETHTOOL:
881 if (ag->phy_dev == NULL)
882 break;
883
884 spin_lock_irq(&ag->lock);
885 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
886 spin_unlock_irq(&ag->lock);
887 return ret;
888
889 case SIOCSIFHWADDR:
890 if (copy_from_user
891 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
892 return -EFAULT;
893 return 0;
894
895 case SIOCGIFHWADDR:
896 if (copy_to_user
897 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
898 return -EFAULT;
899 return 0;
900
901 case SIOCGMIIPHY:
902 case SIOCGMIIREG:
903 case SIOCSMIIREG:
904 if (ag->phy_dev == NULL)
905 break;
906
907 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
908
909 default:
910 break;
911 }
912
913 return -EOPNOTSUPP;
914 }
915
916 static void ag71xx_oom_timer_handler(unsigned long data)
917 {
918 struct net_device *dev = (struct net_device *) data;
919 struct ag71xx *ag = netdev_priv(dev);
920
921 napi_schedule(&ag->napi);
922 }
923
924 static void ag71xx_tx_timeout(struct net_device *dev)
925 {
926 struct ag71xx *ag = netdev_priv(dev);
927
928 if (netif_msg_tx_err(ag))
929 pr_info("%s: tx timeout\n", ag->dev->name);
930
931 schedule_delayed_work(&ag->restart_work, 1);
932 }
933
934 static void ag71xx_restart_work_func(struct work_struct *work)
935 {
936 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work.work);
937
938 rtnl_lock();
939 ag71xx_hw_disable(ag);
940 ag71xx_hw_enable(ag);
941 if (ag->link)
942 __ag71xx_link_adjust(ag, false);
943 rtnl_unlock();
944 }
945
946 static bool ag71xx_check_dma_stuck(struct ag71xx *ag)
947 {
948 unsigned long timestamp;
949 u32 rx_sm, tx_sm, rx_fd;
950
951 timestamp = netdev_get_tx_queue(ag->dev, 0)->trans_start;
952 if (likely(time_before(jiffies, timestamp + HZ/10)))
953 return false;
954
955 if (!netif_carrier_ok(ag->dev))
956 return false;
957
958 rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
959 if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
960 return true;
961
962 tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
963 rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
964 if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
965 ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
966 return true;
967
968 return false;
969 }
970
971 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush)
972 {
973 struct ag71xx_ring *ring = &ag->tx_ring;
974 bool dma_stuck = false;
975 int ring_mask = BIT(ring->order) - 1;
976 int ring_size = BIT(ring->order);
977 int sent = 0;
978 int bytes_compl = 0;
979 int n = 0;
980
981 DBG("%s: processing TX ring\n", ag->dev->name);
982
983 while (ring->dirty + n != ring->curr) {
984 unsigned int i = (ring->dirty + n) & ring_mask;
985 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
986 struct sk_buff *skb = ring->buf[i].skb;
987
988 if (!flush && !ag71xx_desc_empty(desc)) {
989 if (ag->tx_hang_workaround &&
990 ag71xx_check_dma_stuck(ag)) {
991 schedule_delayed_work(&ag->restart_work, HZ / 2);
992 dma_stuck = true;
993 }
994 break;
995 }
996
997 if (flush)
998 desc->ctrl |= DESC_EMPTY;
999
1000 n++;
1001 if (!skb)
1002 continue;
1003
1004 dev_kfree_skb_any(skb);
1005 ring->buf[i].skb = NULL;
1006
1007 bytes_compl += ring->buf[i].len;
1008
1009 sent++;
1010 ring->dirty += n;
1011
1012 while (n > 0) {
1013 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
1014 n--;
1015 }
1016 }
1017
1018 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
1019
1020 if (!sent)
1021 return 0;
1022
1023 ag->dev->stats.tx_bytes += bytes_compl;
1024 ag->dev->stats.tx_packets += sent;
1025
1026 netdev_completed_queue(ag->dev, sent, bytes_compl);
1027 if ((ring->curr - ring->dirty) < (ring_size * 3) / 4)
1028 netif_wake_queue(ag->dev);
1029
1030 if (!dma_stuck)
1031 cancel_delayed_work(&ag->restart_work);
1032
1033 return sent;
1034 }
1035
1036 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
1037 {
1038 struct net_device *dev = ag->dev;
1039 struct ag71xx_ring *ring = &ag->rx_ring;
1040 unsigned int pktlen_mask = ag->desc_pktlen_mask;
1041 unsigned int offset = ag->rx_buf_offset;
1042 int ring_mask = BIT(ring->order) - 1;
1043 int ring_size = BIT(ring->order);
1044 struct sk_buff_head queue;
1045 struct sk_buff *skb;
1046 int done = 0;
1047
1048 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
1049 dev->name, limit, ring->curr, ring->dirty);
1050
1051 skb_queue_head_init(&queue);
1052
1053 while (done < limit) {
1054 unsigned int i = ring->curr & ring_mask;
1055 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
1056 int pktlen;
1057 int err = 0;
1058
1059 if (ag71xx_desc_empty(desc))
1060 break;
1061
1062 if ((ring->dirty + ring_size) == ring->curr) {
1063 ag71xx_assert(0);
1064 break;
1065 }
1066
1067 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
1068
1069 pktlen = desc->ctrl & pktlen_mask;
1070 pktlen -= ETH_FCS_LEN;
1071
1072 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
1073 ag->rx_buf_size, DMA_FROM_DEVICE);
1074
1075 dev->stats.rx_packets++;
1076 dev->stats.rx_bytes += pktlen;
1077
1078 skb = build_skb(ring->buf[i].rx_buf, ag71xx_buffer_size(ag));
1079 if (!skb) {
1080 skb_free_frag(ring->buf[i].rx_buf);
1081 goto next;
1082 }
1083
1084 skb_reserve(skb, offset);
1085 skb_put(skb, pktlen);
1086
1087 if (err) {
1088 dev->stats.rx_dropped++;
1089 kfree_skb(skb);
1090 } else {
1091 skb->dev = dev;
1092 skb->ip_summed = CHECKSUM_NONE;
1093 __skb_queue_tail(&queue, skb);
1094 }
1095
1096 next:
1097 ring->buf[i].rx_buf = NULL;
1098 done++;
1099
1100 ring->curr++;
1101 }
1102
1103 ag71xx_ring_rx_refill(ag);
1104
1105 while ((skb = __skb_dequeue(&queue)) != NULL) {
1106 skb->protocol = eth_type_trans(skb, dev);
1107 netif_receive_skb(skb);
1108 }
1109
1110 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
1111 dev->name, ring->curr, ring->dirty, done);
1112
1113 return done;
1114 }
1115
1116 static int ag71xx_poll(struct napi_struct *napi, int limit)
1117 {
1118 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
1119 struct net_device *dev = ag->dev;
1120 struct ag71xx_ring *rx_ring = &ag->rx_ring;
1121 int rx_ring_size = BIT(rx_ring->order);
1122 unsigned long flags;
1123 u32 status;
1124 int tx_done;
1125 int rx_done;
1126
1127 tx_done = ag71xx_tx_packets(ag, false);
1128
1129 DBG("%s: processing RX ring\n", dev->name);
1130 rx_done = ag71xx_rx_packets(ag, limit);
1131
1132 ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
1133
1134 if (rx_ring->buf[rx_ring->dirty % rx_ring_size].rx_buf == NULL)
1135 goto oom;
1136
1137 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
1138 if (unlikely(status & RX_STATUS_OF)) {
1139 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
1140 dev->stats.rx_fifo_errors++;
1141
1142 /* restart RX */
1143 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
1144 }
1145
1146 if (rx_done < limit) {
1147 if (status & RX_STATUS_PR)
1148 goto more;
1149
1150 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
1151 if (status & TX_STATUS_PS)
1152 goto more;
1153
1154 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
1155 dev->name, rx_done, tx_done, limit);
1156
1157 napi_complete(napi);
1158
1159 /* enable interrupts */
1160 spin_lock_irqsave(&ag->lock, flags);
1161 ag71xx_int_enable(ag, AG71XX_INT_POLL);
1162 spin_unlock_irqrestore(&ag->lock, flags);
1163 return rx_done;
1164 }
1165
1166 more:
1167 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
1168 dev->name, rx_done, tx_done, limit);
1169 return limit;
1170
1171 oom:
1172 if (netif_msg_rx_err(ag))
1173 pr_info("%s: out of memory\n", dev->name);
1174
1175 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
1176 napi_complete(napi);
1177 return 0;
1178 }
1179
1180 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
1181 {
1182 struct net_device *dev = dev_id;
1183 struct ag71xx *ag = netdev_priv(dev);
1184 u32 status;
1185
1186 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
1187 ag71xx_dump_intr(ag, "raw", status);
1188
1189 if (unlikely(!status))
1190 return IRQ_NONE;
1191
1192 if (unlikely(status & AG71XX_INT_ERR)) {
1193 if (status & AG71XX_INT_TX_BE) {
1194 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
1195 dev_err(&dev->dev, "TX BUS error\n");
1196 }
1197 if (status & AG71XX_INT_RX_BE) {
1198 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
1199 dev_err(&dev->dev, "RX BUS error\n");
1200 }
1201 }
1202
1203 if (likely(status & AG71XX_INT_POLL)) {
1204 ag71xx_int_disable(ag, AG71XX_INT_POLL);
1205 DBG("%s: enable polling mode\n", dev->name);
1206 napi_schedule(&ag->napi);
1207 }
1208
1209 ag71xx_debugfs_update_int_stats(ag, status);
1210
1211 return IRQ_HANDLED;
1212 }
1213
1214 #ifdef CONFIG_NET_POLL_CONTROLLER
1215 /*
1216 * Polling 'interrupt' - used by things like netconsole to send skbs
1217 * without having to re-enable interrupts. It's not called while
1218 * the interrupt routine is executing.
1219 */
1220 static void ag71xx_netpoll(struct net_device *dev)
1221 {
1222 disable_irq(dev->irq);
1223 ag71xx_interrupt(dev->irq, dev);
1224 enable_irq(dev->irq);
1225 }
1226 #endif
1227
1228 static int ag71xx_change_mtu(struct net_device *dev, int new_mtu)
1229 {
1230 struct ag71xx *ag = netdev_priv(dev);
1231
1232 dev->mtu = new_mtu;
1233 ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
1234 ag71xx_max_frame_len(dev->mtu));
1235
1236 return 0;
1237 }
1238
1239 static const struct net_device_ops ag71xx_netdev_ops = {
1240 .ndo_open = ag71xx_open,
1241 .ndo_stop = ag71xx_stop,
1242 .ndo_start_xmit = ag71xx_hard_start_xmit,
1243 .ndo_do_ioctl = ag71xx_do_ioctl,
1244 .ndo_tx_timeout = ag71xx_tx_timeout,
1245 .ndo_change_mtu = ag71xx_change_mtu,
1246 .ndo_set_mac_address = eth_mac_addr,
1247 .ndo_validate_addr = eth_validate_addr,
1248 #ifdef CONFIG_NET_POLL_CONTROLLER
1249 .ndo_poll_controller = ag71xx_netpoll,
1250 #endif
1251 };
1252
1253 static const char *ag71xx_get_phy_if_mode_name(phy_interface_t mode)
1254 {
1255 switch (mode) {
1256 case PHY_INTERFACE_MODE_MII:
1257 return "MII";
1258 case PHY_INTERFACE_MODE_GMII:
1259 return "GMII";
1260 case PHY_INTERFACE_MODE_RMII:
1261 return "RMII";
1262 case PHY_INTERFACE_MODE_RGMII:
1263 return "RGMII";
1264 case PHY_INTERFACE_MODE_SGMII:
1265 return "SGMII";
1266 default:
1267 break;
1268 }
1269
1270 return "unknown";
1271 }
1272
1273 static int ag71xx_probe(struct platform_device *pdev)
1274 {
1275 struct device_node *np = pdev->dev.of_node;
1276 struct net_device *dev;
1277 struct resource *res;
1278 struct ag71xx *ag;
1279 const void *mac_addr;
1280 u32 max_frame_len;
1281 int tx_size, err;
1282
1283 if (!np)
1284 return -ENODEV;
1285
1286 dev = alloc_etherdev(sizeof(*ag));
1287 if (!dev)
1288 return -ENOMEM;
1289
1290 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1291 if (!res)
1292 return -EINVAL;
1293
1294 err = ag71xx_setup_gmac(np);
1295 if (err)
1296 return err;
1297
1298 SET_NETDEV_DEV(dev, &pdev->dev);
1299
1300 ag = netdev_priv(dev);
1301 ag->pdev = pdev;
1302 ag->dev = dev;
1303 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1304 AG71XX_DEFAULT_MSG_ENABLE);
1305 spin_lock_init(&ag->lock);
1306
1307 ag->mac_reset = devm_reset_control_get(&pdev->dev, "mac");
1308 if (IS_ERR(ag->mac_reset)) {
1309 dev_err(&pdev->dev, "missing mac reset\n");
1310 err = PTR_ERR(ag->mac_reset);
1311 goto err_free;
1312 }
1313
1314 ag->phy_reset = devm_reset_control_get_optional(&pdev->dev, "phy");
1315
1316 if (of_property_read_u32_array(np, "fifo-data", ag->fifodata, 3)) {
1317 if (of_device_is_compatible(np, "qca,ar9130-eth") ||
1318 of_device_is_compatible(np, "qca,ar7100-eth")) {
1319 ag->fifodata[0] = 0x0fff0000;
1320 ag->fifodata[1] = 0x00001fff;
1321 } else {
1322 ag->fifodata[0] = 0x0010ffff;
1323 ag->fifodata[1] = 0x015500aa;
1324 ag->fifodata[2] = 0x01f00140;
1325 }
1326 if (of_device_is_compatible(np, "qca,ar9130-eth"))
1327 ag->fifodata[2] = 0x00780fff;
1328 else if (of_device_is_compatible(np, "qca,ar7100-eth"))
1329 ag->fifodata[2] = 0x008001ff;
1330 }
1331
1332 if (of_property_read_u32_array(np, "pll-data", ag->plldata, 3))
1333 dev_dbg(&pdev->dev, "failed to read pll-data property\n");
1334
1335 if (of_property_read_u32_array(np, "pll-reg", ag->pllreg, 3))
1336 dev_dbg(&pdev->dev, "failed to read pll-reg property\n");
1337
1338 ag->pllregmap = syscon_regmap_lookup_by_phandle(np, "pll-handle");
1339 if (IS_ERR(ag->pllregmap)) {
1340 dev_dbg(&pdev->dev, "failed to read pll-handle property\n");
1341 ag->pllregmap = NULL;
1342 }
1343
1344 ag->mac_base = devm_ioremap_nocache(&pdev->dev, res->start,
1345 res->end - res->start + 1);
1346 if (!ag->mac_base) {
1347 err = -ENOMEM;
1348 goto err_free;
1349 }
1350 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1351 if (res) {
1352 ag->mii_base = devm_ioremap_nocache(&pdev->dev, res->start,
1353 res->end - res->start + 1);
1354 if (!ag->mii_base) {
1355 err = -ENOMEM;
1356 goto err_free;
1357 }
1358 }
1359
1360 dev->irq = platform_get_irq(pdev, 0);
1361 err = devm_request_irq(&pdev->dev, dev->irq, ag71xx_interrupt,
1362 0x0, dev_name(&pdev->dev), dev);
1363 if (err) {
1364 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1365 goto err_free;
1366 }
1367
1368 dev->netdev_ops = &ag71xx_netdev_ops;
1369 dev->ethtool_ops = &ag71xx_ethtool_ops;
1370
1371 INIT_DELAYED_WORK(&ag->restart_work, ag71xx_restart_work_func);
1372
1373 init_timer(&ag->oom_timer);
1374 ag->oom_timer.data = (unsigned long) dev;
1375 ag->oom_timer.function = ag71xx_oom_timer_handler;
1376
1377 tx_size = AG71XX_TX_RING_SIZE_DEFAULT;
1378 ag->rx_ring.order = ag71xx_ring_size_order(AG71XX_RX_RING_SIZE_DEFAULT);
1379
1380 if (of_device_is_compatible(np, "qca,ar9340-eth") ||
1381 of_device_is_compatible(np, "qca,qca9530-eth") ||
1382 of_device_is_compatible(np, "qca,qca9550-eth") ||
1383 of_device_is_compatible(np, "qca,qca9560-eth"))
1384 ag->desc_pktlen_mask = SZ_16K - 1;
1385 else
1386 ag->desc_pktlen_mask = SZ_4K - 1;
1387
1388 if (ag->desc_pktlen_mask == SZ_16K - 1 &&
1389 !of_device_is_compatible(np, "qca,qca9550-eth") &&
1390 !of_device_is_compatible(np, "qca,qca9560-eth"))
1391 max_frame_len = ag->desc_pktlen_mask;
1392 else
1393 max_frame_len = 1540;
1394
1395 dev->min_mtu = 68;
1396 dev->max_mtu = max_frame_len - ag71xx_max_frame_len(0);
1397
1398 if (of_device_is_compatible(np, "qca,ar7240-eth"))
1399 ag->tx_hang_workaround = 1;
1400
1401 ag->rx_buf_offset = NET_SKB_PAD;
1402 if (!of_device_is_compatible(np, "qca,ar7100-eth") &&
1403 !of_device_is_compatible(np, "qca,ar9130-eth"))
1404 ag->rx_buf_offset += NET_IP_ALIGN;
1405
1406 if (of_device_is_compatible(np, "qca,ar7100-eth")) {
1407 ag->tx_ring.desc_split = AG71XX_TX_RING_SPLIT;
1408 tx_size *= AG71XX_TX_RING_DS_PER_PKT;
1409 }
1410 ag->tx_ring.order = ag71xx_ring_size_order(tx_size);
1411
1412 ag->stop_desc = dmam_alloc_coherent(&pdev->dev,
1413 sizeof(struct ag71xx_desc),
1414 &ag->stop_desc_dma, GFP_KERNEL);
1415 if (!ag->stop_desc)
1416 goto err_free;
1417
1418 ag->stop_desc->data = 0;
1419 ag->stop_desc->ctrl = 0;
1420 ag->stop_desc->next = (u32) ag->stop_desc_dma;
1421
1422 mac_addr = of_get_mac_address(np);
1423 if (mac_addr)
1424 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
1425 if (!mac_addr || !is_valid_ether_addr(dev->dev_addr)) {
1426 dev_err(&pdev->dev, "invalid MAC address, using random address\n");
1427 eth_random_addr(dev->dev_addr);
1428 }
1429
1430 ag->phy_if_mode = of_get_phy_mode(np);
1431 if (ag->phy_if_mode < 0) {
1432 dev_err(&pdev->dev, "missing phy-mode property in DT\n");
1433 err = ag->phy_if_mode;
1434 goto err_free;
1435 }
1436
1437 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1438
1439 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, 0);
1440 ag71xx_hw_init(ag);
1441 ag71xx_mdio_init(ag);
1442
1443 err = ag71xx_phy_connect(ag);
1444 if (err)
1445 goto err_mdio_free;
1446
1447 err = ag71xx_debugfs_init(ag);
1448 if (err)
1449 goto err_phy_disconnect;
1450
1451 platform_set_drvdata(pdev, dev);
1452
1453 err = register_netdev(dev);
1454 if (err) {
1455 dev_err(&pdev->dev, "unable to register net device\n");
1456 platform_set_drvdata(pdev, NULL);
1457 ag71xx_debugfs_exit(ag);
1458 goto err_phy_disconnect;
1459 }
1460
1461 pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d, mode:%s\n",
1462 dev->name, (unsigned long) ag->mac_base, dev->irq,
1463 ag71xx_get_phy_if_mode_name(ag->phy_if_mode));
1464
1465 return 0;
1466
1467 err_phy_disconnect:
1468 ag71xx_phy_disconnect(ag);
1469 err_mdio_free:
1470 ag71xx_mdio_cleanup(ag);
1471 err_free:
1472 free_netdev(dev);
1473 return err;
1474 }
1475
1476 static int ag71xx_remove(struct platform_device *pdev)
1477 {
1478 struct net_device *dev = platform_get_drvdata(pdev);
1479 struct ag71xx *ag;
1480
1481 if (!dev)
1482 return 0;
1483
1484 ag = netdev_priv(dev);
1485 ag71xx_debugfs_exit(ag);
1486 ag71xx_phy_disconnect(ag);
1487 ag71xx_mdio_cleanup(ag);
1488 unregister_netdev(dev);
1489 free_irq(dev->irq, dev);
1490 iounmap(ag->mac_base);
1491 kfree(dev);
1492 platform_set_drvdata(pdev, NULL);
1493
1494 return 0;
1495 }
1496
1497 static const struct of_device_id ag71xx_match[] = {
1498 { .compatible = "qca,ar7100-eth" },
1499 { .compatible = "qca,ar7240-eth" },
1500 { .compatible = "qca,ar7241-eth" },
1501 { .compatible = "qca,ar7242-eth" },
1502 { .compatible = "qca,ar9130-eth" },
1503 { .compatible = "qca,ar9330-eth" },
1504 { .compatible = "qca,ar9340-eth" },
1505 { .compatible = "qca,qca9530-eth" },
1506 { .compatible = "qca,qca9550-eth" },
1507 { .compatible = "qca,qca9560-eth" },
1508 {}
1509 };
1510
1511 static struct platform_driver ag71xx_driver = {
1512 .probe = ag71xx_probe,
1513 .remove = ag71xx_remove,
1514 .driver = {
1515 .name = AG71XX_DRV_NAME,
1516 .of_match_table = ag71xx_match,
1517 }
1518 };
1519
1520 static int __init ag71xx_module_init(void)
1521 {
1522 int ret;
1523
1524 ret = ag71xx_debugfs_root_init();
1525 if (ret)
1526 goto err_out;
1527
1528 ret = platform_driver_register(&ag71xx_driver);
1529 if (ret)
1530 goto err_debugfs_exit;
1531
1532 return 0;
1533
1534 err_debugfs_exit:
1535 ag71xx_debugfs_root_exit();
1536 err_out:
1537 return ret;
1538 }
1539
1540 static void __exit ag71xx_module_exit(void)
1541 {
1542 platform_driver_unregister(&ag71xx_driver);
1543 ag71xx_debugfs_root_exit();
1544 }
1545
1546 module_init(ag71xx_module_init);
1547 module_exit(ag71xx_module_exit);
1548
1549 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1550 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1551 MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
1552 MODULE_LICENSE("GPL v2");
1553 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
OpenWrt Source Repository