target/linux/ath79/patches-4.14/0011-MIPS-ath79-fix-register-address-in-ath79_ddr_wb_flus.patch

   1 From 54204ef3edbb1aa2390cabba61fe185a12cc39f0 Mon Sep 17 00:00:00 2001
   2 From: Felix Fietkau <nbd@nbd.name>
   3 Date: Tue, 6 Mar 2018 08:35:44 +0100
   4 Subject: [PATCH 11/27] MIPS: ath79: fix register address in
   5  ath79_ddr_wb_flush()
   6
   7 ath79_ddr_wb_flush_base has the type void __iomem *, so register offsets
   8 need to be a multiple of 4.
   9
  10 Cc: Alban Bedel <albeu@free.fr>
  11 Fixes: 24b0e3e84fbf ("MIPS: ath79: Improve the DDR controller interface")
  12 Signed-off-by: Felix Fietkau <nbd@nbd.name>
  13 ---
  14  arch/mips/ath79/common.c | 2 +-
  15  1 file changed, 1 insertion(+), 1 deletion(-)
  16
  17 --- a/arch/mips/ath79/common.c
  18 +++ b/arch/mips/ath79/common.c
  19 @@ -58,7 +58,7 @@ EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init);
  20
  21  void ath79_ddr_wb_flush(u32 reg)
  22  {
  23 -       void __iomem *flush_reg = ath79_ddr_wb_flush_base + reg;
  24 +       void __iomem *flush_reg = ath79_ddr_wb_flush_base + (reg * 4);
  25
  26         /* Flush the DDR write buffer. */
  27         __raw_writel(0x1, flush_reg);