target/linux/ath79/patches-4.14/0017-MIPS-ath79-add-support-for-qca956x-soc.patch

   1 From 6aeb24b9508bbe91f89cd4eb21d0d7582d971146 Mon Sep 17 00:00:00 2001
   2 From: Weijie Gao <hackpascal@gmail.com>
   3 Date: Tue, 6 Mar 2018 08:48:31 +0100
   4 Subject: [PATCH 17/27] MIPS: ath79: add support for qca956x soc
   5
   6 This patch adds soc support for QCA9561 and TP9343.
   7 TP9343 is a reduced version of QCA9561, which can be found in TP-LINK routers in China.
   8 The qca956x_wmac has not yet been supported by ath9k.
   9
  10 tested on TL-WDR6500 and TL-WR882N v1 (Chinese version)
  11
  12 Signed-off-by: Weijie Gao <hackpascal@gmail.com>
  13 ---
  14  arch/mips/ath79/Kconfig                  |  2 +-
  15  arch/mips/ath79/clock.c                  | 96 ++++++++++++++++++++++++++++++++
  16  arch/mips/ath79/common.c                 |  4 ++
  17  arch/mips/ath79/dev-common.c             |  7 ++-
  18  arch/mips/ath79/early_printk.c           |  2 +
  19  arch/mips/ath79/irq.c                    | 87 ++++++++++++++++++++++++++++-
  20  arch/mips/ath79/pci.c                    | 12 ++++
  21  arch/mips/ath79/setup.c                  | 17 +++++-
  22  arch/mips/include/asm/mach-ath79/ath79.h | 22 ++++++++
  23  9 files changed, 245 insertions(+), 4 deletions(-)
  24
  25 --- a/arch/mips/ath79/Kconfig
  26 +++ b/arch/mips/ath79/Kconfig
  27 @@ -119,7 +119,7 @@ config ATH79_DEV_USB
  28         def_bool n
  29
  30  config ATH79_DEV_WMAC
  31 -       depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
  32 +       depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X || SOC_QCA956X)
  33         def_bool n
  34
  35  endif
  36 --- a/arch/mips/ath79/clock.c
  37 +++ b/arch/mips/ath79/clock.c
  38 @@ -525,6 +525,100 @@ static void __init qca955x_clocks_init(v
  39         clk_add_alias("uart", NULL, "ref", NULL);
  40  }
  41
  42 +static void __init qca956x_clocks_init(void)
  43 +{
  44 +       unsigned long ref_rate;
  45 +       unsigned long cpu_rate;
  46 +       unsigned long ddr_rate;
  47 +       unsigned long ahb_rate;
  48 +       u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv;
  49 +       u32 cpu_pll, ddr_pll;
  50 +       u32 bootstrap;
  51 +
  52 +       bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
  53 +       if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40)
  54 +               ref_rate = 40 * 1000 * 1000;
  55 +       else
  56 +               ref_rate = 25 * 1000 * 1000;
  57 +
  58 +       pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG);
  59 +       out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
  60 +                 QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
  61 +       ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
  62 +                 QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
  63 +
  64 +       pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG);
  65 +       nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
  66 +              QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
  67 +       hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
  68 +              QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK;
  69 +       lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) &
  70 +              QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK;
  71 +
  72 +       cpu_pll = nint * ref_rate / ref_div;
  73 +       cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
  74 +       cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
  75 +       cpu_pll /= (1 << out_div);
  76 +
  77 +       pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG);
  78 +       out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
  79 +                 QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
  80 +       ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
  81 +                 QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
  82 +       pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG);
  83 +       nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
  84 +              QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
  85 +       hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
  86 +              QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK;
  87 +       lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) &
  88 +              QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK;
  89 +
  90 +       ddr_pll = nint * ref_rate / ref_div;
  91 +       ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
  92 +       ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
  93 +       ddr_pll /= (1 << out_div);
  94 +
  95 +       clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG);
  96 +
  97 +       postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
  98 +                 QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
  99 +
 100 +       if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
 101 +               cpu_rate = ref_rate;
 102 +       else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL)
 103 +               cpu_rate = ddr_pll / (postdiv + 1);
 104 +       else
 105 +               cpu_rate = cpu_pll / (postdiv + 1);
 106 +
 107 +       postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
 108 +                 QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
 109 +
 110 +       if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
 111 +               ddr_rate = ref_rate;
 112 +       else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL)
 113 +               ddr_rate = cpu_pll / (postdiv + 1);
 114 +       else
 115 +               ddr_rate = ddr_pll / (postdiv + 1);
 116 +
 117 +       postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
 118 +                 QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
 119 +
 120 +       if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
 121 +               ahb_rate = ref_rate;
 122 +       else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
 123 +               ahb_rate = ddr_pll / (postdiv + 1);
 124 +       else
 125 +               ahb_rate = cpu_pll / (postdiv + 1);
 126 +
 127 +       ath79_add_sys_clkdev("ref", ref_rate);
 128 +       ath79_add_sys_clkdev("cpu", cpu_rate);
 129 +       ath79_add_sys_clkdev("ddr", ddr_rate);
 130 +       ath79_add_sys_clkdev("ahb", ahb_rate);
 131 +
 132 +       clk_add_alias("wdt", NULL, "ref", NULL);
 133 +       clk_add_alias("uart", NULL, "ref", NULL);
 134 +}
 135 +
 136  void __init ath79_clocks_init(void)
 137  {
 138         if (soc_is_ar71xx())
 139 @@ -539,6 +633,8 @@ void __init ath79_clocks_init(void)
 140                 qca953x_clocks_init();
 141         else if (soc_is_qca955x())
 142                 qca955x_clocks_init();
 143 +       else if (soc_is_qca956x() || soc_is_tp9343())
 144 +               qca956x_clocks_init();
 145         else
 146                 BUG();
 147  }
 148 --- a/arch/mips/ath79/common.c
 149 +++ b/arch/mips/ath79/common.c
 150 @@ -107,6 +107,8 @@ void ath79_device_reset_set(u32 mask)
 151                 reg = QCA953X_RESET_REG_RESET_MODULE;
 152         else if (soc_is_qca955x())
 153                 reg = QCA955X_RESET_REG_RESET_MODULE;
 154 +       else if (soc_is_qca956x() || soc_is_tp9343())
 155 +               reg = QCA956X_RESET_REG_RESET_MODULE;
 156         else
 157                 panic("Reset register not defined for this SOC");
 158
 159 @@ -137,6 +139,8 @@ void ath79_device_reset_clear(u32 mask)
 160                 reg = QCA953X_RESET_REG_RESET_MODULE;
 161         else if (soc_is_qca955x())
 162                 reg = QCA955X_RESET_REG_RESET_MODULE;
 163 +       else if (soc_is_qca956x() || soc_is_tp9343())
 164 +               reg = QCA956X_RESET_REG_RESET_MODULE;
 165         else
 166                 panic("Reset register not defined for this SOC");
 167
 168 --- a/arch/mips/ath79/dev-common.c
 169 +++ b/arch/mips/ath79/dev-common.c
 170 @@ -86,7 +86,9 @@ void __init ath79_register_uart(void)
 171             soc_is_ar913x() ||
 172             soc_is_ar934x() ||
 173             soc_is_qca953x() ||
 174 -           soc_is_qca955x()) {
 175 +           soc_is_qca955x() ||
 176 +           soc_is_qca956x() ||
 177 +           soc_is_tp9343()) {
 178                 ath79_uart_data[0].uartclk = uart_clk_rate;
 179                 platform_device_register(&ath79_uart_device);
 180         } else if (soc_is_ar933x()) {
 181 @@ -155,6 +157,9 @@ void __init ath79_gpio_init(void)
 182         } else if (soc_is_qca955x()) {
 183                 ath79_gpio_pdata.ngpios = QCA955X_GPIO_COUNT;
 184                 ath79_gpio_pdata.oe_inverted = 1;
 185 +       } else if (soc_is_qca956x() || soc_is_tp9343()) {
 186 +               ath79_gpio_pdata.ngpios = QCA956X_GPIO_COUNT;
 187 +               ath79_gpio_pdata.oe_inverted = 1;
 188         } else {
 189                 BUG();
 190         }
 191 --- a/arch/mips/ath79/early_printk.c
 192 +++ b/arch/mips/ath79/early_printk.c
 193 @@ -120,6 +120,8 @@ static void prom_putchar_init(void)
 194         case REV_ID_MAJOR_QCA9533_V2:
 195         case REV_ID_MAJOR_QCA9556:
 196         case REV_ID_MAJOR_QCA9558:
 197 +       case REV_ID_MAJOR_TP9343:
 198 +       case REV_ID_MAJOR_QCA956X:
 199                 _prom_putchar = prom_putchar_ar71xx;
 200                 break;
 201
 202 --- a/arch/mips/ath79/irq.c
 203 +++ b/arch/mips/ath79/irq.c
 204 @@ -156,6 +156,87 @@ static void qca955x_irq_init(void)
 205         irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
 206  }
 207
 208 +static void qca956x_ip2_irq_dispatch(struct irq_desc *desc)
 209 +{
 210 +       u32 status;
 211 +
 212 +       status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
 213 +       status &= QCA956X_EXT_INT_PCIE_RC1_ALL | QCA956X_EXT_INT_WMAC_ALL;
 214 +
 215 +       if (status == 0) {
 216 +               spurious_interrupt();
 217 +               return;
 218 +       }
 219 +
 220 +       if (status & QCA956X_EXT_INT_PCIE_RC1_ALL) {
 221 +               /* TODO: flush DDR? */
 222 +               generic_handle_irq(ATH79_IP2_IRQ(0));
 223 +       }
 224 +
 225 +       if (status & QCA956X_EXT_INT_WMAC_ALL) {
 226 +               /* TODO: flsuh DDR? */
 227 +               generic_handle_irq(ATH79_IP2_IRQ(1));
 228 +       }
 229 +}
 230 +
 231 +static void qca956x_ip3_irq_dispatch(struct irq_desc *desc)
 232 +{
 233 +       u32 status;
 234 +
 235 +       status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
 236 +       status &= QCA956X_EXT_INT_PCIE_RC2_ALL |
 237 +                 QCA956X_EXT_INT_USB1 | QCA956X_EXT_INT_USB2;
 238 +
 239 +       if (status == 0) {
 240 +               spurious_interrupt();
 241 +               return;
 242 +       }
 243 +
 244 +       if (status & QCA956X_EXT_INT_USB1) {
 245 +               /* TODO: flush DDR? */
 246 +               generic_handle_irq(ATH79_IP3_IRQ(0));
 247 +       }
 248 +
 249 +       if (status & QCA956X_EXT_INT_USB2) {
 250 +               /* TODO: flush DDR? */
 251 +               generic_handle_irq(ATH79_IP3_IRQ(1));
 252 +       }
 253 +
 254 +       if (status & QCA956X_EXT_INT_PCIE_RC2_ALL) {
 255 +               /* TODO: flush DDR? */
 256 +               generic_handle_irq(ATH79_IP3_IRQ(2));
 257 +       }
 258 +}
 259 +
 260 +static void qca956x_enable_timer_cb(void) {
 261 +       u32 misc;
 262 +
 263 +       misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
 264 +       misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
 265 +       ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);
 266 +}
 267 +
 268 +static void qca956x_irq_init(void)
 269 +{
 270 +       int i;
 271 +
 272 +       for (i = ATH79_IP2_IRQ_BASE;
 273 +            i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
 274 +               irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
 275 +
 276 +       irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
 277 +
 278 +       for (i = ATH79_IP3_IRQ_BASE;
 279 +            i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
 280 +               irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
 281 +
 282 +       irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
 283 +
 284 +       /* QCA956x timer init workaround has to be applied right before setting
 285 +        * up the clock. Else, there will be no jiffies */
 286 +       late_time_init = &qca956x_enable_timer_cb;
 287 +}
 288 +
 289  void __init arch_init_irq(void)
 290  {
 291         unsigned irq_wb_chan2 = -1;
 292 @@ -183,7 +264,9 @@ void __init arch_init_irq(void)
 293                  soc_is_ar933x() ||
 294                  soc_is_ar934x() ||
 295                  soc_is_qca953x() ||
 296 -                soc_is_qca955x())
 297 +                soc_is_qca955x() ||
 298 +                soc_is_qca956x() ||
 299 +                soc_is_tp9343())
 300                 misc_is_ar71xx = false;
 301         else
 302                 BUG();
 303 @@ -197,4 +280,6 @@ void __init arch_init_irq(void)
 304                 qca953x_irq_init();
 305         else if (soc_is_qca955x())
 306                 qca955x_irq_init();
 307 +       else if (soc_is_qca956x() || soc_is_tp9343())
 308 +               qca956x_irq_init();
 309  }
 310 --- a/arch/mips/ath79/pci.c
 311 +++ b/arch/mips/ath79/pci.c
 312 @@ -82,6 +82,9 @@ int pcibios_map_irq(const struct pci_dev
 313                 } else if (soc_is_qca955x()) {
 314                         ath79_pci_irq_map = qca955x_pci_irq_map;
 315                         ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
 316 +               } else if (soc_is_qca956x()) {
 317 +                       ath79_pci_irq_map = qca956x_pci_irq_map;
 318 +                       ath79_pci_nr_irqs = ARRAY_SIZE(qca956x_pci_irq_map);
 319                 } else {
 320                         pr_crit("pci %s: invalid irq map\n",
 321                                 pci_name((struct pci_dev *) dev));
 322 @@ -261,6 +264,15 @@ int __init ath79_register_pci(void)
 323                                                  QCA955X_PCI_MEM_SIZE,
 324                                                  1,
 325                                                  ATH79_IP3_IRQ(2));
 326 +       } else if (soc_is_qca956x()) {
 327 +               pdev = ath79_register_pci_ar724x(0,
 328 +                                                QCA956X_PCI_CFG_BASE1,
 329 +                                                QCA956X_PCI_CTRL_BASE1,
 330 +                                                QCA956X_PCI_CRP_BASE1,
 331 +                                                QCA956X_PCI_MEM_BASE1,
 332 +                                                QCA956X_PCI_MEM_SIZE,
 333 +                                                1,
 334 +                                                ATH79_IP3_IRQ(2));
 335         } else {
 336                 /* No PCI support */
 337                 return -ENODEV;
 338 --- a/arch/mips/ath79/setup.c
 339 +++ b/arch/mips/ath79/setup.c
 340 @@ -176,6 +176,18 @@ static void __init ath79_detect_sys_type
 341                 rev = id & QCA955X_REV_ID_REVISION_MASK;
 342                 break;
 343
 344 +       case REV_ID_MAJOR_QCA956X:
 345 +               ath79_soc = ATH79_SOC_QCA956X;
 346 +               chip = "956X";
 347 +               rev = id & QCA956X_REV_ID_REVISION_MASK;
 348 +               break;
 349 +
 350 +       case REV_ID_MAJOR_TP9343:
 351 +               ath79_soc = ATH79_SOC_TP9343;
 352 +               chip = "9343";
 353 +               rev = id & QCA956X_REV_ID_REVISION_MASK;
 354 +               break;
 355 +
 356         default:
 357                 panic("ath79: unknown SoC, id:0x%08x", id);
 358         }
 359 @@ -183,9 +195,12 @@ static void __init ath79_detect_sys_type
 360         if (ver == 1)
 361                 ath79_soc_rev = rev;
 362
 363 -       if (soc_is_qca953x() || soc_is_qca955x())
 364 +       if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca956x())
 365                 sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
 366                         chip, ver, rev);
 367 +       else if (soc_is_tp9343())
 368 +               sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u",
 369 +                       chip, rev);
 370         else
 371                 sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
 372         pr_info("SoC: %s\n", ath79_sys_type);
 373 --- a/arch/mips/include/asm/mach-ath79/ath79.h
 374 +++ b/arch/mips/include/asm/mach-ath79/ath79.h
 375 @@ -35,6 +35,8 @@ enum ath79_soc_type {
 376         ATH79_SOC_QCA9533,
 377         ATH79_SOC_QCA9556,
 378         ATH79_SOC_QCA9558,
 379 +       ATH79_SOC_TP9343,
 380 +       ATH79_SOC_QCA956X,
 381  };
 382
 383  extern enum ath79_soc_type ath79_soc;
 384 @@ -126,6 +128,26 @@ static inline int soc_is_qca955x(void)
 385         return soc_is_qca9556() || soc_is_qca9558();
 386  }
 387
 388 +static inline int soc_is_tp9343(void)
 389 +{
 390 +       return ath79_soc == ATH79_SOC_TP9343;
 391 +}
 392 +
 393 +static inline int soc_is_qca9561(void)
 394 +{
 395 +       return ath79_soc == ATH79_SOC_QCA956X;
 396 +}
 397 +
 398 +static inline int soc_is_qca9563(void)
 399 +{
 400 +       return ath79_soc == ATH79_SOC_QCA956X;
 401 +}
 402 +
 403 +static inline int soc_is_qca956x(void)
 404 +{
 405 +       return soc_is_qca9561() || soc_is_qca9563();
 406 +}
 407 +
 408  void ath79_ddr_wb_flush(unsigned int reg);
 409  void ath79_ddr_set_pci_windows(void);
 410