target/linux/ath79/patches-4.19/0025-MIPS-ath79-support-setting-up-clock-via-DT-on-all-So.patch

   1 From 6325626de001df98aebe51f3008b1aca05798d19 Mon Sep 17 00:00:00 2001
   2 From: Felix Fietkau <nbd@nbd.name>
   3 Date: Tue, 6 Mar 2018 13:26:27 +0100
   4 Subject: [PATCH 25/33] MIPS: ath79: support setting up clock via DT on all SoC
   5  types
   6
   7 Use the same functions as the legacy code
   8
   9 Signed-off-by: Felix Fietkau <nbd@nbd.name>
  10 Signed-off-by: John Crispin <john@phrozen.org>
  11 ---
  12  arch/mips/ath79/clock.c | 39 ++++++++++++++++++++++-----------------
  13  1 file changed, 22 insertions(+), 17 deletions(-)
  14
  15 --- a/arch/mips/ath79/clock.c
  16 +++ b/arch/mips/ath79/clock.c
  17 @@ -669,16 +669,6 @@ ath79_get_sys_clk_rate(const char *id)
  18  #ifdef CONFIG_OF
  19  static void __init ath79_clocks_init_dt(struct device_node *np)
  20  {
  21 -       of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
  22 -}
  23 -
  24 -CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt);
  25 -CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt);
  26 -CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt);
  27 -CLK_OF_DECLARE(ar9550, "qca,qca9550-pll", ath79_clocks_init_dt);
  28 -
  29 -static void __init ath79_clocks_init_dt_ng(struct device_node *np)
  30 -{
  31         struct clk *ref_clk;
  32         void __iomem *pll_base;
  33
  34 @@ -692,14 +682,21 @@ static void __init ath79_clocks_init_dt_
  35                 goto err_clk;
  36         }
  37
  38 -       if (of_device_is_compatible(np, "qca,ar9130-pll"))
  39 +       if (of_device_is_compatible(np, "qca,ar7100-pll"))
  40 +               ar71xx_clocks_init(pll_base);
  41 +       else if (of_device_is_compatible(np, "qca,ar7240-pll") ||
  42 +                of_device_is_compatible(np, "qca,ar9130-pll"))
  43                 ar724x_clocks_init(pll_base);
  44         else if (of_device_is_compatible(np, "qca,ar9330-pll"))
  45                 ar933x_clocks_init(pll_base);
  46 -       else {
  47 -               pr_err("%pOF: could not find any appropriate clk_init()\n", np);
  48 -               goto err_iounmap;
  49 -       }
  50 +       else if (of_device_is_compatible(np, "qca,ar9340-pll"))
  51 +               ar934x_clocks_init(pll_base);
  52 +       else if (of_device_is_compatible(np, "qca,qca9530-pll"))
  53 +               qca953x_clocks_init(pll_base);
  54 +       else if (of_device_is_compatible(np, "qca,qca9550-pll"))
  55 +               qca955x_clocks_init(pll_base);
  56 +       else if (of_device_is_compatible(np, "qca,qca9560-pll"))
  57 +               qca956x_clocks_init(pll_base);
  58
  59         if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
  60                 pr_err("%pOF: could not register clk provider\n", np);
  61 @@ -714,6 +711,14 @@ err_iounmap:
  62  err_clk:
  63         clk_put(ref_clk);
  64  }
  65 -CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt_ng);
  66 -CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt_ng);
  67 +
  68 +CLK_OF_DECLARE(ar7100_clk, "qca,ar7100-pll", ath79_clocks_init_dt);
  69 +CLK_OF_DECLARE(ar7240_clk, "qca,ar7240-pll", ath79_clocks_init_dt);
  70 +CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt);
  71 +CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt);
  72 +CLK_OF_DECLARE(ar9340_clk, "qca,ar9340-pll", ath79_clocks_init_dt);
  73 +CLK_OF_DECLARE(ar9530_clk, "qca,qca9530-pll", ath79_clocks_init_dt);
  74 +CLK_OF_DECLARE(ar9550_clk, "qca,qca9550-pll", ath79_clocks_init_dt);
  75 +CLK_OF_DECLARE(ar9560_clk, "qca,qca9560-pll", ath79_clocks_init_dt);
  76 +
  77  #endif