target/linux/ath79/patches-4.19/0026-MIPS-ath79-export-switch-MDIO-reference-clock.patch

   1 From 78538d673801902108797f2c813e70cfbce280c9 Mon Sep 17 00:00:00 2001
   2 From: Felix Fietkau <nbd@nbd.name>
   3 Date: Tue, 6 Mar 2018 13:27:28 +0100
   4 Subject: [PATCH 26/33] MIPS: ath79: export switch MDIO reference clock
   5
   6 On AR934x, the MDIO reference clock can be configured to a fixed 100 MHz
   7 clock. If that feature is not used, it defaults to the main reference
   8 clock, like on all other SoC.
   9
  10 Signed-off-by: Felix Fietkau <nbd@nbd.name>
  11 Signed-off-by: John Crispin <john@phrozen.org>
  12 ---
  13  arch/mips/ath79/clock.c               | 8 ++++++++
  14  include/dt-bindings/clock/ath79-clk.h | 3 ++-
  15  2 files changed, 10 insertions(+), 1 deletion(-)
  16
  17 --- a/arch/mips/ath79/clock.c
  18 +++ b/arch/mips/ath79/clock.c
  19 @@ -42,6 +42,7 @@ static const char * const clk_names[ATH7
  20         [ATH79_CLK_DDR] = "ddr",
  21         [ATH79_CLK_AHB] = "ahb",
  22         [ATH79_CLK_REF] = "ref",
  23 +       [ATH79_CLK_MDIO] = "mdio",
  24  };
  25
  26  static const char * __init ath79_clk_name(int type)
  27 @@ -342,6 +343,10 @@ static void __init ar934x_clocks_init(vo
  28         ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
  29         ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
  30
  31 +       clk_ctrl = __raw_readl(pll_base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
  32 +       if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL)
  33 +               ath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000);
  34 +
  35         iounmap(dpll_base);
  36  }
  37
  38 @@ -698,6 +703,9 @@ static void __init ath79_clocks_init_dt(
  39         else if (of_device_is_compatible(np, "qca,qca9560-pll"))
  40                 qca956x_clocks_init(pll_base);
  41
  42 +       if (!clks[ATH79_CLK_MDIO])
  43 +               clks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF];
  44 +
  45         if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
  46                 pr_err("%pOF: could not register clk provider\n", np);
  47                 goto err_iounmap;
  48 --- a/include/dt-bindings/clock/ath79-clk.h
  49 +++ b/include/dt-bindings/clock/ath79-clk.h
  50 @@ -14,7 +14,8 @@
  51  #define ATH79_CLK_DDR          1
  52  #define ATH79_CLK_AHB          2
  53  #define ATH79_CLK_REF          3
  54 +#define ATH79_CLK_MDIO         4
  55
  56 -#define ATH79_CLK_END          4
  57 +#define ATH79_CLK_END          5
  58
  59  #endif /* __DT_BINDINGS_ATH79_CLK_H */