target/linux/ath79/patches-5.4/0019-dt-bindings-PCI-qcom-ar7240-adds-binding-doc.patch

   1 From ea27764bc3ef2a05decf3ae05edffc289cd0d93c Mon Sep 17 00:00:00 2001
   2 From: John Crispin <john@phrozen.org>
   3 Date: Mon, 25 Jun 2018 15:52:02 +0200
   4 Subject: [PATCH 19/33] dt-bindings: PCI: qcom,ar7240: adds binding doc
   5
   6 With the driver being converted from platform_data to pure OF, we need to
   7 also add some docs.
   8
   9 Cc: Rob Herring <robh+dt@kernel.org>
  10 Cc: devicetree@vger.kernel.org
  11 Signed-off-by: John Crispin <john@phrozen.org>
  12 ---
  13  .../devicetree/bindings/pci/qcom,ar7240-pci.txt    | 42 ++++++++++++++++++++++
  14  1 file changed, 42 insertions(+)
  15  create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt
  16
  17 --- /dev/null
  18 +++ b/Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt
  19 @@ -0,0 +1,42 @@
  20 +* Qualcomm Atheros AR724X PCI express root complex
  21 +
  22 +Required properties:
  23 +- compatible: should contain "qcom,ar7240-pci" to identify the core.
  24 +- reg: Should contain the register ranges as listed in the reg-names property.
  25 +- reg-names: Definition: Must include the following entries
  26 +       - "crp_base"    Configuration registers
  27 +       - "ctrl_base"   Control registers
  28 +       - "cfg_base"    IO Memory
  29 +- #address-cells: set to <3>
  30 +- #size-cells: set to <2>
  31 +- ranges: ranges for the PCI memory and I/O regions
  32 +- interrupt-map-mask and interrupt-map: standard PCI
  33 +       properties to define the mapping of the PCIe interface to interrupt
  34 +       numbers.
  35 +- #interrupt-cells: set to <1>
  36 +- interrupt-parent: phandle to the MIPS IRQ controller
  37 +
  38 +Optional properties:
  39 +- interrupt-controller: define to enable the builtin IRQ cascade.
  40 +
  41 +* Example for qca9557
  42 +       pcie-controller@180c0000 {
  43 +               compatible = "qcom,ar7240-pci";
  44 +               #address-cells = <3>;
  45 +               #size-cells = <2>;
  46 +               bus-range = <0x0 0x0>;
  47 +               reg = <0x180c0000 0x1000>,
  48 +                     <0x180f0000 0x100>,
  49 +                     <0x14000000 0x1000>;
  50 +               reg-names = "crp_base", "ctrl_base", "cfg_base";
  51 +               ranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000
  52 +                         0x1000000 0 0x00000000 0x00000000 0 0x00000001>;
  53 +               interrupt-parent = <&intc2>;
  54 +               interrupts = <1>;
  55 +
  56 +               interrupt-controller;
  57 +               #interrupt-cells = <1>;
  58 +
  59 +               interrupt-map-mask = <0 0 0 1>;
  60 +               interrupt-map = <0 0 0 0 &pcie0 0>;
  61 +       };