target/linux/ath79/patches-5.4/0051-spi-add-driver-for-ar934x-spi-controller.patch

   1 From 7e161c423a232ef7ddf6c11b09ebe471dd5a23cf Mon Sep 17 00:00:00 2001
   2 From: Chuanhong Guo <gch981213@gmail.com>
   3 Date: Wed, 5 Feb 2020 18:25:37 +0800
   4 Subject: [PATCH v4 1/2] spi: add driver for ar934x spi controller
   5
   6 This patch adds driver for SPI controller found in Qualcomm Atheros
   7 AR934x/QCA95xx SoCs.
   8 This controller is a superset of the already supported qca,ar7100-spi.
   9 Besides the bit-bang mode in spi-ath79.c, this new controller added
  10 a new "shift register" mode, allowing faster spi operations.
  11
  12 Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
  13 ---
  14  drivers/spi/Kconfig      |   7 ++
  15  drivers/spi/Makefile     |   1 +
  16  drivers/spi/spi-ar934x.c | 235 +++++++++++++++++++++++++++++++++++++++
  17  3 files changed, 243 insertions(+)
  18  create mode 100644 drivers/spi/spi-ar934x.c
  19
  20 --- a/drivers/spi/Kconfig
  21 +++ b/drivers/spi/Kconfig
  22 @@ -62,6 +62,13 @@ config SPI_ALTERA
  23         help
  24           This is the driver for the Altera SPI Controller.
  25
  26 +config SPI_AR934X
  27 +       tristate "Qualcomm Atheros AR934X/QCA95XX SPI controller driver"
  28 +       depends on ATH79 || COMPILE_TEST
  29 +       help
  30 +         This enables support for the SPI controller present on the
  31 +         Qualcomm Atheros AR934X/QCA95XX SoCs.
  32 +
  33  config SPI_ATH79
  34         tristate "Atheros AR71XX/AR724X/AR913X SPI controller driver"
  35         depends on ATH79 || COMPILE_TEST
  36 --- a/drivers/spi/Makefile
  37 +++ b/drivers/spi/Makefile
  38 @@ -14,6 +14,7 @@ obj-$(CONFIG_SPI_LOOPBACK_TEST)               += spi-
  39
  40  # SPI master controller drivers (bus)
  41  obj-$(CONFIG_SPI_ALTERA)               += spi-altera.o
  42 +obj-$(CONFIG_SPI_AR934X)               += spi-ar934x.o
  43  obj-$(CONFIG_SPI_ARMADA_3700)          += spi-armada-3700.o
  44  obj-$(CONFIG_SPI_ATMEL)                        += spi-atmel.o
  45  obj-$(CONFIG_SPI_ATMEL_QUADSPI)                += atmel-quadspi.o
  46 --- /dev/null
  47 +++ b/drivers/spi/spi-ar934x.c
  48 @@ -0,0 +1,235 @@
  49 +// SPDX-License-Identifier: GPL-2.0
  50 +//
  51 +// SPI controller driver for Qualcomm Atheros AR934x/QCA95xx SoCs
  52 +//
  53 +// Copyright (C) 2020 Chuanhong Guo <gch981213@gmail.com>
  54 +//
  55 +// Based on spi-mt7621.c:
  56 +// Copyright (C) 2011 Sergiy <piratfm@gmail.com>
  57 +// Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
  58 +// Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
  59 +
  60 +#include <linux/clk.h>
  61 +#include <linux/io.h>
  62 +#include <linux/iopoll.h>
  63 +#include <linux/kernel.h>
  64 +#include <linux/module.h>
  65 +#include <linux/of_device.h>
  66 +#include <linux/spi/spi.h>
  67 +
  68 +#define DRIVER_NAME "spi-ar934x"
  69 +
  70 +#define AR934X_SPI_REG_FS              0x00
  71 +#define AR934X_SPI_ENABLE              BIT(0)
  72 +
  73 +#define AR934X_SPI_REG_IOC             0x08
  74 +#define AR934X_SPI_IOC_INITVAL         0x70000
  75 +
  76 +#define AR934X_SPI_REG_CTRL            0x04
  77 +#define AR934X_SPI_CLK_MASK            GENMASK(5, 0)
  78 +
  79 +#define AR934X_SPI_DATAOUT             0x10
  80 +
  81 +#define AR934X_SPI_REG_SHIFT_CTRL      0x14
  82 +#define AR934X_SPI_SHIFT_EN            BIT(31)
  83 +#define AR934X_SPI_SHIFT_CS(n)         BIT(28 + (n))
  84 +#define AR934X_SPI_SHIFT_TERM          26
  85 +#define AR934X_SPI_SHIFT_VAL(cs, term, count)                  \
  86 +       (AR934X_SPI_SHIFT_EN | AR934X_SPI_SHIFT_CS(cs) |        \
  87 +       (term) << AR934X_SPI_SHIFT_TERM | (count))
  88 +
  89 +#define AR934X_SPI_DATAIN 0x18
  90 +
  91 +struct ar934x_spi {
  92 +       struct spi_controller *ctlr;
  93 +       void __iomem *base;
  94 +       struct clk *clk;
  95 +       unsigned int clk_freq;
  96 +};
  97 +
  98 +static inline int ar934x_spi_clk_div(struct ar934x_spi *sp, unsigned int freq)
  99 +{
 100 +       int div = DIV_ROUND_UP(sp->clk_freq, freq * 2) - 1;
 101 +
 102 +       if (div < 0)
 103 +               return 0;
 104 +       else if (div > AR934X_SPI_CLK_MASK)
 105 +               return -EINVAL;
 106 +       else
 107 +               return div;
 108 +}
 109 +
 110 +static int ar934x_spi_setup(struct spi_device *spi)
 111 +{
 112 +       struct ar934x_spi *sp = spi_controller_get_devdata(spi->master);
 113 +
 114 +       if ((spi->max_speed_hz == 0) ||
 115 +           (spi->max_speed_hz > (sp->clk_freq / 2))) {
 116 +               spi->max_speed_hz = sp->clk_freq / 2;
 117 +       } else if (spi->max_speed_hz < (sp->clk_freq / 128)) {
 118 +               dev_err(&spi->dev, "spi clock is too low\n");
 119 +               return -EINVAL;
 120 +       }
 121 +
 122 +       return 0;
 123 +}
 124 +
 125 +static int ar934x_spi_transfer_one_message(struct spi_controller *master,
 126 +                                          struct spi_message *m)
 127 +{
 128 +       struct ar934x_spi *sp = spi_controller_get_devdata(master);
 129 +       struct spi_transfer *t = NULL;
 130 +       struct spi_device *spi = m->spi;
 131 +       unsigned long trx_done, trx_cur;
 132 +       int stat = 0;
 133 +       u8 term = 0;
 134 +       int div, i;
 135 +       u32 reg;
 136 +       const u8 *tx_buf;
 137 +       u8 *buf;
 138 +
 139 +       m->actual_length = 0;
 140 +       list_for_each_entry(t, &m->transfers, transfer_list) {
 141 +               if (t->speed_hz)
 142 +                       div = ar934x_spi_clk_div(sp, t->speed_hz);
 143 +               else
 144 +                       div = ar934x_spi_clk_div(sp, spi->max_speed_hz);
 145 +               if (div < 0) {
 146 +                       stat = -EIO;
 147 +                       goto msg_done;
 148 +               }
 149 +
 150 +               reg = ioread32(sp->base + AR934X_SPI_REG_CTRL);
 151 +               reg &= ~AR934X_SPI_CLK_MASK;
 152 +               reg |= div;
 153 +               iowrite32(reg, sp->base + AR934X_SPI_REG_CTRL);
 154 +               iowrite32(0, sp->base + AR934X_SPI_DATAOUT);
 155 +
 156 +               for (trx_done = 0; trx_done < t->len; trx_done += 4) {
 157 +                       trx_cur = t->len - trx_done;
 158 +                       if (trx_cur > 4)
 159 +                               trx_cur = 4;
 160 +                       else if (list_is_last(&t->transfer_list, &m->transfers))
 161 +                               term = 1;
 162 +
 163 +                       if (t->tx_buf) {
 164 +                               tx_buf = t->tx_buf + trx_done;
 165 +                               reg = tx_buf[0];
 166 +                               for (i = 1; i < trx_cur; i++)
 167 +                                       reg = reg << 8 | tx_buf[i];
 168 +                               iowrite32(reg, sp->base + AR934X_SPI_DATAOUT);
 169 +                       }
 170 +
 171 +                       reg = AR934X_SPI_SHIFT_VAL(spi->chip_select, term,
 172 +                                                  trx_cur * 8);
 173 +                       iowrite32(reg, sp->base + AR934X_SPI_REG_SHIFT_CTRL);
 174 +                       stat = readl_poll_timeout(
 175 +                               sp->base + AR934X_SPI_REG_SHIFT_CTRL, reg,
 176 +                               !(reg & AR934X_SPI_SHIFT_EN), 0, 5);
 177 +                       if (stat < 0)
 178 +                               goto msg_done;
 179 +
 180 +                       if (t->rx_buf) {
 181 +                               reg = ioread32(sp->base + AR934X_SPI_DATAIN);
 182 +                               buf = t->rx_buf + trx_done;
 183 +                               for (i = 0; i < trx_cur; i++) {
 184 +                                       buf[trx_cur - i - 1] = reg & 0xff;
 185 +                                       reg >>= 8;
 186 +                               }
 187 +                       }
 188 +               }
 189 +               m->actual_length += t->len;
 190 +       }
 191 +
 192 +msg_done:
 193 +       m->status = stat;
 194 +       spi_finalize_current_message(master);
 195 +
 196 +       return 0;
 197 +}
 198 +
 199 +static const struct of_device_id ar934x_spi_match[] = {
 200 +       { .compatible = "qca,ar934x-spi" },
 201 +       {},
 202 +};
 203 +MODULE_DEVICE_TABLE(of, ar934x_spi_match);
 204 +
 205 +static int ar934x_spi_probe(struct platform_device *pdev)
 206 +{
 207 +       struct spi_controller *ctlr;
 208 +       struct ar934x_spi *sp;
 209 +       void __iomem *base;
 210 +       struct clk *clk;
 211 +       int ret;
 212 +
 213 +       base = devm_platform_ioremap_resource(pdev, 0);
 214 +       if (IS_ERR(base))
 215 +               return PTR_ERR(base);
 216 +
 217 +       clk = devm_clk_get(&pdev->dev, NULL);
 218 +       if (IS_ERR(clk)) {
 219 +               dev_err(&pdev->dev, "failed to get clock\n");
 220 +               return PTR_ERR(clk);
 221 +       }
 222 +
 223 +       ret = clk_prepare_enable(clk);
 224 +       if (ret)
 225 +               return ret;
 226 +
 227 +       ctlr = spi_alloc_master(&pdev->dev, sizeof(*sp));
 228 +       if (!ctlr) {
 229 +               dev_info(&pdev->dev, "failed to allocate spi controller\n");
 230 +               return -ENOMEM;
 231 +       }
 232 +
 233 +       /* disable flash mapping and expose spi controller registers */
 234 +       iowrite32(AR934X_SPI_ENABLE, base + AR934X_SPI_REG_FS);
 235 +       /* restore pins to default state: CSn=1 DO=CLK=0 */
 236 +       iowrite32(AR934X_SPI_IOC_INITVAL, base + AR934X_SPI_REG_IOC);
 237 +
 238 +       ctlr->mode_bits = SPI_LSB_FIRST;
 239 +       ctlr->setup = ar934x_spi_setup;
 240 +       ctlr->transfer_one_message = ar934x_spi_transfer_one_message;
 241 +       ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
 242 +       ctlr->dev.of_node = pdev->dev.of_node;
 243 +       ctlr->num_chipselect = 3;
 244 +
 245 +       dev_set_drvdata(&pdev->dev, ctlr);
 246 +
 247 +       sp = spi_controller_get_devdata(ctlr);
 248 +       sp->base = base;
 249 +       sp->clk = clk;
 250 +       sp->clk_freq = clk_get_rate(clk);
 251 +       sp->ctlr = ctlr;
 252 +
 253 +       return devm_spi_register_controller(&pdev->dev, ctlr);
 254 +}
 255 +
 256 +static int ar934x_spi_remove(struct platform_device *pdev)
 257 +{
 258 +       struct spi_controller *ctlr;
 259 +       struct ar934x_spi *sp;
 260 +
 261 +       ctlr = dev_get_drvdata(&pdev->dev);
 262 +       sp = spi_controller_get_devdata(ctlr);
 263 +
 264 +       clk_disable_unprepare(sp->clk);
 265 +
 266 +       return 0;
 267 +}
 268 +
 269 +static struct platform_driver ar934x_spi_driver = {
 270 +       .driver = {
 271 +               .name = DRIVER_NAME,
 272 +               .of_match_table = ar934x_spi_match,
 273 +       },
 274 +       .probe = ar934x_spi_probe,
 275 +       .remove = ar934x_spi_remove,
 276 +};
 277 +
 278 +module_platform_driver(ar934x_spi_driver);
 279 +
 280 +MODULE_DESCRIPTION("SPI controller driver for Qualcomm Atheros AR934x/QCA95xx");
 281 +MODULE_AUTHOR("Chuanhong Guo <gch981213@gmail.com>");
 282 +MODULE_LICENSE("GPL v2");
 283 +MODULE_ALIAS("platform:" DRIVER_NAME);