target/linux/ath79/patches-5.4/0062-MIPS-pci-ar724x-add-QCA9550-reset-sequence.patch

   1 From: David Bauer <mail@david-bauer.net>
   2 Date: Sat, 11 Apr 2020 14:03:12 +0200
   3 Subject: MIPS: pci-ar724x: add QCA9550 reset sequence
   4
   5 The QCA9550 family of SoCs have a slightly different reset
   6 sequence compared to older chips.
   7
   8 Normally the bootloader performs this sequence, however
   9 some bootloader implementation expect the operating system
  10 to clear the reset.
  11
  12 Also get the resets from OF to support handling of the second
  13 PCIe root-complex on the QCA9558.
  14
  15 Signed-off-by: David Bauer <mail@david-bauer.net>
  16
  17 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  18 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  19 @@ -391,6 +391,7 @@
  20  #define QCA955X_PLL_CPU_CONFIG_REG             0x00
  21  #define QCA955X_PLL_DDR_CONFIG_REG             0x04
  22  #define QCA955X_PLL_CLK_CTRL_REG               0x08
  23 +#define QCA955X_PLL_PCIE_CONFIG_REG            0x0c
  24  #define QCA955X_PLL_ETH_XMII_CONTROL_REG       0x28
  25  #define QCA955X_PLL_ETH_SGMII_CONTROL_REG      0x48
  26  #define QCA955X_PLL_ETH_SGMII_SERDES_REG       0x4c
  27 @@ -476,6 +477,9 @@
  28  #define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL    BIT(21)
  29  #define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL                BIT(24)
  30
  31 +#define QCA955X_PLL_PCIE_CONFIG_PLL_PWD                        BIT(30)
  32 +#define QCA955X_PLL_PCIE_CONFIG_PLL_BYPASS             BIT(16)
  33 +
  34  #define QCA956X_PLL_SWITCH_CLOCK_SPARE_I2C_CLK_SELB            BIT(5)
  35  #define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1         BIT(6)
  36  #define QCA956X_PLL_SWITCH_CLOCK_SPARE_UART1_CLK_SEL           BIT(7)
  37 --- a/arch/mips/pci/pci-ar724x.c
  38 +++ b/arch/mips/pci/pci-ar724x.c
  39 @@ -8,6 +8,7 @@
  40
  41  #include <linux/irq.h>
  42  #include <linux/pci.h>
  43 +#include <linux/reset.h>
  44  #include <linux/init.h>
  45  #include <linux/delay.h>
  46  #include <linux/platform_device.h>
  47 @@ -55,6 +56,9 @@ struct ar724x_pci_controller {
  48         struct irq_domain *domain;
  49         struct resource io_res;
  50         struct resource mem_res;
  51 +
  52 +       struct reset_control *hc_reset;
  53 +       struct reset_control *phy_reset;
  54  };
  55
  56  static struct irq_chip ar724x_pci_irq_chip;
  57 @@ -340,18 +344,30 @@ static void ar724x_pci_hw_init(struct ar
  58         int wait = 0;
  59
  60         /* deassert PCIe host controller and PCIe PHY reset */
  61 -       ath79_device_reset_clear(AR724X_RESET_PCIE);
  62 -       ath79_device_reset_clear(AR724X_RESET_PCIE_PHY);
  63 +       reset_control_deassert(apc->hc_reset);
  64 +       reset_control_deassert(apc->phy_reset);
  65
  66 -       /* remove the reset of the PCIE PLL */
  67 -       ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
  68 -       ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET;
  69 -       ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
  70 -
  71 -       /* deassert bypass for the PCIE PLL */
  72 -       ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
  73 -       ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;
  74 -       ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
  75 +       if (of_device_is_compatible(apc->np, "qcom,qca9550-pci")) {
  76 +               /* remove the reset of the PCIE PLL */
  77 +               ppl = ath79_pll_rr(QCA955X_PLL_PCIE_CONFIG_REG);
  78 +               ppl &= ~QCA955X_PLL_PCIE_CONFIG_PLL_PWD;
  79 +               ath79_pll_wr(QCA955X_PLL_PCIE_CONFIG_REG, ppl);
  80 +
  81 +               /* deassert bypass for the PCIE PLL */
  82 +               ppl = ath79_pll_rr(QCA955X_PLL_PCIE_CONFIG_REG);
  83 +               ppl &= ~QCA955X_PLL_PCIE_CONFIG_PLL_BYPASS;
  84 +               ath79_pll_wr(QCA955X_PLL_PCIE_CONFIG_REG, ppl);
  85 +       } else {
  86 +               /* remove the reset of the PCIE PLL */
  87 +               ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
  88 +               ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET;
  89 +               ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
  90 +
  91 +               /* deassert bypass for the PCIE PLL */
  92 +               ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
  93 +               ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;
  94 +               ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
  95 +       }
  96
  97         /* set PCIE Application Control to ready */
  98         app = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP);
  99 @@ -399,6 +415,14 @@ static int ar724x_pci_probe(struct platf
 100         if (apc->irq < 0)
 101                 return -EINVAL;
 102
 103 +       apc->hc_reset = devm_reset_control_get_exclusive(&pdev->dev, "hc");
 104 +       if (IS_ERR(apc->hc_reset))
 105 +               return PTR_ERR(apc->hc_reset);
 106 +
 107 +       apc->phy_reset = devm_reset_control_get_exclusive(&pdev->dev, "phy");
 108 +       if (IS_ERR(apc->phy_reset))
 109 +               return PTR_ERR(apc->phy_reset);
 110 +
 111         apc->np = pdev->dev.of_node;
 112         apc->pci_controller.pci_ops = &ar724x_pci_ops;
 113         apc->pci_controller.io_resource = &apc->io_res;
 114 @@ -409,7 +433,7 @@ static int ar724x_pci_probe(struct platf
 115          * Do the full PCIE Root Complex Initialization Sequence if the PCIe
 116          * host controller is in reset.
 117          */
 118 -       if (ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE) & AR724X_RESET_PCIE)
 119 +       if (reset_control_status(apc->hc_reset))
 120                 ar724x_pci_hw_init(apc);
 121
 122         apc->link_up = ar724x_pci_check_link(apc);
 123 @@ -427,6 +451,7 @@ static int ar724x_pci_probe(struct platf
 124
 125  static const struct of_device_id ar724x_pci_ids[] = {
 126         { .compatible = "qcom,ar7240-pci" },
 127 +       { .compatible = "qcom,qca9550-pci" },
 128         {},
 129  };
 130