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[openwrt/openwrt.git] / target / linux / atheros / patches-2.6.28 / 110-ar2313_ethernet.patch
1 --- a/drivers/net/Kconfig
2 +++ b/drivers/net/Kconfig
3 @@ -359,6 +359,12 @@ config AX88796_93CX6
4 help
5 Select this if your platform comes with an external 93CX6 eeprom.
6
7 +config AR231X_ETHERNET
8 + tristate "AR231x Ethernet support"
9 + depends on NET_ETHERNET && ATHEROS
10 + help
11 + Support for the AR231x/531x ethernet controller
12 +
13 config MACE
14 tristate "MACE (Power Mac ethernet) support"
15 depends on PPC_PMAC && PPC32
16 --- a/drivers/net/Makefile
17 +++ b/drivers/net/Makefile
18 @@ -199,6 +199,7 @@ obj-$(CONFIG_EQUALIZER) += eql.o
19 obj-$(CONFIG_KORINA) += korina.o
20 obj-$(CONFIG_MIPS_JAZZ_SONIC) += jazzsonic.o
21 obj-$(CONFIG_MIPS_AU1X00_ENET) += au1000_eth.o
22 +obj-$(CONFIG_AR231X_ETHERNET) += ar231x.o
23 obj-$(CONFIG_MIPS_SIM_NET) += mipsnet.o
24 obj-$(CONFIG_SGI_IOC3_ETH) += ioc3-eth.o
25 obj-$(CONFIG_DECLANCE) += declance.o
26 --- /dev/null
27 +++ b/drivers/net/ar231x.c
28 @@ -0,0 +1,1264 @@
29 +/*
30 + * ar231x.c: Linux driver for the Atheros AR231x Ethernet device.
31 + *
32 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
33 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
34 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
35 + *
36 + * Thanks to Atheros for providing hardware and documentation
37 + * enabling me to write this driver.
38 + *
39 + * This program is free software; you can redistribute it and/or modify
40 + * it under the terms of the GNU General Public License as published by
41 + * the Free Software Foundation; either version 2 of the License, or
42 + * (at your option) any later version.
43 + *
44 + * Additional credits:
45 + * This code is taken from John Taylor's Sibyte driver and then
46 + * modified for the AR2313.
47 + */
48 +
49 +#include <linux/module.h>
50 +#include <linux/version.h>
51 +#include <linux/types.h>
52 +#include <linux/errno.h>
53 +#include <linux/ioport.h>
54 +#include <linux/pci.h>
55 +#include <linux/netdevice.h>
56 +#include <linux/etherdevice.h>
57 +#include <linux/skbuff.h>
58 +#include <linux/init.h>
59 +#include <linux/delay.h>
60 +#include <linux/mm.h>
61 +#include <linux/highmem.h>
62 +#include <linux/sockios.h>
63 +#include <linux/pkt_sched.h>
64 +#include <linux/mii.h>
65 +#include <linux/phy.h>
66 +#include <linux/ethtool.h>
67 +#include <linux/ctype.h>
68 +#include <linux/platform_device.h>
69 +
70 +#include <net/sock.h>
71 +#include <net/ip.h>
72 +
73 +#include <asm/system.h>
74 +#include <asm/io.h>
75 +#include <asm/irq.h>
76 +#include <asm/byteorder.h>
77 +#include <asm/uaccess.h>
78 +#include <asm/bootinfo.h>
79 +
80 +#define AR2313_MTU 1692
81 +#define AR2313_PRIOS 1
82 +#define AR2313_QUEUES (2*AR2313_PRIOS)
83 +#define AR2313_DESCR_ENTRIES 64
84 +
85 +
86 +#ifndef min
87 +#define min(a,b) (((a)<(b))?(a):(b))
88 +#endif
89 +
90 +#ifndef SMP_CACHE_BYTES
91 +#define SMP_CACHE_BYTES L1_CACHE_BYTES
92 +#endif
93 +
94 +#define AR2313_MBOX_SET_BIT 0x8
95 +
96 +#include "ar231x.h"
97 +
98 +/*
99 + * New interrupt handler strategy:
100 + *
101 + * An old interrupt handler worked using the traditional method of
102 + * replacing an skbuff with a new one when a packet arrives. However
103 + * the rx rings do not need to contain a static number of buffer
104 + * descriptors, thus it makes sense to move the memory allocation out
105 + * of the main interrupt handler and do it in a bottom half handler
106 + * and only allocate new buffers when the number of buffers in the
107 + * ring is below a certain threshold. In order to avoid starving the
108 + * NIC under heavy load it is however necessary to force allocation
109 + * when hitting a minimum threshold. The strategy for alloction is as
110 + * follows:
111 + *
112 + * RX_LOW_BUF_THRES - allocate buffers in the bottom half
113 + * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
114 + * the buffers in the interrupt handler
115 + * RX_RING_THRES - maximum number of buffers in the rx ring
116 + *
117 + * One advantagous side effect of this allocation approach is that the
118 + * entire rx processing can be done without holding any spin lock
119 + * since the rx rings and registers are totally independent of the tx
120 + * ring and its registers. This of course includes the kmalloc's of
121 + * new skb's. Thus start_xmit can run in parallel with rx processing
122 + * and the memory allocation on SMP systems.
123 + *
124 + * Note that running the skb reallocation in a bottom half opens up
125 + * another can of races which needs to be handled properly. In
126 + * particular it can happen that the interrupt handler tries to run
127 + * the reallocation while the bottom half is either running on another
128 + * CPU or was interrupted on the same CPU. To get around this the
129 + * driver uses bitops to prevent the reallocation routines from being
130 + * reentered.
131 + *
132 + * TX handling can also be done without holding any spin lock, wheee
133 + * this is fun! since tx_csm is only written to by the interrupt
134 + * handler.
135 + */
136 +
137 +/*
138 + * Threshold values for RX buffer allocation - the low water marks for
139 + * when to start refilling the rings are set to 75% of the ring
140 + * sizes. It seems to make sense to refill the rings entirely from the
141 + * intrrupt handler once it gets below the panic threshold, that way
142 + * we don't risk that the refilling is moved to another CPU when the
143 + * one running the interrupt handler just got the slab code hot in its
144 + * cache.
145 + */
146 +#define RX_RING_SIZE AR2313_DESCR_ENTRIES
147 +#define RX_PANIC_THRES (RX_RING_SIZE/4)
148 +#define RX_LOW_THRES ((3*RX_RING_SIZE)/4)
149 +#define CRC_LEN 4
150 +#define RX_OFFSET 2
151 +
152 +#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
153 +#define VLAN_HDR 4
154 +#else
155 +#define VLAN_HDR 0
156 +#endif
157 +
158 +#define AR2313_BUFSIZE (AR2313_MTU + VLAN_HDR + ETH_HLEN + CRC_LEN + RX_OFFSET)
159 +
160 +#ifdef MODULE
161 +MODULE_LICENSE("GPL");
162 +MODULE_AUTHOR("Sameer Dekate <sdekate@arubanetworks.com>, Imre Kaloz <kaloz@openwrt.org>, Felix Fietkau <nbd@openwrt.org>");
163 +MODULE_DESCRIPTION("AR231x Ethernet driver");
164 +#endif
165 +
166 +#define virt_to_phys(x) ((u32)(x) & 0x1fffffff)
167 +
168 +// prototypes
169 +static void ar231x_halt(struct net_device *dev);
170 +static void rx_tasklet_func(unsigned long data);
171 +static void rx_tasklet_cleanup(struct net_device *dev);
172 +static void ar231x_multicast_list(struct net_device *dev);
173 +
174 +static int ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum);
175 +static int ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value);
176 +static int ar231x_mdiobus_reset(struct mii_bus *bus);
177 +static int ar231x_mdiobus_probe (struct net_device *dev);
178 +static void ar231x_adjust_link(struct net_device *dev);
179 +
180 +#ifndef ERR
181 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
182 +#endif
183 +
184 +
185 +int __init ar231x_probe(struct platform_device *pdev)
186 +{
187 + struct net_device *dev;
188 + struct ar231x_private *sp;
189 + struct resource *res;
190 + unsigned long ar_eth_base;
191 + char buf[64];
192 +
193 + dev = alloc_etherdev(sizeof(struct ar231x_private));
194 +
195 + if (dev == NULL) {
196 + printk(KERN_ERR
197 + "ar231x: Unable to allocate net_device structure!\n");
198 + return -ENOMEM;
199 + }
200 +
201 + platform_set_drvdata(pdev, dev);
202 +
203 + sp = netdev_priv(dev);
204 + sp->dev = dev;
205 + sp->cfg = pdev->dev.platform_data;
206 +
207 + sprintf(buf, "eth%d_membase", pdev->id);
208 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, buf);
209 + if (!res)
210 + return -ENODEV;
211 +
212 + sp->link = 0;
213 + ar_eth_base = res->start;
214 +
215 + sprintf(buf, "eth%d_irq", pdev->id);
216 + dev->irq = platform_get_irq_byname(pdev, buf);
217 +
218 + spin_lock_init(&sp->lock);
219 +
220 + /* initialize func pointers */
221 + dev->open = &ar231x_open;
222 + dev->stop = &ar231x_close;
223 + dev->hard_start_xmit = &ar231x_start_xmit;
224 +
225 + dev->set_multicast_list = &ar231x_multicast_list;
226 + dev->do_ioctl = &ar231x_ioctl;
227 +
228 + // SAMEER: do we need this?
229 + dev->features |= NETIF_F_HIGHDMA;
230 +
231 + tasklet_init(&sp->rx_tasklet, rx_tasklet_func, (unsigned long) dev);
232 + tasklet_disable(&sp->rx_tasklet);
233 +
234 + sp->eth_regs =
235 + ioremap_nocache(virt_to_phys(ar_eth_base), sizeof(*sp->eth_regs));
236 + if (!sp->eth_regs) {
237 + printk("Can't remap eth registers\n");
238 + return (-ENXIO);
239 + }
240 +
241 + /*
242 + * When there's only one MAC, PHY regs are typically on ENET0,
243 + * even though the MAC might be on ENET1.
244 + * Needto remap PHY regs separately in this case
245 + */
246 + if (virt_to_phys(ar_eth_base) == virt_to_phys(sp->phy_regs))
247 + sp->phy_regs = sp->eth_regs;
248 + else {
249 + sp->phy_regs =
250 + ioremap_nocache(virt_to_phys(sp->cfg->phy_base),
251 + sizeof(*sp->phy_regs));
252 + if (!sp->phy_regs) {
253 + printk("Can't remap phy registers\n");
254 + return (-ENXIO);
255 + }
256 + }
257 +
258 + sp->dma_regs =
259 + ioremap_nocache(virt_to_phys(ar_eth_base + 0x1000),
260 + sizeof(*sp->dma_regs));
261 + dev->base_addr = (unsigned int) sp->dma_regs;
262 + if (!sp->dma_regs) {
263 + printk("Can't remap DMA registers\n");
264 + return (-ENXIO);
265 + }
266 +
267 + sp->int_regs = ioremap_nocache(virt_to_phys(sp->cfg->reset_base), 4);
268 + if (!sp->int_regs) {
269 + printk("Can't remap INTERRUPT registers\n");
270 + return (-ENXIO);
271 + }
272 +
273 + strncpy(sp->name, "Atheros AR231x", sizeof(sp->name) - 1);
274 + sp->name[sizeof(sp->name) - 1] = '\0';
275 + memcpy(dev->dev_addr, sp->cfg->macaddr, 6);
276 +
277 + if (ar231x_init(dev)) {
278 + /*
279 + * ar231x_init() calls ar231x_init_cleanup() on error.
280 + */
281 + kfree(dev);
282 + return -ENODEV;
283 + }
284 +
285 + if (register_netdev(dev)) {
286 + printk("%s: register_netdev failed\n", __func__);
287 + return -1;
288 + }
289 +
290 + printk("%s: %s: %02x:%02x:%02x:%02x:%02x:%02x, irq %d\n",
291 + dev->name, sp->name,
292 + dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
293 + dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5], dev->irq);
294 +
295 + sp->mii_bus = mdiobus_alloc();
296 + if (sp->mii_bus == NULL)
297 + return -1;
298 +
299 + sp->mii_bus->priv = dev;
300 + sp->mii_bus->read = ar231x_mdiobus_read;
301 + sp->mii_bus->write = ar231x_mdiobus_write;
302 + sp->mii_bus->reset = ar231x_mdiobus_reset;
303 + sp->mii_bus->name = "ar231x_eth_mii";
304 + snprintf(sp->mii_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
305 + sp->mii_bus->irq = kmalloc(sizeof(int), GFP_KERNEL);
306 + *sp->mii_bus->irq = PHY_POLL;
307 +
308 + mdiobus_register(sp->mii_bus);
309 +
310 + if (ar231x_mdiobus_probe(dev) != 0) {
311 + printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name);
312 + rx_tasklet_cleanup(dev);
313 + ar231x_init_cleanup(dev);
314 + unregister_netdev(dev);
315 + kfree(dev);
316 + return -ENODEV;
317 + }
318 +
319 + /* start link poll timer */
320 + ar231x_setup_timer(dev);
321 +
322 + return 0;
323 +}
324 +
325 +
326 +static void ar231x_multicast_list(struct net_device *dev)
327 +{
328 + struct ar231x_private *sp = netdev_priv(dev);
329 + unsigned int filter;
330 +
331 + filter = sp->eth_regs->mac_control;
332 +
333 + if (dev->flags & IFF_PROMISC)
334 + filter |= MAC_CONTROL_PR;
335 + else
336 + filter &= ~MAC_CONTROL_PR;
337 + if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 0))
338 + filter |= MAC_CONTROL_PM;
339 + else
340 + filter &= ~MAC_CONTROL_PM;
341 +
342 + sp->eth_regs->mac_control = filter;
343 +}
344 +
345 +static void rx_tasklet_cleanup(struct net_device *dev)
346 +{
347 + struct ar231x_private *sp = netdev_priv(dev);
348 +
349 + /*
350 + * Tasklet may be scheduled. Need to get it removed from the list
351 + * since we're about to free the struct.
352 + */
353 +
354 + sp->unloading = 1;
355 + tasklet_enable(&sp->rx_tasklet);
356 + tasklet_kill(&sp->rx_tasklet);
357 +}
358 +
359 +static int __exit ar231x_remove(struct platform_device *pdev)
360 +{
361 + struct net_device *dev = platform_get_drvdata(pdev);
362 + struct ar231x_private *sp = netdev_priv(dev);
363 + rx_tasklet_cleanup(dev);
364 + ar231x_init_cleanup(dev);
365 + unregister_netdev(dev);
366 + mdiobus_unregister(sp->mii_bus);
367 + mdiobus_free(sp->mii_bus);
368 + kfree(dev);
369 + return 0;
370 +}
371 +
372 +
373 +/*
374 + * Restart the AR2313 ethernet controller.
375 + */
376 +static int ar231x_restart(struct net_device *dev)
377 +{
378 + /* disable interrupts */
379 + disable_irq(dev->irq);
380 +
381 + /* stop mac */
382 + ar231x_halt(dev);
383 +
384 + /* initialize */
385 + ar231x_init(dev);
386 +
387 + /* enable interrupts */
388 + enable_irq(dev->irq);
389 +
390 + return 0;
391 +}
392 +
393 +static struct platform_driver ar231x_driver = {
394 + .driver.name = "ar231x-eth",
395 + .probe = ar231x_probe,
396 + .remove = ar231x_remove,
397 +};
398 +
399 +int __init ar231x_module_init(void)
400 +{
401 + return platform_driver_register(&ar231x_driver);
402 +}
403 +
404 +void __exit ar231x_module_cleanup(void)
405 +{
406 + platform_driver_unregister(&ar231x_driver);
407 +}
408 +
409 +module_init(ar231x_module_init);
410 +module_exit(ar231x_module_cleanup);
411 +
412 +
413 +static void ar231x_free_descriptors(struct net_device *dev)
414 +{
415 + struct ar231x_private *sp = netdev_priv(dev);
416 + if (sp->rx_ring != NULL) {
417 + kfree((void *) KSEG0ADDR(sp->rx_ring));
418 + sp->rx_ring = NULL;
419 + sp->tx_ring = NULL;
420 + }
421 +}
422 +
423 +
424 +static int ar231x_allocate_descriptors(struct net_device *dev)
425 +{
426 + struct ar231x_private *sp = netdev_priv(dev);
427 + int size;
428 + int j;
429 + ar231x_descr_t *space;
430 +
431 + if (sp->rx_ring != NULL) {
432 + printk("%s: already done.\n", __FUNCTION__);
433 + return 0;
434 + }
435 +
436 + size =
437 + (sizeof(ar231x_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES));
438 + space = kmalloc(size, GFP_KERNEL);
439 + if (space == NULL)
440 + return 1;
441 +
442 + /* invalidate caches */
443 + dma_cache_inv((unsigned int) space, size);
444 +
445 + /* now convert pointer to KSEG1 */
446 + space = (ar231x_descr_t *) KSEG1ADDR(space);
447 +
448 + memset((void *) space, 0, size);
449 +
450 + sp->rx_ring = space;
451 + space += AR2313_DESCR_ENTRIES;
452 +
453 + sp->tx_ring = space;
454 + space += AR2313_DESCR_ENTRIES;
455 +
456 + /* Initialize the transmit Descriptors */
457 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
458 + ar231x_descr_t *td = &sp->tx_ring[j];
459 + td->status = 0;
460 + td->devcs = DMA_TX1_CHAINED;
461 + td->addr = 0;
462 + td->descr =
463 + virt_to_phys(&sp->
464 + tx_ring[(j + 1) & (AR2313_DESCR_ENTRIES - 1)]);
465 + }
466 +
467 + return 0;
468 +}
469 +
470 +
471 +/*
472 + * Generic cleanup handling data allocated during init. Used when the
473 + * module is unloaded or if an error occurs during initialization
474 + */
475 +static void ar231x_init_cleanup(struct net_device *dev)
476 +{
477 + struct ar231x_private *sp = netdev_priv(dev);
478 + struct sk_buff *skb;
479 + int j;
480 +
481 + ar231x_free_descriptors(dev);
482 +
483 + if (sp->eth_regs)
484 + iounmap((void *) sp->eth_regs);
485 + if (sp->dma_regs)
486 + iounmap((void *) sp->dma_regs);
487 +
488 + if (sp->rx_skb) {
489 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
490 + skb = sp->rx_skb[j];
491 + if (skb) {
492 + sp->rx_skb[j] = NULL;
493 + dev_kfree_skb(skb);
494 + }
495 + }
496 + kfree(sp->rx_skb);
497 + sp->rx_skb = NULL;
498 + }
499 +
500 + if (sp->tx_skb) {
501 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
502 + skb = sp->tx_skb[j];
503 + if (skb) {
504 + sp->tx_skb[j] = NULL;
505 + dev_kfree_skb(skb);
506 + }
507 + }
508 + kfree(sp->tx_skb);
509 + sp->tx_skb = NULL;
510 + }
511 +}
512 +
513 +static int ar231x_setup_timer(struct net_device *dev)
514 +{
515 + struct ar231x_private *sp = netdev_priv(dev);
516 +
517 + init_timer(&sp->link_timer);
518 +
519 + sp->link_timer.function = ar231x_link_timer_fn;
520 + sp->link_timer.data = (int) dev;
521 + sp->link_timer.expires = jiffies + HZ;
522 +
523 + add_timer(&sp->link_timer);
524 + return 0;
525 +
526 +}
527 +
528 +static void ar231x_link_timer_fn(unsigned long data)
529 +{
530 + struct net_device *dev = (struct net_device *) data;
531 + struct ar231x_private *sp = netdev_priv(dev);
532 +
533 + // see if the link status changed
534 + // This was needed to make sure we set the PHY to the
535 + // autonegotiated value of half or full duplex.
536 + ar231x_check_link(dev);
537 +
538 + // Loop faster when we don't have link.
539 + // This was needed to speed up the AP bootstrap time.
540 + if (sp->link == 0) {
541 + mod_timer(&sp->link_timer, jiffies + HZ / 2);
542 + } else {
543 + mod_timer(&sp->link_timer, jiffies + LINK_TIMER);
544 + }
545 +}
546 +
547 +static void ar231x_check_link(struct net_device *dev)
548 +{
549 + struct ar231x_private *sp = netdev_priv(dev);
550 + u16 phyData;
551 +
552 + phyData = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMSR);
553 + if (sp->phyData != phyData) {
554 + if (phyData & BMSR_LSTATUS) {
555 + /* link is present, ready link partner ability to deterine
556 + duplexity */
557 + int duplex = 0;
558 + u16 reg;
559 +
560 + sp->link = 1;
561 + reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMCR);
562 + if (reg & BMCR_ANENABLE) {
563 + /* auto neg enabled */
564 + reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_LPA);
565 + duplex = (reg & (LPA_100FULL | LPA_10FULL)) ? 1 : 0;
566 + } else {
567 + /* no auto neg, just read duplex config */
568 + duplex = (reg & BMCR_FULLDPLX) ? 1 : 0;
569 + }
570 +
571 + printk(KERN_INFO "%s: Configuring MAC for %s duplex\n",
572 + dev->name, (duplex) ? "full" : "half");
573 +
574 + if (duplex) {
575 + /* full duplex */
576 + sp->eth_regs->mac_control =
577 + ((sp->eth_regs->
578 + mac_control | MAC_CONTROL_F) & ~MAC_CONTROL_DRO);
579 + } else {
580 + /* half duplex */
581 + sp->eth_regs->mac_control =
582 + ((sp->eth_regs->
583 + mac_control | MAC_CONTROL_DRO) & ~MAC_CONTROL_F);
584 + }
585 + } else {
586 + /* no link */
587 + sp->link = 0;
588 + }
589 + sp->phyData = phyData;
590 + }
591 +}
592 +
593 +static int ar231x_reset_reg(struct net_device *dev)
594 +{
595 + struct ar231x_private *sp = netdev_priv(dev);
596 + unsigned int ethsal, ethsah;
597 + unsigned int flags;
598 +
599 + *sp->int_regs |= sp->cfg->reset_mac;
600 + mdelay(10);
601 + *sp->int_regs &= ~sp->cfg->reset_mac;
602 + mdelay(10);
603 + *sp->int_regs |= sp->cfg->reset_phy;
604 + mdelay(10);
605 + *sp->int_regs &= ~sp->cfg->reset_phy;
606 + mdelay(10);
607 +
608 + sp->dma_regs->bus_mode = (DMA_BUS_MODE_SWR);
609 + mdelay(10);
610 + sp->dma_regs->bus_mode =
611 + ((32 << DMA_BUS_MODE_PBL_SHIFT) | DMA_BUS_MODE_BLE);
612 +
613 + /* enable interrupts */
614 + sp->dma_regs->intr_ena = (DMA_STATUS_AIS |
615 + DMA_STATUS_NIS |
616 + DMA_STATUS_RI |
617 + DMA_STATUS_TI | DMA_STATUS_FBE);
618 + sp->dma_regs->xmt_base = virt_to_phys(sp->tx_ring);
619 + sp->dma_regs->rcv_base = virt_to_phys(sp->rx_ring);
620 + sp->dma_regs->control =
621 + (DMA_CONTROL_SR | DMA_CONTROL_ST | DMA_CONTROL_SF);
622 +
623 + sp->eth_regs->flow_control = (FLOW_CONTROL_FCE);
624 + sp->eth_regs->vlan_tag = (0x8100);
625 +
626 + /* Enable Ethernet Interface */
627 + flags = (MAC_CONTROL_TE | /* transmit enable */
628 + MAC_CONTROL_PM | /* pass mcast */
629 + MAC_CONTROL_F | /* full duplex */
630 + MAC_CONTROL_HBD); /* heart beat disabled */
631 +
632 + if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
633 + flags |= MAC_CONTROL_PR;
634 + }
635 + sp->eth_regs->mac_control = flags;
636 +
637 + /* Set all Ethernet station address registers to their initial values */
638 + ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
639 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF));
640 +
641 + ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
642 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
643 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
644 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF));
645 +
646 + sp->eth_regs->mac_addr[0] = ethsah;
647 + sp->eth_regs->mac_addr[1] = ethsal;
648 +
649 + mdelay(10);
650 +
651 + return (0);
652 +}
653 +
654 +
655 +static int ar231x_init(struct net_device *dev)
656 +{
657 + struct ar231x_private *sp = netdev_priv(dev);
658 + int ecode = 0;
659 +
660 + /*
661 + * Allocate descriptors
662 + */
663 + if (ar231x_allocate_descriptors(dev)) {
664 + printk("%s: %s: ar231x_allocate_descriptors failed\n",
665 + dev->name, __FUNCTION__);
666 + ecode = -EAGAIN;
667 + goto init_error;
668 + }
669 +
670 + /*
671 + * Get the memory for the skb rings.
672 + */
673 + if (sp->rx_skb == NULL) {
674 + sp->rx_skb =
675 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
676 + GFP_KERNEL);
677 + if (!(sp->rx_skb)) {
678 + printk("%s: %s: rx_skb kmalloc failed\n",
679 + dev->name, __FUNCTION__);
680 + ecode = -EAGAIN;
681 + goto init_error;
682 + }
683 + }
684 + memset(sp->rx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
685 +
686 + if (sp->tx_skb == NULL) {
687 + sp->tx_skb =
688 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
689 + GFP_KERNEL);
690 + if (!(sp->tx_skb)) {
691 + printk("%s: %s: tx_skb kmalloc failed\n",
692 + dev->name, __FUNCTION__);
693 + ecode = -EAGAIN;
694 + goto init_error;
695 + }
696 + }
697 + memset(sp->tx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
698 +
699 + /*
700 + * Set tx_csm before we start receiving interrupts, otherwise
701 + * the interrupt handler might think it is supposed to process
702 + * tx ints before we are up and running, which may cause a null
703 + * pointer access in the int handler.
704 + */
705 + sp->rx_skbprd = 0;
706 + sp->cur_rx = 0;
707 + sp->tx_prd = 0;
708 + sp->tx_csm = 0;
709 +
710 + /*
711 + * Zero the stats before starting the interface
712 + */
713 + memset(&dev->stats, 0, sizeof(dev->stats));
714 +
715 + /*
716 + * We load the ring here as there seem to be no way to tell the
717 + * firmware to wipe the ring without re-initializing it.
718 + */
719 + ar231x_load_rx_ring(dev, RX_RING_SIZE);
720 +
721 + /*
722 + * Init hardware
723 + */
724 + ar231x_reset_reg(dev);
725 +
726 + /*
727 + * Get the IRQ
728 + */
729 + ecode =
730 + request_irq(dev->irq, &ar231x_interrupt,
731 + IRQF_SHARED | IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
732 + dev->name, dev);
733 + if (ecode) {
734 + printk(KERN_WARNING "%s: %s: Requested IRQ %d is busy\n",
735 + dev->name, __FUNCTION__, dev->irq);
736 + goto init_error;
737 + }
738 +
739 +
740 + tasklet_enable(&sp->rx_tasklet);
741 +
742 + return 0;
743 +
744 + init_error:
745 + ar231x_init_cleanup(dev);
746 + return ecode;
747 +}
748 +
749 +/*
750 + * Load the rx ring.
751 + *
752 + * Loading rings is safe without holding the spin lock since this is
753 + * done only before the device is enabled, thus no interrupts are
754 + * generated and by the interrupt handler/tasklet handler.
755 + */
756 +static void ar231x_load_rx_ring(struct net_device *dev, int nr_bufs)
757 +{
758 +
759 + struct ar231x_private *sp = netdev_priv(dev);
760 + short i, idx;
761 +
762 + idx = sp->rx_skbprd;
763 +
764 + for (i = 0; i < nr_bufs; i++) {
765 + struct sk_buff *skb;
766 + ar231x_descr_t *rd;
767 +
768 + if (sp->rx_skb[idx])
769 + break;
770 +
771 + skb = netdev_alloc_skb(dev, AR2313_BUFSIZE);
772 + if (!skb) {
773 + printk("\n\n\n\n %s: No memory in system\n\n\n\n",
774 + __FUNCTION__);
775 + break;
776 + }
777 +
778 + /*
779 + * Make sure IP header starts on a fresh cache line.
780 + */
781 + skb->dev = dev;
782 + skb_reserve(skb, RX_OFFSET);
783 + sp->rx_skb[idx] = skb;
784 +
785 + rd = (ar231x_descr_t *) & sp->rx_ring[idx];
786 +
787 + /* initialize dma descriptor */
788 + rd->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
789 + DMA_RX1_CHAINED);
790 + rd->addr = virt_to_phys(skb->data);
791 + rd->descr =
792 + virt_to_phys(&sp->
793 + rx_ring[(idx + 1) & (AR2313_DESCR_ENTRIES - 1)]);
794 + rd->status = DMA_RX_OWN;
795 +
796 + idx = DSC_NEXT(idx);
797 + }
798 +
799 + if (i)
800 + sp->rx_skbprd = idx;
801 +
802 + return;
803 +}
804 +
805 +#define AR2313_MAX_PKTS_PER_CALL 64
806 +
807 +static int ar231x_rx_int(struct net_device *dev)
808 +{
809 + struct ar231x_private *sp = netdev_priv(dev);
810 + struct sk_buff *skb, *skb_new;
811 + ar231x_descr_t *rxdesc;
812 + unsigned int status;
813 + u32 idx;
814 + int pkts = 0;
815 + int rval;
816 +
817 + idx = sp->cur_rx;
818 +
819 + /* process at most the entire ring and then wait for another interrupt
820 + */
821 + while (1) {
822 +
823 + rxdesc = &sp->rx_ring[idx];
824 + status = rxdesc->status;
825 + if (status & DMA_RX_OWN) {
826 + /* SiByte owns descriptor or descr not yet filled in */
827 + rval = 0;
828 + break;
829 + }
830 +
831 + if (++pkts > AR2313_MAX_PKTS_PER_CALL) {
832 + rval = 1;
833 + break;
834 + }
835 +
836 + if ((status & DMA_RX_ERROR) && !(status & DMA_RX_LONG)) {
837 + dev->stats.rx_errors++;
838 + dev->stats.rx_dropped++;
839 +
840 + /* add statistics counters */
841 + if (status & DMA_RX_ERR_CRC)
842 + dev->stats.rx_crc_errors++;
843 + if (status & DMA_RX_ERR_COL)
844 + dev->stats.rx_over_errors++;
845 + if (status & DMA_RX_ERR_LENGTH)
846 + dev->stats.rx_length_errors++;
847 + if (status & DMA_RX_ERR_RUNT)
848 + dev->stats.rx_over_errors++;
849 + if (status & DMA_RX_ERR_DESC)
850 + dev->stats.rx_over_errors++;
851 +
852 + } else {
853 + /* alloc new buffer. */
854 + skb_new = netdev_alloc_skb(dev, AR2313_BUFSIZE + RX_OFFSET);
855 + if (skb_new != NULL) {
856 +
857 + skb = sp->rx_skb[idx];
858 + /* set skb */
859 + skb_put(skb,
860 + ((status >> DMA_RX_LEN_SHIFT) & 0x3fff) - CRC_LEN);
861 +
862 + dev->stats.rx_bytes += skb->len;
863 + skb->protocol = eth_type_trans(skb, dev);
864 + /* pass the packet to upper layers */
865 + netif_rx(skb);
866 +
867 + skb_new->dev = dev;
868 + /* 16 bit align */
869 + skb_reserve(skb_new, RX_OFFSET);
870 + /* reset descriptor's curr_addr */
871 + rxdesc->addr = virt_to_phys(skb_new->data);
872 +
873 + dev->stats.rx_packets++;
874 + sp->rx_skb[idx] = skb_new;
875 + } else {
876 + dev->stats.rx_dropped++;
877 + }
878 + }
879 +
880 + rxdesc->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
881 + DMA_RX1_CHAINED);
882 + rxdesc->status = DMA_RX_OWN;
883 +
884 + idx = DSC_NEXT(idx);
885 + }
886 +
887 + sp->cur_rx = idx;
888 +
889 + return rval;
890 +}
891 +
892 +
893 +static void ar231x_tx_int(struct net_device *dev)
894 +{
895 + struct ar231x_private *sp = netdev_priv(dev);
896 + u32 idx;
897 + struct sk_buff *skb;
898 + ar231x_descr_t *txdesc;
899 + unsigned int status = 0;
900 +
901 + idx = sp->tx_csm;
902 +
903 + while (idx != sp->tx_prd) {
904 + txdesc = &sp->tx_ring[idx];
905 +
906 + if ((status = txdesc->status) & DMA_TX_OWN) {
907 + /* ar231x dma still owns descr */
908 + break;
909 + }
910 + /* done with this descriptor */
911 + dma_unmap_single(NULL, txdesc->addr,
912 + txdesc->devcs & DMA_TX1_BSIZE_MASK,
913 + DMA_TO_DEVICE);
914 + txdesc->status = 0;
915 +
916 + if (status & DMA_TX_ERROR) {
917 + dev->stats.tx_errors++;
918 + dev->stats.tx_dropped++;
919 + if (status & DMA_TX_ERR_UNDER)
920 + dev->stats.tx_fifo_errors++;
921 + if (status & DMA_TX_ERR_HB)
922 + dev->stats.tx_heartbeat_errors++;
923 + if (status & (DMA_TX_ERR_LOSS | DMA_TX_ERR_LINK))
924 + dev->stats.tx_carrier_errors++;
925 + if (status & (DMA_TX_ERR_LATE |
926 + DMA_TX_ERR_COL |
927 + DMA_TX_ERR_JABBER | DMA_TX_ERR_DEFER))
928 + dev->stats.tx_aborted_errors++;
929 + } else {
930 + /* transmit OK */
931 + dev->stats.tx_packets++;
932 + }
933 +
934 + skb = sp->tx_skb[idx];
935 + sp->tx_skb[idx] = NULL;
936 + idx = DSC_NEXT(idx);
937 + dev->stats.tx_bytes += skb->len;
938 + dev_kfree_skb_irq(skb);
939 + }
940 +
941 + sp->tx_csm = idx;
942 +
943 + return;
944 +}
945 +
946 +
947 +static void rx_tasklet_func(unsigned long data)
948 +{
949 + struct net_device *dev = (struct net_device *) data;
950 + struct ar231x_private *sp = netdev_priv(dev);
951 +
952 + if (sp->unloading) {
953 + return;
954 + }
955 +
956 + if (ar231x_rx_int(dev)) {
957 + tasklet_hi_schedule(&sp->rx_tasklet);
958 + } else {
959 + unsigned long flags;
960 + spin_lock_irqsave(&sp->lock, flags);
961 + sp->dma_regs->intr_ena |= DMA_STATUS_RI;
962 + spin_unlock_irqrestore(&sp->lock, flags);
963 + }
964 +}
965 +
966 +static void rx_schedule(struct net_device *dev)
967 +{
968 + struct ar231x_private *sp = netdev_priv(dev);
969 +
970 + sp->dma_regs->intr_ena &= ~DMA_STATUS_RI;
971 +
972 + tasklet_hi_schedule(&sp->rx_tasklet);
973 +}
974 +
975 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id)
976 +{
977 + struct net_device *dev = (struct net_device *) dev_id;
978 + struct ar231x_private *sp = netdev_priv(dev);
979 + unsigned int status, enabled;
980 +
981 + /* clear interrupt */
982 + /*
983 + * Don't clear RI bit if currently disabled.
984 + */
985 + status = sp->dma_regs->status;
986 + enabled = sp->dma_regs->intr_ena;
987 + sp->dma_regs->status = status & enabled;
988 +
989 + if (status & DMA_STATUS_NIS) {
990 + /* normal status */
991 + /*
992 + * Don't schedule rx processing if interrupt
993 + * is already disabled.
994 + */
995 + if (status & enabled & DMA_STATUS_RI) {
996 + /* receive interrupt */
997 + rx_schedule(dev);
998 + }
999 + if (status & DMA_STATUS_TI) {
1000 + /* transmit interrupt */
1001 + ar231x_tx_int(dev);
1002 + }
1003 + }
1004 +
1005 + /* abnormal status */
1006 + if (status & (DMA_STATUS_FBE | DMA_STATUS_TPS)) {
1007 + ar231x_restart(dev);
1008 + }
1009 + return IRQ_HANDLED;
1010 +}
1011 +
1012 +
1013 +static int ar231x_open(struct net_device *dev)
1014 +{
1015 + struct ar231x_private *sp = netdev_priv(dev);
1016 + unsigned int ethsal, ethsah;
1017 +
1018 + /* reset the hardware, in case the MAC address changed */
1019 + ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
1020 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF));
1021 +
1022 + ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
1023 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
1024 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
1025 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF));
1026 +
1027 + sp->eth_regs->mac_addr[0] = ethsah;
1028 + sp->eth_regs->mac_addr[1] = ethsal;
1029 +
1030 + mdelay(10);
1031 +
1032 + dev->mtu = 1500;
1033 + netif_start_queue(dev);
1034 +
1035 + sp->eth_regs->mac_control |= MAC_CONTROL_RE;
1036 +
1037 + return 0;
1038 +}
1039 +
1040 +static void ar231x_halt(struct net_device *dev)
1041 +{
1042 + struct ar231x_private *sp = netdev_priv(dev);
1043 + int j;
1044 +
1045 + tasklet_disable(&sp->rx_tasklet);
1046 +
1047 + /* kill the MAC */
1048 + sp->eth_regs->mac_control &= ~(MAC_CONTROL_RE | /* disable Receives */
1049 + MAC_CONTROL_TE); /* disable Transmits */
1050 + /* stop dma */
1051 + sp->dma_regs->control = 0;
1052 + sp->dma_regs->bus_mode = DMA_BUS_MODE_SWR;
1053 +
1054 + /* place phy and MAC in reset */
1055 + *sp->int_regs |= (sp->cfg->reset_mac | sp->cfg->reset_phy);
1056 +
1057 + /* free buffers on tx ring */
1058 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
1059 + struct sk_buff *skb;
1060 + ar231x_descr_t *txdesc;
1061 +
1062 + txdesc = &sp->tx_ring[j];
1063 + txdesc->descr = 0;
1064 +
1065 + skb = sp->tx_skb[j];
1066 + if (skb) {
1067 + dev_kfree_skb(skb);
1068 + sp->tx_skb[j] = NULL;
1069 + }
1070 + }
1071 +}
1072 +
1073 +/*
1074 + * close should do nothing. Here's why. It's called when
1075 + * 'ifconfig bond0 down' is run. If it calls free_irq then
1076 + * the irq is gone forever ! When bond0 is made 'up' again,
1077 + * the ar231x_open () does not call request_irq (). Worse,
1078 + * the call to ar231x_halt() generates a WDOG reset due to
1079 + * the write to 'sp->int_regs' and the box reboots.
1080 + * Commenting this out is good since it allows the
1081 + * system to resume when bond0 is made up again.
1082 + */
1083 +static int ar231x_close(struct net_device *dev)
1084 +{
1085 +#if 0
1086 + /*
1087 + * Disable interrupts
1088 + */
1089 + disable_irq(dev->irq);
1090 +
1091 + /*
1092 + * Without (or before) releasing irq and stopping hardware, this
1093 + * is an absolute non-sense, by the way. It will be reset instantly
1094 + * by the first irq.
1095 + */
1096 + netif_stop_queue(dev);
1097 +
1098 + /* stop the MAC and DMA engines */
1099 + ar231x_halt(dev);
1100 +
1101 + /* release the interrupt */
1102 + free_irq(dev->irq, dev);
1103 +
1104 +#endif
1105 + return 0;
1106 +}
1107 +
1108 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev)
1109 +{
1110 + struct ar231x_private *sp = netdev_priv(dev);
1111 + ar231x_descr_t *td;
1112 + u32 idx;
1113 +
1114 + idx = sp->tx_prd;
1115 + td = &sp->tx_ring[idx];
1116 +
1117 + if (td->status & DMA_TX_OWN) {
1118 + /* free skbuf and lie to the caller that we sent it out */
1119 + dev->stats.tx_dropped++;
1120 + dev_kfree_skb(skb);
1121 +
1122 + /* restart transmitter in case locked */
1123 + sp->dma_regs->xmt_poll = 0;
1124 + return 0;
1125 + }
1126 +
1127 + /* Setup the transmit descriptor. */
1128 + td->devcs = ((skb->len << DMA_TX1_BSIZE_SHIFT) |
1129 + (DMA_TX1_LS | DMA_TX1_IC | DMA_TX1_CHAINED));
1130 + td->addr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
1131 + td->status = DMA_TX_OWN;
1132 +
1133 + /* kick transmitter last */
1134 + sp->dma_regs->xmt_poll = 0;
1135 +
1136 + sp->tx_skb[idx] = skb;
1137 + idx = DSC_NEXT(idx);
1138 + sp->tx_prd = idx;
1139 +
1140 + return 0;
1141 +}
1142 +
1143 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1144 +{
1145 + struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data;
1146 + struct ar231x_private *sp = netdev_priv(dev);
1147 + int ret;
1148 +
1149 + switch (cmd) {
1150 +
1151 + case SIOCETHTOOL:
1152 + spin_lock_irq(&sp->lock);
1153 + ret = phy_ethtool_ioctl(sp->phy_dev, (void *) ifr->ifr_data);
1154 + spin_unlock_irq(&sp->lock);
1155 + return ret;
1156 +
1157 + case SIOCSIFHWADDR:
1158 + if (copy_from_user
1159 + (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
1160 + return -EFAULT;
1161 + return 0;
1162 +
1163 + case SIOCGIFHWADDR:
1164 + if (copy_to_user
1165 + (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
1166 + return -EFAULT;
1167 + return 0;
1168 +
1169 + case SIOCGMIIPHY:
1170 + case SIOCGMIIREG:
1171 + case SIOCSMIIREG:
1172 + return phy_mii_ioctl(sp->phy_dev, data, cmd);
1173 +
1174 + default:
1175 + break;
1176 + }
1177 +
1178 + return -EOPNOTSUPP;
1179 +}
1180 +
1181 +static void ar231x_adjust_link(struct net_device *dev)
1182 +{
1183 + struct ar231x_private *sp = netdev_priv(dev);
1184 + unsigned int mc;
1185 +
1186 + if (!sp->phy_dev->link)
1187 + return;
1188 +
1189 + if (sp->phy_dev->duplex != sp->oldduplex) {
1190 + mc = readl(&sp->eth_regs->mac_control);
1191 + mc &= ~(MAC_CONTROL_F | MAC_CONTROL_DRO);
1192 + if (sp->phy_dev->duplex)
1193 + mc |= MAC_CONTROL_F;
1194 + else
1195 + mc |= MAC_CONTROL_DRO;
1196 + writel(mc, &sp->eth_regs->mac_control);
1197 + sp->oldduplex = sp->phy_dev->duplex;
1198 + }
1199 +}
1200 +
1201 +#define MII_ADDR(phy, reg) \
1202 + ((reg << MII_ADDR_REG_SHIFT) | (phy << MII_ADDR_PHY_SHIFT))
1203 +
1204 +static int
1205 +ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
1206 +{
1207 + struct net_device *const dev = bus->priv;
1208 + struct ar231x_private *sp = netdev_priv(dev);
1209 + volatile ETHERNET_STRUCT *ethernet = sp->phy_regs;
1210 +
1211 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum);
1212 + while (ethernet->mii_addr & MII_ADDR_BUSY);
1213 + return (ethernet->mii_data >> MII_DATA_SHIFT);
1214 +}
1215 +
1216 +static int
1217 +ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
1218 + u16 value)
1219 +{
1220 + struct net_device *const dev = bus->priv;
1221 + struct ar231x_private *sp = netdev_priv(dev);
1222 + volatile ETHERNET_STRUCT *ethernet = sp->phy_regs;
1223 +
1224 + while (ethernet->mii_addr & MII_ADDR_BUSY);
1225 + ethernet->mii_data = value << MII_DATA_SHIFT;
1226 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum) | MII_ADDR_WRITE;
1227 +
1228 + return 0;
1229 +}
1230 +
1231 +static int ar231x_mdiobus_reset(struct mii_bus *bus)
1232 +{
1233 + struct net_device *const dev = bus->priv;
1234 +
1235 + ar231x_reset_reg(dev);
1236 +
1237 + return 0;
1238 +}
1239 +
1240 +static int ar231x_mdiobus_probe (struct net_device *dev)
1241 +{
1242 + struct ar231x_private *const sp = netdev_priv(dev);
1243 + struct phy_device *phydev = NULL;
1244 + int phy_addr;
1245 +
1246 + /* find the first (lowest address) PHY on the current MAC's MII bus */
1247 + for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
1248 + if (sp->mii_bus->phy_map[phy_addr]) {
1249 + phydev = sp->mii_bus->phy_map[phy_addr];
1250 + sp->phy = phy_addr;
1251 + break; /* break out with first one found */
1252 + }
1253 +
1254 + if (!phydev) {
1255 + printk (KERN_ERR "ar231x: %s: no PHY found\n", dev->name);
1256 + return -1;
1257 + }
1258 +
1259 + /* now we are supposed to have a proper phydev, to attach to... */
1260 + BUG_ON(!phydev);
1261 + BUG_ON(phydev->attached_dev);
1262 +
1263 + phydev = phy_connect(dev, phydev->dev.bus_id, &ar231x_adjust_link, 0,
1264 + PHY_INTERFACE_MODE_MII);
1265 +
1266 + if (IS_ERR(phydev)) {
1267 + printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
1268 + return PTR_ERR(phydev);
1269 + }
1270 +
1271 + /* mask with MAC supported features */
1272 + phydev->supported &= (SUPPORTED_10baseT_Half
1273 + | SUPPORTED_10baseT_Full
1274 + | SUPPORTED_100baseT_Half
1275 + | SUPPORTED_100baseT_Full
1276 + | SUPPORTED_Autoneg
1277 + /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
1278 + | SUPPORTED_MII
1279 + | SUPPORTED_TP);
1280 +
1281 + phydev->advertising = phydev->supported;
1282 +
1283 + sp->oldduplex = -1;
1284 + sp->phy_dev = phydev;
1285 +
1286 + printk(KERN_INFO "%s: attached PHY driver [%s] "
1287 + "(mii_bus:phy_addr=%s)\n",
1288 + dev->name, phydev->drv->name, phydev->dev.bus_id);
1289 +
1290 + return 0;
1291 +}
1292 +
1293 --- /dev/null
1294 +++ b/drivers/net/ar231x.h
1295 @@ -0,0 +1,302 @@
1296 +/*
1297 + * ar231x.h: Linux driver for the Atheros AR231x Ethernet device.
1298 + *
1299 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
1300 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1301 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1302 + *
1303 + * Thanks to Atheros for providing hardware and documentation
1304 + * enabling me to write this driver.
1305 + *
1306 + * This program is free software; you can redistribute it and/or modify
1307 + * it under the terms of the GNU General Public License as published by
1308 + * the Free Software Foundation; either version 2 of the License, or
1309 + * (at your option) any later version.
1310 + */
1311 +
1312 +#ifndef _AR2313_H_
1313 +#define _AR2313_H_
1314 +
1315 +#include <linux/autoconf.h>
1316 +#include <linux/bitops.h>
1317 +#include <asm/bootinfo.h>
1318 +#include <ar231x_platform.h>
1319 +
1320 +/*
1321 + * probe link timer - 5 secs
1322 + */
1323 +#define LINK_TIMER (5*HZ)
1324 +
1325 +#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0)
1326 +#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0)
1327 +#define IS_DRIVER_OWNED(X) (((X) & (DMA_TX_OWN)) == 0)
1328 +
1329 +#define AR2313_TX_TIMEOUT (HZ/4)
1330 +
1331 +/*
1332 + * Rings
1333 + */
1334 +#define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc))
1335 +#define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1))
1336 +
1337 +#define AR2313_MBGET 2
1338 +#define AR2313_MBSET 3
1339 +#define AR2313_PCI_RECONFIG 4
1340 +#define AR2313_PCI_DUMP 5
1341 +#define AR2313_TEST_PANIC 6
1342 +#define AR2313_TEST_NULLPTR 7
1343 +#define AR2313_READ_DATA 8
1344 +#define AR2313_WRITE_DATA 9
1345 +#define AR2313_GET_VERSION 10
1346 +#define AR2313_TEST_HANG 11
1347 +#define AR2313_SYNC 12
1348 +
1349 +#define DMA_RX_ERR_CRC BIT(1)
1350 +#define DMA_RX_ERR_DRIB BIT(2)
1351 +#define DMA_RX_ERR_MII BIT(3)
1352 +#define DMA_RX_EV2 BIT(5)
1353 +#define DMA_RX_ERR_COL BIT(6)
1354 +#define DMA_RX_LONG BIT(7)
1355 +#define DMA_RX_LS BIT(8) /* last descriptor */
1356 +#define DMA_RX_FS BIT(9) /* first descriptor */
1357 +#define DMA_RX_MF BIT(10) /* multicast frame */
1358 +#define DMA_RX_ERR_RUNT BIT(11) /* runt frame */
1359 +#define DMA_RX_ERR_LENGTH BIT(12) /* length error */
1360 +#define DMA_RX_ERR_DESC BIT(14) /* descriptor error */
1361 +#define DMA_RX_ERROR BIT(15) /* error summary */
1362 +#define DMA_RX_LEN_MASK 0x3fff0000
1363 +#define DMA_RX_LEN_SHIFT 16
1364 +#define DMA_RX_FILT BIT(30)
1365 +#define DMA_RX_OWN BIT(31) /* desc owned by DMA controller */
1366 +
1367 +#define DMA_RX1_BSIZE_MASK 0x000007ff
1368 +#define DMA_RX1_BSIZE_SHIFT 0
1369 +#define DMA_RX1_CHAINED BIT(24)
1370 +#define DMA_RX1_RER BIT(25)
1371 +
1372 +#define DMA_TX_ERR_UNDER BIT(1) /* underflow error */
1373 +#define DMA_TX_ERR_DEFER BIT(2) /* excessive deferral */
1374 +#define DMA_TX_COL_MASK 0x78
1375 +#define DMA_TX_COL_SHIFT 3
1376 +#define DMA_TX_ERR_HB BIT(7) /* hearbeat failure */
1377 +#define DMA_TX_ERR_COL BIT(8) /* excessive collisions */
1378 +#define DMA_TX_ERR_LATE BIT(9) /* late collision */
1379 +#define DMA_TX_ERR_LINK BIT(10) /* no carrier */
1380 +#define DMA_TX_ERR_LOSS BIT(11) /* loss of carrier */
1381 +#define DMA_TX_ERR_JABBER BIT(14) /* transmit jabber timeout */
1382 +#define DMA_TX_ERROR BIT(15) /* frame aborted */
1383 +#define DMA_TX_OWN BIT(31) /* descr owned by DMA controller */
1384 +
1385 +#define DMA_TX1_BSIZE_MASK 0x000007ff
1386 +#define DMA_TX1_BSIZE_SHIFT 0
1387 +#define DMA_TX1_CHAINED BIT(24) /* chained descriptors */
1388 +#define DMA_TX1_TER BIT(25) /* transmit end of ring */
1389 +#define DMA_TX1_FS BIT(29) /* first segment */
1390 +#define DMA_TX1_LS BIT(30) /* last segment */
1391 +#define DMA_TX1_IC BIT(31) /* interrupt on completion */
1392 +
1393 +#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */
1394 +
1395 +#define MAC_CONTROL_RE BIT(2) /* receive enable */
1396 +#define MAC_CONTROL_TE BIT(3) /* transmit enable */
1397 +#define MAC_CONTROL_DC BIT(5) /* Deferral check */
1398 +#define MAC_CONTROL_ASTP BIT(8) /* Auto pad strip */
1399 +#define MAC_CONTROL_DRTY BIT(10) /* Disable retry */
1400 +#define MAC_CONTROL_DBF BIT(11) /* Disable bcast frames */
1401 +#define MAC_CONTROL_LCC BIT(12) /* late collision ctrl */
1402 +#define MAC_CONTROL_HP BIT(13) /* Hash Perfect filtering */
1403 +#define MAC_CONTROL_HASH BIT(14) /* Unicast hash filtering */
1404 +#define MAC_CONTROL_HO BIT(15) /* Hash only filtering */
1405 +#define MAC_CONTROL_PB BIT(16) /* Pass Bad frames */
1406 +#define MAC_CONTROL_IF BIT(17) /* Inverse filtering */
1407 +#define MAC_CONTROL_PR BIT(18) /* promiscuous mode (valid frames only) */
1408 +#define MAC_CONTROL_PM BIT(19) /* pass multicast */
1409 +#define MAC_CONTROL_F BIT(20) /* full-duplex */
1410 +#define MAC_CONTROL_DRO BIT(23) /* Disable Receive Own */
1411 +#define MAC_CONTROL_HBD BIT(28) /* heart-beat disabled (MUST BE SET) */
1412 +#define MAC_CONTROL_BLE BIT(30) /* big endian mode */
1413 +#define MAC_CONTROL_RA BIT(31) /* receive all (valid and invalid frames) */
1414 +
1415 +#define MII_ADDR_BUSY BIT(0)
1416 +#define MII_ADDR_WRITE BIT(1)
1417 +#define MII_ADDR_REG_SHIFT 6
1418 +#define MII_ADDR_PHY_SHIFT 11
1419 +#define MII_DATA_SHIFT 0
1420 +
1421 +#define FLOW_CONTROL_FCE BIT(1)
1422 +
1423 +#define DMA_BUS_MODE_SWR BIT(0) /* software reset */
1424 +#define DMA_BUS_MODE_BLE BIT(7) /* big endian mode */
1425 +#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */
1426 +#define DMA_BUS_MODE_DBO BIT(20) /* big-endian descriptors */
1427 +
1428 +#define DMA_STATUS_TI BIT(0) /* transmit interrupt */
1429 +#define DMA_STATUS_TPS BIT(1) /* transmit process stopped */
1430 +#define DMA_STATUS_TU BIT(2) /* transmit buffer unavailable */
1431 +#define DMA_STATUS_TJT BIT(3) /* transmit buffer timeout */
1432 +#define DMA_STATUS_UNF BIT(5) /* transmit underflow */
1433 +#define DMA_STATUS_RI BIT(6) /* receive interrupt */
1434 +#define DMA_STATUS_RU BIT(7) /* receive buffer unavailable */
1435 +#define DMA_STATUS_RPS BIT(8) /* receive process stopped */
1436 +#define DMA_STATUS_ETI BIT(10) /* early transmit interrupt */
1437 +#define DMA_STATUS_FBE BIT(13) /* fatal bus interrupt */
1438 +#define DMA_STATUS_ERI BIT(14) /* early receive interrupt */
1439 +#define DMA_STATUS_AIS BIT(15) /* abnormal interrupt summary */
1440 +#define DMA_STATUS_NIS BIT(16) /* normal interrupt summary */
1441 +#define DMA_STATUS_RS_SHIFT 17 /* receive process state */
1442 +#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */
1443 +#define DMA_STATUS_EB_SHIFT 23 /* error bits */
1444 +
1445 +#define DMA_CONTROL_SR BIT(1) /* start receive */
1446 +#define DMA_CONTROL_ST BIT(13) /* start transmit */
1447 +#define DMA_CONTROL_SF BIT(21) /* store and forward */
1448 +
1449 +
1450 +typedef struct {
1451 + volatile unsigned int status; // OWN, Device control and status.
1452 + volatile unsigned int devcs; // pkt Control bits + Length
1453 + volatile unsigned int addr; // Current Address.
1454 + volatile unsigned int descr; // Next descriptor in chain.
1455 +} ar231x_descr_t;
1456 +
1457 +
1458 +
1459 +//
1460 +// New Combo structure for Both Eth0 AND eth1
1461 +//
1462 +typedef struct {
1463 + volatile unsigned int mac_control; /* 0x00 */
1464 + volatile unsigned int mac_addr[2]; /* 0x04 - 0x08 */
1465 + volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */
1466 + volatile unsigned int mii_addr; /* 0x14 */
1467 + volatile unsigned int mii_data; /* 0x18 */
1468 + volatile unsigned int flow_control; /* 0x1c */
1469 + volatile unsigned int vlan_tag; /* 0x20 */
1470 + volatile unsigned int pad[7]; /* 0x24 - 0x3c */
1471 + volatile unsigned int ucast_table[8]; /* 0x40-0x5c */
1472 +
1473 +} ETHERNET_STRUCT;
1474 +
1475 +/********************************************************************
1476 + * Interrupt controller
1477 + ********************************************************************/
1478 +
1479 +typedef struct {
1480 + volatile unsigned int wdog_control; /* 0x08 */
1481 + volatile unsigned int wdog_timer; /* 0x0c */
1482 + volatile unsigned int misc_status; /* 0x10 */
1483 + volatile unsigned int misc_mask; /* 0x14 */
1484 + volatile unsigned int global_status; /* 0x18 */
1485 + volatile unsigned int reserved; /* 0x1c */
1486 + volatile unsigned int reset_control; /* 0x20 */
1487 +} INTERRUPT;
1488 +
1489 +/********************************************************************
1490 + * DMA controller
1491 + ********************************************************************/
1492 +typedef struct {
1493 + volatile unsigned int bus_mode; /* 0x00 (CSR0) */
1494 + volatile unsigned int xmt_poll; /* 0x04 (CSR1) */
1495 + volatile unsigned int rcv_poll; /* 0x08 (CSR2) */
1496 + volatile unsigned int rcv_base; /* 0x0c (CSR3) */
1497 + volatile unsigned int xmt_base; /* 0x10 (CSR4) */
1498 + volatile unsigned int status; /* 0x14 (CSR5) */
1499 + volatile unsigned int control; /* 0x18 (CSR6) */
1500 + volatile unsigned int intr_ena; /* 0x1c (CSR7) */
1501 + volatile unsigned int rcv_missed; /* 0x20 (CSR8) */
1502 + volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */
1503 + volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */
1504 + volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */
1505 +} DMA;
1506 +
1507 +/*
1508 + * Struct private for the Sibyte.
1509 + *
1510 + * Elements are grouped so variables used by the tx handling goes
1511 + * together, and will go into the same cache lines etc. in order to
1512 + * avoid cache line contention between the rx and tx handling on SMP.
1513 + *
1514 + * Frequently accessed variables are put at the beginning of the
1515 + * struct to help the compiler generate better/shorter code.
1516 + */
1517 +struct ar231x_private {
1518 + struct net_device *dev;
1519 + int version;
1520 + u32 mb[2];
1521 +
1522 + volatile ETHERNET_STRUCT *phy_regs;
1523 + volatile ETHERNET_STRUCT *eth_regs;
1524 + volatile DMA *dma_regs;
1525 + volatile u32 *int_regs;
1526 + struct ar231x_eth *cfg;
1527 +
1528 + spinlock_t lock; /* Serialise access to device */
1529 +
1530 + /*
1531 + * RX and TX descriptors, must be adjacent
1532 + */
1533 + ar231x_descr_t *rx_ring;
1534 + ar231x_descr_t *tx_ring;
1535 +
1536 +
1537 + struct sk_buff **rx_skb;
1538 + struct sk_buff **tx_skb;
1539 +
1540 + /*
1541 + * RX elements
1542 + */
1543 + u32 rx_skbprd;
1544 + u32 cur_rx;
1545 +
1546 + /*
1547 + * TX elements
1548 + */
1549 + u32 tx_prd;
1550 + u32 tx_csm;
1551 +
1552 + /*
1553 + * Misc elements
1554 + */
1555 + char name[48];
1556 + struct {
1557 + u32 address;
1558 + u32 length;
1559 + char *mapping;
1560 + } desc;
1561 +
1562 +
1563 + struct timer_list link_timer;
1564 + unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */
1565 + unsigned short mac;
1566 + unsigned short link; /* 0 - link down, 1 - link up */
1567 + u16 phyData;
1568 +
1569 + struct tasklet_struct rx_tasklet;
1570 + int unloading;
1571 +
1572 + struct phy_device *phy_dev;
1573 + struct mii_bus *mii_bus;
1574 + int oldduplex;
1575 +};
1576 +
1577 +
1578 +/*
1579 + * Prototypes
1580 + */
1581 +static int ar231x_init(struct net_device *dev);
1582 +#ifdef TX_TIMEOUT
1583 +static void ar231x_tx_timeout(struct net_device *dev);
1584 +#endif
1585 +static int ar231x_restart(struct net_device *dev);
1586 +static void ar231x_load_rx_ring(struct net_device *dev, int bufs);
1587 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id);
1588 +static int ar231x_open(struct net_device *dev);
1589 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev);
1590 +static int ar231x_close(struct net_device *dev);
1591 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr,
1592 + int cmd);
1593 +static void ar231x_init_cleanup(struct net_device *dev);
1594 +static int ar231x_setup_timer(struct net_device *dev);
1595 +static void ar231x_link_timer_fn(unsigned long data);
1596 +static void ar231x_check_link(struct net_device *dev);
1597 +#endif /* _AR2313_H_ */
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