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1bd445b2a7946dc1ef225f2c57917a31fc471075
[openwrt/openwrt.git] / target / linux / atheros / patches-3.14 / 110-ar2313_ethernet.patch
1 --- a/drivers/net/ethernet/atheros/Makefile
2 +++ b/drivers/net/ethernet/atheros/Makefile
3 @@ -7,3 +7,4 @@ obj-$(CONFIG_ATL2) += atlx/
4 obj-$(CONFIG_ATL1E) += atl1e/
5 obj-$(CONFIG_ATL1C) += atl1c/
6 obj-$(CONFIG_ALX) += alx/
7 +obj-$(CONFIG_NET_AR231X) += ar231x/
8 --- a/drivers/net/ethernet/atheros/Kconfig
9 +++ b/drivers/net/ethernet/atheros/Kconfig
10 @@ -5,7 +5,7 @@
11 config NET_VENDOR_ATHEROS
12 bool "Atheros devices"
13 default y
14 - depends on PCI
15 + depends on (PCI || ATHEROS_AR231X)
16 ---help---
17 If you have a network (Ethernet) card belonging to this class, say Y
18 and read the Ethernet-HOWTO, available from
19 @@ -80,4 +80,10 @@ config ALX
20 To compile this driver as a module, choose M here. The module
21 will be called alx.
22
23 +config NET_AR231X
24 + tristate "Atheros AR231X built-in Ethernet support"
25 + depends on ATHEROS_AR231X
26 + help
27 + Support for the AR231x/531x ethernet controller
28 +
29 endif # NET_VENDOR_ATHEROS
30 --- /dev/null
31 +++ b/drivers/net/ethernet/atheros/ar231x/Makefile
32 @@ -0,0 +1 @@
33 +obj-$(CONFIG_NET_AR231X) += ar231x.o
34 --- /dev/null
35 +++ b/drivers/net/ethernet/atheros/ar231x/ar231x.c
36 @@ -0,0 +1,1218 @@
37 +/*
38 + * ar231x.c: Linux driver for the Atheros AR231x Ethernet device.
39 + *
40 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
41 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
42 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
43 + *
44 + * Thanks to Atheros for providing hardware and documentation
45 + * enabling me to write this driver.
46 + *
47 + * This program is free software; you can redistribute it and/or modify
48 + * it under the terms of the GNU General Public License as published by
49 + * the Free Software Foundation; either version 2 of the License, or
50 + * (at your option) any later version.
51 + *
52 + * Additional credits:
53 + * This code is taken from John Taylor's Sibyte driver and then
54 + * modified for the AR2313.
55 + */
56 +
57 +#include <linux/module.h>
58 +#include <linux/types.h>
59 +#include <linux/errno.h>
60 +#include <linux/ioport.h>
61 +#include <linux/netdevice.h>
62 +#include <linux/etherdevice.h>
63 +#include <linux/interrupt.h>
64 +#include <linux/skbuff.h>
65 +#include <linux/init.h>
66 +#include <linux/delay.h>
67 +#include <linux/mm.h>
68 +#include <linux/mii.h>
69 +#include <linux/phy.h>
70 +#include <linux/platform_device.h>
71 +#include <linux/io.h>
72 +
73 +#define AR2313_MTU 1692
74 +#define AR2313_PRIOS 1
75 +#define AR2313_QUEUES (2*AR2313_PRIOS)
76 +#define AR2313_DESCR_ENTRIES 64
77 +
78 +#ifndef min
79 +#define min(a, b) (((a) < (b)) ? (a) : (b))
80 +#endif
81 +
82 +#ifndef SMP_CACHE_BYTES
83 +#define SMP_CACHE_BYTES L1_CACHE_BYTES
84 +#endif
85 +
86 +#define AR2313_MBOX_SET_BIT 0x8
87 +
88 +#include "ar231x.h"
89 +
90 +/**
91 + * New interrupt handler strategy:
92 + *
93 + * An old interrupt handler worked using the traditional method of
94 + * replacing an skbuff with a new one when a packet arrives. However
95 + * the rx rings do not need to contain a static number of buffer
96 + * descriptors, thus it makes sense to move the memory allocation out
97 + * of the main interrupt handler and do it in a bottom half handler
98 + * and only allocate new buffers when the number of buffers in the
99 + * ring is below a certain threshold. In order to avoid starving the
100 + * NIC under heavy load it is however necessary to force allocation
101 + * when hitting a minimum threshold. The strategy for alloction is as
102 + * follows:
103 + *
104 + * RX_LOW_BUF_THRES - allocate buffers in the bottom half
105 + * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
106 + * the buffers in the interrupt handler
107 + * RX_RING_THRES - maximum number of buffers in the rx ring
108 + *
109 + * One advantagous side effect of this allocation approach is that the
110 + * entire rx processing can be done without holding any spin lock
111 + * since the rx rings and registers are totally independent of the tx
112 + * ring and its registers. This of course includes the kmalloc's of
113 + * new skb's. Thus start_xmit can run in parallel with rx processing
114 + * and the memory allocation on SMP systems.
115 + *
116 + * Note that running the skb reallocation in a bottom half opens up
117 + * another can of races which needs to be handled properly. In
118 + * particular it can happen that the interrupt handler tries to run
119 + * the reallocation while the bottom half is either running on another
120 + * CPU or was interrupted on the same CPU. To get around this the
121 + * driver uses bitops to prevent the reallocation routines from being
122 + * reentered.
123 + *
124 + * TX handling can also be done without holding any spin lock, wheee
125 + * this is fun! since tx_csm is only written to by the interrupt
126 + * handler.
127 + */
128 +
129 +/**
130 + * Threshold values for RX buffer allocation - the low water marks for
131 + * when to start refilling the rings are set to 75% of the ring
132 + * sizes. It seems to make sense to refill the rings entirely from the
133 + * intrrupt handler once it gets below the panic threshold, that way
134 + * we don't risk that the refilling is moved to another CPU when the
135 + * one running the interrupt handler just got the slab code hot in its
136 + * cache.
137 + */
138 +#define RX_RING_SIZE AR2313_DESCR_ENTRIES
139 +#define RX_PANIC_THRES (RX_RING_SIZE/4)
140 +#define RX_LOW_THRES ((3*RX_RING_SIZE)/4)
141 +#define CRC_LEN 4
142 +#define RX_OFFSET 2
143 +
144 +#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
145 +#define VLAN_HDR 4
146 +#else
147 +#define VLAN_HDR 0
148 +#endif
149 +
150 +#define AR2313_BUFSIZE (AR2313_MTU + VLAN_HDR + ETH_HLEN + CRC_LEN + \
151 + RX_OFFSET)
152 +
153 +#ifdef MODULE
154 +MODULE_LICENSE("GPL");
155 +MODULE_AUTHOR("Sameer Dekate <sdekate@arubanetworks.com>, Imre Kaloz <kaloz@openwrt.org>, Felix Fietkau <nbd@openwrt.org>");
156 +MODULE_DESCRIPTION("AR231x Ethernet driver");
157 +#endif
158 +
159 +#define virt_to_phys(x) ((u32)(x) & 0x1fffffff)
160 +
161 +/* prototypes */
162 +static void ar231x_halt(struct net_device *dev);
163 +static void rx_tasklet_func(unsigned long data);
164 +static void rx_tasklet_cleanup(struct net_device *dev);
165 +static void ar231x_multicast_list(struct net_device *dev);
166 +static void ar231x_tx_timeout(struct net_device *dev);
167 +
168 +static int ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum);
169 +static int ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
170 + u16 value);
171 +static int ar231x_mdiobus_reset(struct mii_bus *bus);
172 +static int ar231x_mdiobus_probe(struct net_device *dev);
173 +static void ar231x_adjust_link(struct net_device *dev);
174 +
175 +#ifndef ERR
176 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
177 +#endif
178 +
179 +#ifdef CONFIG_NET_POLL_CONTROLLER
180 +static void
181 +ar231x_netpoll(struct net_device *dev)
182 +{
183 + unsigned long flags;
184 +
185 + local_irq_save(flags);
186 + ar231x_interrupt(dev->irq, dev);
187 + local_irq_restore(flags);
188 +}
189 +#endif
190 +
191 +static const struct net_device_ops ar231x_ops = {
192 + .ndo_open = ar231x_open,
193 + .ndo_stop = ar231x_close,
194 + .ndo_start_xmit = ar231x_start_xmit,
195 + .ndo_set_rx_mode = ar231x_multicast_list,
196 + .ndo_do_ioctl = ar231x_ioctl,
197 + .ndo_change_mtu = eth_change_mtu,
198 + .ndo_validate_addr = eth_validate_addr,
199 + .ndo_set_mac_address = eth_mac_addr,
200 + .ndo_tx_timeout = ar231x_tx_timeout,
201 +#ifdef CONFIG_NET_POLL_CONTROLLER
202 + .ndo_poll_controller = ar231x_netpoll,
203 +#endif
204 +};
205 +
206 +static int ar231x_probe(struct platform_device *pdev)
207 +{
208 + struct net_device *dev;
209 + struct ar231x_private *sp;
210 + struct resource *res;
211 + unsigned long ar_eth_base;
212 + char buf[64];
213 +
214 + dev = alloc_etherdev(sizeof(struct ar231x_private));
215 +
216 + if (dev == NULL) {
217 + printk(KERN_ERR
218 + "ar231x: Unable to allocate net_device structure!\n");
219 + return -ENOMEM;
220 + }
221 +
222 + platform_set_drvdata(pdev, dev);
223 +
224 + sp = netdev_priv(dev);
225 + sp->dev = dev;
226 + sp->cfg = pdev->dev.platform_data;
227 +
228 + sprintf(buf, "eth%d_membase", pdev->id);
229 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, buf);
230 + if (!res)
231 + return -ENODEV;
232 +
233 + sp->link = 0;
234 + ar_eth_base = res->start;
235 +
236 + sprintf(buf, "eth%d_irq", pdev->id);
237 + dev->irq = platform_get_irq_byname(pdev, buf);
238 +
239 + spin_lock_init(&sp->lock);
240 +
241 + dev->features |= NETIF_F_HIGHDMA;
242 + dev->netdev_ops = &ar231x_ops;
243 +
244 + tasklet_init(&sp->rx_tasklet, rx_tasklet_func, (unsigned long) dev);
245 + tasklet_disable(&sp->rx_tasklet);
246 +
247 + sp->eth_regs = ioremap_nocache(ar_eth_base, sizeof(*sp->eth_regs));
248 + if (!sp->eth_regs) {
249 + printk("Can't remap eth registers\n");
250 + return -ENXIO;
251 + }
252 +
253 + /**
254 + * When there's only one MAC, PHY regs are typically on ENET0,
255 + * even though the MAC might be on ENET1.
256 + * So remap PHY regs separately.
257 + */
258 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "eth0_mii");
259 + if (!res) {
260 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
261 + "eth1_mii");
262 + if (!res)
263 + return -ENODEV;
264 + }
265 + sp->phy_regs = ioremap_nocache(res->start, resource_size(res));
266 + if (!sp->phy_regs) {
267 + printk("Can't remap phy registers\n");
268 + return -ENXIO;
269 + }
270 +
271 + sp->dma_regs = ioremap_nocache(ar_eth_base + 0x1000,
272 + sizeof(*sp->dma_regs));
273 + if (!sp->dma_regs) {
274 + printk("Can't remap DMA registers\n");
275 + return -ENXIO;
276 + }
277 + dev->base_addr = ar_eth_base + 0x1000;
278 +
279 + strncpy(sp->name, "Atheros AR231x", sizeof(sp->name) - 1);
280 + sp->name[sizeof(sp->name) - 1] = '\0';
281 + memcpy(dev->dev_addr, sp->cfg->macaddr, 6);
282 +
283 + if (ar231x_init(dev)) {
284 + /* ar231x_init() calls ar231x_init_cleanup() on error */
285 + kfree(dev);
286 + return -ENODEV;
287 + }
288 +
289 + if (register_netdev(dev)) {
290 + printk("%s: register_netdev failed\n", __func__);
291 + return -1;
292 + }
293 +
294 + printk("%s: %s: %pM, irq %d\n", dev->name, sp->name, dev->dev_addr,
295 + dev->irq);
296 +
297 + sp->mii_bus = mdiobus_alloc();
298 + if (sp->mii_bus == NULL)
299 + return -1;
300 +
301 + sp->mii_bus->priv = dev;
302 + sp->mii_bus->read = ar231x_mdiobus_read;
303 + sp->mii_bus->write = ar231x_mdiobus_write;
304 + sp->mii_bus->reset = ar231x_mdiobus_reset;
305 + sp->mii_bus->name = "ar231x_eth_mii";
306 + snprintf(sp->mii_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
307 + sp->mii_bus->irq = kmalloc(sizeof(int), GFP_KERNEL);
308 + *sp->mii_bus->irq = PHY_POLL;
309 +
310 + mdiobus_register(sp->mii_bus);
311 +
312 + if (ar231x_mdiobus_probe(dev) != 0) {
313 + printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name);
314 + rx_tasklet_cleanup(dev);
315 + ar231x_init_cleanup(dev);
316 + unregister_netdev(dev);
317 + kfree(dev);
318 + return -ENODEV;
319 + }
320 +
321 + /* start link poll timer */
322 + ar231x_setup_timer(dev);
323 +
324 + return 0;
325 +}
326 +
327 +
328 +static void ar231x_multicast_list(struct net_device *dev)
329 +{
330 + struct ar231x_private *sp = netdev_priv(dev);
331 + unsigned int filter;
332 +
333 + filter = sp->eth_regs->mac_control;
334 +
335 + if (dev->flags & IFF_PROMISC)
336 + filter |= MAC_CONTROL_PR;
337 + else
338 + filter &= ~MAC_CONTROL_PR;
339 + if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 0))
340 + filter |= MAC_CONTROL_PM;
341 + else
342 + filter &= ~MAC_CONTROL_PM;
343 +
344 + sp->eth_regs->mac_control = filter;
345 +}
346 +
347 +static void rx_tasklet_cleanup(struct net_device *dev)
348 +{
349 + struct ar231x_private *sp = netdev_priv(dev);
350 +
351 + /**
352 + * Tasklet may be scheduled. Need to get it removed from the list
353 + * since we're about to free the struct.
354 + */
355 +
356 + sp->unloading = 1;
357 + tasklet_enable(&sp->rx_tasklet);
358 + tasklet_kill(&sp->rx_tasklet);
359 +}
360 +
361 +static int ar231x_remove(struct platform_device *pdev)
362 +{
363 + struct net_device *dev = platform_get_drvdata(pdev);
364 + struct ar231x_private *sp = netdev_priv(dev);
365 +
366 + rx_tasklet_cleanup(dev);
367 + ar231x_init_cleanup(dev);
368 + unregister_netdev(dev);
369 + mdiobus_unregister(sp->mii_bus);
370 + mdiobus_free(sp->mii_bus);
371 + kfree(dev);
372 + return 0;
373 +}
374 +
375 +
376 +/**
377 + * Restart the AR2313 ethernet controller.
378 + */
379 +static int ar231x_restart(struct net_device *dev)
380 +{
381 + /* disable interrupts */
382 + disable_irq(dev->irq);
383 +
384 + /* stop mac */
385 + ar231x_halt(dev);
386 +
387 + /* initialize */
388 + ar231x_init(dev);
389 +
390 + /* enable interrupts */
391 + enable_irq(dev->irq);
392 +
393 + return 0;
394 +}
395 +
396 +static struct platform_driver ar231x_driver = {
397 + .driver.name = "ar231x-eth",
398 + .probe = ar231x_probe,
399 + .remove = ar231x_remove,
400 +};
401 +
402 +module_platform_driver(ar231x_driver);
403 +
404 +static void ar231x_free_descriptors(struct net_device *dev)
405 +{
406 + struct ar231x_private *sp = netdev_priv(dev);
407 +
408 + if (sp->rx_ring != NULL) {
409 + kfree((void *)KSEG0ADDR(sp->rx_ring));
410 + sp->rx_ring = NULL;
411 + sp->tx_ring = NULL;
412 + }
413 +}
414 +
415 +
416 +static int ar231x_allocate_descriptors(struct net_device *dev)
417 +{
418 + struct ar231x_private *sp = netdev_priv(dev);
419 + int size;
420 + int j;
421 + ar231x_descr_t *space;
422 +
423 + if (sp->rx_ring != NULL) {
424 + printk("%s: already done.\n", __func__);
425 + return 0;
426 + }
427 +
428 + size = sizeof(ar231x_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES);
429 + space = kmalloc(size, GFP_KERNEL);
430 + if (space == NULL)
431 + return 1;
432 +
433 + /* invalidate caches */
434 + dma_cache_inv((unsigned int) space, size);
435 +
436 + /* now convert pointer to KSEG1 */
437 + space = (ar231x_descr_t *)KSEG1ADDR(space);
438 +
439 + memset((void *)space, 0, size);
440 +
441 + sp->rx_ring = space;
442 + space += AR2313_DESCR_ENTRIES;
443 +
444 + sp->tx_ring = space;
445 + space += AR2313_DESCR_ENTRIES;
446 +
447 + /* Initialize the transmit Descriptors */
448 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
449 + ar231x_descr_t *td = &sp->tx_ring[j];
450 +
451 + td->status = 0;
452 + td->devcs = DMA_TX1_CHAINED;
453 + td->addr = 0;
454 + td->descr = virt_to_phys(&sp->tx_ring[DSC_NEXT(j)]);
455 + }
456 +
457 + return 0;
458 +}
459 +
460 +
461 +/**
462 + * Generic cleanup handling data allocated during init. Used when the
463 + * module is unloaded or if an error occurs during initialization
464 + */
465 +static void ar231x_init_cleanup(struct net_device *dev)
466 +{
467 + struct ar231x_private *sp = netdev_priv(dev);
468 + struct sk_buff *skb;
469 + int j;
470 +
471 + ar231x_free_descriptors(dev);
472 +
473 + if (sp->eth_regs)
474 + iounmap((void *)sp->eth_regs);
475 + if (sp->dma_regs)
476 + iounmap((void *)sp->dma_regs);
477 + if (sp->phy_regs)
478 + iounmap((void *)sp->phy_regs);
479 +
480 + if (sp->rx_skb) {
481 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
482 + skb = sp->rx_skb[j];
483 + if (skb) {
484 + sp->rx_skb[j] = NULL;
485 + dev_kfree_skb(skb);
486 + }
487 + }
488 + kfree(sp->rx_skb);
489 + sp->rx_skb = NULL;
490 + }
491 +
492 + if (sp->tx_skb) {
493 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
494 + skb = sp->tx_skb[j];
495 + if (skb) {
496 + sp->tx_skb[j] = NULL;
497 + dev_kfree_skb(skb);
498 + }
499 + }
500 + kfree(sp->tx_skb);
501 + sp->tx_skb = NULL;
502 + }
503 +}
504 +
505 +static int ar231x_setup_timer(struct net_device *dev)
506 +{
507 + struct ar231x_private *sp = netdev_priv(dev);
508 +
509 + init_timer(&sp->link_timer);
510 +
511 + sp->link_timer.function = ar231x_link_timer_fn;
512 + sp->link_timer.data = (int) dev;
513 + sp->link_timer.expires = jiffies + HZ;
514 +
515 + add_timer(&sp->link_timer);
516 + return 0;
517 +}
518 +
519 +static void ar231x_link_timer_fn(unsigned long data)
520 +{
521 + struct net_device *dev = (struct net_device *)data;
522 + struct ar231x_private *sp = netdev_priv(dev);
523 +
524 + /**
525 + * See if the link status changed.
526 + * This was needed to make sure we set the PHY to the
527 + * autonegotiated value of half or full duplex.
528 + */
529 + ar231x_check_link(dev);
530 +
531 + /**
532 + * Loop faster when we don't have link.
533 + * This was needed to speed up the AP bootstrap time.
534 + */
535 + if (sp->link == 0)
536 + mod_timer(&sp->link_timer, jiffies + HZ / 2);
537 + else
538 + mod_timer(&sp->link_timer, jiffies + LINK_TIMER);
539 +}
540 +
541 +static void ar231x_check_link(struct net_device *dev)
542 +{
543 + struct ar231x_private *sp = netdev_priv(dev);
544 + u16 phy_data;
545 +
546 + phy_data = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMSR);
547 + if (sp->phy_data != phy_data) {
548 + if (phy_data & BMSR_LSTATUS) {
549 + /**
550 + * Link is present, ready link partner ability to
551 + * deterine duplexity.
552 + */
553 + int duplex = 0;
554 + u16 reg;
555 +
556 + sp->link = 1;
557 + reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy,
558 + MII_BMCR);
559 + if (reg & BMCR_ANENABLE) {
560 + /* auto neg enabled */
561 + reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy,
562 + MII_LPA);
563 + duplex = reg & (LPA_100FULL | LPA_10FULL) ?
564 + 1 : 0;
565 + } else {
566 + /* no auto neg, just read duplex config */
567 + duplex = (reg & BMCR_FULLDPLX) ? 1 : 0;
568 + }
569 +
570 + printk(KERN_INFO "%s: Configuring MAC for %s duplex\n",
571 + dev->name, (duplex) ? "full" : "half");
572 +
573 + if (duplex) {
574 + /* full duplex */
575 + sp->eth_regs->mac_control =
576 + (sp->eth_regs->mac_control |
577 + MAC_CONTROL_F) & ~MAC_CONTROL_DRO;
578 + } else {
579 + /* half duplex */
580 + sp->eth_regs->mac_control =
581 + (sp->eth_regs->mac_control |
582 + MAC_CONTROL_DRO) & ~MAC_CONTROL_F;
583 + }
584 + } else {
585 + /* no link */
586 + sp->link = 0;
587 + }
588 + sp->phy_data = phy_data;
589 + }
590 +}
591 +
592 +static int ar231x_reset_reg(struct net_device *dev)
593 +{
594 + struct ar231x_private *sp = netdev_priv(dev);
595 + unsigned int ethsal, ethsah;
596 + unsigned int flags;
597 +
598 + sp->cfg->reset_set(sp->cfg->reset_mac);
599 + mdelay(10);
600 + sp->cfg->reset_clear(sp->cfg->reset_mac);
601 + mdelay(10);
602 + sp->cfg->reset_set(sp->cfg->reset_phy);
603 + mdelay(10);
604 + sp->cfg->reset_clear(sp->cfg->reset_phy);
605 + mdelay(10);
606 +
607 + sp->dma_regs->bus_mode = (DMA_BUS_MODE_SWR);
608 + mdelay(10);
609 + sp->dma_regs->bus_mode =
610 + ((32 << DMA_BUS_MODE_PBL_SHIFT) | DMA_BUS_MODE_BLE);
611 +
612 + /* enable interrupts */
613 + sp->dma_regs->intr_ena = DMA_STATUS_AIS | DMA_STATUS_NIS |
614 + DMA_STATUS_RI | DMA_STATUS_TI |
615 + DMA_STATUS_FBE;
616 + sp->dma_regs->xmt_base = virt_to_phys(sp->tx_ring);
617 + sp->dma_regs->rcv_base = virt_to_phys(sp->rx_ring);
618 + sp->dma_regs->control =
619 + (DMA_CONTROL_SR | DMA_CONTROL_ST | DMA_CONTROL_SF);
620 +
621 + sp->eth_regs->flow_control = (FLOW_CONTROL_FCE);
622 + sp->eth_regs->vlan_tag = (0x8100);
623 +
624 + /* Enable Ethernet Interface */
625 + flags = (MAC_CONTROL_TE | /* transmit enable */
626 + MAC_CONTROL_PM | /* pass mcast */
627 + MAC_CONTROL_F | /* full duplex */
628 + MAC_CONTROL_HBD); /* heart beat disabled */
629 +
630 + if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
631 + flags |= MAC_CONTROL_PR;
632 + }
633 + sp->eth_regs->mac_control = flags;
634 +
635 + /* Set all Ethernet station address registers to their initial values */
636 + ethsah = (((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
637 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF);
638 +
639 + ethsal = (((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
640 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
641 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
642 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF);
643 +
644 + sp->eth_regs->mac_addr[0] = ethsah;
645 + sp->eth_regs->mac_addr[1] = ethsal;
646 +
647 + mdelay(10);
648 +
649 + return 0;
650 +}
651 +
652 +
653 +static int ar231x_init(struct net_device *dev)
654 +{
655 + struct ar231x_private *sp = netdev_priv(dev);
656 + int ecode = 0;
657 +
658 + /* Allocate descriptors */
659 + if (ar231x_allocate_descriptors(dev)) {
660 + printk("%s: %s: ar231x_allocate_descriptors failed\n",
661 + dev->name, __func__);
662 + ecode = -EAGAIN;
663 + goto init_error;
664 + }
665 +
666 + /* Get the memory for the skb rings */
667 + if (sp->rx_skb == NULL) {
668 + sp->rx_skb =
669 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
670 + GFP_KERNEL);
671 + if (!(sp->rx_skb)) {
672 + printk("%s: %s: rx_skb kmalloc failed\n",
673 + dev->name, __func__);
674 + ecode = -EAGAIN;
675 + goto init_error;
676 + }
677 + }
678 + memset(sp->rx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
679 +
680 + if (sp->tx_skb == NULL) {
681 + sp->tx_skb =
682 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
683 + GFP_KERNEL);
684 + if (!(sp->tx_skb)) {
685 + printk("%s: %s: tx_skb kmalloc failed\n",
686 + dev->name, __func__);
687 + ecode = -EAGAIN;
688 + goto init_error;
689 + }
690 + }
691 + memset(sp->tx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
692 +
693 + /**
694 + * Set tx_csm before we start receiving interrupts, otherwise
695 + * the interrupt handler might think it is supposed to process
696 + * tx ints before we are up and running, which may cause a null
697 + * pointer access in the int handler.
698 + */
699 + sp->rx_skbprd = 0;
700 + sp->cur_rx = 0;
701 + sp->tx_prd = 0;
702 + sp->tx_csm = 0;
703 +
704 + /* Zero the stats before starting the interface */
705 + memset(&dev->stats, 0, sizeof(dev->stats));
706 +
707 + /**
708 + * We load the ring here as there seem to be no way to tell the
709 + * firmware to wipe the ring without re-initializing it.
710 + */
711 + ar231x_load_rx_ring(dev, RX_RING_SIZE);
712 +
713 + /* Init hardware */
714 + ar231x_reset_reg(dev);
715 +
716 + /* Get the IRQ */
717 + ecode =
718 + request_irq(dev->irq, &ar231x_interrupt,
719 + IRQF_DISABLED,
720 + dev->name, dev);
721 + if (ecode) {
722 + printk(KERN_WARNING "%s: %s: Requested IRQ %d is busy\n",
723 + dev->name, __func__, dev->irq);
724 + goto init_error;
725 + }
726 +
727 +
728 + tasklet_enable(&sp->rx_tasklet);
729 +
730 + return 0;
731 +
732 +init_error:
733 + ar231x_init_cleanup(dev);
734 + return ecode;
735 +}
736 +
737 +/**
738 + * Load the rx ring.
739 + *
740 + * Loading rings is safe without holding the spin lock since this is
741 + * done only before the device is enabled, thus no interrupts are
742 + * generated and by the interrupt handler/tasklet handler.
743 + */
744 +static void ar231x_load_rx_ring(struct net_device *dev, int nr_bufs)
745 +{
746 + struct ar231x_private *sp = netdev_priv(dev);
747 + short i, idx;
748 +
749 + idx = sp->rx_skbprd;
750 +
751 + for (i = 0; i < nr_bufs; i++) {
752 + struct sk_buff *skb;
753 + ar231x_descr_t *rd;
754 +
755 + if (sp->rx_skb[idx])
756 + break;
757 +
758 + skb = netdev_alloc_skb_ip_align(dev, AR2313_BUFSIZE);
759 + if (!skb) {
760 + printk("\n\n\n\n %s: No memory in system\n\n\n\n",
761 + __func__);
762 + break;
763 + }
764 +
765 + /* Make sure IP header starts on a fresh cache line */
766 + skb->dev = dev;
767 + sp->rx_skb[idx] = skb;
768 +
769 + rd = (ar231x_descr_t *)&sp->rx_ring[idx];
770 +
771 + /* initialize dma descriptor */
772 + rd->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
773 + DMA_RX1_CHAINED);
774 + rd->addr = virt_to_phys(skb->data);
775 + rd->descr = virt_to_phys(&sp->rx_ring[DSC_NEXT(idx)]);
776 + rd->status = DMA_RX_OWN;
777 +
778 + idx = DSC_NEXT(idx);
779 + }
780 +
781 + if (i)
782 + sp->rx_skbprd = idx;
783 +}
784 +
785 +#define AR2313_MAX_PKTS_PER_CALL 64
786 +
787 +static int ar231x_rx_int(struct net_device *dev)
788 +{
789 + struct ar231x_private *sp = netdev_priv(dev);
790 + struct sk_buff *skb, *skb_new;
791 + ar231x_descr_t *rxdesc;
792 + unsigned int status;
793 + u32 idx;
794 + int pkts = 0;
795 + int rval;
796 +
797 + idx = sp->cur_rx;
798 +
799 + /* process at most the entire ring and then wait for another int */
800 + while (1) {
801 + rxdesc = &sp->rx_ring[idx];
802 + status = rxdesc->status;
803 +
804 + if (status & DMA_RX_OWN) {
805 + /* SiByte owns descriptor or descr not yet filled in */
806 + rval = 0;
807 + break;
808 + }
809 +
810 + if (++pkts > AR2313_MAX_PKTS_PER_CALL) {
811 + rval = 1;
812 + break;
813 + }
814 +
815 + if ((status & DMA_RX_ERROR) && !(status & DMA_RX_LONG)) {
816 + dev->stats.rx_errors++;
817 + dev->stats.rx_dropped++;
818 +
819 + /* add statistics counters */
820 + if (status & DMA_RX_ERR_CRC)
821 + dev->stats.rx_crc_errors++;
822 + if (status & DMA_RX_ERR_COL)
823 + dev->stats.rx_over_errors++;
824 + if (status & DMA_RX_ERR_LENGTH)
825 + dev->stats.rx_length_errors++;
826 + if (status & DMA_RX_ERR_RUNT)
827 + dev->stats.rx_over_errors++;
828 + if (status & DMA_RX_ERR_DESC)
829 + dev->stats.rx_over_errors++;
830 +
831 + } else {
832 + /* alloc new buffer. */
833 + skb_new = netdev_alloc_skb_ip_align(dev,
834 + AR2313_BUFSIZE);
835 + if (skb_new != NULL) {
836 + skb = sp->rx_skb[idx];
837 + /* set skb */
838 + skb_put(skb, ((status >> DMA_RX_LEN_SHIFT) &
839 + 0x3fff) - CRC_LEN);
840 +
841 + dev->stats.rx_bytes += skb->len;
842 + skb->protocol = eth_type_trans(skb, dev);
843 + /* pass the packet to upper layers */
844 + netif_rx(skb);
845 +
846 + skb_new->dev = dev;
847 + /* reset descriptor's curr_addr */
848 + rxdesc->addr = virt_to_phys(skb_new->data);
849 +
850 + dev->stats.rx_packets++;
851 + sp->rx_skb[idx] = skb_new;
852 + } else {
853 + dev->stats.rx_dropped++;
854 + }
855 + }
856 +
857 + rxdesc->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
858 + DMA_RX1_CHAINED);
859 + rxdesc->status = DMA_RX_OWN;
860 +
861 + idx = DSC_NEXT(idx);
862 + }
863 +
864 + sp->cur_rx = idx;
865 +
866 + return rval;
867 +}
868 +
869 +
870 +static void ar231x_tx_int(struct net_device *dev)
871 +{
872 + struct ar231x_private *sp = netdev_priv(dev);
873 + u32 idx;
874 + struct sk_buff *skb;
875 + ar231x_descr_t *txdesc;
876 + unsigned int status = 0;
877 +
878 + idx = sp->tx_csm;
879 +
880 + while (idx != sp->tx_prd) {
881 + txdesc = &sp->tx_ring[idx];
882 + status = txdesc->status;
883 +
884 + if (status & DMA_TX_OWN) {
885 + /* ar231x dma still owns descr */
886 + break;
887 + }
888 + /* done with this descriptor */
889 + dma_unmap_single(NULL, txdesc->addr,
890 + txdesc->devcs & DMA_TX1_BSIZE_MASK,
891 + DMA_TO_DEVICE);
892 + txdesc->status = 0;
893 +
894 + if (status & DMA_TX_ERROR) {
895 + dev->stats.tx_errors++;
896 + dev->stats.tx_dropped++;
897 + if (status & DMA_TX_ERR_UNDER)
898 + dev->stats.tx_fifo_errors++;
899 + if (status & DMA_TX_ERR_HB)
900 + dev->stats.tx_heartbeat_errors++;
901 + if (status & (DMA_TX_ERR_LOSS | DMA_TX_ERR_LINK))
902 + dev->stats.tx_carrier_errors++;
903 + if (status & (DMA_TX_ERR_LATE | DMA_TX_ERR_COL |
904 + DMA_TX_ERR_JABBER | DMA_TX_ERR_DEFER))
905 + dev->stats.tx_aborted_errors++;
906 + } else {
907 + /* transmit OK */
908 + dev->stats.tx_packets++;
909 + }
910 +
911 + skb = sp->tx_skb[idx];
912 + sp->tx_skb[idx] = NULL;
913 + idx = DSC_NEXT(idx);
914 + dev->stats.tx_bytes += skb->len;
915 + dev_kfree_skb_irq(skb);
916 + }
917 +
918 + sp->tx_csm = idx;
919 +}
920 +
921 +
922 +static void rx_tasklet_func(unsigned long data)
923 +{
924 + struct net_device *dev = (struct net_device *)data;
925 + struct ar231x_private *sp = netdev_priv(dev);
926 +
927 + if (sp->unloading)
928 + return;
929 +
930 + if (ar231x_rx_int(dev)) {
931 + tasklet_hi_schedule(&sp->rx_tasklet);
932 + } else {
933 + unsigned long flags;
934 +
935 + spin_lock_irqsave(&sp->lock, flags);
936 + sp->dma_regs->intr_ena |= DMA_STATUS_RI;
937 + spin_unlock_irqrestore(&sp->lock, flags);
938 + }
939 +}
940 +
941 +static void rx_schedule(struct net_device *dev)
942 +{
943 + struct ar231x_private *sp = netdev_priv(dev);
944 +
945 + sp->dma_regs->intr_ena &= ~DMA_STATUS_RI;
946 +
947 + tasklet_hi_schedule(&sp->rx_tasklet);
948 +}
949 +
950 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id)
951 +{
952 + struct net_device *dev = (struct net_device *)dev_id;
953 + struct ar231x_private *sp = netdev_priv(dev);
954 + unsigned int status, enabled;
955 +
956 + /* clear interrupt */
957 + /* Don't clear RI bit if currently disabled */
958 + status = sp->dma_regs->status;
959 + enabled = sp->dma_regs->intr_ena;
960 + sp->dma_regs->status = status & enabled;
961 +
962 + if (status & DMA_STATUS_NIS) {
963 + /* normal status */
964 + /**
965 + * Don't schedule rx processing if interrupt
966 + * is already disabled.
967 + */
968 + if (status & enabled & DMA_STATUS_RI) {
969 + /* receive interrupt */
970 + rx_schedule(dev);
971 + }
972 + if (status & DMA_STATUS_TI) {
973 + /* transmit interrupt */
974 + ar231x_tx_int(dev);
975 + }
976 + }
977 +
978 + /* abnormal status */
979 + if (status & (DMA_STATUS_FBE | DMA_STATUS_TPS))
980 + ar231x_restart(dev);
981 +
982 + return IRQ_HANDLED;
983 +}
984 +
985 +
986 +static int ar231x_open(struct net_device *dev)
987 +{
988 + struct ar231x_private *sp = netdev_priv(dev);
989 + unsigned int ethsal, ethsah;
990 +
991 + /* reset the hardware, in case the MAC address changed */
992 + ethsah = (((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
993 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF);
994 +
995 + ethsal = (((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
996 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
997 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
998 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF);
999 +
1000 + sp->eth_regs->mac_addr[0] = ethsah;
1001 + sp->eth_regs->mac_addr[1] = ethsal;
1002 +
1003 + mdelay(10);
1004 +
1005 + dev->mtu = 1500;
1006 + netif_start_queue(dev);
1007 +
1008 + sp->eth_regs->mac_control |= MAC_CONTROL_RE;
1009 +
1010 + return 0;
1011 +}
1012 +
1013 +static void ar231x_tx_timeout(struct net_device *dev)
1014 +{
1015 + struct ar231x_private *sp = netdev_priv(dev);
1016 + unsigned long flags;
1017 +
1018 + spin_lock_irqsave(&sp->lock, flags);
1019 + ar231x_restart(dev);
1020 + spin_unlock_irqrestore(&sp->lock, flags);
1021 +}
1022 +
1023 +static void ar231x_halt(struct net_device *dev)
1024 +{
1025 + struct ar231x_private *sp = netdev_priv(dev);
1026 + int j;
1027 +
1028 + tasklet_disable(&sp->rx_tasklet);
1029 +
1030 + /* kill the MAC */
1031 + sp->eth_regs->mac_control &= ~(MAC_CONTROL_RE | /* disable Receives */
1032 + MAC_CONTROL_TE); /* disable Transmits */
1033 + /* stop dma */
1034 + sp->dma_regs->control = 0;
1035 + sp->dma_regs->bus_mode = DMA_BUS_MODE_SWR;
1036 +
1037 + /* place phy and MAC in reset */
1038 + sp->cfg->reset_set(sp->cfg->reset_mac);
1039 + sp->cfg->reset_set(sp->cfg->reset_phy);
1040 +
1041 + /* free buffers on tx ring */
1042 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
1043 + struct sk_buff *skb;
1044 + ar231x_descr_t *txdesc;
1045 +
1046 + txdesc = &sp->tx_ring[j];
1047 + txdesc->descr = 0;
1048 +
1049 + skb = sp->tx_skb[j];
1050 + if (skb) {
1051 + dev_kfree_skb(skb);
1052 + sp->tx_skb[j] = NULL;
1053 + }
1054 + }
1055 +}
1056 +
1057 +/**
1058 + * close should do nothing. Here's why. It's called when
1059 + * 'ifconfig bond0 down' is run. If it calls free_irq then
1060 + * the irq is gone forever ! When bond0 is made 'up' again,
1061 + * the ar231x_open () does not call request_irq (). Worse,
1062 + * the call to ar231x_halt() generates a WDOG reset due to
1063 + * the write to reset register and the box reboots.
1064 + * Commenting this out is good since it allows the
1065 + * system to resume when bond0 is made up again.
1066 + */
1067 +static int ar231x_close(struct net_device *dev)
1068 +{
1069 +#if 0
1070 + /* Disable interrupts */
1071 + disable_irq(dev->irq);
1072 +
1073 + /**
1074 + * Without (or before) releasing irq and stopping hardware, this
1075 + * is an absolute non-sense, by the way. It will be reset instantly
1076 + * by the first irq.
1077 + */
1078 + netif_stop_queue(dev);
1079 +
1080 + /* stop the MAC and DMA engines */
1081 + ar231x_halt(dev);
1082 +
1083 + /* release the interrupt */
1084 + free_irq(dev->irq, dev);
1085 +
1086 +#endif
1087 + return 0;
1088 +}
1089 +
1090 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev)
1091 +{
1092 + struct ar231x_private *sp = netdev_priv(dev);
1093 + ar231x_descr_t *td;
1094 + u32 idx;
1095 +
1096 + idx = sp->tx_prd;
1097 + td = &sp->tx_ring[idx];
1098 +
1099 + if (td->status & DMA_TX_OWN) {
1100 + /* free skbuf and lie to the caller that we sent it out */
1101 + dev->stats.tx_dropped++;
1102 + dev_kfree_skb(skb);
1103 +
1104 + /* restart transmitter in case locked */
1105 + sp->dma_regs->xmt_poll = 0;
1106 + return 0;
1107 + }
1108 +
1109 + /* Setup the transmit descriptor. */
1110 + td->devcs = ((skb->len << DMA_TX1_BSIZE_SHIFT) |
1111 + (DMA_TX1_LS | DMA_TX1_IC | DMA_TX1_CHAINED));
1112 + td->addr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
1113 + td->status = DMA_TX_OWN;
1114 +
1115 + /* kick transmitter last */
1116 + sp->dma_regs->xmt_poll = 0;
1117 +
1118 + sp->tx_skb[idx] = skb;
1119 + idx = DSC_NEXT(idx);
1120 + sp->tx_prd = idx;
1121 +
1122 + return 0;
1123 +}
1124 +
1125 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1126 +{
1127 + struct ar231x_private *sp = netdev_priv(dev);
1128 +
1129 + switch (cmd) {
1130 + case SIOCGMIIPHY:
1131 + case SIOCGMIIREG:
1132 + case SIOCSMIIREG:
1133 + return phy_mii_ioctl(sp->phy_dev, ifr, cmd);
1134 +
1135 + default:
1136 + break;
1137 + }
1138 +
1139 + return -EOPNOTSUPP;
1140 +}
1141 +
1142 +static void ar231x_adjust_link(struct net_device *dev)
1143 +{
1144 + struct ar231x_private *sp = netdev_priv(dev);
1145 + unsigned int mc;
1146 +
1147 + if (!sp->phy_dev->link)
1148 + return;
1149 +
1150 + if (sp->phy_dev->duplex != sp->oldduplex) {
1151 + mc = readl(&sp->eth_regs->mac_control);
1152 + mc &= ~(MAC_CONTROL_F | MAC_CONTROL_DRO);
1153 + if (sp->phy_dev->duplex)
1154 + mc |= MAC_CONTROL_F;
1155 + else
1156 + mc |= MAC_CONTROL_DRO;
1157 + writel(mc, &sp->eth_regs->mac_control);
1158 + sp->oldduplex = sp->phy_dev->duplex;
1159 + }
1160 +}
1161 +
1162 +#define MII_ADDR(phy, reg) \
1163 + ((reg << MII_ADDR_REG_SHIFT) | (phy << MII_ADDR_PHY_SHIFT))
1164 +
1165 +static int
1166 +ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
1167 +{
1168 + struct net_device *const dev = bus->priv;
1169 + struct ar231x_private *sp = netdev_priv(dev);
1170 + volatile MII *ethernet = sp->phy_regs;
1171 +
1172 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum);
1173 + while (ethernet->mii_addr & MII_ADDR_BUSY)
1174 + ;
1175 + return ethernet->mii_data >> MII_DATA_SHIFT;
1176 +}
1177 +
1178 +static int
1179 +ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value)
1180 +{
1181 + struct net_device *const dev = bus->priv;
1182 + struct ar231x_private *sp = netdev_priv(dev);
1183 + volatile MII *ethernet = sp->phy_regs;
1184 +
1185 + while (ethernet->mii_addr & MII_ADDR_BUSY)
1186 + ;
1187 + ethernet->mii_data = value << MII_DATA_SHIFT;
1188 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum) | MII_ADDR_WRITE;
1189 +
1190 + return 0;
1191 +}
1192 +
1193 +static int ar231x_mdiobus_reset(struct mii_bus *bus)
1194 +{
1195 + struct net_device *const dev = bus->priv;
1196 +
1197 + ar231x_reset_reg(dev);
1198 +
1199 + return 0;
1200 +}
1201 +
1202 +static int ar231x_mdiobus_probe(struct net_device *dev)
1203 +{
1204 + struct ar231x_private *const sp = netdev_priv(dev);
1205 + struct phy_device *phydev = NULL;
1206 + int phy_addr;
1207 +
1208 + /* find the first (lowest address) PHY on the current MAC's MII bus */
1209 + for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
1210 + if (sp->mii_bus->phy_map[phy_addr]) {
1211 + phydev = sp->mii_bus->phy_map[phy_addr];
1212 + sp->phy = phy_addr;
1213 + break; /* break out with first one found */
1214 + }
1215 +
1216 + if (!phydev) {
1217 + printk(KERN_ERR "ar231x: %s: no PHY found\n", dev->name);
1218 + return -1;
1219 + }
1220 +
1221 + /* now we are supposed to have a proper phydev, to attach to... */
1222 + BUG_ON(!phydev);
1223 + BUG_ON(phydev->attached_dev);
1224 +
1225 + phydev = phy_connect(dev, dev_name(&phydev->dev), &ar231x_adjust_link,
1226 + PHY_INTERFACE_MODE_MII);
1227 +
1228 + if (IS_ERR(phydev)) {
1229 + printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
1230 + return PTR_ERR(phydev);
1231 + }
1232 +
1233 + /* mask with MAC supported features */
1234 + phydev->supported &= (SUPPORTED_10baseT_Half
1235 + | SUPPORTED_10baseT_Full
1236 + | SUPPORTED_100baseT_Half
1237 + | SUPPORTED_100baseT_Full
1238 + | SUPPORTED_Autoneg
1239 + /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
1240 + | SUPPORTED_MII
1241 + | SUPPORTED_TP);
1242 +
1243 + phydev->advertising = phydev->supported;
1244 +
1245 + sp->oldduplex = -1;
1246 + sp->phy_dev = phydev;
1247 +
1248 + printk(KERN_INFO "%s: attached PHY driver [%s] "
1249 + "(mii_bus:phy_addr=%s)\n",
1250 + dev->name, phydev->drv->name, dev_name(&phydev->dev));
1251 +
1252 + return 0;
1253 +}
1254 +
1255 --- /dev/null
1256 +++ b/drivers/net/ethernet/atheros/ar231x/ar231x.h
1257 @@ -0,0 +1,295 @@
1258 +/*
1259 + * ar231x.h: Linux driver for the Atheros AR231x Ethernet device.
1260 + *
1261 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
1262 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1263 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1264 + *
1265 + * Thanks to Atheros for providing hardware and documentation
1266 + * enabling me to write this driver.
1267 + *
1268 + * This program is free software; you can redistribute it and/or modify
1269 + * it under the terms of the GNU General Public License as published by
1270 + * the Free Software Foundation; either version 2 of the License, or
1271 + * (at your option) any later version.
1272 + */
1273 +
1274 +#ifndef _AR2313_H_
1275 +#define _AR2313_H_
1276 +
1277 +#include <linux/interrupt.h>
1278 +#include <generated/autoconf.h>
1279 +#include <linux/bitops.h>
1280 +#include <ar231x_platform.h>
1281 +
1282 +/* probe link timer - 5 secs */
1283 +#define LINK_TIMER (5*HZ)
1284 +
1285 +#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0)
1286 +#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0)
1287 +#define IS_DRIVER_OWNED(X) (((X) & (DMA_TX_OWN)) == 0)
1288 +
1289 +#define AR2313_TX_TIMEOUT (HZ/4)
1290 +
1291 +/* Rings */
1292 +#define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc))
1293 +#define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1))
1294 +
1295 +#define AR2313_MBGET 2
1296 +#define AR2313_MBSET 3
1297 +#define AR2313_PCI_RECONFIG 4
1298 +#define AR2313_PCI_DUMP 5
1299 +#define AR2313_TEST_PANIC 6
1300 +#define AR2313_TEST_NULLPTR 7
1301 +#define AR2313_READ_DATA 8
1302 +#define AR2313_WRITE_DATA 9
1303 +#define AR2313_GET_VERSION 10
1304 +#define AR2313_TEST_HANG 11
1305 +#define AR2313_SYNC 12
1306 +
1307 +#define DMA_RX_ERR_CRC BIT(1)
1308 +#define DMA_RX_ERR_DRIB BIT(2)
1309 +#define DMA_RX_ERR_MII BIT(3)
1310 +#define DMA_RX_EV2 BIT(5)
1311 +#define DMA_RX_ERR_COL BIT(6)
1312 +#define DMA_RX_LONG BIT(7)
1313 +#define DMA_RX_LS BIT(8) /* last descriptor */
1314 +#define DMA_RX_FS BIT(9) /* first descriptor */
1315 +#define DMA_RX_MF BIT(10) /* multicast frame */
1316 +#define DMA_RX_ERR_RUNT BIT(11) /* runt frame */
1317 +#define DMA_RX_ERR_LENGTH BIT(12) /* length error */
1318 +#define DMA_RX_ERR_DESC BIT(14) /* descriptor error */
1319 +#define DMA_RX_ERROR BIT(15) /* error summary */
1320 +#define DMA_RX_LEN_MASK 0x3fff0000
1321 +#define DMA_RX_LEN_SHIFT 16
1322 +#define DMA_RX_FILT BIT(30)
1323 +#define DMA_RX_OWN BIT(31) /* desc owned by DMA controller */
1324 +
1325 +#define DMA_RX1_BSIZE_MASK 0x000007ff
1326 +#define DMA_RX1_BSIZE_SHIFT 0
1327 +#define DMA_RX1_CHAINED BIT(24)
1328 +#define DMA_RX1_RER BIT(25)
1329 +
1330 +#define DMA_TX_ERR_UNDER BIT(1) /* underflow error */
1331 +#define DMA_TX_ERR_DEFER BIT(2) /* excessive deferral */
1332 +#define DMA_TX_COL_MASK 0x78
1333 +#define DMA_TX_COL_SHIFT 3
1334 +#define DMA_TX_ERR_HB BIT(7) /* hearbeat failure */
1335 +#define DMA_TX_ERR_COL BIT(8) /* excessive collisions */
1336 +#define DMA_TX_ERR_LATE BIT(9) /* late collision */
1337 +#define DMA_TX_ERR_LINK BIT(10) /* no carrier */
1338 +#define DMA_TX_ERR_LOSS BIT(11) /* loss of carrier */
1339 +#define DMA_TX_ERR_JABBER BIT(14) /* transmit jabber timeout */
1340 +#define DMA_TX_ERROR BIT(15) /* frame aborted */
1341 +#define DMA_TX_OWN BIT(31) /* descr owned by DMA controller */
1342 +
1343 +#define DMA_TX1_BSIZE_MASK 0x000007ff
1344 +#define DMA_TX1_BSIZE_SHIFT 0
1345 +#define DMA_TX1_CHAINED BIT(24) /* chained descriptors */
1346 +#define DMA_TX1_TER BIT(25) /* transmit end of ring */
1347 +#define DMA_TX1_FS BIT(29) /* first segment */
1348 +#define DMA_TX1_LS BIT(30) /* last segment */
1349 +#define DMA_TX1_IC BIT(31) /* interrupt on completion */
1350 +
1351 +#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */
1352 +
1353 +#define MAC_CONTROL_RE BIT(2) /* receive enable */
1354 +#define MAC_CONTROL_TE BIT(3) /* transmit enable */
1355 +#define MAC_CONTROL_DC BIT(5) /* Deferral check */
1356 +#define MAC_CONTROL_ASTP BIT(8) /* Auto pad strip */
1357 +#define MAC_CONTROL_DRTY BIT(10) /* Disable retry */
1358 +#define MAC_CONTROL_DBF BIT(11) /* Disable bcast frames */
1359 +#define MAC_CONTROL_LCC BIT(12) /* late collision ctrl */
1360 +#define MAC_CONTROL_HP BIT(13) /* Hash Perfect filtering */
1361 +#define MAC_CONTROL_HASH BIT(14) /* Unicast hash filtering */
1362 +#define MAC_CONTROL_HO BIT(15) /* Hash only filtering */
1363 +#define MAC_CONTROL_PB BIT(16) /* Pass Bad frames */
1364 +#define MAC_CONTROL_IF BIT(17) /* Inverse filtering */
1365 +#define MAC_CONTROL_PR BIT(18) /* promis mode (valid frames only) */
1366 +#define MAC_CONTROL_PM BIT(19) /* pass multicast */
1367 +#define MAC_CONTROL_F BIT(20) /* full-duplex */
1368 +#define MAC_CONTROL_DRO BIT(23) /* Disable Receive Own */
1369 +#define MAC_CONTROL_HBD BIT(28) /* heart-beat disabled (MUST BE SET) */
1370 +#define MAC_CONTROL_BLE BIT(30) /* big endian mode */
1371 +#define MAC_CONTROL_RA BIT(31) /* rcv all (valid and invalid frames) */
1372 +
1373 +#define MII_ADDR_BUSY BIT(0)
1374 +#define MII_ADDR_WRITE BIT(1)
1375 +#define MII_ADDR_REG_SHIFT 6
1376 +#define MII_ADDR_PHY_SHIFT 11
1377 +#define MII_DATA_SHIFT 0
1378 +
1379 +#define FLOW_CONTROL_FCE BIT(1)
1380 +
1381 +#define DMA_BUS_MODE_SWR BIT(0) /* software reset */
1382 +#define DMA_BUS_MODE_BLE BIT(7) /* big endian mode */
1383 +#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */
1384 +#define DMA_BUS_MODE_DBO BIT(20) /* big-endian descriptors */
1385 +
1386 +#define DMA_STATUS_TI BIT(0) /* transmit interrupt */
1387 +#define DMA_STATUS_TPS BIT(1) /* transmit process stopped */
1388 +#define DMA_STATUS_TU BIT(2) /* transmit buffer unavailable */
1389 +#define DMA_STATUS_TJT BIT(3) /* transmit buffer timeout */
1390 +#define DMA_STATUS_UNF BIT(5) /* transmit underflow */
1391 +#define DMA_STATUS_RI BIT(6) /* receive interrupt */
1392 +#define DMA_STATUS_RU BIT(7) /* receive buffer unavailable */
1393 +#define DMA_STATUS_RPS BIT(8) /* receive process stopped */
1394 +#define DMA_STATUS_ETI BIT(10) /* early transmit interrupt */
1395 +#define DMA_STATUS_FBE BIT(13) /* fatal bus interrupt */
1396 +#define DMA_STATUS_ERI BIT(14) /* early receive interrupt */
1397 +#define DMA_STATUS_AIS BIT(15) /* abnormal interrupt summary */
1398 +#define DMA_STATUS_NIS BIT(16) /* normal interrupt summary */
1399 +#define DMA_STATUS_RS_SHIFT 17 /* receive process state */
1400 +#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */
1401 +#define DMA_STATUS_EB_SHIFT 23 /* error bits */
1402 +
1403 +#define DMA_CONTROL_SR BIT(1) /* start receive */
1404 +#define DMA_CONTROL_ST BIT(13) /* start transmit */
1405 +#define DMA_CONTROL_SF BIT(21) /* store and forward */
1406 +
1407 +
1408 +typedef struct {
1409 + volatile unsigned int status; /* OWN, Device control and status. */
1410 + volatile unsigned int devcs; /* pkt Control bits + Length */
1411 + volatile unsigned int addr; /* Current Address. */
1412 + volatile unsigned int descr; /* Next descriptor in chain. */
1413 +} ar231x_descr_t;
1414 +
1415 +
1416 +
1417 +/**
1418 + * New Combo structure for Both Eth0 AND eth1
1419 + *
1420 + * Don't directly access MII related regs since phy chip could be actually
1421 + * connected to another ethernet block.
1422 + */
1423 +typedef struct {
1424 + volatile unsigned int mac_control; /* 0x00 */
1425 + volatile unsigned int mac_addr[2]; /* 0x04 - 0x08 */
1426 + volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */
1427 + volatile unsigned int __mii_addr; /* 0x14 */
1428 + volatile unsigned int __mii_data; /* 0x18 */
1429 + volatile unsigned int flow_control; /* 0x1c */
1430 + volatile unsigned int vlan_tag; /* 0x20 */
1431 + volatile unsigned int pad[7]; /* 0x24 - 0x3c */
1432 + volatile unsigned int ucast_table[8]; /* 0x40-0x5c */
1433 +
1434 +} ETHERNET_STRUCT;
1435 +
1436 +typedef struct {
1437 + volatile unsigned int mii_addr;
1438 + volatile unsigned int mii_data;
1439 +} MII;
1440 +
1441 +/********************************************************************
1442 + * Interrupt controller
1443 + ********************************************************************/
1444 +
1445 +typedef struct {
1446 + volatile unsigned int wdog_control; /* 0x08 */
1447 + volatile unsigned int wdog_timer; /* 0x0c */
1448 + volatile unsigned int misc_status; /* 0x10 */
1449 + volatile unsigned int misc_mask; /* 0x14 */
1450 + volatile unsigned int global_status; /* 0x18 */
1451 + volatile unsigned int reserved; /* 0x1c */
1452 + volatile unsigned int reset_control; /* 0x20 */
1453 +} INTERRUPT;
1454 +
1455 +/********************************************************************
1456 + * DMA controller
1457 + ********************************************************************/
1458 +typedef struct {
1459 + volatile unsigned int bus_mode; /* 0x00 (CSR0) */
1460 + volatile unsigned int xmt_poll; /* 0x04 (CSR1) */
1461 + volatile unsigned int rcv_poll; /* 0x08 (CSR2) */
1462 + volatile unsigned int rcv_base; /* 0x0c (CSR3) */
1463 + volatile unsigned int xmt_base; /* 0x10 (CSR4) */
1464 + volatile unsigned int status; /* 0x14 (CSR5) */
1465 + volatile unsigned int control; /* 0x18 (CSR6) */
1466 + volatile unsigned int intr_ena; /* 0x1c (CSR7) */
1467 + volatile unsigned int rcv_missed; /* 0x20 (CSR8) */
1468 + volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */
1469 + volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */
1470 + volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */
1471 +} DMA;
1472 +
1473 +/**
1474 + * Struct private for the Sibyte.
1475 + *
1476 + * Elements are grouped so variables used by the tx handling goes
1477 + * together, and will go into the same cache lines etc. in order to
1478 + * avoid cache line contention between the rx and tx handling on SMP.
1479 + *
1480 + * Frequently accessed variables are put at the beginning of the
1481 + * struct to help the compiler generate better/shorter code.
1482 + */
1483 +struct ar231x_private {
1484 + struct net_device *dev;
1485 + int version;
1486 + u32 mb[2];
1487 +
1488 + volatile MII *phy_regs;
1489 + volatile ETHERNET_STRUCT *eth_regs;
1490 + volatile DMA *dma_regs;
1491 + struct ar231x_eth *cfg;
1492 +
1493 + spinlock_t lock; /* Serialise access to device */
1494 +
1495 + /* RX and TX descriptors, must be adjacent */
1496 + ar231x_descr_t *rx_ring;
1497 + ar231x_descr_t *tx_ring;
1498 +
1499 +
1500 + struct sk_buff **rx_skb;
1501 + struct sk_buff **tx_skb;
1502 +
1503 + /* RX elements */
1504 + u32 rx_skbprd;
1505 + u32 cur_rx;
1506 +
1507 + /* TX elements */
1508 + u32 tx_prd;
1509 + u32 tx_csm;
1510 +
1511 + /* Misc elements */
1512 + char name[48];
1513 + struct {
1514 + u32 address;
1515 + u32 length;
1516 + char *mapping;
1517 + } desc;
1518 +
1519 +
1520 + struct timer_list link_timer;
1521 + unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */
1522 + unsigned short mac;
1523 + unsigned short link; /* 0 - link down, 1 - link up */
1524 + u16 phy_data;
1525 +
1526 + struct tasklet_struct rx_tasklet;
1527 + int unloading;
1528 +
1529 + struct phy_device *phy_dev;
1530 + struct mii_bus *mii_bus;
1531 + int oldduplex;
1532 +};
1533 +
1534 +
1535 +/* Prototypes */
1536 +static int ar231x_init(struct net_device *dev);
1537 +#ifdef TX_TIMEOUT
1538 +static void ar231x_tx_timeout(struct net_device *dev);
1539 +#endif
1540 +static int ar231x_restart(struct net_device *dev);
1541 +static void ar231x_load_rx_ring(struct net_device *dev, int bufs);
1542 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id);
1543 +static int ar231x_open(struct net_device *dev);
1544 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev);
1545 +static int ar231x_close(struct net_device *dev);
1546 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr,
1547 + int cmd);
1548 +static void ar231x_init_cleanup(struct net_device *dev);
1549 +static int ar231x_setup_timer(struct net_device *dev);
1550 +static void ar231x_link_timer_fn(unsigned long data);
1551 +static void ar231x_check_link(struct net_device *dev);
1552 +#endif /* _AR2313_H_ */
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