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[openwrt/openwrt.git] / target / linux / atheros / patches-3.18 / 100-board.patch
1 --- a/arch/mips/Kconfig
2 +++ b/arch/mips/Kconfig
3 @@ -96,6 +96,19 @@ config AR7
4 Support for the Texas Instruments AR7 System-on-a-Chip
5 family: TNETD7100, 7200 and 7300.
6
7 +config ATH25
8 + bool "Atheros 231x/531x SoC support"
9 + select CEVT_R4K
10 + select CSRC_R4K
11 + select DMA_NONCOHERENT
12 + select IRQ_CPU
13 + select SYS_HAS_CPU_MIPS32_R1
14 + select SYS_SUPPORTS_BIG_ENDIAN
15 + select SYS_SUPPORTS_32BIT_KERNEL
16 + select ARCH_REQUIRE_GPIOLIB
17 + help
18 + Support for AR231x and AR531x based boards
19 +
20 config ATH79
21 bool "Atheros AR71XX/AR724X/AR913X based boards"
22 select ARCH_REQUIRE_GPIOLIB
23 @@ -834,6 +847,7 @@ config MIPS_PARAVIRT
24
25 endchoice
26
27 +source "arch/mips/ar231x/Kconfig"
28 source "arch/mips/alchemy/Kconfig"
29 source "arch/mips/ath79/Kconfig"
30 source "arch/mips/bcm47xx/Kconfig"
31 --- a/arch/mips/Kbuild.platforms
32 +++ b/arch/mips/Kbuild.platforms
33 @@ -6,6 +6,7 @@ platforms += ath79
34 platforms += bcm47xx
35 platforms += bcm63xx
36 platforms += cavium-octeon
37 +platforms += ar231x
38 platforms += cobalt
39 platforms += dec
40 platforms += emma
41 --- /dev/null
42 +++ b/arch/mips/ar231x/Platform
43 @@ -0,0 +1,6 @@
44 +#
45 +# Atheros AR531X/AR231X WiSoC
46 +#
47 +platform-$(CONFIG_ATH25) += ar231x/
48 +cflags-$(CONFIG_ATH25) += -I$(srctree)/arch/mips/include/asm/mach-ar231x
49 +load-$(CONFIG_ATH25) += 0xffffffff80041000
50 --- /dev/null
51 +++ b/arch/mips/ar231x/Kconfig
52 @@ -0,0 +1,9 @@
53 +config SOC_AR5312
54 + bool "Atheros 5312/2312+ support"
55 + depends on ATH25
56 + default y
57 +
58 +config SOC_AR2315
59 + bool "Atheros 2315+ support"
60 + depends on ATH25
61 + default y
62 --- /dev/null
63 +++ b/arch/mips/ar231x/Makefile
64 @@ -0,0 +1,13 @@
65 +#
66 +# This file is subject to the terms and conditions of the GNU General Public
67 +# License. See the file "COPYING" in the main directory of this archive
68 +# for more details.
69 +#
70 +# Copyright (C) 2006 FON Technology, SL.
71 +# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
72 +# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
73 +#
74 +
75 +obj-y += board.o prom.o devices.o
76 +obj-$(CONFIG_SOC_AR5312) += ar5312.o
77 +obj-$(CONFIG_SOC_AR2315) += ar2315.o
78 --- /dev/null
79 +++ b/arch/mips/ar231x/board.c
80 @@ -0,0 +1,229 @@
81 +/*
82 + * This file is subject to the terms and conditions of the GNU General Public
83 + * License. See the file "COPYING" in the main directory of this archive
84 + * for more details.
85 + *
86 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
87 + * Copyright (C) 2006 FON Technology, SL.
88 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
89 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
90 + */
91 +
92 +#include <generated/autoconf.h>
93 +#include <linux/init.h>
94 +#include <linux/module.h>
95 +#include <linux/types.h>
96 +#include <linux/string.h>
97 +#include <linux/platform_device.h>
98 +#include <linux/kernel.h>
99 +#include <linux/random.h>
100 +#include <linux/etherdevice.h>
101 +#include <linux/irq.h>
102 +#include <linux/io.h>
103 +#include <asm/irq_cpu.h>
104 +#include <asm/reboot.h>
105 +#include <asm/bootinfo.h>
106 +#include <asm/time.h>
107 +
108 +#include <ar231x_platform.h>
109 +#include "devices.h"
110 +#include "ar5312.h"
111 +#include "ar2315.h"
112 +
113 +void (*ar231x_irq_dispatch)(void);
114 +
115 +static inline bool check_radio_magic(u8 *addr)
116 +{
117 + addr += 0x7a; /* offset for flash magic */
118 + return (addr[0] == 0x5a) && (addr[1] == 0xa5);
119 +}
120 +
121 +static inline bool check_notempty(u8 *addr)
122 +{
123 + return *(u32 *)addr != 0xffffffff;
124 +}
125 +
126 +static inline bool check_board_data(u8 *flash_limit, u8 *addr, bool broken)
127 +{
128 + /* config magic found */
129 + if (*((u32 *)addr) == AR231X_BD_MAGIC)
130 + return true;
131 +
132 + if (!broken)
133 + return false;
134 +
135 + if (check_radio_magic(addr + 0xf8))
136 + ar231x_board.radio = addr + 0xf8;
137 + if ((addr < flash_limit + 0x10000) &&
138 + check_radio_magic(addr + 0x10000))
139 + ar231x_board.radio = addr + 0x10000;
140 +
141 + if (ar231x_board.radio) {
142 + /* broken board data detected, use radio data to find the
143 + * offset, user will fix this */
144 + return true;
145 + }
146 +
147 + return false;
148 +}
149 +
150 +static u8 * __init find_board_config(u8 *flash_limit, bool broken)
151 +{
152 + u8 *addr;
153 + u8 *begin = flash_limit - 0x1000;
154 + u8 *end = flash_limit - 0x30000;
155 +
156 + for (addr = begin; addr >= end; addr -= 0x1000)
157 + if (check_board_data(flash_limit, addr, broken))
158 + return addr;
159 +
160 + return NULL;
161 +}
162 +
163 +static u8 * __init find_radio_config(u8 *flash_limit, u8 *bcfg)
164 +{
165 + u8 *rcfg, *begin, *end;
166 +
167 + /*
168 + * Now find the start of Radio Configuration data, using heuristics:
169 + * Search forward from Board Configuration data by 0x1000 bytes
170 + * at a time until we find non-0xffffffff.
171 + */
172 + begin = bcfg + 0x1000;
173 + end = flash_limit;
174 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
175 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
176 + return rcfg;
177 +
178 + /* AR2316 relocates radio config to new location */
179 + begin = bcfg + 0xf8;
180 + end = flash_limit - 0x1000 + 0xf8;
181 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
182 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
183 + return rcfg;
184 +
185 + pr_warn("WARNING: Could not find Radio Configuration data\n");
186 +
187 + return NULL;
188 +}
189 +
190 +int __init ar231x_find_config(u8 *flash_limit)
191 +{
192 + struct ar231x_boarddata *config;
193 + unsigned int rcfg_size;
194 + int broken_boarddata = 0;
195 + u8 *bcfg, *rcfg;
196 + u8 *board_data;
197 + u8 *radio_data;
198 + u8 *mac_addr;
199 + u32 offset;
200 +
201 + ar231x_board.config = NULL;
202 + ar231x_board.radio = NULL;
203 + /* Copy the board and radio data to RAM, because accessing the mapped
204 + * memory of the flash directly after booting is not safe */
205 +
206 + /* Try to find valid board and radio data */
207 + bcfg = find_board_config(flash_limit, false);
208 +
209 + /* If that fails, try to at least find valid radio data */
210 + if (!bcfg) {
211 + bcfg = find_board_config(flash_limit, true);
212 + broken_boarddata = 1;
213 + }
214 +
215 + if (!bcfg) {
216 + pr_warn("WARNING: No board configuration data found!\n");
217 + return -ENODEV;
218 + }
219 +
220 + board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
221 + ar231x_board.config = (struct ar231x_boarddata *)board_data;
222 + memcpy(board_data, bcfg, 0x100);
223 + if (broken_boarddata) {
224 + pr_warn("WARNING: broken board data detected\n");
225 + config = ar231x_board.config;
226 + if (is_zero_ether_addr(config->enet0_mac)) {
227 + pr_info("Fixing up empty mac addresses\n");
228 + config->reset_config_gpio = 0xffff;
229 + config->sys_led_gpio = 0xffff;
230 + random_ether_addr(config->wlan0_mac);
231 + config->wlan0_mac[0] &= ~0x06;
232 + random_ether_addr(config->enet0_mac);
233 + random_ether_addr(config->enet1_mac);
234 + }
235 + }
236 +
237 + /* Radio config starts 0x100 bytes after board config, regardless
238 + * of what the physical layout on the flash chip looks like */
239 +
240 + if (ar231x_board.radio)
241 + rcfg = (u8 *)ar231x_board.radio;
242 + else
243 + rcfg = find_radio_config(flash_limit, bcfg);
244 +
245 + if (!rcfg)
246 + return -ENODEV;
247 +
248 + radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
249 + ar231x_board.radio = radio_data;
250 + offset = radio_data - board_data;
251 + pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
252 + offset);
253 + rcfg_size = BOARD_CONFIG_BUFSZ - offset;
254 + memcpy(radio_data, rcfg, rcfg_size);
255 +
256 + mac_addr = &radio_data[0x1d * 2];
257 + if (is_broadcast_ether_addr(mac_addr)) {
258 + pr_info("Radio MAC is blank; using board-data\n");
259 + ether_addr_copy(mac_addr, ar231x_board.config->wlan0_mac);
260 + }
261 +
262 + return 0;
263 +}
264 +
265 +static void ar231x_halt(void)
266 +{
267 + local_irq_disable();
268 + while (1)
269 + ;
270 +}
271 +
272 +void __init plat_mem_setup(void)
273 +{
274 + _machine_halt = ar231x_halt;
275 + pm_power_off = ar231x_halt;
276 +
277 + ar5312_plat_setup();
278 + ar2315_plat_setup();
279 +
280 + /* Disable data watchpoints */
281 + write_c0_watchlo0(0);
282 +}
283 +
284 +asmlinkage void plat_irq_dispatch(void)
285 +{
286 + ar231x_irq_dispatch();
287 +}
288 +
289 +void __init plat_time_init(void)
290 +{
291 + ar5312_time_init();
292 + ar2315_time_init();
293 +}
294 +
295 +unsigned int __cpuinit get_c0_compare_int(void)
296 +{
297 + return CP0_LEGACY_COMPARE_IRQ;
298 +}
299 +
300 +void __init arch_init_irq(void)
301 +{
302 + clear_c0_status(ST0_IM);
303 + mips_cpu_irq_init();
304 +
305 + /* Initialize interrupt controllers */
306 + ar5312_irq_init();
307 + ar2315_irq_init();
308 +}
309 +
310 --- /dev/null
311 +++ b/arch/mips/ar231x/prom.c
312 @@ -0,0 +1,37 @@
313 +/*
314 + * This file is subject to the terms and conditions of the GNU General Public
315 + * License. See the file "COPYING" in the main directory of this archive
316 + * for more details.
317 + *
318 + * Copyright MontaVista Software Inc
319 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
320 + * Copyright (C) 2006 FON Technology, SL.
321 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
322 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
323 + */
324 +
325 +/*
326 + * Prom setup file for ar231x
327 + */
328 +
329 +#include <linux/init.h>
330 +#include <generated/autoconf.h>
331 +#include <linux/kernel.h>
332 +#include <linux/string.h>
333 +#include <linux/mm.h>
334 +#include <linux/bootmem.h>
335 +
336 +#include <asm/bootinfo.h>
337 +#include <asm/addrspace.h>
338 +#include "ar5312.h"
339 +#include "ar2315.h"
340 +
341 +void __init prom_init(void)
342 +{
343 + ar5312_prom_init();
344 + ar2315_prom_init();
345 +}
346 +
347 +void __init prom_free_prom_memory(void)
348 +{
349 +}
350 --- /dev/null
351 +++ b/arch/mips/include/asm/mach-ar231x/ar231x_platform.h
352 @@ -0,0 +1,85 @@
353 +#ifndef __ASM_MACH_AR231X_PLATFORM_H
354 +#define __ASM_MACH_AR231X_PLATFORM_H
355 +
356 +#include <linux/etherdevice.h>
357 +
358 +/*
359 + * This is board-specific data that is stored in a "fixed" location in flash.
360 + * It is shared across operating systems, so it should not be changed lightly.
361 + * The main reason we need it is in order to extract the ethernet MAC
362 + * address(es).
363 + */
364 +struct ar231x_boarddata {
365 + u32 magic; /* board data is valid */
366 +#define AR231X_BD_MAGIC 0x35333131 /* "5311", for all 531x/231x platforms */
367 + u16 cksum; /* checksum (starting with BD_REV 2) */
368 + u16 rev; /* revision of this struct */
369 +#define BD_REV 4
370 + char board_name[64]; /* Name of board */
371 + u16 major; /* Board major number */
372 + u16 minor; /* Board minor number */
373 + u32 flags; /* Board configuration */
374 +#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
375 +#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
376 +#define BD_UART1 0x00000004 /* UART1 is stuffed */
377 +#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
378 +#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
379 +#define BD_SYSLED 0x00000020 /* System LED stuffed */
380 +#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
381 +#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
382 +#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
383 +#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
384 +#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ mem_cap for testing */
385 +#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
386 +#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
387 +#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
388 +#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
389 +#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
390 +#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
391 +#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
392 + u16 reset_config_gpio; /* Reset factory GPIO pin */
393 + u16 sys_led_gpio; /* System LED GPIO pin */
394 +
395 + u32 cpu_freq; /* CPU core frequency in Hz */
396 + u32 sys_freq; /* System frequency in Hz */
397 + u32 cnt_freq; /* Calculated C0_COUNT frequency */
398 +
399 + u8 wlan0_mac[ETH_ALEN];
400 + u8 enet0_mac[ETH_ALEN];
401 + u8 enet1_mac[ETH_ALEN];
402 +
403 + u16 pci_id; /* Pseudo PCIID for common code */
404 + u16 mem_cap; /* cap bank1 in MB */
405 +
406 + /* version 3 */
407 + u8 wlan1_mac[ETH_ALEN]; /* (ar5212) */
408 +};
409 +
410 +#define BOARD_CONFIG_BUFSZ 0x1000
411 +
412 +/*
413 + * Platform device information for the Wireless MAC
414 + */
415 +struct ar231x_board_config {
416 + u16 devid;
417 +
418 + /* board config data */
419 + struct ar231x_boarddata *config;
420 +
421 + /* radio calibration data */
422 + const char *radio;
423 +};
424 +
425 +/*
426 + * Platform device information for the Ethernet MAC
427 + */
428 +struct ar231x_eth {
429 + void (*reset_set)(u32);
430 + void (*reset_clear)(u32);
431 + u32 reset_mac;
432 + u32 reset_phy;
433 + struct ar231x_board_config *config;
434 + char *macaddr;
435 +};
436 +
437 +#endif /* __ASM_MACH_AR231X_PLATFORM_H */
438 --- /dev/null
439 +++ b/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h
440 @@ -0,0 +1,84 @@
441 +/*
442 + * Atheros AR231x/AR531x SoC specific CPU feature overrides
443 + *
444 + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
445 + *
446 + * This file was derived from: include/asm-mips/cpu-features.h
447 + * Copyright (C) 2003, 2004 Ralf Baechle
448 + * Copyright (C) 2004 Maciej W. Rozycki
449 + *
450 + * This program is free software; you can redistribute it and/or modify it
451 + * under the terms of the GNU General Public License version 2 as published
452 + * by the Free Software Foundation.
453 + *
454 + */
455 +#ifndef __ASM_MACH_AR231X_CPU_FEATURE_OVERRIDES_H
456 +#define __ASM_MACH_AR231X_CPU_FEATURE_OVERRIDES_H
457 +
458 +/*
459 + * The Atheros AR531x/AR231x SoCs have MIPS 4Kc/4KEc core.
460 + */
461 +#define cpu_has_tlb 1
462 +#define cpu_has_4kex 1
463 +#define cpu_has_3k_cache 0
464 +#define cpu_has_4k_cache 1
465 +#define cpu_has_tx39_cache 0
466 +#define cpu_has_sb1_cache 0
467 +#define cpu_has_fpu 0
468 +#define cpu_has_32fpr 0
469 +#define cpu_has_counter 1
470 +/* #define cpu_has_watch ? */
471 +/* #define cpu_has_divec ? */
472 +/* #define cpu_has_vce ? */
473 +/* #define cpu_has_cache_cdex_p ? */
474 +/* #define cpu_has_cache_cdex_s ? */
475 +/* #define cpu_has_prefetch ? */
476 +/* #define cpu_has_mcheck ? */
477 +#define cpu_has_ejtag 1
478 +
479 +#if !defined(CONFIG_SOC_AR5312)
480 +# define cpu_has_llsc 1
481 +#else
482 +/*
483 + * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
484 + * ll/sc instructions.
485 + */
486 +# define cpu_has_llsc 0
487 +#endif
488 +
489 +#define cpu_has_mips16 0
490 +#define cpu_has_mdmx 0
491 +#define cpu_has_mips3d 0
492 +#define cpu_has_smartmips 0
493 +
494 +/* #define cpu_has_vtag_icache ? */
495 +/* #define cpu_has_dc_aliases ? */
496 +/* #define cpu_has_ic_fills_f_dc ? */
497 +/* #define cpu_has_pindexed_dcache ? */
498 +
499 +/* #define cpu_icache_snoops_remote_store ? */
500 +
501 +#define cpu_has_mips32r1 1
502 +
503 +#if !defined(CONFIG_SOC_AR5312)
504 +# define cpu_has_mips32r2 1
505 +#endif
506 +
507 +#define cpu_has_mips64r1 0
508 +#define cpu_has_mips64r2 0
509 +
510 +#define cpu_has_dsp 0
511 +#define cpu_has_mipsmt 0
512 +
513 +/* #define cpu_has_nofpuex ? */
514 +#define cpu_has_64bits 0
515 +#define cpu_has_64bit_zero_reg 0
516 +#define cpu_has_64bit_gp_regs 0
517 +#define cpu_has_64bit_addresses 0
518 +
519 +/* #define cpu_has_inclusive_pcaches ? */
520 +
521 +/* #define cpu_dcache_line_size() ? */
522 +/* #define cpu_icache_line_size() ? */
523 +
524 +#endif /* __ASM_MACH_AR231X_CPU_FEATURE_OVERRIDES_H */
525 --- /dev/null
526 +++ b/arch/mips/include/asm/mach-ar231x/dma-coherence.h
527 @@ -0,0 +1,76 @@
528 +/*
529 + * This file is subject to the terms and conditions of the GNU General Public
530 + * License. See the file "COPYING" in the main directory of this archive
531 + * for more details.
532 + *
533 + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
534 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
535 + *
536 + */
537 +#ifndef __ASM_MACH_AR231X_DMA_COHERENCE_H
538 +#define __ASM_MACH_AR231X_DMA_COHERENCE_H
539 +
540 +#include <linux/device.h>
541 +#include <ar2315_regs.h>
542 +
543 +static inline dma_addr_t ar231x_dev_offset(struct device *dev)
544 +{
545 +#ifdef CONFIG_PCI
546 + extern struct bus_type pci_bus_type;
547 +
548 + if (dev && dev->bus == &pci_bus_type)
549 + return AR2315_PCI_HOST_SDRAM_BASEADDR;
550 +#endif
551 + return 0;
552 +}
553 +
554 +static inline dma_addr_t
555 +plat_map_dma_mem(struct device *dev, void *addr, size_t size)
556 +{
557 + return virt_to_phys(addr) + ar231x_dev_offset(dev);
558 +}
559 +
560 +static inline dma_addr_t
561 +plat_map_dma_mem_page(struct device *dev, struct page *page)
562 +{
563 + return page_to_phys(page) + ar231x_dev_offset(dev);
564 +}
565 +
566 +static inline unsigned long
567 +plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
568 +{
569 + return dma_addr - ar231x_dev_offset(dev);
570 +}
571 +
572 +static inline void
573 +plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size,
574 + enum dma_data_direction direction)
575 +{
576 +}
577 +
578 +static inline int plat_dma_supported(struct device *dev, u64 mask)
579 +{
580 + return 1;
581 +}
582 +
583 +static inline void plat_extra_sync_for_device(struct device *dev)
584 +{
585 +}
586 +
587 +static inline int plat_dma_mapping_error(struct device *dev,
588 + dma_addr_t dma_addr)
589 +{
590 + return 0;
591 +}
592 +
593 +static inline int plat_device_is_coherent(struct device *dev)
594 +{
595 +#ifdef CONFIG_DMA_COHERENT
596 + return 1;
597 +#endif
598 +#ifdef CONFIG_DMA_NONCOHERENT
599 + return 0;
600 +#endif
601 +}
602 +
603 +#endif /* __ASM_MACH_AR231X_DMA_COHERENCE_H */
604 --- /dev/null
605 +++ b/arch/mips/include/asm/mach-ar231x/gpio.h
606 @@ -0,0 +1,16 @@
607 +#ifndef __ASM_MACH_AR231X_GPIO_H
608 +#define __ASM_MACH_AR231X_GPIO_H
609 +
610 +#include <asm-generic/gpio.h>
611 +
612 +#define gpio_get_value __gpio_get_value
613 +#define gpio_set_value __gpio_set_value
614 +#define gpio_cansleep __gpio_cansleep
615 +#define gpio_to_irq __gpio_to_irq
616 +
617 +static inline int irq_to_gpio(unsigned irq)
618 +{
619 + return -EINVAL;
620 +}
621 +
622 +#endif /* __ASM_MACH_AR231X_GPIO_H */
623 --- /dev/null
624 +++ b/arch/mips/include/asm/mach-ar231x/reset.h
625 @@ -0,0 +1,6 @@
626 +#ifndef __ASM_MACH_AR231X_RESET_H
627 +#define __ASM_MACH_AR231X_RESET_H
628 +
629 +void ar231x_disable_reset_button(void);
630 +
631 +#endif /* __ASM_MACH_AR231X_RESET_H */
632 --- /dev/null
633 +++ b/arch/mips/include/asm/mach-ar231x/war.h
634 @@ -0,0 +1,25 @@
635 +/*
636 + * This file is subject to the terms and conditions of the GNU General Public
637 + * License. See the file "COPYING" in the main directory of this archive
638 + * for more details.
639 + *
640 + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
641 + */
642 +#ifndef __ASM_MACH_AR231X_WAR_H
643 +#define __ASM_MACH_AR231X_WAR_H
644 +
645 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
646 +#define R4600_V1_HIT_CACHEOP_WAR 0
647 +#define R4600_V2_HIT_CACHEOP_WAR 0
648 +#define R5432_CP0_INTERRUPT_WAR 0
649 +#define BCM1250_M3_WAR 0
650 +#define SIBYTE_1956_WAR 0
651 +#define MIPS4K_ICACHE_REFILL_WAR 0
652 +#define MIPS_CACHE_SYNC_WAR 0
653 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
654 +#define RM9000_CDEX_SMP_WAR 0
655 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
656 +#define R10000_LLSC_WAR 0
657 +#define MIPS34K_MISSED_ITLB_WAR 0
658 +
659 +#endif /* __ASM_MACH_AR231X_WAR_H */
660 --- /dev/null
661 +++ b/arch/mips/include/asm/mach-ar231x/ar2315_regs.h
662 @@ -0,0 +1,608 @@
663 +/*
664 + * Register definitions for AR2315+
665 + *
666 + * This file is subject to the terms and conditions of the GNU General Public
667 + * License. See the file "COPYING" in the main directory of this archive
668 + * for more details.
669 + *
670 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
671 + * Copyright (C) 2006 FON Technology, SL.
672 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
673 + * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
674 + */
675 +
676 +#ifndef __ASM_MACH_AR231X_AR2315_REGS_H
677 +#define __ASM_MACH_AR231X_AR2315_REGS_H
678 +
679 +/*
680 + * IRQs
681 + */
682 +#define AR2315_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
683 +#define AR2315_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
684 +#define AR2315_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
685 +#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
686 +#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
687 +
688 +/*
689 + * Miscellaneous interrupts, which share IP2.
690 + */
691 +#define AR2315_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+0)
692 +#define AR2315_MISC_IRQ_I2C_RSVD (AR231X_MISC_IRQ_BASE+1)
693 +#define AR2315_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+2)
694 +#define AR2315_MISC_IRQ_AHB (AR231X_MISC_IRQ_BASE+3)
695 +#define AR2315_MISC_IRQ_APB (AR231X_MISC_IRQ_BASE+4)
696 +#define AR2315_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+5)
697 +#define AR2315_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+6)
698 +#define AR2315_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+7)
699 +#define AR2315_MISC_IRQ_IR_RSVD (AR231X_MISC_IRQ_BASE+8)
700 +#define AR2315_MISC_IRQ_COUNT 9
701 +
702 +/*
703 + * PCI interrupts, which share IP5
704 + * Keep ordered according to AR2315_PCI_INT_XXX bits
705 + */
706 +#define AR2315_PCI_IRQ_BASE 0x50
707 +#define AR2315_PCI_IRQ_EXT (AR2315_PCI_IRQ_BASE+0)
708 +#define AR2315_PCI_IRQ_ABORT (AR2315_PCI_IRQ_BASE+1)
709 +#define AR2315_PCI_IRQ_COUNT 2
710 +#define AR2315_PCI_IRQ_SHIFT 25 /* in AR2315_PCI_INT_STATUS */
711 +
712 +/*
713 + * Address map
714 + */
715 +#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */
716 +#define AR2315_WLAN0 0x10000000 /* Wireless MMR */
717 +#define AR2315_PCI 0x10100000 /* PCI MMR */
718 +#define AR2315_SDRAMCTL 0x10300000 /* SDRAM MMR */
719 +#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */
720 +#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */
721 +#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */
722 +#define AR2315_UART0 0x11100000 /* UART MMR */
723 +#define AR2315_SPI_MMR 0x11300000 /* SPI FLASH MMR */
724 +#define AR2315_PCIEXT 0x80000000 /* pci external */
725 +#define AR2315_PCIEXT_SZ 0x40000000
726 +
727 +/* MII registers offset inside Ethernet MMR region */
728 +#define AR2315_ENET0_MII (AR2315_ENET0 + 0x14)
729 +
730 +/*
731 + * Cold reset register
732 + */
733 +#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000)
734 +
735 +#define AR2315_RESET_COLD_AHB 0x00000001
736 +#define AR2315_RESET_COLD_APB 0x00000002
737 +#define AR2315_RESET_COLD_CPU 0x00000004
738 +#define AR2315_RESET_COLD_CPUWARM 0x00000008
739 +#define AR2315_RESET_SYSTEM \
740 + (RESET_COLD_CPU |\
741 + RESET_COLD_APB |\
742 + RESET_COLD_AHB) /* full system */
743 +#define AR2317_RESET_SYSTEM 0x00000010
744 +
745 +/*
746 + * Reset register
747 + */
748 +#define AR2315_RESET (AR2315_DSLBASE + 0x0004)
749 +
750 +/* warm reset WLAN0 MAC */
751 +#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001
752 +/* warm reset WLAN0 BaseBand */
753 +#define AR2315_RESET_WARM_WLAN0_BB 0x00000002
754 +/* warm reset MPEG-TS */
755 +#define AR2315_RESET_MPEGTS_RSVD 0x00000004
756 +/* warm reset PCI ahb/dma */
757 +#define AR2315_RESET_PCIDMA 0x00000008
758 +/* warm reset memory controller */
759 +#define AR2315_RESET_MEMCTL 0x00000010
760 +/* warm reset local bus */
761 +#define AR2315_RESET_LOCAL 0x00000020
762 +/* warm reset I2C bus */
763 +#define AR2315_RESET_I2C_RSVD 0x00000040
764 +/* warm reset SPI interface */
765 +#define AR2315_RESET_SPI 0x00000080
766 +/* warm reset UART0 */
767 +#define AR2315_RESET_UART0 0x00000100
768 +/* warm reset IR interface */
769 +#define AR2315_RESET_IR_RSVD 0x00000200
770 +/* cold reset ENET0 phy */
771 +#define AR2315_RESET_EPHY0 0x00000400
772 +/* cold reset ENET0 mac */
773 +#define AR2315_RESET_ENET0 0x00000800
774 +
775 +/*
776 + * AHB master arbitration control
777 + */
778 +#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008)
779 +
780 +/* CPU, default */
781 +#define AR2315_ARB_CPU 0x00000001
782 +/* WLAN */
783 +#define AR2315_ARB_WLAN 0x00000002
784 +/* MPEG-TS */
785 +#define AR2315_ARB_MPEGTS_RSVD 0x00000004
786 +/* LOCAL */
787 +#define AR2315_ARB_LOCAL 0x00000008
788 +/* PCI */
789 +#define AR2315_ARB_PCI 0x00000010
790 +/* Ethernet */
791 +#define AR2315_ARB_ETHERNET 0x00000020
792 +/* retry policy, debug only */
793 +#define AR2315_ARB_RETRY 0x00000100
794 +
795 +/*
796 + * Config Register
797 + */
798 +#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c)
799 +
800 +/* EC - AHB bridge endianess */
801 +#define AR2315_CONFIG_AHB 0x00000001
802 +/* WLAN byteswap */
803 +#define AR2315_CONFIG_WLAN 0x00000002
804 +/* MPEG-TS byteswap */
805 +#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004
806 +/* PCI byteswap */
807 +#define AR2315_CONFIG_PCI 0x00000008
808 +/* Memory controller endianess */
809 +#define AR2315_CONFIG_MEMCTL 0x00000010
810 +/* Local bus byteswap */
811 +#define AR2315_CONFIG_LOCAL 0x00000020
812 +/* Ethernet byteswap */
813 +#define AR2315_CONFIG_ETHERNET 0x00000040
814 +
815 +/* CPU write buffer merge */
816 +#define AR2315_CONFIG_MERGE 0x00000200
817 +/* CPU big endian */
818 +#define AR2315_CONFIG_CPU 0x00000400
819 +#define AR2315_CONFIG_PCIAHB 0x00000800
820 +#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
821 +/* SPI byteswap */
822 +#define AR2315_CONFIG_SPI 0x00008000
823 +#define AR2315_CONFIG_CPU_DRAM 0x00010000
824 +#define AR2315_CONFIG_CPU_PCI 0x00020000
825 +#define AR2315_CONFIG_CPU_MMR 0x00040000
826 +#define AR2315_CONFIG_BIG 0x00000400
827 +
828 +/*
829 + * NMI control
830 + */
831 +#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010)
832 +
833 +#define AR2315_NMI_EN 1
834 +
835 +/*
836 + * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0).
837 + */
838 +#define AR2315_SREV (AR2315_DSLBASE + 0x0014)
839 +
840 +#define AR2315_REV_MAJ 0x00f0
841 +#define AR2315_REV_MAJ_S 4
842 +#define AR2315_REV_MIN 0x000f
843 +#define AR2315_REV_MIN_S 0
844 +#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
845 +
846 +/*
847 + * Interface Enable
848 + */
849 +#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018)
850 +
851 +#define AR2315_IF_MASK 0x00000007
852 +#define AR2315_IF_DISABLED 0
853 +#define AR2315_IF_PCI 1
854 +#define AR2315_IF_TS_LOCAL 2
855 +/* only for emulation with separate pins */
856 +#define AR2315_IF_ALL 3
857 +#define AR2315_IF_LOCAL_HOST 0x00000008
858 +#define AR2315_IF_PCI_HOST 0x00000010
859 +#define AR2315_IF_PCI_INTR 0x00000020
860 +#define AR2315_IF_PCI_CLK_MASK 0x00030000
861 +#define AR2315_IF_PCI_CLK_INPUT 0
862 +#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
863 +#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
864 +#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
865 +#define AR2315_IF_PCI_CLK_SHIFT 16
866 +
867 +/*
868 + * APB Interrupt control
869 + */
870 +
871 +#define AR2315_ISR (AR2315_DSLBASE + 0x0020)
872 +#define AR2315_IMR (AR2315_DSLBASE + 0x0024)
873 +#define AR2315_GISR (AR2315_DSLBASE + 0x0028)
874 +
875 +#define AR2315_ISR_UART0 0x0001 /* high speed UART */
876 +#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
877 +#define AR2315_ISR_SPI 0x0004 /* SPI bus */
878 +#define AR2315_ISR_AHB 0x0008 /* AHB error */
879 +#define AR2315_ISR_APB 0x0010 /* APB error */
880 +#define AR2315_ISR_TIMER 0x0020 /* timer */
881 +#define AR2315_ISR_GPIO 0x0040 /* GPIO */
882 +#define AR2315_ISR_WD 0x0080 /* watchdog */
883 +#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
884 +
885 +#define AR2315_GISR_MISC 0x0001
886 +#define AR2315_GISR_WLAN0 0x0002
887 +#define AR2315_GISR_MPEGTS_RSVD 0x0004
888 +#define AR2315_GISR_LOCALPCI 0x0008
889 +#define AR2315_GISR_WMACPOLL 0x0010
890 +#define AR2315_GISR_TIMER 0x0020
891 +#define AR2315_GISR_ETHERNET 0x0040
892 +
893 +/*
894 + * Interrupt routing from IO to the processor IP bits
895 + * Define our inter mask and level
896 + */
897 +#define AR2315_INTR_MISCIO SR_IBIT3
898 +#define AR2315_INTR_WLAN0 SR_IBIT4
899 +#define AR2315_INTR_ENET0 SR_IBIT5
900 +#define AR2315_INTR_LOCALPCI SR_IBIT6
901 +#define AR2315_INTR_WMACPOLL SR_IBIT7
902 +#define AR2315_INTR_COMPARE SR_IBIT8
903 +
904 +/*
905 + * Timers
906 + */
907 +#define AR2315_TIMER (AR2315_DSLBASE + 0x0030)
908 +#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034)
909 +#define AR2315_WD (AR2315_DSLBASE + 0x0038)
910 +#define AR2315_WDC (AR2315_DSLBASE + 0x003c)
911 +
912 +#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
913 +#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
914 +#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */
915 +
916 +/*
917 + * CPU Performance Counters
918 + */
919 +#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048)
920 +#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c)
921 +
922 +#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
923 +#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
924 +#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
925 +#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
926 +#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
927 +#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
928 +#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
929 +
930 +#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
931 +#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
932 +#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
933 +#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
934 +#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
935 +#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
936 +#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
937 +
938 +/*
939 + * AHB Error Reporting.
940 + */
941 +#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */
942 +#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */
943 +#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */
944 +#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */
945 +#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */
946 +
947 +#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
948 + /* write 1 to clear all bits in ERR0 */
949 +#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
950 +#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
951 +
952 +#define AR2315_PROCERR_HMAST 0x0000000f
953 +#define AR2315_PROCERR_HMAST_DFLT 0
954 +#define AR2315_PROCERR_HMAST_WMAC 1
955 +#define AR2315_PROCERR_HMAST_ENET 2
956 +#define AR2315_PROCERR_HMAST_PCIENDPT 3
957 +#define AR2315_PROCERR_HMAST_LOCAL 4
958 +#define AR2315_PROCERR_HMAST_CPU 5
959 +#define AR2315_PROCERR_HMAST_PCITGT 6
960 +
961 +#define AR2315_PROCERR_HMAST_S 0
962 +#define AR2315_PROCERR_HWRITE 0x00000010
963 +#define AR2315_PROCERR_HSIZE 0x00000060
964 +#define AR2315_PROCERR_HSIZE_S 5
965 +#define AR2315_PROCERR_HTRANS 0x00000180
966 +#define AR2315_PROCERR_HTRANS_S 7
967 +#define AR2315_PROCERR_HBURST 0x00000e00
968 +#define AR2315_PROCERR_HBURST_S 9
969 +
970 +/*
971 + * Clock Control
972 + */
973 +#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064)
974 +#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068)
975 +#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c)
976 +#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070)
977 +#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074)
978 +#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080)
979 +#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084)
980 +
981 +/* PLLc Control fields */
982 +#define PLLC_REF_DIV_M 0x00000003
983 +#define PLLC_REF_DIV_S 0
984 +#define PLLC_FDBACK_DIV_M 0x0000007C
985 +#define PLLC_FDBACK_DIV_S 2
986 +#define PLLC_ADD_FDBACK_DIV_M 0x00000080
987 +#define PLLC_ADD_FDBACK_DIV_S 7
988 +#define PLLC_CLKC_DIV_M 0x0001c000
989 +#define PLLC_CLKC_DIV_S 14
990 +#define PLLC_CLKM_DIV_M 0x00700000
991 +#define PLLC_CLKM_DIV_S 20
992 +
993 +/* CPU CLK Control fields */
994 +#define CPUCLK_CLK_SEL_M 0x00000003
995 +#define CPUCLK_CLK_SEL_S 0
996 +#define CPUCLK_CLK_DIV_M 0x0000000c
997 +#define CPUCLK_CLK_DIV_S 2
998 +
999 +/* AMBA CLK Control fields */
1000 +#define AMBACLK_CLK_SEL_M 0x00000003
1001 +#define AMBACLK_CLK_SEL_S 0
1002 +#define AMBACLK_CLK_DIV_M 0x0000000c
1003 +#define AMBACLK_CLK_DIV_S 2
1004 +
1005 +/* GPIO MMR base address */
1006 +#define AR2315_GPIO (AR2315_DSLBASE + 0x0088)
1007 +
1008 +#define AR2315_RESET_GPIO 5
1009 +
1010 +/*
1011 + * PCI Clock Control
1012 + */
1013 +#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4)
1014 +
1015 +#define AR2315_PCICLK_INPUT_M 0x3
1016 +#define AR2315_PCICLK_INPUT_S 0
1017 +
1018 +#define AR2315_PCICLK_PLLC_CLKM 0
1019 +#define AR2315_PCICLK_PLLC_CLKM1 1
1020 +#define AR2315_PCICLK_PLLC_CLKC 2
1021 +#define AR2315_PCICLK_REF_CLK 3
1022 +
1023 +#define AR2315_PCICLK_DIV_M 0xc
1024 +#define AR2315_PCICLK_DIV_S 2
1025 +
1026 +#define AR2315_PCICLK_IN_FREQ 0
1027 +#define AR2315_PCICLK_IN_FREQ_DIV_6 1
1028 +#define AR2315_PCICLK_IN_FREQ_DIV_8 2
1029 +#define AR2315_PCICLK_IN_FREQ_DIV_10 3
1030 +
1031 +/*
1032 + * Observation Control Register
1033 + */
1034 +#define AR2315_OCR (AR2315_DSLBASE + 0x00b0)
1035 +#define OCR_GPIO0_IRIN 0x0040
1036 +#define OCR_GPIO1_IROUT 0x0080
1037 +#define OCR_GPIO3_RXCLR 0x0200
1038 +
1039 +/*
1040 + * General Clock Control
1041 + */
1042 +
1043 +#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4)
1044 +#define MISCCLK_PLLBYPASS_EN 0x00000001
1045 +#define MISCCLK_PROCREFCLK 0x00000002
1046 +
1047 +/*
1048 + * SDRAM Controller
1049 + * - No read or write buffers are included.
1050 + */
1051 +#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00)
1052 +#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c)
1053 +#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10)
1054 +
1055 +#define SDRAM_DATA_WIDTH_M 0x00006000
1056 +#define SDRAM_DATA_WIDTH_S 13
1057 +
1058 +#define SDRAM_COL_WIDTH_M 0x00001E00
1059 +#define SDRAM_COL_WIDTH_S 9
1060 +
1061 +#define SDRAM_ROW_WIDTH_M 0x000001E0
1062 +#define SDRAM_ROW_WIDTH_S 5
1063 +
1064 +#define SDRAM_BANKADDR_BITS_M 0x00000018
1065 +#define SDRAM_BANKADDR_BITS_S 3
1066 +
1067 +/*
1068 + * PCI Bus Interface Registers
1069 + */
1070 +#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008)
1071 +#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1072 +
1073 +#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c)
1074 +#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
1075 +#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */
1076 +#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
1077 +#define AR2315_PCIMISC_RST_MODE 0x00000030
1078 +#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
1079 +#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
1080 +#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
1081 +#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
1082 +#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
1083 +#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
1084 +#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
1085 +#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache
1086 + * disable */
1087 +
1088 +#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010)
1089 +
1090 +#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014)
1091 +
1092 +#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100)
1093 +#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
1094 +#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
1095 +#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
1096 +#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
1097 +
1098 +#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104)
1099 +#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
1100 +#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
1101 +#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
1102 +#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
1103 +
1104 +#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200)
1105 +
1106 +#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400)
1107 +#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
1108 +
1109 +#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404)
1110 +#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
1111 +
1112 +#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408)
1113 +
1114 +#define AR2315_PCI_ISR (AR2315_PCI + 0x0500) /* write one to clr */
1115 +#define AR2315_PCI_INT_TX 0x00000001 /* Desc In Completed */
1116 +#define AR2315_PCI_INT_TXOK 0x00000002 /* Desc In OK */
1117 +#define AR2315_PCI_INT_TXERR 0x00000004 /* Desc In ERR */
1118 +#define AR2315_PCI_INT_TXEOL 0x00000008 /* Desc In End-of-List */
1119 +#define AR2315_PCI_INT_RX 0x00000010 /* Desc Out Completed */
1120 +#define AR2315_PCI_INT_RXOK 0x00000020 /* Desc Out OK */
1121 +#define AR2315_PCI_INT_RXERR 0x00000040 /* Desc Out ERR */
1122 +#define AR2315_PCI_INT_RXEOL 0x00000080 /* Desc Out EOL */
1123 +#define AR2315_PCI_INT_TXOOD 0x00000200 /* Desc In Out-of-Desc */
1124 +#define AR2315_PCI_INT_DESCMASK 0x0000FFFF /* Desc Mask */
1125 +#define AR2315_PCI_INT_EXT 0x02000000 /* Extern PCI INTA */
1126 +#define AR2315_PCI_INT_ABORT 0x04000000 /* PCI bus abort event */
1127 +
1128 +#define AR2315_PCI_IMR (AR2315_PCI + 0x0504) /* mask _PCI_ISR bits */
1129 +
1130 +#define AR2315_PCI_IER (AR2315_PCI + 0x0508) /* global PCI int en */
1131 +#define AR2315_PCI_IER_DISABLE 0x00 /* disable pci interrupts */
1132 +#define AR2315_PCI_IER_ENABLE 0x01 /* enable pci interrupts */
1133 +
1134 +#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800)
1135 +#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804)
1136 +#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810)
1137 +#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900)
1138 +#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904)
1139 +#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908)
1140 +
1141 +/*
1142 + * Local Bus Interface Registers
1143 + */
1144 +#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000)
1145 +#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
1146 +#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
1147 +#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
1148 +#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
1149 +#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
1150 +#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
1151 +#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
1152 +#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
1153 +#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
1154 +#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
1155 +#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
1156 +#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
1157 +#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
1158 +#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
1159 +#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
1160 +#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
1161 +#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
1162 +#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
1163 +#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
1164 +#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
1165 +#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
1166 +#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
1167 +#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
1168 +#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
1169 +#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
1170 +
1171 +#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004)
1172 +#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
1173 +
1174 +#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008)
1175 +#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1176 +
1177 +#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C)
1178 +#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
1179 +#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
1180 +#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
1181 +#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
1182 +#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
1183 +#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80
1184 +#define AR2315_LBM_TIMEOUT_SHFT 7
1185 +#define AR2315_LBM_PORTMUX 0x07000000
1186 +
1187 +#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010)
1188 +
1189 +#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100)
1190 +#define AR2315_LB_TXEN_0 0x01
1191 +#define AR2315_LB_TXEN_1 0x02
1192 +#define AR2315_LB_TXEN_2 0x04
1193 +#define AR2315_LB_TXEN_3 0x08
1194 +
1195 +#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104)
1196 +#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200)
1197 +
1198 +#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400)
1199 +#define AR2315_LB_RXEN 0x01
1200 +
1201 +#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404)
1202 +#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408)
1203 +
1204 +#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500)
1205 +#define AR2315_INT_TX_DESC 0x0001
1206 +#define AR2315_INT_TX_OK 0x0002
1207 +#define AR2315_INT_TX_ERR 0x0004
1208 +#define AR2315_INT_TX_EOF 0x0008
1209 +#define AR2315_INT_RX_DESC 0x0010
1210 +#define AR2315_INT_RX_OK 0x0020
1211 +#define AR2315_INT_RX_ERR 0x0040
1212 +#define AR2315_INT_RX_EOF 0x0080
1213 +#define AR2315_INT_TX_TRUNC 0x0100
1214 +#define AR2315_INT_TX_STARVE 0x0200
1215 +#define AR2315_INT_LB_TIMEOUT 0x0400
1216 +#define AR2315_INT_LB_ERR 0x0800
1217 +#define AR2315_INT_MBOX_WR 0x1000
1218 +#define AR2315_INT_MBOX_RD 0x2000
1219 +
1220 +/* Bit definitions for INT MASK are the same as INT_STATUS */
1221 +#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504)
1222 +
1223 +#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508)
1224 +#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600)
1225 +
1226 +/*
1227 + * IR Interface Registers
1228 + */
1229 +#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000)
1230 +
1231 +#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */
1232 +
1233 +#define AR2315_IR_CONTROL (AR2315_IR + 0x0800)
1234 +#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */
1235 +#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */
1236 +#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor */
1237 +#define AR2315_IRCTL_SAMPLECLK_SHFT 1
1238 +#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk div */
1239 +#define AR2315_IRCTL_OUTPUTCLK_SHFT 14
1240 +
1241 +#define AR2315_IR_STATUS (AR2315_IR + 0x0804)
1242 +#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */
1243 +#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */
1244 +
1245 +#define AR2315_IR_CONFIG (AR2315_IR + 0x0808)
1246 +#define AR2315_IRCFG_INVIN 0x00000001 /* invert in polarity */
1247 +#define AR2315_IRCFG_INVOUT 0x00000002 /* invert out polarity */
1248 +#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */
1249 +#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0
1250 +#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100
1251 +#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00
1252 +#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000
1253 +#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000
1254 +#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000
1255 +
1256 +/*
1257 + * We need some arbitrary non-zero value to be programmed to the BAR1 register
1258 + * of PCI host controller to enable DMA. The same value should be used as the
1259 + * offset to calculate the physical address of DMA buffer for PCI devices.
1260 + */
1261 +#define AR2315_PCI_HOST_SDRAM_BASEADDR 0x20000000
1262 +
1263 +/* ??? access BAR */
1264 +#define AR2315_PCI_HOST_MBAR0 0x10000000
1265 +/* RAM access BAR */
1266 +#define AR2315_PCI_HOST_MBAR1 AR2315_PCI_HOST_SDRAM_BASEADDR
1267 +/* ??? access BAR */
1268 +#define AR2315_PCI_HOST_MBAR2 0x30000000
1269 +
1270 +#endif /* __ASM_MACH_AR231X_AR2315_REGS_H */
1271 --- /dev/null
1272 +++ b/arch/mips/include/asm/mach-ar231x/ar5312_regs.h
1273 @@ -0,0 +1,235 @@
1274 +/*
1275 + * This file is subject to the terms and conditions of the GNU General Public
1276 + * License. See the file "COPYING" in the main directory of this archive
1277 + * for more details.
1278 + *
1279 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1280 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1281 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1282 + */
1283 +
1284 +#ifndef __ASM_MACH_AR231X_AR5312_REGS_H
1285 +#define __ASM_MACH_AR231X_AR5312_REGS_H
1286 +
1287 +#include <asm/addrspace.h>
1288 +
1289 +/*
1290 + * IRQs
1291 + */
1292 +#define AR5312_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
1293 +#define AR5312_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
1294 +#define AR5312_IRQ_ENET1_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
1295 +#define AR5312_IRQ_WLAN1_INTRS (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
1296 +#define AR5312_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
1297 +
1298 +/*
1299 + * Miscellaneous interrupts, which share IP6.
1300 + */
1301 +#define AR5312_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+0)
1302 +#define AR5312_MISC_IRQ_AHB_PROC (AR231X_MISC_IRQ_BASE+1)
1303 +#define AR5312_MISC_IRQ_AHB_DMA (AR231X_MISC_IRQ_BASE+2)
1304 +#define AR5312_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+3)
1305 +#define AR5312_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+4)
1306 +#define AR5312_MISC_IRQ_UART0_DMA (AR231X_MISC_IRQ_BASE+5)
1307 +#define AR5312_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+6)
1308 +#define AR5312_MISC_IRQ_LOCAL (AR231X_MISC_IRQ_BASE+7)
1309 +#define AR5312_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+8)
1310 +#define AR5312_MISC_IRQ_COUNT 9
1311 +
1312 +/*
1313 + * Address Map
1314 + */
1315 +#define AR5312_WLAN0 0x18000000
1316 +#define AR5312_WLAN1 0x18500000
1317 +#define AR5312_ENET0 0x18100000
1318 +#define AR5312_ENET1 0x18200000
1319 +#define AR5312_SDRAMCTL 0x18300000
1320 +#define AR5312_FLASHCTL 0x18400000
1321 +#define AR5312_APBBASE 0x1c000000
1322 +#define AR5312_UART0 0x1c000000 /* UART MMR */
1323 +#define AR5312_FLASH 0x1e000000
1324 +
1325 +/*
1326 + * AR5312_NUM_ENET_MAC defines the number of ethernet MACs that
1327 + * should be considered available. The AR5312 supports 2 enet MACS,
1328 + * even though many reference boards only actually use 1 of them
1329 + * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
1330 + * The AR2312 supports 1 enet MAC.
1331 + */
1332 +#define AR5312_NUM_ENET_MAC 2
1333 +
1334 +/*
1335 + * Need these defines to determine true number of ethernet MACs
1336 + */
1337 +#define AR5312_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1338 +#define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1339 +#define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1340 +
1341 +/* MII registers offset inside Ethernet MMR region */
1342 +#define AR5312_ENET0_MII (AR5312_ENET0 + 0x14)
1343 +#define AR5312_ENET1_MII (AR5312_ENET1 + 0x14)
1344 +
1345 +/*
1346 + * AR5312_NUM_WMAC defines the number of Wireless MACs that\
1347 + * should be considered available.
1348 + */
1349 +#define AR5312_NUM_WMAC 2
1350 +
1351 +/* Reset/Timer Block Address Map */
1352 +#define AR5312_RESETTMR (AR5312_APBBASE + 0x3000)
1353 +#define AR5312_TIMER (AR5312_RESETTMR + 0x0000) /* countdown timer */
1354 +#define AR5312_WD_CTRL (AR5312_RESETTMR + 0x0008) /* watchdog cntrl */
1355 +#define AR5312_WD_TIMER (AR5312_RESETTMR + 0x000c) /* watchdog timer */
1356 +#define AR5312_ISR (AR5312_RESETTMR + 0x0010) /* Intr Status Reg */
1357 +#define AR5312_IMR (AR5312_RESETTMR + 0x0014) /* Intr Mask Reg */
1358 +#define AR5312_RESET (AR5312_RESETTMR + 0x0020)
1359 +#define AR5312_CLOCKCTL1 (AR5312_RESETTMR + 0x0064)
1360 +#define AR5312_SCRATCH (AR5312_RESETTMR + 0x006c)
1361 +#define AR5312_PROCADDR (AR5312_RESETTMR + 0x0070)
1362 +#define AR5312_PROC1 (AR5312_RESETTMR + 0x0074)
1363 +#define AR5312_DMAADDR (AR5312_RESETTMR + 0x0078)
1364 +#define AR5312_DMA1 (AR5312_RESETTMR + 0x007c)
1365 +#define AR5312_ENABLE (AR5312_RESETTMR + 0x0080) /* interface enb */
1366 +#define AR5312_REV (AR5312_RESETTMR + 0x0090) /* revision */
1367 +
1368 +/* AR5312_WD_CTRL register bit field definitions */
1369 +#define AR5312_WD_CTRL_IGNORE_EXPIRATION 0x0000
1370 +#define AR5312_WD_CTRL_NMI 0x0001
1371 +#define AR5312_WD_CTRL_RESET 0x0002
1372 +
1373 +/* AR5312_ISR register bit field definitions */
1374 +#define AR5312_ISR_TIMER 0x0001
1375 +#define AR5312_ISR_AHBPROC 0x0002
1376 +#define AR5312_ISR_AHBDMA 0x0004
1377 +#define AR5312_ISR_GPIO 0x0008
1378 +#define AR5312_ISR_UART0 0x0010
1379 +#define AR5312_ISR_UART0DMA 0x0020
1380 +#define AR5312_ISR_WD 0x0040
1381 +#define AR5312_ISR_LOCAL 0x0080
1382 +
1383 +/* AR5312_RESET register bit field definitions */
1384 +#define AR5312_RESET_SYSTEM 0x00000001 /* cold reset full system */
1385 +#define AR5312_RESET_PROC 0x00000002 /* cold reset MIPS core */
1386 +#define AR5312_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
1387 +#define AR5312_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1388 +#define AR5312_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1389 +#define AR5312_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
1390 +#define AR5312_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
1391 +#define AR5312_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
1392 +#define AR5312_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1393 +#define AR5312_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
1394 +#define AR5312_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1395 +#define AR5312_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1396 +#define AR5312_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
1397 +#define AR5312_RESET_NMI 0x00010000 /* send an NMI to the processor */
1398 +#define AR5312_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
1399 +#define AR5312_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
1400 +#define AR5312_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1401 +#define AR5312_RESET_WDOG 0x00100000 /* last reset was a watchdog */
1402 +
1403 +#define AR5312_RESET_WMAC0_BITS \
1404 + (AR5312_RESET_WLAN0 |\
1405 + AR5312_RESET_WARM_WLAN0_MAC |\
1406 + AR5312_RESET_WARM_WLAN0_BB)
1407 +
1408 +#define AR5312_RESET_WMAC1_BITS \
1409 + (AR5312_RESET_WLAN1 |\
1410 + AR5312_RESET_WARM_WLAN1_MAC |\
1411 + AR5312_RESET_WARM_WLAN1_BB)
1412 +
1413 +/* AR5312_CLOCKCTL1 register bit field definitions */
1414 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1415 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1416 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1417 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1418 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1419 +
1420 +/* Valid for AR5312 and AR2312 */
1421 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1422 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1423 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1424 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1425 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1426 +
1427 +/* Valid for AR2313 */
1428 +#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1429 +#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1430 +#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1431 +#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1432 +#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1433 +
1434 +/* AR5312_ENABLE register bit field definitions */
1435 +#define AR5312_ENABLE_WLAN0 0x0001
1436 +#define AR5312_ENABLE_ENET0 0x0002
1437 +#define AR5312_ENABLE_ENET1 0x0004
1438 +#define AR5312_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
1439 +#define AR5312_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
1440 +#define AR5312_ENABLE_WLAN1 \
1441 + (AR5312_ENABLE_UART_AND_WLAN1_PIO |\
1442 + AR5312_ENABLE_WLAN1_DMA)
1443 +
1444 +/* AR5312_REV register bit field definitions */
1445 +#define AR5312_REV_WMAC_MAJ 0xf000
1446 +#define AR5312_REV_WMAC_MAJ_S 12
1447 +#define AR5312_REV_WMAC_MIN 0x0f00
1448 +#define AR5312_REV_WMAC_MIN_S 8
1449 +#define AR5312_REV_MAJ 0x00f0
1450 +#define AR5312_REV_MAJ_S 4
1451 +#define AR5312_REV_MIN 0x000f
1452 +#define AR5312_REV_MIN_S 0
1453 +#define AR5312_REV_CHIP (AR5312_REV_MAJ|AR5312_REV_MIN)
1454 +
1455 +/* Major revision numbers, bits 7..4 of Revision ID register */
1456 +#define AR5312_REV_MAJ_AR5312 0x4
1457 +#define AR5312_REV_MAJ_AR2313 0x5
1458 +
1459 +/* Minor revision numbers, bits 3..0 of Revision ID register */
1460 +#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1461 +#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1462 +
1463 +/* AR5312_FLASHCTL register bit field definitions */
1464 +#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
1465 +#define FLASHCTL_IDCY_S 0
1466 +#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1467 +#define FLASHCTL_WST1_S 5
1468 +#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1469 +#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1470 +#define FLASHCTL_WST2_S 11
1471 +#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
1472 +#define FLASHCTL_AC_S 16
1473 +#define FLASHCTL_AC_128K 0x00000000
1474 +#define FLASHCTL_AC_256K 0x00010000
1475 +#define FLASHCTL_AC_512K 0x00020000
1476 +#define FLASHCTL_AC_1M 0x00030000
1477 +#define FLASHCTL_AC_2M 0x00040000
1478 +#define FLASHCTL_AC_4M 0x00050000
1479 +#define FLASHCTL_AC_8M 0x00060000
1480 +#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1481 +#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1482 +#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
1483 +#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
1484 +#define FLASHCTL_WP 0x04000000 /* Write protect */
1485 +#define FLASHCTL_BM 0x08000000 /* Burst mode */
1486 +#define FLASHCTL_MW 0x30000000 /* Memory width */
1487 +#define FLASHCTL_MW8 0x00000000 /* Memory width x8 */
1488 +#define FLASHCTL_MW16 0x10000000 /* Memory width x16 */
1489 +#define FLASHCTL_MW32 0x20000000 /* Memory width x32 (not supported) */
1490 +#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
1491 +#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
1492 +#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
1493 +
1494 +/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
1495 +#define AR5312_FLASHCTL0 (AR5312_FLASHCTL + 0x00)
1496 +#define AR5312_FLASHCTL1 (AR5312_FLASHCTL + 0x04)
1497 +#define AR5312_FLASHCTL2 (AR5312_FLASHCTL + 0x08)
1498 +
1499 +/* ARM SDRAM Controller -- just enough to determine memory size */
1500 +#define AR5312_MEM_CFG1 (AR5312_SDRAMCTL + 0x04)
1501 +#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */
1502 +#define MEM_CFG1_AC0_S 8
1503 +#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
1504 +#define MEM_CFG1_AC1_S 12
1505 +
1506 +#define AR5312_GPIO (AR5312_APBBASE + 0x2000)
1507 +
1508 +#endif /* __ASM_MACH_AR231X_AR5312_REGS_H */
1509 --- /dev/null
1510 +++ b/arch/mips/ar231x/ar5312.c
1511 @@ -0,0 +1,476 @@
1512 +/*
1513 + * This file is subject to the terms and conditions of the GNU General Public
1514 + * License. See the file "COPYING" in the main directory of this archive
1515 + * for more details.
1516 + *
1517 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1518 + * Copyright (C) 2006 FON Technology, SL.
1519 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1520 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1521 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1522 + */
1523 +
1524 +/*
1525 + * Platform devices for Atheros SoCs
1526 + */
1527 +
1528 +#include <generated/autoconf.h>
1529 +#include <linux/init.h>
1530 +#include <linux/module.h>
1531 +#include <linux/types.h>
1532 +#include <linux/string.h>
1533 +#include <linux/mtd/physmap.h>
1534 +#include <linux/platform_device.h>
1535 +#include <linux/kernel.h>
1536 +#include <linux/reboot.h>
1537 +#include <linux/leds.h>
1538 +#include <linux/gpio.h>
1539 +#include <asm/bootinfo.h>
1540 +#include <asm/reboot.h>
1541 +#include <asm/time.h>
1542 +#include <linux/irq.h>
1543 +#include <linux/io.h>
1544 +
1545 +#include <ar231x_platform.h>
1546 +#include <ar5312_regs.h>
1547 +#include <ar231x.h>
1548 +#include "devices.h"
1549 +#include "ar5312.h"
1550 +
1551 +static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
1552 +{
1553 + unsigned int ar231x_misc_intrs = ar231x_read_reg(AR5312_ISR) &
1554 + ar231x_read_reg(AR5312_IMR);
1555 +
1556 + if (ar231x_misc_intrs & AR5312_ISR_TIMER) {
1557 + generic_handle_irq(AR5312_MISC_IRQ_TIMER);
1558 + (void)ar231x_read_reg(AR5312_TIMER);
1559 + } else if (ar231x_misc_intrs & AR5312_ISR_AHBPROC)
1560 + generic_handle_irq(AR5312_MISC_IRQ_AHB_PROC);
1561 + else if ((ar231x_misc_intrs & AR5312_ISR_UART0))
1562 + generic_handle_irq(AR5312_MISC_IRQ_UART0);
1563 + else if (ar231x_misc_intrs & AR5312_ISR_WD)
1564 + generic_handle_irq(AR5312_MISC_IRQ_WATCHDOG);
1565 + else
1566 + spurious_interrupt();
1567 +}
1568 +
1569 +static asmlinkage void
1570 +ar5312_irq_dispatch(void)
1571 +{
1572 + int pending = read_c0_status() & read_c0_cause();
1573 +
1574 + if (pending & CAUSEF_IP2)
1575 + do_IRQ(AR5312_IRQ_WLAN0_INTRS);
1576 + else if (pending & CAUSEF_IP3)
1577 + do_IRQ(AR5312_IRQ_ENET0_INTRS);
1578 + else if (pending & CAUSEF_IP4)
1579 + do_IRQ(AR5312_IRQ_ENET1_INTRS);
1580 + else if (pending & CAUSEF_IP5)
1581 + do_IRQ(AR5312_IRQ_WLAN1_INTRS);
1582 + else if (pending & CAUSEF_IP6)
1583 + do_IRQ(AR5312_IRQ_MISC_INTRS);
1584 + else if (pending & CAUSEF_IP7)
1585 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
1586 + else
1587 + spurious_interrupt();
1588 +}
1589 +
1590 +/* Enable the specified AR5312_MISC_IRQ interrupt */
1591 +static void
1592 +ar5312_misc_irq_unmask(struct irq_data *d)
1593 +{
1594 + unsigned int imr;
1595 +
1596 + imr = ar231x_read_reg(AR5312_IMR);
1597 + imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE);
1598 + ar231x_write_reg(AR5312_IMR, imr);
1599 +}
1600 +
1601 +/* Disable the specified AR5312_MISC_IRQ interrupt */
1602 +static void
1603 +ar5312_misc_irq_mask(struct irq_data *d)
1604 +{
1605 + unsigned int imr;
1606 +
1607 + imr = ar231x_read_reg(AR5312_IMR);
1608 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE));
1609 + ar231x_write_reg(AR5312_IMR, imr);
1610 + ar231x_read_reg(AR5312_IMR); /* flush write buffer */
1611 +}
1612 +
1613 +static struct irq_chip ar5312_misc_irq_chip = {
1614 + .name = "AR5312-MISC",
1615 + .irq_unmask = ar5312_misc_irq_unmask,
1616 + .irq_mask = ar5312_misc_irq_mask,
1617 +};
1618 +
1619 +static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
1620 +{
1621 + u32 proc1 = ar231x_read_reg(AR5312_PROC1);
1622 + u32 proc_addr = ar231x_read_reg(AR5312_PROCADDR); /* clears error */
1623 + u32 dma1 = ar231x_read_reg(AR5312_DMA1);
1624 + u32 dma_addr = ar231x_read_reg(AR5312_DMAADDR); /* clears error */
1625 +
1626 + pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
1627 + proc_addr, proc1, dma_addr, dma1);
1628 +
1629 + machine_restart("AHB error"); /* Catastrophic failure */
1630 + return IRQ_HANDLED;
1631 +}
1632 +
1633 +static struct irqaction ar5312_ahb_proc_interrupt = {
1634 + .handler = ar5312_ahb_proc_handler,
1635 + .name = "ar5312_ahb_proc_interrupt",
1636 +};
1637 +
1638 +void __init ar5312_irq_init(void)
1639 +{
1640 + int i;
1641 +
1642 + if (!is_5312())
1643 + return;
1644 +
1645 + ar231x_irq_dispatch = ar5312_irq_dispatch;
1646 + for (i = 0; i < AR5312_MISC_IRQ_COUNT; i++) {
1647 + int irq = AR231X_MISC_IRQ_BASE + i;
1648 +
1649 + irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip,
1650 + handle_level_irq);
1651 + }
1652 + setup_irq(AR5312_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
1653 + irq_set_chained_handler(AR5312_IRQ_MISC_INTRS, ar5312_misc_irq_handler);
1654 +}
1655 +
1656 +static void ar5312_device_reset_set(u32 mask)
1657 +{
1658 + u32 val;
1659 +
1660 + val = ar231x_read_reg(AR5312_RESET);
1661 + ar231x_write_reg(AR5312_RESET, val | mask);
1662 +}
1663 +
1664 +static void ar5312_device_reset_clear(u32 mask)
1665 +{
1666 + u32 val;
1667 +
1668 + val = ar231x_read_reg(AR5312_RESET);
1669 + ar231x_write_reg(AR5312_RESET, val & ~mask);
1670 +}
1671 +
1672 +static struct physmap_flash_data ar5312_flash_data = {
1673 + .width = 2,
1674 +};
1675 +
1676 +static struct resource ar5312_flash_resource = {
1677 + .start = AR5312_FLASH,
1678 + .end = AR5312_FLASH + 0x800000 - 1,
1679 + .flags = IORESOURCE_MEM,
1680 +};
1681 +
1682 +static struct ar231x_eth ar5312_eth0_data = {
1683 + .reset_set = ar5312_device_reset_set,
1684 + .reset_clear = ar5312_device_reset_clear,
1685 + .reset_mac = AR5312_RESET_ENET0,
1686 + .reset_phy = AR5312_RESET_EPHY0,
1687 + .config = &ar231x_board,
1688 +};
1689 +
1690 +static struct ar231x_eth ar5312_eth1_data = {
1691 + .reset_set = ar5312_device_reset_set,
1692 + .reset_clear = ar5312_device_reset_clear,
1693 + .reset_mac = AR5312_RESET_ENET1,
1694 + .reset_phy = AR5312_RESET_EPHY1,
1695 + .config = &ar231x_board,
1696 +};
1697 +
1698 +static struct platform_device ar5312_physmap_flash = {
1699 + .name = "physmap-flash",
1700 + .id = 0,
1701 + .dev.platform_data = &ar5312_flash_data,
1702 + .resource = &ar5312_flash_resource,
1703 + .num_resources = 1,
1704 +};
1705 +
1706 +#ifdef CONFIG_LEDS_GPIO
1707 +static struct gpio_led ar5312_leds[] = {
1708 + { .name = "wlan", .gpio = 0, .active_low = 1, },
1709 +};
1710 +
1711 +static const struct gpio_led_platform_data ar5312_led_data = {
1712 + .num_leds = ARRAY_SIZE(ar5312_leds),
1713 + .leds = (void *)ar5312_leds,
1714 +};
1715 +
1716 +static struct platform_device ar5312_gpio_leds = {
1717 + .name = "leds-gpio",
1718 + .id = -1,
1719 + .dev.platform_data = (void *)&ar5312_led_data,
1720 +};
1721 +#endif
1722 +
1723 +/*
1724 + * NB: This mapping size is larger than the actual flash size,
1725 + * but this shouldn't be a problem here, because the flash
1726 + * will simply be mapped multiple times.
1727 + */
1728 +static char __init *ar5312_flash_limit(void)
1729 +{
1730 + u32 ctl;
1731 + /*
1732 + * Configure flash bank 0.
1733 + * Assume 8M window size. Flash will be aliased if it's smaller
1734 + */
1735 + ctl = FLASHCTL_E |
1736 + FLASHCTL_AC_8M |
1737 + FLASHCTL_RBLE |
1738 + (0x01 << FLASHCTL_IDCY_S) |
1739 + (0x07 << FLASHCTL_WST1_S) |
1740 + (0x07 << FLASHCTL_WST2_S) |
1741 + (ar231x_read_reg(AR5312_FLASHCTL0) & FLASHCTL_MW);
1742 +
1743 + ar231x_write_reg(AR5312_FLASHCTL0, ctl);
1744 +
1745 + /* Disable other flash banks */
1746 + ar231x_write_reg(AR5312_FLASHCTL1,
1747 + ar231x_read_reg(AR5312_FLASHCTL1) &
1748 + ~(FLASHCTL_E | FLASHCTL_AC));
1749 +
1750 + ar231x_write_reg(AR5312_FLASHCTL2,
1751 + ar231x_read_reg(AR5312_FLASHCTL2) &
1752 + ~(FLASHCTL_E | FLASHCTL_AC));
1753 +
1754 + return (char *)KSEG1ADDR(AR5312_FLASH + 0x800000);
1755 +}
1756 +
1757 +int __init ar5312_init_devices(void)
1758 +{
1759 + struct ar231x_boarddata *config;
1760 + u32 fctl = 0;
1761 + u8 *c;
1762 +
1763 + if (!is_5312())
1764 + return 0;
1765 +
1766 + /* Locate board/radio config data */
1767 + ar231x_find_config(ar5312_flash_limit());
1768 + config = ar231x_board.config;
1769 +
1770 + /* AR2313 has CPU minor rev. 10 */
1771 + if ((current_cpu_data.processor_id & 0xff) == 0x0a)
1772 + ar231x_devtype = DEV_TYPE_AR2313;
1773 +
1774 + /* AR2312 shares the same Silicon ID as AR5312 */
1775 + else if (config->flags & BD_ISCASPER)
1776 + ar231x_devtype = DEV_TYPE_AR2312;
1777 +
1778 + /* Everything else is probably AR5312 or compatible */
1779 + else
1780 + ar231x_devtype = DEV_TYPE_AR5312;
1781 +
1782 + /* fixup flash width */
1783 + fctl = ar231x_read_reg(AR5312_FLASHCTL) & FLASHCTL_MW;
1784 + switch (fctl) {
1785 + case FLASHCTL_MW16:
1786 + ar5312_flash_data.width = 2;
1787 + break;
1788 + case FLASHCTL_MW8:
1789 + default:
1790 + ar5312_flash_data.width = 1;
1791 + break;
1792 + }
1793 +
1794 + platform_device_register(&ar5312_physmap_flash);
1795 +
1796 +#ifdef CONFIG_LEDS_GPIO
1797 + ar5312_leds[0].gpio = config->sys_led_gpio;
1798 + platform_device_register(&ar5312_gpio_leds);
1799 +#endif
1800 +
1801 + /* Fix up MAC addresses if necessary */
1802 + if (is_broadcast_ether_addr(config->enet0_mac))
1803 + ether_addr_copy(config->enet0_mac, config->enet1_mac);
1804 +
1805 + /* If ENET0 and ENET1 have the same mac address,
1806 + * increment the one from ENET1 */
1807 + if (ether_addr_equal(config->enet0_mac, config->enet1_mac)) {
1808 + c = config->enet1_mac + 5;
1809 + while ((c >= config->enet1_mac) && !(++(*c)))
1810 + c--;
1811 + }
1812 +
1813 + switch (ar231x_devtype) {
1814 + case DEV_TYPE_AR5312:
1815 + ar5312_eth0_data.macaddr = config->enet0_mac;
1816 + ar231x_add_ethernet(0, AR5312_ENET0, "eth0_mii",
1817 + AR5312_ENET0_MII, AR5312_IRQ_ENET0_INTRS,
1818 + &ar5312_eth0_data);
1819 +
1820 + ar5312_eth1_data.macaddr = config->enet1_mac;
1821 + ar231x_add_ethernet(1, AR5312_ENET1, "eth1_mii",
1822 + AR5312_ENET1_MII, AR5312_IRQ_ENET1_INTRS,
1823 + &ar5312_eth1_data);
1824 +
1825 + if (!ar231x_board.radio)
1826 + return 0;
1827 +
1828 + if (!(config->flags & BD_WLAN0))
1829 + break;
1830 +
1831 + ar231x_add_wmac(0, AR5312_WLAN0, AR5312_IRQ_WLAN0_INTRS);
1832 + break;
1833 + /*
1834 + * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
1835 + * of ENET1. Atheros calls it 'twisted' for a reason :)
1836 + */
1837 + case DEV_TYPE_AR2312:
1838 + case DEV_TYPE_AR2313:
1839 + ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
1840 + ar5312_eth1_data.macaddr = config->enet0_mac;
1841 + ar231x_add_ethernet(1, AR5312_ENET1, "eth0_mii",
1842 + AR5312_ENET0_MII, AR5312_IRQ_ENET1_INTRS,
1843 + &ar5312_eth1_data);
1844 +
1845 + if (!ar231x_board.radio)
1846 + return 0;
1847 + break;
1848 + default:
1849 + break;
1850 + }
1851 +
1852 + if (config->flags & BD_WLAN1)
1853 + ar231x_add_wmac(1, AR5312_WLAN1, AR5312_IRQ_WLAN1_INTRS);
1854 +
1855 + return 0;
1856 +}
1857 +
1858 +static void ar5312_restart(char *command)
1859 +{
1860 + /* reset the system */
1861 + local_irq_disable();
1862 + while (1)
1863 + ar231x_write_reg(AR5312_RESET, AR5312_RESET_SYSTEM);
1864 +}
1865 +
1866 +/*
1867 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
1868 + * to determine the predevisor value.
1869 + */
1870 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
1871 +
1872 +static int __init
1873 +ar5312_cpu_frequency(void)
1874 +{
1875 + unsigned int scratch;
1876 + unsigned int predivide_mask, predivide_shift;
1877 + unsigned int multiplier_mask, multiplier_shift;
1878 + unsigned int clock_ctl1, predivide_select, predivisor, multiplier;
1879 + unsigned int doubler_mask;
1880 + u16 devid;
1881 +
1882 + /* Trust the bootrom's idea of cpu frequency. */
1883 + scratch = ar231x_read_reg(AR5312_SCRATCH);
1884 + if (scratch)
1885 + return scratch;
1886 +
1887 + devid = ar231x_read_reg(AR5312_REV);
1888 + devid &= AR5312_REV_MAJ;
1889 + devid >>= AR5312_REV_MAJ_S;
1890 + if (devid == AR5312_REV_MAJ_AR2313) {
1891 + predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
1892 + predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
1893 + multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
1894 + multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
1895 + doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
1896 + } else { /* AR5312 and AR2312 */
1897 + predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
1898 + predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
1899 + multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
1900 + multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
1901 + doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
1902 + }
1903 +
1904 + /*
1905 + * Clocking is derived from a fixed 40MHz input clock.
1906 + *
1907 + * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
1908 + * sys_freq = cpu_freq / 4 (used for APB clock, serial,
1909 + * flash, Timer, Watchdog Timer)
1910 + *
1911 + * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
1912 + *
1913 + * So, for example, with a PLL multiplier of 5, we have
1914 + *
1915 + * cpu_freq = 200MHz
1916 + * sys_freq = 50MHz
1917 + * cnt_freq = 100MHz
1918 + *
1919 + * We compute the CPU frequency, based on PLL settings.
1920 + */
1921 +
1922 + clock_ctl1 = ar231x_read_reg(AR5312_CLOCKCTL1);
1923 + predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
1924 + predivisor = clockctl1_predivide_table[predivide_select];
1925 + multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
1926 +
1927 + if (clock_ctl1 & doubler_mask)
1928 + multiplier = multiplier << 1;
1929 +
1930 + return (40000000 / predivisor) * multiplier;
1931 +}
1932 +
1933 +static inline int
1934 +ar5312_sys_frequency(void)
1935 +{
1936 + return ar5312_cpu_frequency() / 4;
1937 +}
1938 +
1939 +void __init
1940 +ar5312_time_init(void)
1941 +{
1942 + if (!is_5312())
1943 + return;
1944 +
1945 + mips_hpt_frequency = ar5312_cpu_frequency() / 2;
1946 +}
1947 +
1948 +void __init
1949 +ar5312_prom_init(void)
1950 +{
1951 + u32 memsize, memcfg, bank0AC, bank1AC;
1952 + u32 devid;
1953 +
1954 + if (!is_5312())
1955 + return;
1956 +
1957 + /* Detect memory size */
1958 + memcfg = ar231x_read_reg(AR5312_MEM_CFG1);
1959 + bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
1960 + bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
1961 + memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) +
1962 + (bank1AC ? (1 << (bank1AC+1)) : 0);
1963 + memsize <<= 20;
1964 + add_memory_region(0, memsize, BOOT_MEM_RAM);
1965 +
1966 + devid = ar231x_read_reg(AR5312_REV);
1967 + devid >>= AR5312_REV_WMAC_MIN_S;
1968 + devid &= AR5312_REV_CHIP;
1969 + ar231x_board.devid = (u16)devid;
1970 +}
1971 +
1972 +void __init
1973 +ar5312_plat_setup(void)
1974 +{
1975 + if (!is_5312())
1976 + return;
1977 +
1978 + /* Clear any lingering AHB errors */
1979 + ar231x_read_reg(AR5312_PROCADDR);
1980 + ar231x_read_reg(AR5312_DMAADDR);
1981 + ar231x_write_reg(AR5312_WD_CTRL, AR5312_WD_CTRL_IGNORE_EXPIRATION);
1982 +
1983 + _machine_restart = ar5312_restart;
1984 + ar231x_serial_setup(AR5312_UART0, AR5312_MISC_IRQ_UART0,
1985 + ar5312_sys_frequency());
1986 +}
1987 +
1988 --- /dev/null
1989 +++ b/arch/mips/ar231x/ar2315.c
1990 @@ -0,0 +1,431 @@
1991 +/*
1992 + * This file is subject to the terms and conditions of the GNU General Public
1993 + * License. See the file "COPYING" in the main directory of this archive
1994 + * for more details.
1995 + *
1996 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1997 + * Copyright (C) 2006 FON Technology, SL.
1998 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1999 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
2000 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
2001 + */
2002 +
2003 +/*
2004 + * Platform devices for Atheros SoCs
2005 + */
2006 +
2007 +#include <generated/autoconf.h>
2008 +#include <linux/init.h>
2009 +#include <linux/module.h>
2010 +#include <linux/types.h>
2011 +#include <linux/string.h>
2012 +#include <linux/platform_device.h>
2013 +#include <linux/kernel.h>
2014 +#include <linux/reboot.h>
2015 +#include <linux/delay.h>
2016 +#include <linux/leds.h>
2017 +#include <linux/gpio.h>
2018 +#include <asm/bootinfo.h>
2019 +#include <asm/reboot.h>
2020 +#include <asm/time.h>
2021 +#include <linux/irq.h>
2022 +#include <linux/io.h>
2023 +
2024 +#include <ar231x_platform.h>
2025 +#include <ar2315_regs.h>
2026 +#include <ar231x.h>
2027 +#include "devices.h"
2028 +#include "ar2315.h"
2029 +
2030 +static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
2031 +{
2032 + unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) &
2033 + ar231x_read_reg(AR2315_IMR);
2034 +
2035 + if (misc_intr & AR2315_ISR_SPI)
2036 + generic_handle_irq(AR2315_MISC_IRQ_SPI);
2037 + else if (misc_intr & AR2315_ISR_TIMER)
2038 + generic_handle_irq(AR2315_MISC_IRQ_TIMER);
2039 + else if (misc_intr & AR2315_ISR_AHB)
2040 + generic_handle_irq(AR2315_MISC_IRQ_AHB);
2041 + else if (misc_intr & AR2315_ISR_GPIO) {
2042 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
2043 + generic_handle_irq(AR2315_MISC_IRQ_GPIO);
2044 + } else if (misc_intr & AR2315_ISR_UART0)
2045 + generic_handle_irq(AR2315_MISC_IRQ_UART0);
2046 + else if (misc_intr & AR2315_ISR_WD) {
2047 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_WD);
2048 + generic_handle_irq(AR2315_MISC_IRQ_WATCHDOG);
2049 + } else
2050 + spurious_interrupt();
2051 +}
2052 +
2053 +/*
2054 + * Called when an interrupt is received, this function
2055 + * determines exactly which interrupt it was, and it
2056 + * invokes the appropriate handler.
2057 + *
2058 + * Implicitly, we also define interrupt priority by
2059 + * choosing which to dispatch first.
2060 + */
2061 +static asmlinkage void
2062 +ar2315_irq_dispatch(void)
2063 +{
2064 + int pending = read_c0_status() & read_c0_cause();
2065 +
2066 + if (pending & CAUSEF_IP3)
2067 + do_IRQ(AR2315_IRQ_WLAN0_INTRS);
2068 + else if (pending & CAUSEF_IP4)
2069 + do_IRQ(AR2315_IRQ_ENET0_INTRS);
2070 + else if (pending & CAUSEF_IP2)
2071 + do_IRQ(AR2315_IRQ_MISC_INTRS);
2072 + else if (pending & CAUSEF_IP7)
2073 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
2074 + else
2075 + spurious_interrupt();
2076 +}
2077 +
2078 +static void
2079 +ar2315_misc_irq_unmask(struct irq_data *d)
2080 +{
2081 + unsigned int imr;
2082 +
2083 + imr = ar231x_read_reg(AR2315_IMR);
2084 + imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE);
2085 + ar231x_write_reg(AR2315_IMR, imr);
2086 +}
2087 +
2088 +static void
2089 +ar2315_misc_irq_mask(struct irq_data *d)
2090 +{
2091 + unsigned int imr;
2092 +
2093 + imr = ar231x_read_reg(AR2315_IMR);
2094 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE));
2095 + ar231x_write_reg(AR2315_IMR, imr);
2096 +}
2097 +
2098 +static struct irq_chip ar2315_misc_irq_chip = {
2099 + .name = "AR2315-MISC",
2100 + .irq_unmask = ar2315_misc_irq_unmask,
2101 + .irq_mask = ar2315_misc_irq_mask,
2102 +};
2103 +
2104 +static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id)
2105 +{
2106 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2107 + ar231x_read_reg(AR2315_AHB_ERR1);
2108 +
2109 + pr_emerg("AHB fatal error\n");
2110 + machine_restart("AHB error"); /* Catastrophic failure */
2111 +
2112 + return IRQ_HANDLED;
2113 +}
2114 +
2115 +static struct irqaction ar2315_ahb_proc_interrupt = {
2116 + .handler = ar2315_ahb_proc_handler,
2117 + .name = "ar2315_ahb_proc_interrupt",
2118 +};
2119 +
2120 +void
2121 +ar2315_irq_init(void)
2122 +{
2123 + int i;
2124 +
2125 + if (!is_2315())
2126 + return;
2127 +
2128 + ar231x_irq_dispatch = ar2315_irq_dispatch;
2129 + for (i = 0; i < AR2315_MISC_IRQ_COUNT; i++) {
2130 + int irq = AR231X_MISC_IRQ_BASE + i;
2131 +
2132 + irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip,
2133 + handle_level_irq);
2134 + }
2135 + setup_irq(AR2315_MISC_IRQ_AHB, &ar2315_ahb_proc_interrupt);
2136 + irq_set_chained_handler(AR2315_IRQ_MISC_INTRS, ar2315_misc_irq_handler);
2137 +}
2138 +
2139 +static void ar2315_device_reset_set(u32 mask)
2140 +{
2141 + u32 val;
2142 +
2143 + val = ar231x_read_reg(AR2315_RESET);
2144 + ar231x_write_reg(AR2315_RESET, val | mask);
2145 +}
2146 +
2147 +static void ar2315_device_reset_clear(u32 mask)
2148 +{
2149 + u32 val;
2150 +
2151 + val = ar231x_read_reg(AR2315_RESET);
2152 + ar231x_write_reg(AR2315_RESET, val & ~mask);
2153 +}
2154 +
2155 +static struct ar231x_eth ar2315_eth_data = {
2156 + .reset_set = ar2315_device_reset_set,
2157 + .reset_clear = ar2315_device_reset_clear,
2158 + .reset_mac = AR2315_RESET_ENET0,
2159 + .reset_phy = AR2315_RESET_EPHY0,
2160 + .config = &ar231x_board,
2161 +};
2162 +
2163 +static struct resource ar2315_spiflash_res[] = {
2164 + {
2165 + .name = "spiflash_read",
2166 + .flags = IORESOURCE_MEM,
2167 + .start = AR2315_SPI_READ,
2168 + .end = AR2315_SPI_READ + 0x1000000 - 1,
2169 + },
2170 + {
2171 + .name = "spiflash_mmr",
2172 + .flags = IORESOURCE_MEM,
2173 + .start = AR2315_SPI_MMR,
2174 + .end = AR2315_SPI_MMR + 12 - 1,
2175 + },
2176 +};
2177 +
2178 +static struct platform_device ar2315_spiflash = {
2179 + .id = 0,
2180 + .name = "ar2315-spiflash",
2181 + .resource = ar2315_spiflash_res,
2182 + .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
2183 +};
2184 +
2185 +static struct resource ar2315_wdt_res[] = {
2186 + {
2187 + .flags = IORESOURCE_MEM,
2188 + .start = AR2315_WD,
2189 + .end = AR2315_WD + 8 - 1,
2190 + },
2191 + {
2192 + .flags = IORESOURCE_IRQ,
2193 + .start = AR2315_MISC_IRQ_WATCHDOG,
2194 + .end = AR2315_MISC_IRQ_WATCHDOG,
2195 + }
2196 +};
2197 +
2198 +static struct platform_device ar2315_wdt = {
2199 + .id = 0,
2200 + .name = "ar2315-wdt",
2201 + .resource = ar2315_wdt_res,
2202 + .num_resources = ARRAY_SIZE(ar2315_wdt_res)
2203 +};
2204 +
2205 +/*
2206 + * NB: We use mapping size that is larger than the actual flash size,
2207 + * but this shouldn't be a problem here, because the flash will simply
2208 + * be mapped multiple times.
2209 + */
2210 +static u8 __init *ar2315_flash_limit(void)
2211 +{
2212 + return (u8 *)KSEG1ADDR(ar2315_spiflash_res[0].end + 1);
2213 +}
2214 +
2215 +#ifdef CONFIG_LEDS_GPIO
2216 +static struct gpio_led ar2315_leds[6];
2217 +static struct gpio_led_platform_data ar2315_led_data = {
2218 + .leds = (void *)ar2315_leds,
2219 +};
2220 +
2221 +static struct platform_device ar2315_gpio_leds = {
2222 + .name = "leds-gpio",
2223 + .id = -1,
2224 + .dev = {
2225 + .platform_data = (void *)&ar2315_led_data,
2226 + }
2227 +};
2228 +
2229 +static void __init
2230 +ar2315_init_gpio_leds(void)
2231 +{
2232 + static char led_names[6][6];
2233 + int i, led = 0;
2234 +
2235 + ar2315_led_data.num_leds = 0;
2236 + for (i = 1; i < 8; i++) {
2237 + if ((i == AR2315_RESET_GPIO) ||
2238 + (i == ar231x_board.config->reset_config_gpio))
2239 + continue;
2240 +
2241 + if (i == ar231x_board.config->sys_led_gpio)
2242 + strcpy(led_names[led], "wlan");
2243 + else
2244 + sprintf(led_names[led], "gpio%d", i);
2245 +
2246 + ar2315_leds[led].name = led_names[led];
2247 + ar2315_leds[led].gpio = i;
2248 + ar2315_leds[led].active_low = 0;
2249 + led++;
2250 + }
2251 + ar2315_led_data.num_leds = led;
2252 + platform_device_register(&ar2315_gpio_leds);
2253 +}
2254 +#else
2255 +static inline void ar2315_init_gpio_leds(void)
2256 +{
2257 +}
2258 +#endif
2259 +
2260 +int __init
2261 +ar2315_init_devices(void)
2262 +{
2263 + if (!is_2315())
2264 + return 0;
2265 +
2266 + /* Find board configuration */
2267 + ar231x_find_config(ar2315_flash_limit());
2268 + ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac;
2269 +
2270 + ar2315_init_gpio_leds();
2271 + platform_device_register(&ar2315_wdt);
2272 + platform_device_register(&ar2315_spiflash);
2273 + ar231x_add_ethernet(0, AR2315_ENET0, "eth0_mii", AR2315_ENET0_MII,
2274 + AR2315_IRQ_ENET0_INTRS, &ar2315_eth_data);
2275 + ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
2276 +
2277 + return 0;
2278 +}
2279 +
2280 +static void
2281 +ar2315_restart(char *command)
2282 +{
2283 + void (*mips_reset_vec)(void) = (void *)0xbfc00000;
2284 +
2285 + local_irq_disable();
2286 +
2287 + /* try reset the system via reset control */
2288 + ar231x_write_reg(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
2289 +
2290 + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
2291 + * a workaround. Give it some time to attempt a gpio based hardware
2292 + * reset (atheros reference design workaround) */
2293 + gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset");
2294 + mdelay(100);
2295 +
2296 + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
2297 + * workaround. Attempt to jump to the mips reset location -
2298 + * the boot loader itself might be able to recover the system */
2299 + mips_reset_vec();
2300 +}
2301 +
2302 +/*
2303 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2304 + * to determine the predevisor value.
2305 + */
2306 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
2307 +static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
2308 +
2309 +static unsigned int __init
2310 +ar2315_sys_clk(unsigned int clock_ctl)
2311 +{
2312 + unsigned int pllc_ctrl, cpu_div;
2313 + unsigned int pllc_out, refdiv, fdiv, divby2;
2314 + unsigned int clk_div;
2315 +
2316 + pllc_ctrl = ar231x_read_reg(AR2315_PLLC_CTL);
2317 + refdiv = (pllc_ctrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
2318 + refdiv = clockctl1_predivide_table[refdiv];
2319 + fdiv = (pllc_ctrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
2320 + divby2 = (pllc_ctrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
2321 + divby2 += 1;
2322 + pllc_out = (40000000/refdiv)*(2*divby2)*fdiv;
2323 +
2324 + /* clkm input selected */
2325 + switch (clock_ctl & CPUCLK_CLK_SEL_M) {
2326 + case 0:
2327 + case 1:
2328 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKM_DIV_M) >>
2329 + PLLC_CLKM_DIV_S];
2330 + break;
2331 + case 2:
2332 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKC_DIV_M) >>
2333 + PLLC_CLKC_DIV_S];
2334 + break;
2335 + default:
2336 + pllc_out = 40000000;
2337 + clk_div = 1;
2338 + break;
2339 + }
2340 +
2341 + cpu_div = (clock_ctl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
2342 + cpu_div = cpu_div * 2 ?: 1;
2343 +
2344 + return pllc_out / (clk_div * cpu_div);
2345 +}
2346 +
2347 +static inline unsigned int
2348 +ar2315_cpu_frequency(void)
2349 +{
2350 + return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
2351 +}
2352 +
2353 +static inline unsigned int
2354 +ar2315_apb_frequency(void)
2355 +{
2356 + return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
2357 +}
2358 +
2359 +void __init
2360 +ar2315_time_init(void)
2361 +{
2362 + if (!is_2315())
2363 + return;
2364 +
2365 + mips_hpt_frequency = ar2315_cpu_frequency() / 2;
2366 +}
2367 +
2368 +void __init
2369 +ar2315_prom_init(void)
2370 +{
2371 + u32 memsize, memcfg, devid;
2372 +
2373 + if (!is_2315())
2374 + return;
2375 +
2376 + memcfg = ar231x_read_reg(AR2315_MEM_CFG);
2377 + memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
2378 + memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
2379 + memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
2380 + memsize <<= 3;
2381 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2382 +
2383 + /* Detect the hardware based on the device ID */
2384 + devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP;
2385 + switch (devid) {
2386 + case 0x91: /* Need to check */
2387 + ar231x_devtype = DEV_TYPE_AR2318;
2388 + break;
2389 + case 0x90:
2390 + ar231x_devtype = DEV_TYPE_AR2317;
2391 + break;
2392 + case 0x87:
2393 + ar231x_devtype = DEV_TYPE_AR2316;
2394 + break;
2395 + case 0x86:
2396 + default:
2397 + ar231x_devtype = DEV_TYPE_AR2315;
2398 + break;
2399 + }
2400 + ar231x_board.devid = devid;
2401 +}
2402 +
2403 +void __init
2404 +ar2315_plat_setup(void)
2405 +{
2406 + u32 config;
2407 +
2408 + if (!is_2315())
2409 + return;
2410 +
2411 + /* Clear any lingering AHB errors */
2412 + config = read_c0_config();
2413 + write_c0_config(config & ~0x3);
2414 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2415 + ar231x_read_reg(AR2315_AHB_ERR1);
2416 + ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
2417 +
2418 + _machine_restart = ar2315_restart;
2419 + ar231x_serial_setup(AR2315_UART0, AR2315_MISC_IRQ_UART0,
2420 + ar2315_apb_frequency());
2421 +}
2422 --- /dev/null
2423 +++ b/arch/mips/ar231x/ar2315.h
2424 @@ -0,0 +1,37 @@
2425 +#ifndef __AR2315_H
2426 +#define __AR2315_H
2427 +
2428 +#ifdef CONFIG_SOC_AR2315
2429 +
2430 +void ar2315_irq_init(void);
2431 +int ar2315_init_devices(void);
2432 +void ar2315_prom_init(void);
2433 +void ar2315_plat_setup(void);
2434 +void ar2315_time_init(void);
2435 +
2436 +#else
2437 +
2438 +static inline void ar2315_irq_init(void)
2439 +{
2440 +}
2441 +
2442 +static inline int ar2315_init_devices(void)
2443 +{
2444 + return 0;
2445 +}
2446 +
2447 +static inline void ar2315_prom_init(void)
2448 +{
2449 +}
2450 +
2451 +static inline void ar2315_plat_setup(void)
2452 +{
2453 +}
2454 +
2455 +static inline void ar2315_time_init(void)
2456 +{
2457 +}
2458 +
2459 +#endif
2460 +
2461 +#endif
2462 --- /dev/null
2463 +++ b/arch/mips/ar231x/ar5312.h
2464 @@ -0,0 +1,37 @@
2465 +#ifndef __AR5312_H
2466 +#define __AR5312_H
2467 +
2468 +#ifdef CONFIG_SOC_AR5312
2469 +
2470 +void ar5312_irq_init(void);
2471 +int ar5312_init_devices(void);
2472 +void ar5312_prom_init(void);
2473 +void ar5312_plat_setup(void);
2474 +void ar5312_time_init(void);
2475 +
2476 +#else
2477 +
2478 +static inline void ar5312_irq_init(void)
2479 +{
2480 +}
2481 +
2482 +static inline int ar5312_init_devices(void)
2483 +{
2484 + return 0;
2485 +}
2486 +
2487 +static inline void ar5312_prom_init(void)
2488 +{
2489 +}
2490 +
2491 +static inline void ar5312_plat_setup(void)
2492 +{
2493 +}
2494 +
2495 +static inline void ar5312_time_init(void)
2496 +{
2497 +}
2498 +
2499 +#endif
2500 +
2501 +#endif
2502 --- /dev/null
2503 +++ b/arch/mips/include/asm/mach-ar231x/ar231x.h
2504 @@ -0,0 +1,38 @@
2505 +#ifndef __ASM_MACH_AR231X_H
2506 +#define __ASM_MACH_AR231X_H
2507 +
2508 +#include <linux/types.h>
2509 +#include <linux/io.h>
2510 +
2511 +#define AR231X_MISC_IRQ_BASE 0x20
2512 +#define AR231X_GPIO_IRQ_BASE 0x30
2513 +
2514 +/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
2515 +#define AR231X_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE+7) /* C0_CAUSE: 0x8000 */
2516 +
2517 +static inline u32
2518 +ar231x_read_reg(u32 reg)
2519 +{
2520 + return __raw_readl((void __iomem *)KSEG1ADDR(reg));
2521 +}
2522 +
2523 +static inline void
2524 +ar231x_write_reg(u32 reg, u32 val)
2525 +{
2526 + __raw_writel(val, (void __iomem *)KSEG1ADDR(reg));
2527 +}
2528 +
2529 +static inline u32
2530 +ar231x_mask_reg(u32 reg, u32 mask, u32 val)
2531 +{
2532 + u32 ret;
2533 +
2534 + ret = ar231x_read_reg(reg);
2535 + ret &= ~mask;
2536 + ret |= val;
2537 + ar231x_write_reg(reg, ret);
2538 +
2539 + return ret;
2540 +}
2541 +
2542 +#endif /* __ASM_MACH_AR231X_H */
2543 --- /dev/null
2544 +++ b/arch/mips/ar231x/devices.h
2545 @@ -0,0 +1,39 @@
2546 +#ifndef __AR231X_DEVICES_H
2547 +#define __AR231X_DEVICES_H
2548 +
2549 +enum {
2550 + /* handled by ar5312.c */
2551 + DEV_TYPE_AR2312,
2552 + DEV_TYPE_AR2313,
2553 + DEV_TYPE_AR5312,
2554 +
2555 + /* handled by ar2315.c */
2556 + DEV_TYPE_AR2315,
2557 + DEV_TYPE_AR2316,
2558 + DEV_TYPE_AR2317,
2559 + DEV_TYPE_AR2318,
2560 +
2561 + DEV_TYPE_UNKNOWN
2562 +};
2563 +
2564 +extern int ar231x_devtype;
2565 +extern struct ar231x_board_config ar231x_board;
2566 +extern asmlinkage void (*ar231x_irq_dispatch)(void);
2567 +
2568 +int ar231x_find_config(u8 *flash_limit);
2569 +void ar231x_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
2570 +int ar231x_add_wmac(int nr, u32 base, int irq);
2571 +int ar231x_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
2572 + int irq, void *pdata);
2573 +
2574 +static inline bool is_2315(void)
2575 +{
2576 + return (current_cpu_data.cputype == CPU_4KEC);
2577 +}
2578 +
2579 +static inline bool is_5312(void)
2580 +{
2581 + return !is_2315();
2582 +}
2583 +
2584 +#endif
2585 --- /dev/null
2586 +++ b/arch/mips/ar231x/devices.c
2587 @@ -0,0 +1,181 @@
2588 +#include <linux/kernel.h>
2589 +#include <linux/init.h>
2590 +#include <linux/serial.h>
2591 +#include <linux/serial_core.h>
2592 +#include <linux/serial_8250.h>
2593 +#include <linux/platform_device.h>
2594 +#include <asm/bootinfo.h>
2595 +
2596 +#include <ar231x_platform.h>
2597 +#include <ar231x.h>
2598 +#include "devices.h"
2599 +#include "ar5312.h"
2600 +#include "ar2315.h"
2601 +
2602 +struct ar231x_board_config ar231x_board;
2603 +int ar231x_devtype = DEV_TYPE_UNKNOWN;
2604 +
2605 +static struct resource ar231x_eth0_res[] = {
2606 + {
2607 + .name = "eth0_membase",
2608 + .flags = IORESOURCE_MEM,
2609 + },
2610 + {
2611 + .name = "eth0_mii",
2612 + .flags = IORESOURCE_MEM,
2613 + },
2614 + {
2615 + .name = "eth0_irq",
2616 + .flags = IORESOURCE_IRQ,
2617 + }
2618 +};
2619 +
2620 +static struct resource ar231x_eth1_res[] = {
2621 + {
2622 + .name = "eth1_membase",
2623 + .flags = IORESOURCE_MEM,
2624 + },
2625 + {
2626 + .name = "eth1_mii",
2627 + .flags = IORESOURCE_MEM,
2628 + },
2629 + {
2630 + .name = "eth1_irq",
2631 + .flags = IORESOURCE_IRQ,
2632 + }
2633 +};
2634 +
2635 +static struct platform_device ar231x_eth[] = {
2636 + {
2637 + .id = 0,
2638 + .name = "ar231x-eth",
2639 + .resource = ar231x_eth0_res,
2640 + .num_resources = ARRAY_SIZE(ar231x_eth0_res)
2641 + },
2642 + {
2643 + .id = 1,
2644 + .name = "ar231x-eth",
2645 + .resource = ar231x_eth1_res,
2646 + .num_resources = ARRAY_SIZE(ar231x_eth1_res)
2647 + }
2648 +};
2649 +
2650 +static struct resource ar231x_wmac0_res[] = {
2651 + {
2652 + .name = "wmac0_membase",
2653 + .flags = IORESOURCE_MEM,
2654 + },
2655 + {
2656 + .name = "wmac0_irq",
2657 + .flags = IORESOURCE_IRQ,
2658 + }
2659 +};
2660 +
2661 +static struct resource ar231x_wmac1_res[] = {
2662 + {
2663 + .name = "wmac1_membase",
2664 + .flags = IORESOURCE_MEM,
2665 + },
2666 + {
2667 + .name = "wmac1_irq",
2668 + .flags = IORESOURCE_IRQ,
2669 + }
2670 +};
2671 +
2672 +static struct platform_device ar231x_wmac[] = {
2673 + {
2674 + .id = 0,
2675 + .name = "ar231x-wmac",
2676 + .resource = ar231x_wmac0_res,
2677 + .num_resources = ARRAY_SIZE(ar231x_wmac0_res),
2678 + .dev.platform_data = &ar231x_board,
2679 + },
2680 + {
2681 + .id = 1,
2682 + .name = "ar231x-wmac",
2683 + .resource = ar231x_wmac1_res,
2684 + .num_resources = ARRAY_SIZE(ar231x_wmac1_res),
2685 + .dev.platform_data = &ar231x_board,
2686 + },
2687 +};
2688 +
2689 +static const char * const devtype_strings[] = {
2690 + [DEV_TYPE_AR5312] = "Atheros AR5312",
2691 + [DEV_TYPE_AR2312] = "Atheros AR2312",
2692 + [DEV_TYPE_AR2313] = "Atheros AR2313",
2693 + [DEV_TYPE_AR2315] = "Atheros AR2315",
2694 + [DEV_TYPE_AR2316] = "Atheros AR2316",
2695 + [DEV_TYPE_AR2317] = "Atheros AR2317",
2696 + [DEV_TYPE_AR2318] = "Atheros AR2318",
2697 + [DEV_TYPE_UNKNOWN] = "Atheros (unknown)",
2698 +};
2699 +
2700 +const char *get_system_type(void)
2701 +{
2702 + if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) ||
2703 + !devtype_strings[ar231x_devtype])
2704 + return devtype_strings[DEV_TYPE_UNKNOWN];
2705 + return devtype_strings[ar231x_devtype];
2706 +}
2707 +
2708 +int __init
2709 +ar231x_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
2710 + int irq, void *pdata)
2711 +{
2712 + struct resource *res;
2713 +
2714 + ar231x_eth[nr].dev.platform_data = pdata;
2715 + res = &ar231x_eth[nr].resource[0];
2716 + res->start = base;
2717 + res->end = base + 0x2000 - 1;
2718 + res++;
2719 + res->name = mii_name;
2720 + res->start = mii_base;
2721 + res->end = mii_base + 8 - 1;
2722 + res++;
2723 + res->start = irq;
2724 + res->end = irq;
2725 + return platform_device_register(&ar231x_eth[nr]);
2726 +}
2727 +
2728 +void __init
2729 +ar231x_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
2730 +{
2731 + struct uart_port s;
2732 +
2733 + memset(&s, 0, sizeof(s));
2734 +
2735 + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
2736 + s.iotype = UPIO_MEM32;
2737 + s.irq = irq;
2738 + s.regshift = 2;
2739 + s.mapbase = mapbase;
2740 + s.uartclk = uartclk;
2741 +
2742 + early_serial_setup(&s);
2743 +}
2744 +
2745 +int __init
2746 +ar231x_add_wmac(int nr, u32 base, int irq)
2747 +{
2748 + struct resource *res;
2749 +
2750 + ar231x_wmac[nr].dev.platform_data = &ar231x_board;
2751 + res = &ar231x_wmac[nr].resource[0];
2752 + res->start = base;
2753 + res->end = base + 0x10000 - 1;
2754 + res++;
2755 + res->start = irq;
2756 + res->end = irq;
2757 + return platform_device_register(&ar231x_wmac[nr]);
2758 +}
2759 +
2760 +static int __init ar231x_register_devices(void)
2761 +{
2762 + ar5312_init_devices();
2763 + ar2315_init_devices();
2764 +
2765 + return 0;
2766 +}
2767 +
2768 +device_initcall(ar231x_register_devices);
OpenWrt Source Repository