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atheros: v3.18: cleanup register headers
[openwrt/openwrt.git] / target / linux / atheros / patches-3.18 / 100-board.patch
1 --- a/arch/mips/Kconfig
2 +++ b/arch/mips/Kconfig
3 @@ -96,6 +96,19 @@ config AR7
4 Support for the Texas Instruments AR7 System-on-a-Chip
5 family: TNETD7100, 7200 and 7300.
6
7 +config ATH25
8 + bool "Atheros 231x/531x SoC support"
9 + select CEVT_R4K
10 + select CSRC_R4K
11 + select DMA_NONCOHERENT
12 + select IRQ_CPU
13 + select SYS_HAS_CPU_MIPS32_R1
14 + select SYS_SUPPORTS_BIG_ENDIAN
15 + select SYS_SUPPORTS_32BIT_KERNEL
16 + select ARCH_REQUIRE_GPIOLIB
17 + help
18 + Support for AR231x and AR531x based boards
19 +
20 config ATH79
21 bool "Atheros AR71XX/AR724X/AR913X based boards"
22 select ARCH_REQUIRE_GPIOLIB
23 @@ -834,6 +847,7 @@ config MIPS_PARAVIRT
24
25 endchoice
26
27 +source "arch/mips/ath25/Kconfig"
28 source "arch/mips/alchemy/Kconfig"
29 source "arch/mips/ath79/Kconfig"
30 source "arch/mips/bcm47xx/Kconfig"
31 --- a/arch/mips/Kbuild.platforms
32 +++ b/arch/mips/Kbuild.platforms
33 @@ -2,6 +2,7 @@
34
35 platforms += alchemy
36 platforms += ar7
37 +platforms += ath25
38 platforms += ath79
39 platforms += bcm47xx
40 platforms += bcm63xx
41 --- /dev/null
42 +++ b/arch/mips/ath25/Platform
43 @@ -0,0 +1,6 @@
44 +#
45 +# Atheros AR531X/AR231X WiSoC
46 +#
47 +platform-$(CONFIG_ATH25) += ath25/
48 +cflags-$(CONFIG_ATH25) += -I$(srctree)/arch/mips/include/asm/mach-ath25
49 +load-$(CONFIG_ATH25) += 0xffffffff80041000
50 --- /dev/null
51 +++ b/arch/mips/ath25/Kconfig
52 @@ -0,0 +1,9 @@
53 +config SOC_AR5312
54 + bool "Atheros 5312/2312+ support"
55 + depends on ATH25
56 + default y
57 +
58 +config SOC_AR2315
59 + bool "Atheros 2315+ support"
60 + depends on ATH25
61 + default y
62 --- /dev/null
63 +++ b/arch/mips/ath25/Makefile
64 @@ -0,0 +1,13 @@
65 +#
66 +# This file is subject to the terms and conditions of the GNU General Public
67 +# License. See the file "COPYING" in the main directory of this archive
68 +# for more details.
69 +#
70 +# Copyright (C) 2006 FON Technology, SL.
71 +# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
72 +# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
73 +#
74 +
75 +obj-y += board.o prom.o devices.o
76 +obj-$(CONFIG_SOC_AR5312) += ar5312.o
77 +obj-$(CONFIG_SOC_AR2315) += ar2315.o
78 --- /dev/null
79 +++ b/arch/mips/ath25/board.c
80 @@ -0,0 +1,234 @@
81 +/*
82 + * This file is subject to the terms and conditions of the GNU General Public
83 + * License. See the file "COPYING" in the main directory of this archive
84 + * for more details.
85 + *
86 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
87 + * Copyright (C) 2006 FON Technology, SL.
88 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
89 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
90 + */
91 +
92 +#include <generated/autoconf.h>
93 +#include <linux/init.h>
94 +#include <linux/module.h>
95 +#include <linux/types.h>
96 +#include <linux/string.h>
97 +#include <linux/platform_device.h>
98 +#include <linux/kernel.h>
99 +#include <linux/random.h>
100 +#include <linux/etherdevice.h>
101 +#include <linux/irq.h>
102 +#include <linux/io.h>
103 +#include <asm/irq_cpu.h>
104 +#include <asm/reboot.h>
105 +#include <asm/bootinfo.h>
106 +#include <asm/time.h>
107 +
108 +#include <ath25_platform.h>
109 +#include "devices.h"
110 +#include "ar5312.h"
111 +#include "ar2315.h"
112 +
113 +void (*ath25_irq_dispatch)(void);
114 +
115 +static inline bool check_radio_magic(u8 *addr)
116 +{
117 + addr += 0x7a; /* offset for flash magic */
118 + return (addr[0] == 0x5a) && (addr[1] == 0xa5);
119 +}
120 +
121 +static inline bool check_notempty(u8 *addr)
122 +{
123 + return *(u32 *)addr != 0xffffffff;
124 +}
125 +
126 +static inline bool check_board_data(u8 *flash_limit, u8 *addr, bool broken)
127 +{
128 + /* config magic found */
129 + if (*((u32 *)addr) == ATH25_BD_MAGIC)
130 + return true;
131 +
132 + if (!broken)
133 + return false;
134 +
135 + if (check_radio_magic(addr + 0xf8))
136 + ath25_board.radio = addr + 0xf8;
137 + if ((addr < flash_limit + 0x10000) &&
138 + check_radio_magic(addr + 0x10000))
139 + ath25_board.radio = addr + 0x10000;
140 +
141 + if (ath25_board.radio) {
142 + /* broken board data detected, use radio data to find the
143 + * offset, user will fix this */
144 + return true;
145 + }
146 +
147 + return false;
148 +}
149 +
150 +static u8 * __init find_board_config(u8 *flash_limit, bool broken)
151 +{
152 + u8 *addr;
153 + u8 *begin = flash_limit - 0x1000;
154 + u8 *end = flash_limit - 0x30000;
155 +
156 + for (addr = begin; addr >= end; addr -= 0x1000)
157 + if (check_board_data(flash_limit, addr, broken))
158 + return addr;
159 +
160 + return NULL;
161 +}
162 +
163 +static u8 * __init find_radio_config(u8 *flash_limit, u8 *bcfg)
164 +{
165 + u8 *rcfg, *begin, *end;
166 +
167 + /*
168 + * Now find the start of Radio Configuration data, using heuristics:
169 + * Search forward from Board Configuration data by 0x1000 bytes
170 + * at a time until we find non-0xffffffff.
171 + */
172 + begin = bcfg + 0x1000;
173 + end = flash_limit;
174 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
175 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
176 + return rcfg;
177 +
178 + /* AR2316 relocates radio config to new location */
179 + begin = bcfg + 0xf8;
180 + end = flash_limit - 0x1000 + 0xf8;
181 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
182 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
183 + return rcfg;
184 +
185 + pr_warn("WARNING: Could not find Radio Configuration data\n");
186 +
187 + return NULL;
188 +}
189 +
190 +int __init ath25_find_config(u8 *flash_limit)
191 +{
192 + struct ath25_boarddata *config;
193 + unsigned int rcfg_size;
194 + int broken_boarddata = 0;
195 + u8 *bcfg, *rcfg;
196 + u8 *board_data;
197 + u8 *radio_data;
198 + u8 *mac_addr;
199 + u32 offset;
200 +
201 + ath25_board.config = NULL;
202 + ath25_board.radio = NULL;
203 + /* Copy the board and radio data to RAM, because accessing the mapped
204 + * memory of the flash directly after booting is not safe */
205 +
206 + /* Try to find valid board and radio data */
207 + bcfg = find_board_config(flash_limit, false);
208 +
209 + /* If that fails, try to at least find valid radio data */
210 + if (!bcfg) {
211 + bcfg = find_board_config(flash_limit, true);
212 + broken_boarddata = 1;
213 + }
214 +
215 + if (!bcfg) {
216 + pr_warn("WARNING: No board configuration data found!\n");
217 + return -ENODEV;
218 + }
219 +
220 + board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
221 + ath25_board.config = (struct ath25_boarddata *)board_data;
222 + memcpy(board_data, bcfg, 0x100);
223 + if (broken_boarddata) {
224 + pr_warn("WARNING: broken board data detected\n");
225 + config = ath25_board.config;
226 + if (is_zero_ether_addr(config->enet0_mac)) {
227 + pr_info("Fixing up empty mac addresses\n");
228 + config->reset_config_gpio = 0xffff;
229 + config->sys_led_gpio = 0xffff;
230 + random_ether_addr(config->wlan0_mac);
231 + config->wlan0_mac[0] &= ~0x06;
232 + random_ether_addr(config->enet0_mac);
233 + random_ether_addr(config->enet1_mac);
234 + }
235 + }
236 +
237 + /* Radio config starts 0x100 bytes after board config, regardless
238 + * of what the physical layout on the flash chip looks like */
239 +
240 + if (ath25_board.radio)
241 + rcfg = (u8 *)ath25_board.radio;
242 + else
243 + rcfg = find_radio_config(flash_limit, bcfg);
244 +
245 + if (!rcfg)
246 + return -ENODEV;
247 +
248 + radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
249 + ath25_board.radio = radio_data;
250 + offset = radio_data - board_data;
251 + pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
252 + offset);
253 + rcfg_size = BOARD_CONFIG_BUFSZ - offset;
254 + memcpy(radio_data, rcfg, rcfg_size);
255 +
256 + mac_addr = &radio_data[0x1d * 2];
257 + if (is_broadcast_ether_addr(mac_addr)) {
258 + pr_info("Radio MAC is blank; using board-data\n");
259 + ether_addr_copy(mac_addr, ath25_board.config->wlan0_mac);
260 + }
261 +
262 + return 0;
263 +}
264 +
265 +static void ath25_halt(void)
266 +{
267 + local_irq_disable();
268 + while (1)
269 + ;
270 +}
271 +
272 +void __init plat_mem_setup(void)
273 +{
274 + _machine_halt = ath25_halt;
275 + pm_power_off = ath25_halt;
276 +
277 + if (is_ar5312())
278 + ar5312_plat_mem_setup();
279 + else
280 + ar2315_plat_mem_setup();
281 +
282 + /* Disable data watchpoints */
283 + write_c0_watchlo0(0);
284 +}
285 +
286 +asmlinkage void plat_irq_dispatch(void)
287 +{
288 + ath25_irq_dispatch();
289 +}
290 +
291 +void __init plat_time_init(void)
292 +{
293 + if (is_ar5312())
294 + ar5312_plat_time_init();
295 + else
296 + ar2315_plat_time_init();
297 +}
298 +
299 +unsigned int __cpuinit get_c0_compare_int(void)
300 +{
301 + return CP0_LEGACY_COMPARE_IRQ;
302 +}
303 +
304 +void __init arch_init_irq(void)
305 +{
306 + clear_c0_status(ST0_IM);
307 + mips_cpu_irq_init();
308 +
309 + /* Initialize interrupt controllers */
310 + if (is_ar5312())
311 + ar5312_arch_init_irq();
312 + else
313 + ar2315_arch_init_irq();
314 +}
315 --- /dev/null
316 +++ b/arch/mips/ath25/prom.c
317 @@ -0,0 +1,26 @@
318 +/*
319 + * This file is subject to the terms and conditions of the GNU General Public
320 + * License. See the file "COPYING" in the main directory of this archive
321 + * for more details.
322 + *
323 + * Copyright MontaVista Software Inc
324 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
325 + * Copyright (C) 2006 FON Technology, SL.
326 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
327 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
328 + */
329 +
330 +/*
331 + * Prom setup file for ar231x
332 + */
333 +
334 +#include <linux/init.h>
335 +#include <asm/bootinfo.h>
336 +
337 +void __init prom_init(void)
338 +{
339 +}
340 +
341 +void __init prom_free_prom_memory(void)
342 +{
343 +}
344 --- /dev/null
345 +++ b/arch/mips/include/asm/mach-ath25/ath25_platform.h
346 @@ -0,0 +1,84 @@
347 +#ifndef __ASM_MACH_ATH25_PLATFORM_H
348 +#define __ASM_MACH_ATH25_PLATFORM_H
349 +
350 +#include <linux/etherdevice.h>
351 +
352 +/*
353 + * This is board-specific data that is stored in a "fixed" location in flash.
354 + * It is shared across operating systems, so it should not be changed lightly.
355 + * The main reason we need it is in order to extract the ethernet MAC
356 + * address(es).
357 + */
358 +struct ath25_boarddata {
359 + u32 magic; /* board data is valid */
360 +#define ATH25_BD_MAGIC 0x35333131 /* "5311", for all 531x/231x platforms */
361 + u16 cksum; /* checksum (starting with BD_REV 2) */
362 + u16 rev; /* revision of this struct */
363 +#define BD_REV 4
364 + char board_name[64]; /* Name of board */
365 + u16 major; /* Board major number */
366 + u16 minor; /* Board minor number */
367 + u32 flags; /* Board configuration */
368 +#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
369 +#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
370 +#define BD_UART1 0x00000004 /* UART1 is stuffed */
371 +#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
372 +#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
373 +#define BD_SYSLED 0x00000020 /* System LED stuffed */
374 +#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
375 +#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
376 +#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
377 +#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
378 +#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ mem_cap for testing */
379 +#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
380 +#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
381 +#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
382 +#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
383 +#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
384 +#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
385 +#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
386 + u16 reset_config_gpio; /* Reset factory GPIO pin */
387 + u16 sys_led_gpio; /* System LED GPIO pin */
388 +
389 + u32 cpu_freq; /* CPU core frequency in Hz */
390 + u32 sys_freq; /* System frequency in Hz */
391 + u32 cnt_freq; /* Calculated C0_COUNT frequency */
392 +
393 + u8 wlan0_mac[ETH_ALEN];
394 + u8 enet0_mac[ETH_ALEN];
395 + u8 enet1_mac[ETH_ALEN];
396 +
397 + u16 pci_id; /* Pseudo PCIID for common code */
398 + u16 mem_cap; /* cap bank1 in MB */
399 +
400 + /* version 3 */
401 + u8 wlan1_mac[ETH_ALEN]; /* (ar5212) */
402 +};
403 +
404 +#define BOARD_CONFIG_BUFSZ 0x1000
405 +
406 +/*
407 + * Platform device information for the Wireless MAC
408 + */
409 +struct ar231x_board_config {
410 + u16 devid;
411 +
412 + /* board config data */
413 + struct ath25_boarddata *config;
414 +
415 + /* radio calibration data */
416 + const char *radio;
417 +};
418 +
419 +/*
420 + * Platform device information for the Ethernet MAC
421 + */
422 +struct ar231x_eth {
423 + void (*reset_set)(u32);
424 + void (*reset_clear)(u32);
425 + u32 reset_mac;
426 + u32 reset_phy;
427 + char *macaddr;
428 +};
429 +
430 +#endif /* __ASM_MACH_ATH25_PLATFORM_H */
431 --- /dev/null
432 +++ b/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
433 @@ -0,0 +1,64 @@
434 +/*
435 + * Atheros AR231x/AR531x SoC specific CPU feature overrides
436 + *
437 + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
438 + *
439 + * This file was derived from: include/asm-mips/cpu-features.h
440 + * Copyright (C) 2003, 2004 Ralf Baechle
441 + * Copyright (C) 2004 Maciej W. Rozycki
442 + *
443 + * This program is free software; you can redistribute it and/or modify it
444 + * under the terms of the GNU General Public License version 2 as published
445 + * by the Free Software Foundation.
446 + *
447 + */
448 +#ifndef __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
449 +#define __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
450 +
451 +/*
452 + * The Atheros AR531x/AR231x SoCs have MIPS 4Kc/4KEc core.
453 + */
454 +#define cpu_has_tlb 1
455 +#define cpu_has_4kex 1
456 +#define cpu_has_3k_cache 0
457 +#define cpu_has_4k_cache 1
458 +#define cpu_has_tx39_cache 0
459 +#define cpu_has_sb1_cache 0
460 +#define cpu_has_fpu 0
461 +#define cpu_has_32fpr 0
462 +#define cpu_has_counter 1
463 +#define cpu_has_ejtag 1
464 +
465 +#if !defined(CONFIG_SOC_AR5312)
466 +# define cpu_has_llsc 1
467 +#else
468 +/*
469 + * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
470 + * ll/sc instructions.
471 + */
472 +# define cpu_has_llsc 0
473 +#endif
474 +
475 +#define cpu_has_mips16 0
476 +#define cpu_has_mdmx 0
477 +#define cpu_has_mips3d 0
478 +#define cpu_has_smartmips 0
479 +
480 +#define cpu_has_mips32r1 1
481 +
482 +#if !defined(CONFIG_SOC_AR5312)
483 +# define cpu_has_mips32r2 1
484 +#endif
485 +
486 +#define cpu_has_mips64r1 0
487 +#define cpu_has_mips64r2 0
488 +
489 +#define cpu_has_dsp 0
490 +#define cpu_has_mipsmt 0
491 +
492 +#define cpu_has_64bits 0
493 +#define cpu_has_64bit_zero_reg 0
494 +#define cpu_has_64bit_gp_regs 0
495 +#define cpu_has_64bit_addresses 0
496 +
497 +#endif /* __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H */
498 --- /dev/null
499 +++ b/arch/mips/include/asm/mach-ath25/dma-coherence.h
500 @@ -0,0 +1,82 @@
501 +/*
502 + * This file is subject to the terms and conditions of the GNU General Public
503 + * License. See the file "COPYING" in the main directory of this archive
504 + * for more details.
505 + *
506 + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
507 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
508 + *
509 + */
510 +#ifndef __ASM_MACH_ATH25_DMA_COHERENCE_H
511 +#define __ASM_MACH_ATH25_DMA_COHERENCE_H
512 +
513 +#include <linux/device.h>
514 +
515 +/*
516 + * We need some arbitrary non-zero value to be programmed to the BAR1 register
517 + * of PCI host controller to enable DMA. The same value should be used as the
518 + * offset to calculate the physical address of DMA buffer for PCI devices.
519 + */
520 +#define AR2315_PCI_HOST_SDRAM_BASEADDR 0x20000000
521 +
522 +static inline dma_addr_t ath25_dev_offset(struct device *dev)
523 +{
524 +#ifdef CONFIG_PCI
525 + extern struct bus_type pci_bus_type;
526 +
527 + if (dev && dev->bus == &pci_bus_type)
528 + return AR2315_PCI_HOST_SDRAM_BASEADDR;
529 +#endif
530 + return 0;
531 +}
532 +
533 +static inline dma_addr_t
534 +plat_map_dma_mem(struct device *dev, void *addr, size_t size)
535 +{
536 + return virt_to_phys(addr) + ath25_dev_offset(dev);
537 +}
538 +
539 +static inline dma_addr_t
540 +plat_map_dma_mem_page(struct device *dev, struct page *page)
541 +{
542 + return page_to_phys(page) + ath25_dev_offset(dev);
543 +}
544 +
545 +static inline unsigned long
546 +plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
547 +{
548 + return dma_addr - ath25_dev_offset(dev);
549 +}
550 +
551 +static inline void
552 +plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size,
553 + enum dma_data_direction direction)
554 +{
555 +}
556 +
557 +static inline int plat_dma_supported(struct device *dev, u64 mask)
558 +{
559 + return 1;
560 +}
561 +
562 +static inline void plat_extra_sync_for_device(struct device *dev)
563 +{
564 +}
565 +
566 +static inline int plat_dma_mapping_error(struct device *dev,
567 + dma_addr_t dma_addr)
568 +{
569 + return 0;
570 +}
571 +
572 +static inline int plat_device_is_coherent(struct device *dev)
573 +{
574 +#ifdef CONFIG_DMA_COHERENT
575 + return 1;
576 +#endif
577 +#ifdef CONFIG_DMA_NONCOHERENT
578 + return 0;
579 +#endif
580 +}
581 +
582 +#endif /* __ASM_MACH_ATH25_DMA_COHERENCE_H */
583 --- /dev/null
584 +++ b/arch/mips/include/asm/mach-ath25/gpio.h
585 @@ -0,0 +1,16 @@
586 +#ifndef __ASM_MACH_ATH25_GPIO_H
587 +#define __ASM_MACH_ATH25_GPIO_H
588 +
589 +#include <asm-generic/gpio.h>
590 +
591 +#define gpio_get_value __gpio_get_value
592 +#define gpio_set_value __gpio_set_value
593 +#define gpio_cansleep __gpio_cansleep
594 +#define gpio_to_irq __gpio_to_irq
595 +
596 +static inline int irq_to_gpio(unsigned irq)
597 +{
598 + return -EINVAL;
599 +}
600 +
601 +#endif /* __ASM_MACH_ATH25_GPIO_H */
602 --- /dev/null
603 +++ b/arch/mips/include/asm/mach-ath25/war.h
604 @@ -0,0 +1,25 @@
605 +/*
606 + * This file is subject to the terms and conditions of the GNU General Public
607 + * License. See the file "COPYING" in the main directory of this archive
608 + * for more details.
609 + *
610 + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
611 + */
612 +#ifndef __ASM_MACH_ATH25_WAR_H
613 +#define __ASM_MACH_ATH25_WAR_H
614 +
615 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
616 +#define R4600_V1_HIT_CACHEOP_WAR 0
617 +#define R4600_V2_HIT_CACHEOP_WAR 0
618 +#define R5432_CP0_INTERRUPT_WAR 0
619 +#define BCM1250_M3_WAR 0
620 +#define SIBYTE_1956_WAR 0
621 +#define MIPS4K_ICACHE_REFILL_WAR 0
622 +#define MIPS_CACHE_SYNC_WAR 0
623 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
624 +#define RM9000_CDEX_SMP_WAR 0
625 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
626 +#define R10000_LLSC_WAR 0
627 +#define MIPS34K_MISSED_ITLB_WAR 0
628 +
629 +#endif /* __ASM_MACH_ATH25_WAR_H */
630 --- /dev/null
631 +++ b/arch/mips/include/asm/mach-ath25/ar2315_regs.h
632 @@ -0,0 +1,470 @@
633 +/*
634 + * Register definitions for AR2315+
635 + *
636 + * This file is subject to the terms and conditions of the GNU General Public
637 + * License. See the file "COPYING" in the main directory of this archive
638 + * for more details.
639 + *
640 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
641 + * Copyright (C) 2006 FON Technology, SL.
642 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
643 + * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
644 + */
645 +
646 +#ifndef __ASM_MACH_ATH25_AR2315_REGS_H
647 +#define __ASM_MACH_ATH25_AR2315_REGS_H
648 +
649 +/*
650 + * IRQs
651 + */
652 +#define AR2315_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
653 +#define AR2315_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
654 +#define AR2315_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
655 +#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
656 +#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
657 +
658 +/*
659 + * Miscellaneous interrupts, which share IP2.
660 + */
661 +#define AR2315_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+0)
662 +#define AR2315_MISC_IRQ_I2C_RSVD (AR231X_MISC_IRQ_BASE+1)
663 +#define AR2315_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+2)
664 +#define AR2315_MISC_IRQ_AHB (AR231X_MISC_IRQ_BASE+3)
665 +#define AR2315_MISC_IRQ_APB (AR231X_MISC_IRQ_BASE+4)
666 +#define AR2315_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+5)
667 +#define AR2315_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+6)
668 +#define AR2315_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+7)
669 +#define AR2315_MISC_IRQ_IR_RSVD (AR231X_MISC_IRQ_BASE+8)
670 +#define AR2315_MISC_IRQ_COUNT 9
671 +
672 +/*
673 + * Address map
674 + */
675 +#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */
676 +#define AR2315_WLAN0 0x10000000 /* Wireless MMR */
677 +#define AR2315_PCI 0x10100000 /* PCI MMR */
678 +#define AR2315_PCI_SIZE 0x00001000
679 +#define AR2315_SDRAMCTL 0x10300000 /* SDRAM MMR */
680 +#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */
681 +#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */
682 +#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */
683 +#define AR2315_UART0 0x11100000 /* UART MMR */
684 +#define AR2315_SPI_MMR 0x11300000 /* SPI FLASH MMR */
685 +#define AR2315_PCIEXT 0x80000000 /* pci external */
686 +#define AR2315_PCIEXT_SZ 0x40000000
687 +
688 +/* MII registers offset inside Ethernet MMR region */
689 +#define AR2315_ENET0_MII (AR2315_ENET0 + 0x14)
690 +
691 +/*
692 + * Cold reset register
693 + */
694 +#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000)
695 +
696 +#define AR2315_RESET_COLD_AHB 0x00000001
697 +#define AR2315_RESET_COLD_APB 0x00000002
698 +#define AR2315_RESET_COLD_CPU 0x00000004
699 +#define AR2315_RESET_COLD_CPUWARM 0x00000008
700 +#define AR2315_RESET_SYSTEM \
701 + (RESET_COLD_CPU |\
702 + RESET_COLD_APB |\
703 + RESET_COLD_AHB) /* full system */
704 +#define AR2317_RESET_SYSTEM 0x00000010
705 +
706 +/*
707 + * Reset register
708 + */
709 +#define AR2315_RESET (AR2315_DSLBASE + 0x0004)
710 +
711 +/* warm reset WLAN0 MAC */
712 +#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001
713 +/* warm reset WLAN0 BaseBand */
714 +#define AR2315_RESET_WARM_WLAN0_BB 0x00000002
715 +/* warm reset MPEG-TS */
716 +#define AR2315_RESET_MPEGTS_RSVD 0x00000004
717 +/* warm reset PCI ahb/dma */
718 +#define AR2315_RESET_PCIDMA 0x00000008
719 +/* warm reset memory controller */
720 +#define AR2315_RESET_MEMCTL 0x00000010
721 +/* warm reset local bus */
722 +#define AR2315_RESET_LOCAL 0x00000020
723 +/* warm reset I2C bus */
724 +#define AR2315_RESET_I2C_RSVD 0x00000040
725 +/* warm reset SPI interface */
726 +#define AR2315_RESET_SPI 0x00000080
727 +/* warm reset UART0 */
728 +#define AR2315_RESET_UART0 0x00000100
729 +/* warm reset IR interface */
730 +#define AR2315_RESET_IR_RSVD 0x00000200
731 +/* cold reset ENET0 phy */
732 +#define AR2315_RESET_EPHY0 0x00000400
733 +/* cold reset ENET0 mac */
734 +#define AR2315_RESET_ENET0 0x00000800
735 +
736 +/*
737 + * AHB master arbitration control
738 + */
739 +#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008)
740 +
741 +/* CPU, default */
742 +#define AR2315_ARB_CPU 0x00000001
743 +/* WLAN */
744 +#define AR2315_ARB_WLAN 0x00000002
745 +/* MPEG-TS */
746 +#define AR2315_ARB_MPEGTS_RSVD 0x00000004
747 +/* LOCAL */
748 +#define AR2315_ARB_LOCAL 0x00000008
749 +/* PCI */
750 +#define AR2315_ARB_PCI 0x00000010
751 +/* Ethernet */
752 +#define AR2315_ARB_ETHERNET 0x00000020
753 +/* retry policy, debug only */
754 +#define AR2315_ARB_RETRY 0x00000100
755 +
756 +/*
757 + * Config Register
758 + */
759 +#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c)
760 +
761 +/* EC - AHB bridge endianess */
762 +#define AR2315_CONFIG_AHB 0x00000001
763 +/* WLAN byteswap */
764 +#define AR2315_CONFIG_WLAN 0x00000002
765 +/* MPEG-TS byteswap */
766 +#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004
767 +/* PCI byteswap */
768 +#define AR2315_CONFIG_PCI 0x00000008
769 +/* Memory controller endianess */
770 +#define AR2315_CONFIG_MEMCTL 0x00000010
771 +/* Local bus byteswap */
772 +#define AR2315_CONFIG_LOCAL 0x00000020
773 +/* Ethernet byteswap */
774 +#define AR2315_CONFIG_ETHERNET 0x00000040
775 +
776 +/* CPU write buffer merge */
777 +#define AR2315_CONFIG_MERGE 0x00000200
778 +/* CPU big endian */
779 +#define AR2315_CONFIG_CPU 0x00000400
780 +#define AR2315_CONFIG_PCIAHB 0x00000800
781 +#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
782 +/* SPI byteswap */
783 +#define AR2315_CONFIG_SPI 0x00008000
784 +#define AR2315_CONFIG_CPU_DRAM 0x00010000
785 +#define AR2315_CONFIG_CPU_PCI 0x00020000
786 +#define AR2315_CONFIG_CPU_MMR 0x00040000
787 +#define AR2315_CONFIG_BIG 0x00000400
788 +
789 +/*
790 + * NMI control
791 + */
792 +#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010)
793 +
794 +#define AR2315_NMI_EN 1
795 +
796 +/*
797 + * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0).
798 + */
799 +#define AR2315_SREV (AR2315_DSLBASE + 0x0014)
800 +
801 +#define AR2315_REV_MAJ 0x00f0
802 +#define AR2315_REV_MAJ_S 4
803 +#define AR2315_REV_MIN 0x000f
804 +#define AR2315_REV_MIN_S 0
805 +#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
806 +
807 +/*
808 + * Interface Enable
809 + */
810 +#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018)
811 +
812 +#define AR2315_IF_MASK 0x00000007
813 +#define AR2315_IF_DISABLED 0
814 +#define AR2315_IF_PCI 1
815 +#define AR2315_IF_TS_LOCAL 2
816 +/* only for emulation with separate pins */
817 +#define AR2315_IF_ALL 3
818 +#define AR2315_IF_LOCAL_HOST 0x00000008
819 +#define AR2315_IF_PCI_HOST 0x00000010
820 +#define AR2315_IF_PCI_INTR 0x00000020
821 +#define AR2315_IF_PCI_CLK_MASK 0x00030000
822 +#define AR2315_IF_PCI_CLK_INPUT 0
823 +#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
824 +#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
825 +#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
826 +#define AR2315_IF_PCI_CLK_SHIFT 16
827 +
828 +/*
829 + * APB Interrupt control
830 + */
831 +
832 +#define AR2315_ISR (AR2315_DSLBASE + 0x0020)
833 +#define AR2315_IMR (AR2315_DSLBASE + 0x0024)
834 +#define AR2315_GISR (AR2315_DSLBASE + 0x0028)
835 +
836 +#define AR2315_ISR_UART0 0x0001 /* high speed UART */
837 +#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
838 +#define AR2315_ISR_SPI 0x0004 /* SPI bus */
839 +#define AR2315_ISR_AHB 0x0008 /* AHB error */
840 +#define AR2315_ISR_APB 0x0010 /* APB error */
841 +#define AR2315_ISR_TIMER 0x0020 /* timer */
842 +#define AR2315_ISR_GPIO 0x0040 /* GPIO */
843 +#define AR2315_ISR_WD 0x0080 /* watchdog */
844 +#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
845 +
846 +#define AR2315_GISR_MISC 0x0001
847 +#define AR2315_GISR_WLAN0 0x0002
848 +#define AR2315_GISR_MPEGTS_RSVD 0x0004
849 +#define AR2315_GISR_LOCALPCI 0x0008
850 +#define AR2315_GISR_WMACPOLL 0x0010
851 +#define AR2315_GISR_TIMER 0x0020
852 +#define AR2315_GISR_ETHERNET 0x0040
853 +
854 +/*
855 + * Timers
856 + */
857 +#define AR2315_TIMER (AR2315_DSLBASE + 0x0030)
858 +#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034)
859 +#define AR2315_WD (AR2315_DSLBASE + 0x0038)
860 +#define AR2315_WDC (AR2315_DSLBASE + 0x003c)
861 +
862 +#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
863 +#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
864 +#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */
865 +
866 +/*
867 + * CPU Performance Counters
868 + */
869 +#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048)
870 +#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c)
871 +
872 +#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
873 +#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
874 +#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
875 +#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
876 +#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
877 +#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
878 +#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
879 +
880 +#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
881 +#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
882 +#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
883 +#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
884 +#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
885 +#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
886 +#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
887 +
888 +/*
889 + * AHB Error Reporting.
890 + */
891 +#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */
892 +#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */
893 +#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */
894 +#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */
895 +#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */
896 +
897 +#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
898 + /* write 1 to clear all bits in ERR0 */
899 +#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
900 +#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
901 +
902 +#define AR2315_PROCERR_HMAST 0x0000000f
903 +#define AR2315_PROCERR_HMAST_DFLT 0
904 +#define AR2315_PROCERR_HMAST_WMAC 1
905 +#define AR2315_PROCERR_HMAST_ENET 2
906 +#define AR2315_PROCERR_HMAST_PCIENDPT 3
907 +#define AR2315_PROCERR_HMAST_LOCAL 4
908 +#define AR2315_PROCERR_HMAST_CPU 5
909 +#define AR2315_PROCERR_HMAST_PCITGT 6
910 +
911 +#define AR2315_PROCERR_HMAST_S 0
912 +#define AR2315_PROCERR_HWRITE 0x00000010
913 +#define AR2315_PROCERR_HSIZE 0x00000060
914 +#define AR2315_PROCERR_HSIZE_S 5
915 +#define AR2315_PROCERR_HTRANS 0x00000180
916 +#define AR2315_PROCERR_HTRANS_S 7
917 +#define AR2315_PROCERR_HBURST 0x00000e00
918 +#define AR2315_PROCERR_HBURST_S 9
919 +
920 +/*
921 + * Clock Control
922 + */
923 +#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064)
924 +#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068)
925 +#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c)
926 +#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070)
927 +#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074)
928 +#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080)
929 +#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084)
930 +
931 +/* PLLc Control fields */
932 +#define PLLC_REF_DIV_M 0x00000003
933 +#define PLLC_REF_DIV_S 0
934 +#define PLLC_FDBACK_DIV_M 0x0000007C
935 +#define PLLC_FDBACK_DIV_S 2
936 +#define PLLC_ADD_FDBACK_DIV_M 0x00000080
937 +#define PLLC_ADD_FDBACK_DIV_S 7
938 +#define PLLC_CLKC_DIV_M 0x0001c000
939 +#define PLLC_CLKC_DIV_S 14
940 +#define PLLC_CLKM_DIV_M 0x00700000
941 +#define PLLC_CLKM_DIV_S 20
942 +
943 +/* CPU CLK Control fields */
944 +#define CPUCLK_CLK_SEL_M 0x00000003
945 +#define CPUCLK_CLK_SEL_S 0
946 +#define CPUCLK_CLK_DIV_M 0x0000000c
947 +#define CPUCLK_CLK_DIV_S 2
948 +
949 +/* AMBA CLK Control fields */
950 +#define AMBACLK_CLK_SEL_M 0x00000003
951 +#define AMBACLK_CLK_SEL_S 0
952 +#define AMBACLK_CLK_DIV_M 0x0000000c
953 +#define AMBACLK_CLK_DIV_S 2
954 +
955 +/* GPIO MMR base address */
956 +#define AR2315_GPIO (AR2315_DSLBASE + 0x0088)
957 +
958 +#define AR2315_RESET_GPIO 5
959 +
960 +/*
961 + * PCI Clock Control
962 + */
963 +#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4)
964 +
965 +#define AR2315_PCICLK_INPUT_M 0x3
966 +#define AR2315_PCICLK_INPUT_S 0
967 +
968 +#define AR2315_PCICLK_PLLC_CLKM 0
969 +#define AR2315_PCICLK_PLLC_CLKM1 1
970 +#define AR2315_PCICLK_PLLC_CLKC 2
971 +#define AR2315_PCICLK_REF_CLK 3
972 +
973 +#define AR2315_PCICLK_DIV_M 0xc
974 +#define AR2315_PCICLK_DIV_S 2
975 +
976 +#define AR2315_PCICLK_IN_FREQ 0
977 +#define AR2315_PCICLK_IN_FREQ_DIV_6 1
978 +#define AR2315_PCICLK_IN_FREQ_DIV_8 2
979 +#define AR2315_PCICLK_IN_FREQ_DIV_10 3
980 +
981 +/*
982 + * Observation Control Register
983 + */
984 +#define AR2315_OCR (AR2315_DSLBASE + 0x00b0)
985 +#define OCR_GPIO0_IRIN 0x0040
986 +#define OCR_GPIO1_IROUT 0x0080
987 +#define OCR_GPIO3_RXCLR 0x0200
988 +
989 +/*
990 + * General Clock Control
991 + */
992 +
993 +#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4)
994 +#define MISCCLK_PLLBYPASS_EN 0x00000001
995 +#define MISCCLK_PROCREFCLK 0x00000002
996 +
997 +/*
998 + * SDRAM Controller
999 + * - No read or write buffers are included.
1000 + */
1001 +#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00)
1002 +#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c)
1003 +#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10)
1004 +
1005 +#define SDRAM_DATA_WIDTH_M 0x00006000
1006 +#define SDRAM_DATA_WIDTH_S 13
1007 +
1008 +#define SDRAM_COL_WIDTH_M 0x00001E00
1009 +#define SDRAM_COL_WIDTH_S 9
1010 +
1011 +#define SDRAM_ROW_WIDTH_M 0x000001E0
1012 +#define SDRAM_ROW_WIDTH_S 5
1013 +
1014 +#define SDRAM_BANKADDR_BITS_M 0x00000018
1015 +#define SDRAM_BANKADDR_BITS_S 3
1016 +
1017 +/*
1018 + * Local Bus Interface Registers
1019 + */
1020 +#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000)
1021 +#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
1022 +#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
1023 +#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
1024 +#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
1025 +#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
1026 +#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
1027 +#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
1028 +#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
1029 +#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
1030 +#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
1031 +#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
1032 +#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
1033 +#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
1034 +#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
1035 +#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
1036 +#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
1037 +#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
1038 +#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
1039 +#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
1040 +#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
1041 +#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
1042 +#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
1043 +#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
1044 +#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
1045 +#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
1046 +
1047 +#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004)
1048 +#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
1049 +
1050 +#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008)
1051 +#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1052 +
1053 +#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C)
1054 +#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
1055 +#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
1056 +#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
1057 +#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
1058 +#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
1059 +#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80
1060 +#define AR2315_LBM_TIMEOUT_SHFT 7
1061 +#define AR2315_LBM_PORTMUX 0x07000000
1062 +
1063 +#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010)
1064 +
1065 +#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100)
1066 +#define AR2315_LB_TXEN_0 0x01
1067 +#define AR2315_LB_TXEN_1 0x02
1068 +#define AR2315_LB_TXEN_2 0x04
1069 +#define AR2315_LB_TXEN_3 0x08
1070 +
1071 +#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104)
1072 +#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200)
1073 +
1074 +#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400)
1075 +#define AR2315_LB_RXEN 0x01
1076 +
1077 +#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404)
1078 +#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408)
1079 +
1080 +#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500)
1081 +#define AR2315_INT_TX_DESC 0x0001
1082 +#define AR2315_INT_TX_OK 0x0002
1083 +#define AR2315_INT_TX_ERR 0x0004
1084 +#define AR2315_INT_TX_EOF 0x0008
1085 +#define AR2315_INT_RX_DESC 0x0010
1086 +#define AR2315_INT_RX_OK 0x0020
1087 +#define AR2315_INT_RX_ERR 0x0040
1088 +#define AR2315_INT_RX_EOF 0x0080
1089 +#define AR2315_INT_TX_TRUNC 0x0100
1090 +#define AR2315_INT_TX_STARVE 0x0200
1091 +#define AR2315_INT_LB_TIMEOUT 0x0400
1092 +#define AR2315_INT_LB_ERR 0x0800
1093 +#define AR2315_INT_MBOX_WR 0x1000
1094 +#define AR2315_INT_MBOX_RD 0x2000
1095 +
1096 +/* Bit definitions for INT MASK are the same as INT_STATUS */
1097 +#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504)
1098 +
1099 +#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508)
1100 +#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600)
1101 +
1102 +#endif /* __ASM_MACH_ATH25_AR2315_REGS_H */
1103 --- /dev/null
1104 +++ b/arch/mips/include/asm/mach-ath25/ar5312_regs.h
1105 @@ -0,0 +1,224 @@
1106 +/*
1107 + * This file is subject to the terms and conditions of the GNU General Public
1108 + * License. See the file "COPYING" in the main directory of this archive
1109 + * for more details.
1110 + *
1111 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1112 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1113 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1114 + */
1115 +
1116 +#ifndef __ASM_MACH_ATH25_AR5312_REGS_H
1117 +#define __ASM_MACH_ATH25_AR5312_REGS_H
1118 +
1119 +#include <asm/addrspace.h>
1120 +
1121 +/*
1122 + * IRQs
1123 + */
1124 +#define AR5312_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
1125 +#define AR5312_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
1126 +#define AR5312_IRQ_ENET1_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
1127 +#define AR5312_IRQ_WLAN1_INTRS (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
1128 +#define AR5312_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
1129 +
1130 +/*
1131 + * Miscellaneous interrupts, which share IP6.
1132 + */
1133 +#define AR5312_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+0)
1134 +#define AR5312_MISC_IRQ_AHB_PROC (AR231X_MISC_IRQ_BASE+1)
1135 +#define AR5312_MISC_IRQ_AHB_DMA (AR231X_MISC_IRQ_BASE+2)
1136 +#define AR5312_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+3)
1137 +#define AR5312_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+4)
1138 +#define AR5312_MISC_IRQ_UART0_DMA (AR231X_MISC_IRQ_BASE+5)
1139 +#define AR5312_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+6)
1140 +#define AR5312_MISC_IRQ_LOCAL (AR231X_MISC_IRQ_BASE+7)
1141 +#define AR5312_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+8)
1142 +#define AR5312_MISC_IRQ_COUNT 9
1143 +
1144 +/*
1145 + * Address Map
1146 + *
1147 + * The AR5312 supports 2 enet MACS, even though many reference boards only
1148 + * actually use 1 of them (i.e. Only MAC 0 is actually connected to an enet
1149 + * PHY or PHY switch. The AR2312 supports 1 enet MAC.
1150 + */
1151 +#define AR5312_WLAN0 0x18000000
1152 +#define AR5312_WLAN1 0x18500000
1153 +#define AR5312_ENET0 0x18100000
1154 +#define AR5312_ENET1 0x18200000
1155 +#define AR5312_SDRAMCTL 0x18300000
1156 +#define AR5312_FLASHCTL 0x18400000
1157 +#define AR5312_APBBASE 0x1c000000
1158 +#define AR5312_UART0 0x1c000000 /* UART MMR */
1159 +#define AR5312_FLASH 0x1e000000
1160 +
1161 +/*
1162 + * Need these defines to determine true number of ethernet MACs
1163 + */
1164 +#define AR5312_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1165 +#define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1166 +#define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1167 +
1168 +/* MII registers offset inside Ethernet MMR region */
1169 +#define AR5312_ENET0_MII (AR5312_ENET0 + 0x14)
1170 +#define AR5312_ENET1_MII (AR5312_ENET1 + 0x14)
1171 +
1172 +/* Reset/Timer Block Address Map */
1173 +#define AR5312_RESETTMR (AR5312_APBBASE + 0x3000)
1174 +#define AR5312_TIMER (AR5312_RESETTMR + 0x0000) /* countdown timer */
1175 +#define AR5312_WD_CTRL (AR5312_RESETTMR + 0x0008) /* watchdog cntrl */
1176 +#define AR5312_WD_TIMER (AR5312_RESETTMR + 0x000c) /* watchdog timer */
1177 +#define AR5312_ISR (AR5312_RESETTMR + 0x0010) /* Intr Status Reg */
1178 +#define AR5312_IMR (AR5312_RESETTMR + 0x0014) /* Intr Mask Reg */
1179 +#define AR5312_RESET (AR5312_RESETTMR + 0x0020)
1180 +#define AR5312_CLOCKCTL1 (AR5312_RESETTMR + 0x0064)
1181 +#define AR5312_SCRATCH (AR5312_RESETTMR + 0x006c)
1182 +#define AR5312_PROCADDR (AR5312_RESETTMR + 0x0070)
1183 +#define AR5312_PROC1 (AR5312_RESETTMR + 0x0074)
1184 +#define AR5312_DMAADDR (AR5312_RESETTMR + 0x0078)
1185 +#define AR5312_DMA1 (AR5312_RESETTMR + 0x007c)
1186 +#define AR5312_ENABLE (AR5312_RESETTMR + 0x0080) /* interface enb */
1187 +#define AR5312_REV (AR5312_RESETTMR + 0x0090) /* revision */
1188 +
1189 +/* AR5312_WD_CTRL register bit field definitions */
1190 +#define AR5312_WD_CTRL_IGNORE_EXPIRATION 0x0000
1191 +#define AR5312_WD_CTRL_NMI 0x0001
1192 +#define AR5312_WD_CTRL_RESET 0x0002
1193 +
1194 +/* AR5312_ISR register bit field definitions */
1195 +#define AR5312_ISR_TIMER 0x0001
1196 +#define AR5312_ISR_AHBPROC 0x0002
1197 +#define AR5312_ISR_AHBDMA 0x0004
1198 +#define AR5312_ISR_GPIO 0x0008
1199 +#define AR5312_ISR_UART0 0x0010
1200 +#define AR5312_ISR_UART0DMA 0x0020
1201 +#define AR5312_ISR_WD 0x0040
1202 +#define AR5312_ISR_LOCAL 0x0080
1203 +
1204 +/* AR5312_RESET register bit field definitions */
1205 +#define AR5312_RESET_SYSTEM 0x00000001 /* cold reset full system */
1206 +#define AR5312_RESET_PROC 0x00000002 /* cold reset MIPS core */
1207 +#define AR5312_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
1208 +#define AR5312_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1209 +#define AR5312_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1210 +#define AR5312_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
1211 +#define AR5312_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
1212 +#define AR5312_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
1213 +#define AR5312_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1214 +#define AR5312_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
1215 +#define AR5312_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1216 +#define AR5312_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1217 +#define AR5312_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
1218 +#define AR5312_RESET_NMI 0x00010000 /* send an NMI to the processor */
1219 +#define AR5312_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
1220 +#define AR5312_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
1221 +#define AR5312_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1222 +#define AR5312_RESET_WDOG 0x00100000 /* last reset was a watchdog */
1223 +
1224 +#define AR5312_RESET_WMAC0_BITS \
1225 + (AR5312_RESET_WLAN0 |\
1226 + AR5312_RESET_WARM_WLAN0_MAC |\
1227 + AR5312_RESET_WARM_WLAN0_BB)
1228 +
1229 +#define AR5312_RESET_WMAC1_BITS \
1230 + (AR5312_RESET_WLAN1 |\
1231 + AR5312_RESET_WARM_WLAN1_MAC |\
1232 + AR5312_RESET_WARM_WLAN1_BB)
1233 +
1234 +/* AR5312_CLOCKCTL1 register bit field definitions */
1235 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1236 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1237 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1238 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1239 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1240 +
1241 +/* Valid for AR5312 and AR2312 */
1242 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1243 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1244 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1245 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1246 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1247 +
1248 +/* Valid for AR2313 */
1249 +#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1250 +#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1251 +#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1252 +#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1253 +#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1254 +
1255 +/* AR5312_ENABLE register bit field definitions */
1256 +#define AR5312_ENABLE_WLAN0 0x0001
1257 +#define AR5312_ENABLE_ENET0 0x0002
1258 +#define AR5312_ENABLE_ENET1 0x0004
1259 +#define AR5312_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
1260 +#define AR5312_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
1261 +#define AR5312_ENABLE_WLAN1 \
1262 + (AR5312_ENABLE_UART_AND_WLAN1_PIO |\
1263 + AR5312_ENABLE_WLAN1_DMA)
1264 +
1265 +/* AR5312_REV register bit field definitions */
1266 +#define AR5312_REV_WMAC_MAJ 0xf000
1267 +#define AR5312_REV_WMAC_MAJ_S 12
1268 +#define AR5312_REV_WMAC_MIN 0x0f00
1269 +#define AR5312_REV_WMAC_MIN_S 8
1270 +#define AR5312_REV_MAJ 0x00f0
1271 +#define AR5312_REV_MAJ_S 4
1272 +#define AR5312_REV_MIN 0x000f
1273 +#define AR5312_REV_MIN_S 0
1274 +#define AR5312_REV_CHIP (AR5312_REV_MAJ|AR5312_REV_MIN)
1275 +
1276 +/* Major revision numbers, bits 7..4 of Revision ID register */
1277 +#define AR5312_REV_MAJ_AR5312 0x4
1278 +#define AR5312_REV_MAJ_AR2313 0x5
1279 +
1280 +/* Minor revision numbers, bits 3..0 of Revision ID register */
1281 +#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1282 +#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1283 +
1284 +/* AR5312_FLASHCTL register bit field definitions */
1285 +#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
1286 +#define FLASHCTL_IDCY_S 0
1287 +#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1288 +#define FLASHCTL_WST1_S 5
1289 +#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1290 +#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1291 +#define FLASHCTL_WST2_S 11
1292 +#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
1293 +#define FLASHCTL_AC_S 16
1294 +#define FLASHCTL_AC_128K 0x00000000
1295 +#define FLASHCTL_AC_256K 0x00010000
1296 +#define FLASHCTL_AC_512K 0x00020000
1297 +#define FLASHCTL_AC_1M 0x00030000
1298 +#define FLASHCTL_AC_2M 0x00040000
1299 +#define FLASHCTL_AC_4M 0x00050000
1300 +#define FLASHCTL_AC_8M 0x00060000
1301 +#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1302 +#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1303 +#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
1304 +#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
1305 +#define FLASHCTL_WP 0x04000000 /* Write protect */
1306 +#define FLASHCTL_BM 0x08000000 /* Burst mode */
1307 +#define FLASHCTL_MW 0x30000000 /* Memory width */
1308 +#define FLASHCTL_MW8 0x00000000 /* Memory width x8 */
1309 +#define FLASHCTL_MW16 0x10000000 /* Memory width x16 */
1310 +#define FLASHCTL_MW32 0x20000000 /* Memory width x32 (not supported) */
1311 +#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
1312 +#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
1313 +#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
1314 +
1315 +/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
1316 +#define AR5312_FLASHCTL0 (AR5312_FLASHCTL + 0x00)
1317 +#define AR5312_FLASHCTL1 (AR5312_FLASHCTL + 0x04)
1318 +#define AR5312_FLASHCTL2 (AR5312_FLASHCTL + 0x08)
1319 +
1320 +/* ARM SDRAM Controller -- just enough to determine memory size */
1321 +#define AR5312_MEM_CFG1 (AR5312_SDRAMCTL + 0x04)
1322 +#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */
1323 +#define MEM_CFG1_AC0_S 8
1324 +#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
1325 +#define MEM_CFG1_AC1_S 12
1326 +
1327 +#define AR5312_GPIO (AR5312_APBBASE + 0x2000)
1328 +
1329 +#endif /* __ASM_MACH_ATH25_AR5312_REGS_H */
1330 --- /dev/null
1331 +++ b/arch/mips/ath25/ar5312.c
1332 @@ -0,0 +1,449 @@
1333 +/*
1334 + * This file is subject to the terms and conditions of the GNU General Public
1335 + * License. See the file "COPYING" in the main directory of this archive
1336 + * for more details.
1337 + *
1338 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1339 + * Copyright (C) 2006 FON Technology, SL.
1340 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1341 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1342 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1343 + */
1344 +
1345 +/*
1346 + * Platform devices for Atheros SoCs
1347 + */
1348 +
1349 +#include <generated/autoconf.h>
1350 +#include <linux/init.h>
1351 +#include <linux/module.h>
1352 +#include <linux/types.h>
1353 +#include <linux/string.h>
1354 +#include <linux/mtd/physmap.h>
1355 +#include <linux/platform_device.h>
1356 +#include <linux/kernel.h>
1357 +#include <linux/reboot.h>
1358 +#include <linux/leds.h>
1359 +#include <linux/gpio.h>
1360 +#include <asm/bootinfo.h>
1361 +#include <asm/reboot.h>
1362 +#include <asm/time.h>
1363 +#include <linux/irq.h>
1364 +#include <linux/io.h>
1365 +
1366 +#include <ath25_platform.h>
1367 +#include <ar5312_regs.h>
1368 +#include <ar231x.h>
1369 +#include "devices.h"
1370 +#include "ar5312.h"
1371 +
1372 +static irqreturn_t ar5312_ahb_err_handler(int cpl, void *dev_id)
1373 +{
1374 + u32 proc1 = ar231x_read_reg(AR5312_PROC1);
1375 + u32 proc_addr = ar231x_read_reg(AR5312_PROCADDR); /* clears error */
1376 + u32 dma1 = ar231x_read_reg(AR5312_DMA1);
1377 + u32 dma_addr = ar231x_read_reg(AR5312_DMAADDR); /* clears error */
1378 +
1379 + pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
1380 + proc_addr, proc1, dma_addr, dma1);
1381 +
1382 + machine_restart("AHB error"); /* Catastrophic failure */
1383 + return IRQ_HANDLED;
1384 +}
1385 +
1386 +static struct irqaction ar5312_ahb_err_interrupt = {
1387 + .handler = ar5312_ahb_err_handler,
1388 + .name = "ar5312-ahb-error",
1389 +};
1390 +
1391 +static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
1392 +{
1393 + unsigned int ar231x_misc_intrs = ar231x_read_reg(AR5312_ISR) &
1394 + ar231x_read_reg(AR5312_IMR);
1395 +
1396 + if (ar231x_misc_intrs & AR5312_ISR_TIMER) {
1397 + generic_handle_irq(AR5312_MISC_IRQ_TIMER);
1398 + (void)ar231x_read_reg(AR5312_TIMER);
1399 + } else if (ar231x_misc_intrs & AR5312_ISR_AHBPROC)
1400 + generic_handle_irq(AR5312_MISC_IRQ_AHB_PROC);
1401 + else if ((ar231x_misc_intrs & AR5312_ISR_UART0))
1402 + generic_handle_irq(AR5312_MISC_IRQ_UART0);
1403 + else if (ar231x_misc_intrs & AR5312_ISR_WD)
1404 + generic_handle_irq(AR5312_MISC_IRQ_WATCHDOG);
1405 + else
1406 + spurious_interrupt();
1407 +}
1408 +
1409 +/* Enable the specified AR5312_MISC_IRQ interrupt */
1410 +static void ar5312_misc_irq_unmask(struct irq_data *d)
1411 +{
1412 + unsigned int imr;
1413 +
1414 + imr = ar231x_read_reg(AR5312_IMR);
1415 + imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE);
1416 + ar231x_write_reg(AR5312_IMR, imr);
1417 +}
1418 +
1419 +/* Disable the specified AR5312_MISC_IRQ interrupt */
1420 +static void ar5312_misc_irq_mask(struct irq_data *d)
1421 +{
1422 + unsigned int imr;
1423 +
1424 + imr = ar231x_read_reg(AR5312_IMR);
1425 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE));
1426 + ar231x_write_reg(AR5312_IMR, imr);
1427 + ar231x_read_reg(AR5312_IMR); /* flush write buffer */
1428 +}
1429 +
1430 +static struct irq_chip ar5312_misc_irq_chip = {
1431 + .name = "ar5312-misc",
1432 + .irq_unmask = ar5312_misc_irq_unmask,
1433 + .irq_mask = ar5312_misc_irq_mask,
1434 +};
1435 +
1436 +static void ar5312_irq_dispatch(void)
1437 +{
1438 + int pending = read_c0_status() & read_c0_cause();
1439 +
1440 + if (pending & CAUSEF_IP2)
1441 + do_IRQ(AR5312_IRQ_WLAN0_INTRS);
1442 + else if (pending & CAUSEF_IP3)
1443 + do_IRQ(AR5312_IRQ_ENET0_INTRS);
1444 + else if (pending & CAUSEF_IP4)
1445 + do_IRQ(AR5312_IRQ_ENET1_INTRS);
1446 + else if (pending & CAUSEF_IP5)
1447 + do_IRQ(AR5312_IRQ_WLAN1_INTRS);
1448 + else if (pending & CAUSEF_IP6)
1449 + do_IRQ(AR5312_IRQ_MISC_INTRS);
1450 + else if (pending & CAUSEF_IP7)
1451 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
1452 + else
1453 + spurious_interrupt();
1454 +}
1455 +
1456 +void __init ar5312_arch_init_irq(void)
1457 +{
1458 + int i;
1459 +
1460 + ath25_irq_dispatch = ar5312_irq_dispatch;
1461 + for (i = 0; i < AR5312_MISC_IRQ_COUNT; i++) {
1462 + int irq = AR231X_MISC_IRQ_BASE + i;
1463 +
1464 + irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip,
1465 + handle_level_irq);
1466 + }
1467 + setup_irq(AR5312_MISC_IRQ_AHB_PROC, &ar5312_ahb_err_interrupt);
1468 + irq_set_chained_handler(AR5312_IRQ_MISC_INTRS, ar5312_misc_irq_handler);
1469 +}
1470 +
1471 +static void ar5312_device_reset_set(u32 mask)
1472 +{
1473 + u32 val;
1474 +
1475 + val = ar231x_read_reg(AR5312_RESET);
1476 + ar231x_write_reg(AR5312_RESET, val | mask);
1477 +}
1478 +
1479 +static void ar5312_device_reset_clear(u32 mask)
1480 +{
1481 + u32 val;
1482 +
1483 + val = ar231x_read_reg(AR5312_RESET);
1484 + ar231x_write_reg(AR5312_RESET, val & ~mask);
1485 +}
1486 +
1487 +static struct physmap_flash_data ar5312_flash_data = {
1488 + .width = 2,
1489 +};
1490 +
1491 +static struct resource ar5312_flash_resource = {
1492 + .start = AR5312_FLASH,
1493 + .end = AR5312_FLASH + 0x800000 - 1,
1494 + .flags = IORESOURCE_MEM,
1495 +};
1496 +
1497 +static struct ar231x_eth ar5312_eth0_data = {
1498 + .reset_set = ar5312_device_reset_set,
1499 + .reset_clear = ar5312_device_reset_clear,
1500 + .reset_mac = AR5312_RESET_ENET0,
1501 + .reset_phy = AR5312_RESET_EPHY0,
1502 +};
1503 +
1504 +static struct ar231x_eth ar5312_eth1_data = {
1505 + .reset_set = ar5312_device_reset_set,
1506 + .reset_clear = ar5312_device_reset_clear,
1507 + .reset_mac = AR5312_RESET_ENET1,
1508 + .reset_phy = AR5312_RESET_EPHY1,
1509 +};
1510 +
1511 +static struct platform_device ar5312_physmap_flash = {
1512 + .name = "physmap-flash",
1513 + .id = 0,
1514 + .dev.platform_data = &ar5312_flash_data,
1515 + .resource = &ar5312_flash_resource,
1516 + .num_resources = 1,
1517 +};
1518 +
1519 +#ifdef CONFIG_LEDS_GPIO
1520 +static struct gpio_led ar5312_leds[] = {
1521 + { .name = "wlan", .gpio = 0, .active_low = 1, },
1522 +};
1523 +
1524 +static const struct gpio_led_platform_data ar5312_led_data = {
1525 + .num_leds = ARRAY_SIZE(ar5312_leds),
1526 + .leds = (void *)ar5312_leds,
1527 +};
1528 +
1529 +static struct platform_device ar5312_gpio_leds = {
1530 + .name = "leds-gpio",
1531 + .id = -1,
1532 + .dev.platform_data = (void *)&ar5312_led_data,
1533 +};
1534 +#endif
1535 +
1536 +/*
1537 + * NB: This mapping size is larger than the actual flash size,
1538 + * but this shouldn't be a problem here, because the flash
1539 + * will simply be mapped multiple times.
1540 + */
1541 +static char __init *ar5312_flash_limit(void)
1542 +{
1543 + u32 ctl;
1544 + /*
1545 + * Configure flash bank 0.
1546 + * Assume 8M window size. Flash will be aliased if it's smaller
1547 + */
1548 + ctl = FLASHCTL_E |
1549 + FLASHCTL_AC_8M |
1550 + FLASHCTL_RBLE |
1551 + (0x01 << FLASHCTL_IDCY_S) |
1552 + (0x07 << FLASHCTL_WST1_S) |
1553 + (0x07 << FLASHCTL_WST2_S) |
1554 + (ar231x_read_reg(AR5312_FLASHCTL0) & FLASHCTL_MW);
1555 +
1556 + ar231x_write_reg(AR5312_FLASHCTL0, ctl);
1557 +
1558 + /* Disable other flash banks */
1559 + ar231x_write_reg(AR5312_FLASHCTL1,
1560 + ar231x_read_reg(AR5312_FLASHCTL1) &
1561 + ~(FLASHCTL_E | FLASHCTL_AC));
1562 +
1563 + ar231x_write_reg(AR5312_FLASHCTL2,
1564 + ar231x_read_reg(AR5312_FLASHCTL2) &
1565 + ~(FLASHCTL_E | FLASHCTL_AC));
1566 +
1567 + return (char *)KSEG1ADDR(AR5312_FLASH + 0x800000);
1568 +}
1569 +
1570 +void __init ar5312_init_devices(void)
1571 +{
1572 + struct ath25_boarddata *config;
1573 + u32 fctl = 0;
1574 + u8 *c;
1575 +
1576 + /* Locate board/radio config data */
1577 + ath25_find_config(ar5312_flash_limit());
1578 + config = ath25_board.config;
1579 +
1580 + /* AR2313 has CPU minor rev. 10 */
1581 + if ((current_cpu_data.processor_id & 0xff) == 0x0a)
1582 + ath25_soc = ATH25_SOC_AR2313;
1583 +
1584 + /* AR2312 shares the same Silicon ID as AR5312 */
1585 + else if (config->flags & BD_ISCASPER)
1586 + ath25_soc = ATH25_SOC_AR2312;
1587 +
1588 + /* Everything else is probably AR5312 or compatible */
1589 + else
1590 + ath25_soc = ATH25_SOC_AR5312;
1591 +
1592 + /* fixup flash width */
1593 + fctl = ar231x_read_reg(AR5312_FLASHCTL) & FLASHCTL_MW;
1594 + switch (fctl) {
1595 + case FLASHCTL_MW16:
1596 + ar5312_flash_data.width = 2;
1597 + break;
1598 + case FLASHCTL_MW8:
1599 + default:
1600 + ar5312_flash_data.width = 1;
1601 + break;
1602 + }
1603 +
1604 + platform_device_register(&ar5312_physmap_flash);
1605 +
1606 +#ifdef CONFIG_LEDS_GPIO
1607 + ar5312_leds[0].gpio = config->sys_led_gpio;
1608 + platform_device_register(&ar5312_gpio_leds);
1609 +#endif
1610 +
1611 + /* Fix up MAC addresses if necessary */
1612 + if (is_broadcast_ether_addr(config->enet0_mac))
1613 + ether_addr_copy(config->enet0_mac, config->enet1_mac);
1614 +
1615 + /* If ENET0 and ENET1 have the same mac address,
1616 + * increment the one from ENET1 */
1617 + if (ether_addr_equal(config->enet0_mac, config->enet1_mac)) {
1618 + c = config->enet1_mac + 5;
1619 + while ((c >= config->enet1_mac) && !(++(*c)))
1620 + c--;
1621 + }
1622 +
1623 + switch (ath25_soc) {
1624 + case ATH25_SOC_AR5312:
1625 + ar5312_eth0_data.macaddr = config->enet0_mac;
1626 + ath25_add_ethernet(0, AR5312_ENET0, "eth0_mii",
1627 + AR5312_ENET0_MII, AR5312_IRQ_ENET0_INTRS,
1628 + &ar5312_eth0_data);
1629 +
1630 + ar5312_eth1_data.macaddr = config->enet1_mac;
1631 + ath25_add_ethernet(1, AR5312_ENET1, "eth1_mii",
1632 + AR5312_ENET1_MII, AR5312_IRQ_ENET1_INTRS,
1633 + &ar5312_eth1_data);
1634 +
1635 + if (!ath25_board.radio)
1636 + return;
1637 +
1638 + if (!(config->flags & BD_WLAN0))
1639 + break;
1640 +
1641 + ath25_add_wmac(0, AR5312_WLAN0, AR5312_IRQ_WLAN0_INTRS);
1642 + break;
1643 + /*
1644 + * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
1645 + * of ENET1. Atheros calls it 'twisted' for a reason :)
1646 + */
1647 + case ATH25_SOC_AR2312:
1648 + case ATH25_SOC_AR2313:
1649 + ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
1650 + ar5312_eth1_data.macaddr = config->enet0_mac;
1651 + ath25_add_ethernet(1, AR5312_ENET1, "eth0_mii",
1652 + AR5312_ENET0_MII, AR5312_IRQ_ENET1_INTRS,
1653 + &ar5312_eth1_data);
1654 +
1655 + if (!ath25_board.radio)
1656 + return;
1657 + break;
1658 + default:
1659 + break;
1660 + }
1661 +
1662 + if (config->flags & BD_WLAN1)
1663 + ath25_add_wmac(1, AR5312_WLAN1, AR5312_IRQ_WLAN1_INTRS);
1664 +}
1665 +
1666 +static void ar5312_restart(char *command)
1667 +{
1668 + /* reset the system */
1669 + local_irq_disable();
1670 + while (1)
1671 + ar231x_write_reg(AR5312_RESET, AR5312_RESET_SYSTEM);
1672 +}
1673 +
1674 +/*
1675 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
1676 + * to determine the predevisor value.
1677 + */
1678 +static unsigned clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
1679 +
1680 +static unsigned __init ar5312_cpu_frequency(void)
1681 +{
1682 + unsigned int scratch;
1683 + unsigned int predivide_mask, predivide_shift;
1684 + unsigned int multiplier_mask, multiplier_shift;
1685 + unsigned int clock_ctl1, predivide_select, predivisor, multiplier;
1686 + unsigned int doubler_mask;
1687 + u16 devid;
1688 +
1689 + /* Trust the bootrom's idea of cpu frequency. */
1690 + scratch = ar231x_read_reg(AR5312_SCRATCH);
1691 + if (scratch)
1692 + return scratch;
1693 +
1694 + devid = ar231x_read_reg(AR5312_REV);
1695 + devid &= AR5312_REV_MAJ;
1696 + devid >>= AR5312_REV_MAJ_S;
1697 + if (devid == AR5312_REV_MAJ_AR2313) {
1698 + predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
1699 + predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
1700 + multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
1701 + multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
1702 + doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
1703 + } else { /* AR5312 and AR2312 */
1704 + predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
1705 + predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
1706 + multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
1707 + multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
1708 + doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
1709 + }
1710 +
1711 + /*
1712 + * Clocking is derived from a fixed 40MHz input clock.
1713 + *
1714 + * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
1715 + * sys_freq = cpu_freq / 4 (used for APB clock, serial,
1716 + * flash, Timer, Watchdog Timer)
1717 + *
1718 + * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
1719 + *
1720 + * So, for example, with a PLL multiplier of 5, we have
1721 + *
1722 + * cpu_freq = 200MHz
1723 + * sys_freq = 50MHz
1724 + * cnt_freq = 100MHz
1725 + *
1726 + * We compute the CPU frequency, based on PLL settings.
1727 + */
1728 +
1729 + clock_ctl1 = ar231x_read_reg(AR5312_CLOCKCTL1);
1730 + predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
1731 + predivisor = clockctl1_predivide_table[predivide_select];
1732 + multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
1733 +
1734 + if (clock_ctl1 & doubler_mask)
1735 + multiplier = multiplier << 1;
1736 +
1737 + return (40000000 / predivisor) * multiplier;
1738 +}
1739 +
1740 +static inline unsigned ar5312_sys_frequency(void)
1741 +{
1742 + return ar5312_cpu_frequency() / 4;
1743 +}
1744 +
1745 +void __init ar5312_plat_time_init(void)
1746 +{
1747 + mips_hpt_frequency = ar5312_cpu_frequency() / 2;
1748 +}
1749 +
1750 +void __init ar5312_plat_mem_setup(void)
1751 +{
1752 + u32 memsize, memcfg, bank0AC, bank1AC;
1753 + u32 devid;
1754 +
1755 + /* Detect memory size */
1756 + memcfg = ar231x_read_reg(AR5312_MEM_CFG1);
1757 + bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
1758 + bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
1759 + memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) +
1760 + (bank1AC ? (1 << (bank1AC+1)) : 0);
1761 + memsize <<= 20;
1762 + add_memory_region(0, memsize, BOOT_MEM_RAM);
1763 +
1764 + devid = ar231x_read_reg(AR5312_REV);
1765 + devid >>= AR5312_REV_WMAC_MIN_S;
1766 + devid &= AR5312_REV_CHIP;
1767 + ath25_board.devid = (u16)devid;
1768 +
1769 + /* Clear any lingering AHB errors */
1770 + ar231x_read_reg(AR5312_PROCADDR);
1771 + ar231x_read_reg(AR5312_DMAADDR);
1772 + ar231x_write_reg(AR5312_WD_CTRL, AR5312_WD_CTRL_IGNORE_EXPIRATION);
1773 +
1774 + _machine_restart = ar5312_restart;
1775 +}
1776 +
1777 +void __init ar5312_arch_init(void)
1778 +{
1779 + ath25_serial_setup(AR5312_UART0, AR5312_MISC_IRQ_UART0,
1780 + ar5312_sys_frequency());
1781 +}
1782 --- /dev/null
1783 +++ b/arch/mips/ath25/ar2315.c
1784 @@ -0,0 +1,401 @@
1785 +/*
1786 + * This file is subject to the terms and conditions of the GNU General Public
1787 + * License. See the file "COPYING" in the main directory of this archive
1788 + * for more details.
1789 + *
1790 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1791 + * Copyright (C) 2006 FON Technology, SL.
1792 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1793 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1794 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1795 + */
1796 +
1797 +/*
1798 + * Platform devices for Atheros SoCs
1799 + */
1800 +
1801 +#include <generated/autoconf.h>
1802 +#include <linux/init.h>
1803 +#include <linux/module.h>
1804 +#include <linux/types.h>
1805 +#include <linux/string.h>
1806 +#include <linux/platform_device.h>
1807 +#include <linux/kernel.h>
1808 +#include <linux/reboot.h>
1809 +#include <linux/delay.h>
1810 +#include <linux/leds.h>
1811 +#include <linux/gpio.h>
1812 +#include <asm/bootinfo.h>
1813 +#include <asm/reboot.h>
1814 +#include <asm/time.h>
1815 +#include <linux/irq.h>
1816 +#include <linux/io.h>
1817 +
1818 +#include <ath25_platform.h>
1819 +#include <ar2315_regs.h>
1820 +#include <ar231x.h>
1821 +#include "devices.h"
1822 +#include "ar2315.h"
1823 +
1824 +static irqreturn_t ar2315_ahb_err_handler(int cpl, void *dev_id)
1825 +{
1826 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
1827 + ar231x_read_reg(AR2315_AHB_ERR1);
1828 +
1829 + pr_emerg("AHB fatal error\n");
1830 + machine_restart("AHB error"); /* Catastrophic failure */
1831 +
1832 + return IRQ_HANDLED;
1833 +}
1834 +
1835 +static struct irqaction ar2315_ahb_err_interrupt = {
1836 + .handler = ar2315_ahb_err_handler,
1837 + .name = "ar2315-ahb-error",
1838 +};
1839 +
1840 +static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
1841 +{
1842 + unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) &
1843 + ar231x_read_reg(AR2315_IMR);
1844 +
1845 + if (misc_intr & AR2315_ISR_SPI)
1846 + generic_handle_irq(AR2315_MISC_IRQ_SPI);
1847 + else if (misc_intr & AR2315_ISR_TIMER)
1848 + generic_handle_irq(AR2315_MISC_IRQ_TIMER);
1849 + else if (misc_intr & AR2315_ISR_AHB)
1850 + generic_handle_irq(AR2315_MISC_IRQ_AHB);
1851 + else if (misc_intr & AR2315_ISR_GPIO) {
1852 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
1853 + generic_handle_irq(AR2315_MISC_IRQ_GPIO);
1854 + } else if (misc_intr & AR2315_ISR_UART0)
1855 + generic_handle_irq(AR2315_MISC_IRQ_UART0);
1856 + else if (misc_intr & AR2315_ISR_WD) {
1857 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_WD);
1858 + generic_handle_irq(AR2315_MISC_IRQ_WATCHDOG);
1859 + } else
1860 + spurious_interrupt();
1861 +}
1862 +
1863 +static void ar2315_misc_irq_unmask(struct irq_data *d)
1864 +{
1865 + unsigned int imr;
1866 +
1867 + imr = ar231x_read_reg(AR2315_IMR);
1868 + imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE);
1869 + ar231x_write_reg(AR2315_IMR, imr);
1870 +}
1871 +
1872 +static void ar2315_misc_irq_mask(struct irq_data *d)
1873 +{
1874 + unsigned int imr;
1875 +
1876 + imr = ar231x_read_reg(AR2315_IMR);
1877 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE));
1878 + ar231x_write_reg(AR2315_IMR, imr);
1879 +}
1880 +
1881 +static struct irq_chip ar2315_misc_irq_chip = {
1882 + .name = "ar2315-misc",
1883 + .irq_unmask = ar2315_misc_irq_unmask,
1884 + .irq_mask = ar2315_misc_irq_mask,
1885 +};
1886 +
1887 +/*
1888 + * Called when an interrupt is received, this function
1889 + * determines exactly which interrupt it was, and it
1890 + * invokes the appropriate handler.
1891 + *
1892 + * Implicitly, we also define interrupt priority by
1893 + * choosing which to dispatch first.
1894 + */
1895 +static void ar2315_irq_dispatch(void)
1896 +{
1897 + int pending = read_c0_status() & read_c0_cause();
1898 +
1899 + if (pending & CAUSEF_IP3)
1900 + do_IRQ(AR2315_IRQ_WLAN0_INTRS);
1901 + else if (pending & CAUSEF_IP4)
1902 + do_IRQ(AR2315_IRQ_ENET0_INTRS);
1903 + else if (pending & CAUSEF_IP2)
1904 + do_IRQ(AR2315_IRQ_MISC_INTRS);
1905 + else if (pending & CAUSEF_IP7)
1906 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
1907 + else
1908 + spurious_interrupt();
1909 +}
1910 +
1911 +void __init ar2315_arch_init_irq(void)
1912 +{
1913 + int i;
1914 +
1915 + ath25_irq_dispatch = ar2315_irq_dispatch;
1916 + for (i = 0; i < AR2315_MISC_IRQ_COUNT; i++) {
1917 + int irq = AR231X_MISC_IRQ_BASE + i;
1918 +
1919 + irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip,
1920 + handle_level_irq);
1921 + }
1922 + setup_irq(AR2315_MISC_IRQ_AHB, &ar2315_ahb_err_interrupt);
1923 + irq_set_chained_handler(AR2315_IRQ_MISC_INTRS, ar2315_misc_irq_handler);
1924 +}
1925 +
1926 +static void ar2315_device_reset_set(u32 mask)
1927 +{
1928 + u32 val;
1929 +
1930 + val = ar231x_read_reg(AR2315_RESET);
1931 + ar231x_write_reg(AR2315_RESET, val | mask);
1932 +}
1933 +
1934 +static void ar2315_device_reset_clear(u32 mask)
1935 +{
1936 + u32 val;
1937 +
1938 + val = ar231x_read_reg(AR2315_RESET);
1939 + ar231x_write_reg(AR2315_RESET, val & ~mask);
1940 +}
1941 +
1942 +static struct ar231x_eth ar2315_eth_data = {
1943 + .reset_set = ar2315_device_reset_set,
1944 + .reset_clear = ar2315_device_reset_clear,
1945 + .reset_mac = AR2315_RESET_ENET0,
1946 + .reset_phy = AR2315_RESET_EPHY0,
1947 +};
1948 +
1949 +static struct resource ar2315_spiflash_res[] = {
1950 + {
1951 + .name = "spiflash_read",
1952 + .flags = IORESOURCE_MEM,
1953 + .start = AR2315_SPI_READ,
1954 + .end = AR2315_SPI_READ + 0x1000000 - 1,
1955 + },
1956 + {
1957 + .name = "spiflash_mmr",
1958 + .flags = IORESOURCE_MEM,
1959 + .start = AR2315_SPI_MMR,
1960 + .end = AR2315_SPI_MMR + 12 - 1,
1961 + },
1962 +};
1963 +
1964 +static struct platform_device ar2315_spiflash = {
1965 + .id = 0,
1966 + .name = "ar2315-spiflash",
1967 + .resource = ar2315_spiflash_res,
1968 + .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
1969 +};
1970 +
1971 +static struct resource ar2315_wdt_res[] = {
1972 + {
1973 + .flags = IORESOURCE_MEM,
1974 + .start = AR2315_WD,
1975 + .end = AR2315_WD + 8 - 1,
1976 + },
1977 + {
1978 + .flags = IORESOURCE_IRQ,
1979 + .start = AR2315_MISC_IRQ_WATCHDOG,
1980 + .end = AR2315_MISC_IRQ_WATCHDOG,
1981 + }
1982 +};
1983 +
1984 +static struct platform_device ar2315_wdt = {
1985 + .id = 0,
1986 + .name = "ar2315-wdt",
1987 + .resource = ar2315_wdt_res,
1988 + .num_resources = ARRAY_SIZE(ar2315_wdt_res)
1989 +};
1990 +
1991 +/*
1992 + * NB: We use mapping size that is larger than the actual flash size,
1993 + * but this shouldn't be a problem here, because the flash will simply
1994 + * be mapped multiple times.
1995 + */
1996 +static u8 __init *ar2315_flash_limit(void)
1997 +{
1998 + return (u8 *)KSEG1ADDR(ar2315_spiflash_res[0].end + 1);
1999 +}
2000 +
2001 +#ifdef CONFIG_LEDS_GPIO
2002 +static struct gpio_led ar2315_leds[6];
2003 +static struct gpio_led_platform_data ar2315_led_data = {
2004 + .leds = (void *)ar2315_leds,
2005 +};
2006 +
2007 +static struct platform_device ar2315_gpio_leds = {
2008 + .name = "leds-gpio",
2009 + .id = -1,
2010 + .dev = {
2011 + .platform_data = (void *)&ar2315_led_data,
2012 + }
2013 +};
2014 +
2015 +static void __init ar2315_init_gpio_leds(void)
2016 +{
2017 + static char led_names[6][6];
2018 + int i, led = 0;
2019 +
2020 + ar2315_led_data.num_leds = 0;
2021 + for (i = 1; i < 8; i++) {
2022 + if ((i == AR2315_RESET_GPIO) ||
2023 + (i == ath25_board.config->reset_config_gpio))
2024 + continue;
2025 +
2026 + if (i == ath25_board.config->sys_led_gpio)
2027 + strcpy(led_names[led], "wlan");
2028 + else
2029 + sprintf(led_names[led], "gpio%d", i);
2030 +
2031 + ar2315_leds[led].name = led_names[led];
2032 + ar2315_leds[led].gpio = i;
2033 + ar2315_leds[led].active_low = 0;
2034 + led++;
2035 + }
2036 + ar2315_led_data.num_leds = led;
2037 + platform_device_register(&ar2315_gpio_leds);
2038 +}
2039 +#else
2040 +static inline void ar2315_init_gpio_leds(void)
2041 +{
2042 +}
2043 +#endif
2044 +
2045 +void __init ar2315_init_devices(void)
2046 +{
2047 + /* Find board configuration */
2048 + ath25_find_config(ar2315_flash_limit());
2049 + ar2315_eth_data.macaddr = ath25_board.config->enet0_mac;
2050 +
2051 + ar2315_init_gpio_leds();
2052 + platform_device_register(&ar2315_wdt);
2053 + platform_device_register(&ar2315_spiflash);
2054 + ath25_add_ethernet(0, AR2315_ENET0, "eth0_mii", AR2315_ENET0_MII,
2055 + AR2315_IRQ_ENET0_INTRS, &ar2315_eth_data);
2056 + ath25_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
2057 +}
2058 +
2059 +static void ar2315_restart(char *command)
2060 +{
2061 + void (*mips_reset_vec)(void) = (void *)0xbfc00000;
2062 +
2063 + local_irq_disable();
2064 +
2065 + /* try reset the system via reset control */
2066 + ar231x_write_reg(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
2067 +
2068 + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
2069 + * a workaround. Give it some time to attempt a gpio based hardware
2070 + * reset (atheros reference design workaround) */
2071 + gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset");
2072 + mdelay(100);
2073 +
2074 + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
2075 + * workaround. Attempt to jump to the mips reset location -
2076 + * the boot loader itself might be able to recover the system */
2077 + mips_reset_vec();
2078 +}
2079 +
2080 +/*
2081 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2082 + * to determine the predevisor value.
2083 + */
2084 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
2085 +static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
2086 +
2087 +static unsigned __init ar2315_sys_clk(u32 clock_ctl)
2088 +{
2089 + unsigned int pllc_ctrl, cpu_div;
2090 + unsigned int pllc_out, refdiv, fdiv, divby2;
2091 + unsigned int clk_div;
2092 +
2093 + pllc_ctrl = ar231x_read_reg(AR2315_PLLC_CTL);
2094 + refdiv = (pllc_ctrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
2095 + refdiv = clockctl1_predivide_table[refdiv];
2096 + fdiv = (pllc_ctrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
2097 + divby2 = (pllc_ctrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
2098 + divby2 += 1;
2099 + pllc_out = (40000000/refdiv)*(2*divby2)*fdiv;
2100 +
2101 + /* clkm input selected */
2102 + switch (clock_ctl & CPUCLK_CLK_SEL_M) {
2103 + case 0:
2104 + case 1:
2105 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKM_DIV_M) >>
2106 + PLLC_CLKM_DIV_S];
2107 + break;
2108 + case 2:
2109 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKC_DIV_M) >>
2110 + PLLC_CLKC_DIV_S];
2111 + break;
2112 + default:
2113 + pllc_out = 40000000;
2114 + clk_div = 1;
2115 + break;
2116 + }
2117 +
2118 + cpu_div = (clock_ctl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
2119 + cpu_div = cpu_div * 2 ?: 1;
2120 +
2121 + return pllc_out / (clk_div * cpu_div);
2122 +}
2123 +
2124 +static inline unsigned ar2315_cpu_frequency(void)
2125 +{
2126 + return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
2127 +}
2128 +
2129 +static inline unsigned ar2315_apb_frequency(void)
2130 +{
2131 + return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
2132 +}
2133 +
2134 +void __init ar2315_plat_time_init(void)
2135 +{
2136 + mips_hpt_frequency = ar2315_cpu_frequency() / 2;
2137 +}
2138 +
2139 +void __init ar2315_plat_mem_setup(void)
2140 +{
2141 + u32 memsize, memcfg;
2142 + u32 devid;
2143 + u32 config;
2144 +
2145 + memcfg = ar231x_read_reg(AR2315_MEM_CFG);
2146 + memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
2147 + memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
2148 + memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
2149 + memsize <<= 3;
2150 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2151 +
2152 + /* Detect the hardware based on the device ID */
2153 + devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP;
2154 + switch (devid) {
2155 + case 0x91: /* Need to check */
2156 + ath25_soc = ATH25_SOC_AR2318;
2157 + break;
2158 + case 0x90:
2159 + ath25_soc = ATH25_SOC_AR2317;
2160 + break;
2161 + case 0x87:
2162 + ath25_soc = ATH25_SOC_AR2316;
2163 + break;
2164 + case 0x86:
2165 + default:
2166 + ath25_soc = ATH25_SOC_AR2315;
2167 + break;
2168 + }
2169 + ath25_board.devid = devid;
2170 +
2171 + /* Clear any lingering AHB errors */
2172 + config = read_c0_config();
2173 + write_c0_config(config & ~0x3);
2174 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2175 + ar231x_read_reg(AR2315_AHB_ERR1);
2176 + ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
2177 +
2178 + _machine_restart = ar2315_restart;
2179 +}
2180 +
2181 +void __init ar2315_arch_init(void)
2182 +{
2183 + ath25_serial_setup(AR2315_UART0, AR2315_MISC_IRQ_UART0,
2184 + ar2315_apb_frequency());
2185 +}
2186 --- /dev/null
2187 +++ b/arch/mips/ath25/ar2315.h
2188 @@ -0,0 +1,36 @@
2189 +#ifndef __AR2315_H
2190 +#define __AR2315_H
2191 +
2192 +#ifdef CONFIG_SOC_AR2315
2193 +
2194 +void ar2315_arch_init_irq(void);
2195 +void ar2315_init_devices(void);
2196 +void ar2315_plat_time_init(void);
2197 +void ar2315_plat_mem_setup(void);
2198 +void ar2315_arch_init(void);
2199 +
2200 +#else
2201 +
2202 +static inline void ar2315_arch_init_irq(void)
2203 +{
2204 +}
2205 +
2206 +static inline void ar2315_init_devices(void)
2207 +{
2208 +}
2209 +
2210 +static inline void ar2315_plat_time_init(void)
2211 +{
2212 +}
2213 +
2214 +static inline void ar2315_plat_mem_setup(void)
2215 +{
2216 +}
2217 +
2218 +static inline void ar2315_arch_init(void)
2219 +{
2220 +}
2221 +
2222 +#endif
2223 +
2224 +#endif
2225 --- /dev/null
2226 +++ b/arch/mips/ath25/ar5312.h
2227 @@ -0,0 +1,36 @@
2228 +#ifndef __AR5312_H
2229 +#define __AR5312_H
2230 +
2231 +#ifdef CONFIG_SOC_AR5312
2232 +
2233 +void ar5312_arch_init_irq(void);
2234 +void ar5312_init_devices(void);
2235 +void ar5312_plat_time_init(void);
2236 +void ar5312_plat_mem_setup(void);
2237 +void ar5312_arch_init(void);
2238 +
2239 +#else
2240 +
2241 +static inline void ar5312_arch_init_irq(void)
2242 +{
2243 +}
2244 +
2245 +static inline void ar5312_init_devices(void)
2246 +{
2247 +}
2248 +
2249 +static inline void ar5312_plat_time_init(void)
2250 +{
2251 +}
2252 +
2253 +static inline void ar5312_plat_mem_setup(void)
2254 +{
2255 +}
2256 +
2257 +static inline void ar5312_arch_init(void)
2258 +{
2259 +}
2260 +
2261 +#endif
2262 +
2263 +#endif
2264 --- /dev/null
2265 +++ b/arch/mips/include/asm/mach-ath25/ar231x.h
2266 @@ -0,0 +1,38 @@
2267 +#ifndef __ASM_MACH_ATH25_AR231X_H
2268 +#define __ASM_MACH_ATH25_AR231X_H
2269 +
2270 +#include <linux/types.h>
2271 +#include <linux/io.h>
2272 +
2273 +#define AR231X_MISC_IRQ_BASE 0x20
2274 +#define AR231X_GPIO_IRQ_BASE 0x30
2275 +
2276 +/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
2277 +#define AR231X_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE+7) /* C0_CAUSE: 0x8000 */
2278 +
2279 +static inline u32
2280 +ar231x_read_reg(u32 reg)
2281 +{
2282 + return __raw_readl((void __iomem *)KSEG1ADDR(reg));
2283 +}
2284 +
2285 +static inline void
2286 +ar231x_write_reg(u32 reg, u32 val)
2287 +{
2288 + __raw_writel(val, (void __iomem *)KSEG1ADDR(reg));
2289 +}
2290 +
2291 +static inline u32
2292 +ar231x_mask_reg(u32 reg, u32 mask, u32 val)
2293 +{
2294 + u32 ret;
2295 +
2296 + ret = ar231x_read_reg(reg);
2297 + ret &= ~mask;
2298 + ret |= val;
2299 + ar231x_write_reg(reg, ret);
2300 +
2301 + return ret;
2302 +}
2303 +
2304 +#endif /* __ASM_MACH_ATH25_AR231X_H */
2305 --- /dev/null
2306 +++ b/arch/mips/ath25/devices.h
2307 @@ -0,0 +1,39 @@
2308 +#ifndef __ATH25_DEVICES_H
2309 +#define __ATH25_DEVICES_H
2310 +
2311 +enum ath25_soc_type {
2312 + /* handled by ar5312.c */
2313 + ATH25_SOC_AR2312,
2314 + ATH25_SOC_AR2313,
2315 + ATH25_SOC_AR5312,
2316 +
2317 + /* handled by ar2315.c */
2318 + ATH25_SOC_AR2315,
2319 + ATH25_SOC_AR2316,
2320 + ATH25_SOC_AR2317,
2321 + ATH25_SOC_AR2318,
2322 +
2323 + ATH25_SOC_UNKNOWN
2324 +};
2325 +
2326 +extern enum ath25_soc_type ath25_soc;
2327 +extern struct ar231x_board_config ath25_board;
2328 +extern void (*ath25_irq_dispatch)(void);
2329 +
2330 +int ath25_find_config(u8 *flash_limit);
2331 +int ath25_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
2332 + int irq, void *pdata);
2333 +void ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
2334 +int ath25_add_wmac(int nr, u32 base, int irq);
2335 +
2336 +static inline bool is_ar2315(void)
2337 +{
2338 + return (current_cpu_data.cputype == CPU_4KEC);
2339 +}
2340 +
2341 +static inline bool is_ar5312(void)
2342 +{
2343 + return !is_ar2315();
2344 +}
2345 +
2346 +#endif
2347 --- /dev/null
2348 +++ b/arch/mips/ath25/devices.c
2349 @@ -0,0 +1,192 @@
2350 +#include <linux/kernel.h>
2351 +#include <linux/init.h>
2352 +#include <linux/serial.h>
2353 +#include <linux/serial_core.h>
2354 +#include <linux/serial_8250.h>
2355 +#include <linux/platform_device.h>
2356 +#include <asm/bootinfo.h>
2357 +
2358 +#include <ath25_platform.h>
2359 +#include <ar231x.h>
2360 +#include "devices.h"
2361 +#include "ar5312.h"
2362 +#include "ar2315.h"
2363 +
2364 +struct ar231x_board_config ath25_board;
2365 +enum ath25_soc_type ath25_soc = ATH25_SOC_UNKNOWN;
2366 +
2367 +static struct resource ath25_eth0_res[] = {
2368 + {
2369 + .name = "eth0_membase",
2370 + .flags = IORESOURCE_MEM,
2371 + },
2372 + {
2373 + .name = "eth0_mii",
2374 + .flags = IORESOURCE_MEM,
2375 + },
2376 + {
2377 + .name = "eth0_irq",
2378 + .flags = IORESOURCE_IRQ,
2379 + }
2380 +};
2381 +
2382 +static struct resource ath25_eth1_res[] = {
2383 + {
2384 + .name = "eth1_membase",
2385 + .flags = IORESOURCE_MEM,
2386 + },
2387 + {
2388 + .name = "eth1_mii",
2389 + .flags = IORESOURCE_MEM,
2390 + },
2391 + {
2392 + .name = "eth1_irq",
2393 + .flags = IORESOURCE_IRQ,
2394 + }
2395 +};
2396 +
2397 +static struct platform_device ath25_eth[] = {
2398 + {
2399 + .id = 0,
2400 + .name = "ar231x-eth",
2401 + .resource = ath25_eth0_res,
2402 + .num_resources = ARRAY_SIZE(ath25_eth0_res)
2403 + },
2404 + {
2405 + .id = 1,
2406 + .name = "ar231x-eth",
2407 + .resource = ath25_eth1_res,
2408 + .num_resources = ARRAY_SIZE(ath25_eth1_res)
2409 + }
2410 +};
2411 +
2412 +static struct resource ath25_wmac0_res[] = {
2413 + {
2414 + .name = "wmac0_membase",
2415 + .flags = IORESOURCE_MEM,
2416 + },
2417 + {
2418 + .name = "wmac0_irq",
2419 + .flags = IORESOURCE_IRQ,
2420 + }
2421 +};
2422 +
2423 +static struct resource ath25_wmac1_res[] = {
2424 + {
2425 + .name = "wmac1_membase",
2426 + .flags = IORESOURCE_MEM,
2427 + },
2428 + {
2429 + .name = "wmac1_irq",
2430 + .flags = IORESOURCE_IRQ,
2431 + }
2432 +};
2433 +
2434 +static struct platform_device ath25_wmac[] = {
2435 + {
2436 + .id = 0,
2437 + .name = "ar231x-wmac",
2438 + .resource = ath25_wmac0_res,
2439 + .num_resources = ARRAY_SIZE(ath25_wmac0_res),
2440 + .dev.platform_data = &ath25_board,
2441 + },
2442 + {
2443 + .id = 1,
2444 + .name = "ar231x-wmac",
2445 + .resource = ath25_wmac1_res,
2446 + .num_resources = ARRAY_SIZE(ath25_wmac1_res),
2447 + .dev.platform_data = &ath25_board,
2448 + },
2449 +};
2450 +
2451 +static const char * const soc_type_strings[] = {
2452 + [ATH25_SOC_AR5312] = "Atheros AR5312",
2453 + [ATH25_SOC_AR2312] = "Atheros AR2312",
2454 + [ATH25_SOC_AR2313] = "Atheros AR2313",
2455 + [ATH25_SOC_AR2315] = "Atheros AR2315",
2456 + [ATH25_SOC_AR2316] = "Atheros AR2316",
2457 + [ATH25_SOC_AR2317] = "Atheros AR2317",
2458 + [ATH25_SOC_AR2318] = "Atheros AR2318",
2459 + [ATH25_SOC_UNKNOWN] = "Atheros (unknown)",
2460 +};
2461 +
2462 +const char *get_system_type(void)
2463 +{
2464 + if ((ath25_soc >= ARRAY_SIZE(soc_type_strings)) ||
2465 + !soc_type_strings[ath25_soc])
2466 + return soc_type_strings[ATH25_SOC_UNKNOWN];
2467 + return soc_type_strings[ath25_soc];
2468 +}
2469 +
2470 +int __init ath25_add_ethernet(int nr, u32 base, const char *mii_name,
2471 + u32 mii_base, int irq, void *pdata)
2472 +{
2473 + struct resource *res;
2474 +
2475 + ath25_eth[nr].dev.platform_data = pdata;
2476 + res = &ath25_eth[nr].resource[0];
2477 + res->start = base;
2478 + res->end = base + 0x2000 - 1;
2479 + res++;
2480 + res->name = mii_name;
2481 + res->start = mii_base;
2482 + res->end = mii_base + 8 - 1;
2483 + res++;
2484 + res->start = irq;
2485 + res->end = irq;
2486 + return platform_device_register(&ath25_eth[nr]);
2487 +}
2488 +
2489 +void __init ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
2490 +{
2491 + struct uart_port s;
2492 +
2493 + memset(&s, 0, sizeof(s));
2494 +
2495 + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
2496 + s.iotype = UPIO_MEM32;
2497 + s.irq = irq;
2498 + s.regshift = 2;
2499 + s.mapbase = mapbase;
2500 + s.uartclk = uartclk;
2501 +
2502 + early_serial_setup(&s);
2503 +}
2504 +
2505 +int __init ath25_add_wmac(int nr, u32 base, int irq)
2506 +{
2507 + struct resource *res;
2508 +
2509 + ath25_wmac[nr].dev.platform_data = &ath25_board;
2510 + res = &ath25_wmac[nr].resource[0];
2511 + res->start = base;
2512 + res->end = base + 0x10000 - 1;
2513 + res++;
2514 + res->start = irq;
2515 + res->end = irq;
2516 + return platform_device_register(&ath25_wmac[nr]);
2517 +}
2518 +
2519 +static int __init ath25_register_devices(void)
2520 +{
2521 + if (is_ar5312())
2522 + ar5312_init_devices();
2523 + else
2524 + ar2315_init_devices();
2525 +
2526 + return 0;
2527 +}
2528 +
2529 +device_initcall(ath25_register_devices);
2530 +
2531 +static int __init ath25_arch_init(void)
2532 +{
2533 + if (is_ar5312())
2534 + ar5312_arch_init();
2535 + else
2536 + ar2315_arch_init();
2537 +
2538 + return 0;
2539 +}
2540 +
2541 +arch_initcall(ath25_arch_init);
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