projects / openwrt / openwrt.git / blob
? search:


6ce6259b6a60cdbcb2c2b1c9fb6d1df7d262a531
[openwrt/openwrt.git] / target / linux / avr32 / patches / 100-git_sync.patch
1 MAINTAINERS | 7 +
2 Makefile | 2 +-
3 arch/avr32/Kconfig | 7 +
4 arch/avr32/Makefile | 1 +
5 arch/avr32/boards/atngw100/Kconfig | 12 +
6 arch/avr32/boards/atngw100/flash.c | 5 +-
7 arch/avr32/boards/atngw100/setup.c | 26 +-
8 arch/avr32/boards/atstk1000/Kconfig | 12 +
9 arch/avr32/boards/atstk1000/atstk1002.c | 72 ++
10 arch/avr32/boards/atstk1000/flash.c | 5 +-
11 arch/avr32/configs/atngw100_defconfig | 201 +++-
12 arch/avr32/configs/atstk1002_defconfig | 354 +++++-
13 arch/avr32/drivers/Makefile | 1 +
14 arch/avr32/drivers/dw-dmac.c | 761 ++++++++++++
15 arch/avr32/drivers/dw-dmac.h | 42 +
16 arch/avr32/kernel/Makefile | 6 +-
17 arch/avr32/kernel/dma-controller.c | 34 +
18 arch/avr32/kernel/entry-avr32b.S | 26 +-
19 arch/avr32/kernel/setup.c | 2 +-
20 arch/avr32/kernel/vmlinux.lds.S | 143 +++
21 arch/avr32/kernel/vmlinux.lds.c | 142 ---
22 arch/avr32/mach-at32ap/Kconfig | 7 +
23 arch/avr32/mach-at32ap/Makefile | 1 +
24 arch/avr32/mach-at32ap/at32ap7000.c | 241 ++++-
25 arch/avr32/mach-at32ap/clock.c | 116 ++
26 arch/avr32/mach-at32ap/gpio-dev.c | 573 +++++++++
27 arch/avr32/mach-at32ap/hsmc.c | 129 ++-
28 arch/avr32/mach-at32ap/pio.c | 80 ++
29 arch/avr32/mach-at32ap/pm.h | 8 +
30 arch/avr32/mm/dma-coherent.c | 7 +
31 arch/avr32/mm/init.c | 12 +-
32 drivers/i2c/busses/Kconfig | 8 +
33 drivers/i2c/busses/Makefile | 1 +
34 drivers/i2c/busses/i2c-atmeltwi.c | 436 +++++++
35 drivers/i2c/busses/i2c-atmeltwi.h | 117 ++
36 drivers/misc/Kconfig | 9 +
37 drivers/misc/Makefile | 1 +
38 drivers/misc/atmel-ssc.c | 174 +++
39 drivers/mmc/host/Kconfig | 10 +
40 drivers/mmc/host/Makefile | 1 +
41 drivers/mmc/host/atmel-mci.c | 1161 ++++++++++++++++++
42 drivers/mmc/host/atmel-mci.h | 192 +++
43 drivers/mtd/chips/cfi_cmdset_0001.c | 43 +
44 drivers/mtd/chips/cfi_cmdset_0002.c | 6 +-
45 drivers/spi/atmel_spi.c | 4 +-
46 drivers/usb/gadget/Kconfig | 26 +-
47 drivers/usb/gadget/Makefile | 1 +
48 drivers/usb/gadget/atmel_usba_udc.c | 2038 +++++++++++++++++++++++++++++++
49 drivers/usb/gadget/atmel_usba_udc.h | 350 ++++++
50 drivers/video/atmel_lcdfb.c | 6 +-
51 drivers/video/backlight/Kconfig | 12 +
52 drivers/video/backlight/Makefile | 2 +
53 drivers/video/backlight/ltv350qv.c | 339 +++++
54 drivers/video/backlight/ltv350qv.h | 95 ++
55 include/asm-avr32/arch-at32ap/board.h | 20 +
56 include/asm-avr32/arch-at32ap/portmux.h | 13 +
57 include/asm-avr32/arch-at32ap/smc.h | 51 +-
58 include/asm-avr32/dma-controller.h | 166 +++
59 include/asm-avr32/dma-mapping.h | 17 +-
60 include/asm-avr32/system.h | 13 +-
61 include/asm-avr32/unistd.h | 13 +
62 include/linux/atmel-ssc.h | 312 +++++
63 include/linux/spi/at73c213.h | 25 +
64 scripts/checkstack.pl | 5 +
65 sound/Kconfig | 6 +
66 sound/Makefile | 3 +-
67 sound/avr32/Kconfig | 11 +
68 sound/avr32/Makefile | 3 +
69 sound/avr32/ac97c.c | 914 ++++++++++++++
70 sound/avr32/ac97c.h | 71 ++
71 sound/oss/Kconfig | 4 +
72 sound/oss/Makefile | 1 +
73 sound/oss/at32_abdac.c | 722 +++++++++++
74 sound/oss/at32_abdac.h | 59 +
75 sound/spi/Kconfig | 31 +
76 sound/spi/Makefile | 5 +
77 sound/spi/at73c213.c | 1121 +++++++++++++++++
78 sound/spi/at73c213.h | 119 ++
79 78 files changed, 11500 insertions(+), 272 deletions(-)
80 create mode 100644 arch/avr32/boards/atngw100/Kconfig
81 create mode 100644 arch/avr32/drivers/Makefile
82 create mode 100644 arch/avr32/drivers/dw-dmac.c
83 create mode 100644 arch/avr32/drivers/dw-dmac.h
84 create mode 100644 arch/avr32/kernel/dma-controller.c
85 create mode 100644 arch/avr32/kernel/vmlinux.lds.S
86 delete mode 100644 arch/avr32/kernel/vmlinux.lds.c
87 create mode 100644 arch/avr32/mach-at32ap/gpio-dev.c
88 create mode 100644 drivers/i2c/busses/i2c-atmeltwi.c
89 create mode 100644 drivers/i2c/busses/i2c-atmeltwi.h
90 create mode 100644 drivers/misc/atmel-ssc.c
91 create mode 100644 drivers/mmc/host/atmel-mci.c
92 create mode 100644 drivers/mmc/host/atmel-mci.h
93 create mode 100644 drivers/usb/gadget/atmel_usba_udc.c
94 create mode 100644 drivers/usb/gadget/atmel_usba_udc.h
95 create mode 100644 drivers/video/backlight/ltv350qv.c
96 create mode 100644 drivers/video/backlight/ltv350qv.h
97 create mode 100644 include/asm-avr32/dma-controller.h
98 create mode 100644 include/linux/atmel-ssc.h
99 create mode 100644 include/linux/spi/at73c213.h
100 create mode 100644 sound/avr32/Kconfig
101 create mode 100644 sound/avr32/Makefile
102 create mode 100644 sound/avr32/ac97c.c
103 create mode 100644 sound/avr32/ac97c.h
104 create mode 100644 sound/oss/at32_abdac.c
105 create mode 100644 sound/oss/at32_abdac.h
106 create mode 100644 sound/spi/Kconfig
107 create mode 100644 sound/spi/Makefile
108 create mode 100644 sound/spi/at73c213.c
109 create mode 100644 sound/spi/at73c213.h
110
111 diff --git a/MAINTAINERS b/MAINTAINERS
112 index 9a91d9e..587afe3 100644
113 --- a/MAINTAINERS
114 +++ b/MAINTAINERS
115 @@ -669,6 +669,13 @@ P: Haavard Skinnemoen
116 M: hskinnemoen@atmel.com
117 S: Supported
118
119 +ATMEL USBA UDC DRIVER
120 +P: Haavard Skinnemoen
121 +M: hskinnemoen@atmel.com
122 +L: kernel@avr32linux.org
123 +W: http://avr32linux.org/twiki/bin/view/Main/AtmelUsbDeviceDriver
124 +S: Supported
125 +
126 ATMEL WIRELESS DRIVER
127 P: Simon Kelley
128 M: simon@thekelleys.org.uk
129 diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig
130 index d12346a..ec6c7c5 100644
131 --- a/arch/avr32/Kconfig
132 +++ b/arch/avr32/Kconfig
133 @@ -116,6 +116,9 @@ endchoice
134 if BOARD_ATSTK1000
135 source "arch/avr32/boards/atstk1000/Kconfig"
136 endif
137 +if BOARD_ATNGW100
138 +source "arch/avr32/boards/atngw100/Kconfig"
139 +endif
140
141 choice
142 prompt "Boot loader type"
143 @@ -175,6 +178,10 @@ config OWNERSHIP_TRACE
144 enabling Nexus-compliant debuggers to keep track of the PID of the
145 currently executing task.
146
147 +config DW_DMAC
148 + tristate "Synopsys DesignWare DMA Controller support"
149 + default y if CPU_AT32AP7000
150 +
151 # FPU emulation goes here
152
153 source "kernel/Kconfig.hz"
154 diff --git a/arch/avr32/Makefile b/arch/avr32/Makefile
155 index dc6bc01..eb72198 100644
156 --- a/arch/avr32/Makefile
157 +++ b/arch/avr32/Makefile
158 @@ -31,6 +31,7 @@ core-$(CONFIG_BOARD_ATNGW100) += arch/avr32/boards/atngw100/
159 core-$(CONFIG_LOADER_U_BOOT) += arch/avr32/boot/u-boot/
160 core-y += arch/avr32/kernel/
161 core-y += arch/avr32/mm/
162 +drivers-y += arch/avr32/drivers/
163 libs-y += arch/avr32/lib/
164
165 archincdir-$(CONFIG_PLATFORM_AT32AP) := arch-at32ap
166 diff --git a/arch/avr32/boards/atngw100/Kconfig b/arch/avr32/boards/atngw100/Kconfig
167 new file mode 100644
168 index 0000000..5d922df
169 --- /dev/null
170 +++ b/arch/avr32/boards/atngw100/Kconfig
171 @@ -0,0 +1,12 @@
172 +# NGW100 customization
173 +
174 +config BOARD_ATNGW100_I2C_GPIO
175 + bool "Use GPIO for i2c instead of built-in TWI module"
176 + help
177 + The driver for the built-in TWI module has been plagued by
178 + various problems, while the i2c-gpio driver is based on the
179 + trusty old i2c-algo-bit bitbanging engine, making it work
180 + on pretty much any setup.
181 +
182 + Choose 'Y' here if you're having i2c-related problems and
183 + want to rule out the i2c bus driver.
184 diff --git a/arch/avr32/boards/atngw100/flash.c b/arch/avr32/boards/atngw100/flash.c
185 index f9b32a8..b07ae63 100644
186 --- a/arch/avr32/boards/atngw100/flash.c
187 +++ b/arch/avr32/boards/atngw100/flash.c
188 @@ -15,7 +15,7 @@
189
190 #include <asm/arch/smc.h>
191
192 -static struct smc_config flash_config __initdata = {
193 +static struct smc_timing flash_timing __initdata = {
194 .ncs_read_setup = 0,
195 .nrd_setup = 40,
196 .ncs_write_setup = 0,
197 @@ -28,7 +28,9 @@ static struct smc_config flash_config __initdata = {
198
199 .read_cycle = 120,
200 .write_cycle = 120,
201 +};
202
203 +static struct smc_config flash_config __initdata = {
204 .bus_width = 2,
205 .nrd_controlled = 1,
206 .nwe_controlled = 1,
207 @@ -82,6 +84,7 @@ static int __init atngw100_flash_init(void)
208 {
209 int ret;
210
211 + smc_set_timing(&flash_config, &flash_timing);
212 ret = smc_set_configuration(0, &flash_config);
213 if (ret < 0) {
214 printk(KERN_ERR "atngw100: failed to set NOR flash timing\n");
215 diff --git a/arch/avr32/boards/atngw100/setup.c b/arch/avr32/boards/atngw100/setup.c
216 index ef80156..2a5f587 100644
217 --- a/arch/avr32/boards/atngw100/setup.c
218 +++ b/arch/avr32/boards/atngw100/setup.c
219 @@ -42,6 +42,11 @@ static struct spi_board_info spi0_board_info[] __initdata = {
220 },
221 };
222
223 +static struct mci_platform_data __initdata mci0_data = {
224 + .detect_pin = GPIO_PIN_PC(25),
225 + .wp_pin = GPIO_PIN_PE(0),
226 +};
227 +
228 /*
229 * The next two functions should go away as the boot loader is
230 * supposed to initialize the macb address registers with a valid
231 @@ -124,9 +129,13 @@ static struct platform_device ngw_gpio_leds = {
232 }
233 };
234
235 +#ifdef CONFIG_BOARD_ATNGW100_I2C_GPIO
236 static struct i2c_gpio_platform_data i2c_gpio_data = {
237 - .sda_pin = GPIO_PIN_PA(6),
238 - .scl_pin = GPIO_PIN_PA(7),
239 + .sda_pin = GPIO_PIN_PA(6),
240 + .scl_pin = GPIO_PIN_PA(7),
241 + .sda_is_open_drain = 1,
242 + .scl_is_open_drain = 1,
243 + .udelay = 2, /* close to 100 kHz */
244 };
245
246 static struct platform_device i2c_gpio_device = {
247 @@ -136,6 +145,7 @@ static struct platform_device i2c_gpio_device = {
248 .platform_data = &i2c_gpio_data,
249 },
250 };
251 +#endif
252
253 static int __init atngw100_init(void)
254 {
255 @@ -154,6 +164,8 @@ static int __init atngw100_init(void)
256 set_hw_addr(at32_add_device_eth(1, &eth_data[1]));
257
258 at32_add_device_spi(0, spi0_board_info, ARRAY_SIZE(spi0_board_info));
259 + at32_add_device_mci(0, &mci0_data);
260 + at32_add_device_usba(0, NULL);
261
262 for (i = 0; i < ARRAY_SIZE(ngw_leds); i++) {
263 at32_select_gpio(ngw_leds[i].gpio,
264 @@ -161,9 +173,15 @@ static int __init atngw100_init(void)
265 }
266 platform_device_register(&ngw_gpio_leds);
267
268 - at32_select_gpio(i2c_gpio_data.sda_pin, 0);
269 - at32_select_gpio(i2c_gpio_data.scl_pin, 0);
270 +#ifdef CONFIG_BOARD_ATNGW100_I2C_GPIO
271 + at32_select_gpio(i2c_gpio_data.sda_pin,
272 + AT32_GPIOF_MULTIDRV | AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
273 + at32_select_gpio(i2c_gpio_data.scl_pin,
274 + AT32_GPIOF_MULTIDRV | AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
275 platform_device_register(&i2c_gpio_device);
276 +#else
277 + at32_add_device_twi(0);
278 +#endif
279
280 return 0;
281 }
282 diff --git a/arch/avr32/boards/atstk1000/Kconfig b/arch/avr32/boards/atstk1000/Kconfig
283 index 718578f..b1f5a62 100644
284 --- a/arch/avr32/boards/atstk1000/Kconfig
285 +++ b/arch/avr32/boards/atstk1000/Kconfig
286 @@ -76,4 +76,16 @@ config BOARD_ATSTK1002_J2_RGB
287
288 endchoice
289
290 +config BOARD_ATSTK1002_ENABLE_AC97
291 + bool "Use AC97C instead of ABDAC"
292 + help
293 + Select this if you want to use the built-in AC97 controller
294 + instead of the built-in Audio Bitstream DAC. These share
295 + the same I/O pins on the AP7000, so both can't be enabled
296 + at the same time.
297 +
298 + Note that the STK1000/STK1002 kit doesn't ship with an AC97
299 + codec on board, so say N unless you've got an expansion
300 + board with an AC97 codec on it that you want to use.
301 +
302 endif # stk 1002
303 diff --git a/arch/avr32/boards/atstk1000/atstk1002.c b/arch/avr32/boards/atstk1000/atstk1002.c
304 index c9981b7..f7fb509 100644
305 --- a/arch/avr32/boards/atstk1000/atstk1002.c
306 +++ b/arch/avr32/boards/atstk1000/atstk1002.c
307 @@ -16,6 +16,7 @@
308 #include <linux/string.h>
309 #include <linux/types.h>
310 #include <linux/spi/spi.h>
311 +#include <linux/spi/at73c213.h>
312
313 #include <video/atmel_lcdc.h>
314
315 @@ -49,7 +50,25 @@ static struct eth_platform_data __initdata eth_data[2] = {
316 };
317
318 #ifndef CONFIG_BOARD_ATSTK1002_SW1_CUSTOM
319 +#ifndef CONFIG_BOARD_ATSTK1002_SW3_CUSTOM
320 +static struct at73c213_board_info at73c213_data = {
321 + .ssc_id = 0,
322 + .shortname = "AVR32 STK1000 external DAC",
323 +};
324 +#endif
325 +#endif
326 +#ifndef CONFIG_BOARD_ATSTK1002_SW1_CUSTOM
327 static struct spi_board_info spi0_board_info[] __initdata = {
328 +#ifndef CONFIG_BOARD_ATSTK1002_SW3_CUSTOM
329 + {
330 + /* AT73C213 */
331 + .modalias = "at73c213",
332 + .max_speed_hz = 200000,
333 + .chip_select = 0,
334 + .mode = SPI_MODE_1,
335 + .platform_data = &at73c213_data,
336 + },
337 +#endif
338 {
339 /* QVGA display */
340 .modalias = "ltv350qv",
341 @@ -66,6 +85,11 @@ static struct spi_board_info spi1_board_info[] __initdata = { {
342 } };
343 #endif
344
345 +static struct mci_platform_data __initdata mci0_data = {
346 + .detect_pin = GPIO_PIN_NONE,
347 + .wp_pin = GPIO_PIN_NONE,
348 +};
349 +
350 /*
351 * The next two functions should go away as the boot loader is
352 * supposed to initialize the macb address registers with a valid
353 @@ -180,6 +204,38 @@ static void setup_j2_leds(void)
354 }
355 #endif
356
357 +#ifndef CONFIG_BOARD_ATSTK1002_SW1_CUSTOM
358 +#ifndef CONFIG_BOARD_ATSTK1002_SW3_CUSTOM
359 +static void __init at73c213_set_clk(struct at73c213_board_info *info)
360 +{
361 + struct clk *gclk;
362 + struct clk *pll;
363 +
364 + gclk = clk_get(NULL, "gclk0");
365 + if (IS_ERR(gclk))
366 + goto err_gclk;
367 + pll = clk_get(NULL, "pll0");
368 + if (IS_ERR(pll))
369 + goto err_pll;
370 +
371 + if (clk_set_parent(gclk, pll)) {
372 + pr_debug("STK1000: failed to set pll0 as parent for DAC clock\n");
373 + goto err_set_clk;
374 + }
375 +
376 + at32_select_periph(GPIO_PIN_PA(30), GPIO_PERIPH_A, 0);
377 + info->dac_clk = gclk;
378 +
379 +err_set_clk:
380 + clk_put(pll);
381 +err_pll:
382 + clk_put(gclk);
383 +err_gclk:
384 + return;
385 +}
386 +#endif
387 +#endif
388 +
389 void __init setup_board(void)
390 {
391 #ifdef CONFIG_BOARD_ATSTK1002_SW2_CUSTOM
392 @@ -235,18 +291,34 @@ static int __init atstk1002_init(void)
393 #ifdef CONFIG_BOARD_ATSTK1002_SPI1
394 at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info));
395 #endif
396 + at32_add_device_twi(0);
397 +#ifndef CONFIG_BOARD_ATSTK1002_SW2_CUSTOM
398 + at32_add_device_mci(0, &mci0_data);
399 +#endif
400 #ifdef CONFIG_BOARD_ATSTK1002_SW5_CUSTOM
401 set_hw_addr(at32_add_device_eth(1, &eth_data[1]));
402 #else
403 at32_add_device_lcdc(0, &atstk1000_lcdc_data,
404 fbmem_start, fbmem_size);
405 #endif
406 + at32_add_device_usba(0, NULL);
407 +#ifdef CONFIG_BOARD_ATSTK1002_ENABLE_AC97
408 + at32_add_device_ac97c(0);
409 +#else
410 + at32_add_device_abdac(0);
411 +#endif
412 #ifndef CONFIG_BOARD_ATSTK1002_SW3_CUSTOM
413 at32_add_device_ssc(0, ATMEL_SSC_TX);
414 #endif
415
416 setup_j2_leds();
417
418 +#ifndef CONFIG_BOARD_ATSTK1002_SW3_CUSTOM
419 +#ifndef CONFIG_BOARD_ATSTK1002_SW1_CUSTOM
420 + at73c213_set_clk(&at73c213_data);
421 +#endif
422 +#endif
423 +
424 return 0;
425 }
426 postcore_initcall(atstk1002_init);
427 diff --git a/arch/avr32/boards/atstk1000/flash.c b/arch/avr32/boards/atstk1000/flash.c
428 index aac4300..3d0a102 100644
429 --- a/arch/avr32/boards/atstk1000/flash.c
430 +++ b/arch/avr32/boards/atstk1000/flash.c
431 @@ -15,7 +15,7 @@
432
433 #include <asm/arch/smc.h>
434
435 -static struct smc_config flash_config __initdata = {
436 +static struct smc_timing flash_timing __initdata = {
437 .ncs_read_setup = 0,
438 .nrd_setup = 40,
439 .ncs_write_setup = 0,
440 @@ -28,7 +28,9 @@ static struct smc_config flash_config __initdata = {
441
442 .read_cycle = 120,
443 .write_cycle = 120,
444 +};
445
446 +static struct smc_config flash_config __initdata = {
447 .bus_width = 2,
448 .nrd_controlled = 1,
449 .nwe_controlled = 1,
450 @@ -82,6 +84,7 @@ static int __init atstk1000_flash_init(void)
451 {
452 int ret;
453
454 + smc_set_timing(&flash_config, &flash_timing);
455 ret = smc_set_configuration(0, &flash_config);
456 if (ret < 0) {
457 printk(KERN_ERR "atstk1000: failed to set NOR flash timing\n");
458 diff --git a/arch/avr32/configs/atngw100_defconfig b/arch/avr32/configs/atngw100_defconfig
459 index b799a68..adce168 100644
460 --- a/arch/avr32/configs/atngw100_defconfig
461 +++ b/arch/avr32/configs/atngw100_defconfig
462 @@ -1,7 +1,7 @@
463 #
464 # Automatically generated make config: don't edit
465 -# Linux kernel version: 2.6.22-rc5
466 -# Sat Jun 23 15:40:05 2007
467 +# Linux kernel version: 2.6.22.atmel.1
468 +# Thu Jul 12 17:49:20 2007
469 #
470 CONFIG_AVR32=y
471 CONFIG_GENERIC_GPIO=y
472 @@ -114,6 +114,7 @@ CONFIG_PLATFORM_AT32AP=y
473 CONFIG_CPU_AT32AP7000=y
474 # CONFIG_BOARD_ATSTK1000 is not set
475 CONFIG_BOARD_ATNGW100=y
476 +# CONFIG_BOARD_ATNGW100_I2C_GPIO is not set
477 CONFIG_LOADER_U_BOOT=y
478
479 #
480 @@ -122,6 +123,7 @@ CONFIG_LOADER_U_BOOT=y
481 # CONFIG_AP7000_32_BIT_SMC is not set
482 CONFIG_AP7000_16_BIT_SMC=y
483 # CONFIG_AP7000_8_BIT_SMC is not set
484 +CONFIG_GPIO_DEV=y
485 CONFIG_LOAD_ADDRESS=0x10000000
486 CONFIG_ENTRY_ADDRESS=0x90000000
487 CONFIG_PHYS_OFFSET=0x10000000
488 @@ -145,6 +147,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
489 # CONFIG_RESOURCES_64BIT is not set
490 CONFIG_ZONE_DMA_FLAG=0
491 # CONFIG_OWNERSHIP_TRACE is not set
492 +CONFIG_DW_DMAC=y
493 # CONFIG_HZ_100 is not set
494 CONFIG_HZ_250=y
495 # CONFIG_HZ_300 is not set
496 @@ -153,6 +156,27 @@ CONFIG_HZ=250
497 CONFIG_CMDLINE=""
498
499 #
500 +# Power managment options
501 +#
502 +
503 +#
504 +# CPU Frequency scaling
505 +#
506 +CONFIG_CPU_FREQ=y
507 +CONFIG_CPU_FREQ_TABLE=y
508 +# CONFIG_CPU_FREQ_DEBUG is not set
509 +CONFIG_CPU_FREQ_STAT=m
510 +# CONFIG_CPU_FREQ_STAT_DETAILS is not set
511 +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
512 +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
513 +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
514 +CONFIG_CPU_FREQ_GOV_POWERSAVE=y
515 +CONFIG_CPU_FREQ_GOV_USERSPACE=y
516 +CONFIG_CPU_FREQ_GOV_ONDEMAND=y
517 +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
518 +CONFIG_CPU_FREQ_AT32AP=y
519 +
520 +#
521 # Bus options
522 #
523 # CONFIG_ARCH_SUPPORTS_MSI is not set
524 @@ -187,13 +211,8 @@ CONFIG_NET_KEY=y
525 # CONFIG_NET_KEY_MIGRATE is not set
526 CONFIG_INET=y
527 CONFIG_IP_MULTICAST=y
528 -CONFIG_IP_ADVANCED_ROUTER=y
529 -CONFIG_ASK_IP_FIB_HASH=y
530 -# CONFIG_IP_FIB_TRIE is not set
531 +# CONFIG_IP_ADVANCED_ROUTER is not set
532 CONFIG_IP_FIB_HASH=y
533 -# CONFIG_IP_MULTIPLE_TABLES is not set
534 -# CONFIG_IP_ROUTE_MULTIPATH is not set
535 -# CONFIG_IP_ROUTE_VERBOSE is not set
536 CONFIG_IP_PNP=y
537 CONFIG_IP_PNP_DHCP=y
538 # CONFIG_IP_PNP_BOOTP is not set
539 @@ -240,6 +259,7 @@ CONFIG_IPV6_SIT=y
540 # CONFIG_NETWORK_SECMARK is not set
541 CONFIG_NETFILTER=y
542 # CONFIG_NETFILTER_DEBUG is not set
543 +CONFIG_BRIDGE_NETFILTER=y
544
545 #
546 # Core Netfilter Configuration
547 @@ -284,6 +304,7 @@ CONFIG_NETFILTER_XT_MATCH_MAC=m
548 CONFIG_NETFILTER_XT_MATCH_MARK=m
549 CONFIG_NETFILTER_XT_MATCH_POLICY=m
550 CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
551 +# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
552 CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
553 CONFIG_NETFILTER_XT_MATCH_QUOTA=m
554 CONFIG_NETFILTER_XT_MATCH_REALM=m
555 @@ -359,13 +380,19 @@ CONFIG_IP6_NF_TARGET_REJECT=m
556 CONFIG_IP6_NF_MANGLE=m
557 CONFIG_IP6_NF_TARGET_HL=m
558 CONFIG_IP6_NF_RAW=m
559 +
560 +#
561 +# Bridge: Netfilter Configuration
562 +#
563 +# CONFIG_BRIDGE_NF_EBTABLES is not set
564 # CONFIG_IP_DCCP is not set
565 # CONFIG_IP_SCTP is not set
566 # CONFIG_TIPC is not set
567 # CONFIG_ATM is not set
568 -# CONFIG_BRIDGE is not set
569 +CONFIG_BRIDGE=m
570 CONFIG_VLAN_8021Q=m
571 # CONFIG_DECNET is not set
572 +CONFIG_LLC=m
573 # CONFIG_LLC2 is not set
574 # CONFIG_IPX is not set
575 # CONFIG_ATALK is not set
576 @@ -521,7 +548,6 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
577 #
578 # Misc devices
579 #
580 -# CONFIG_BLINK is not set
581 # CONFIG_IDE is not set
582
583 #
584 @@ -545,13 +571,26 @@ CONFIG_NETDEVICES=y
585 # CONFIG_BONDING is not set
586 # CONFIG_EQUALIZER is not set
587 CONFIG_TUN=m
588 -# CONFIG_PHYLIB is not set
589 +CONFIG_PHYLIB=y
590 +
591 +#
592 +# MII PHY device drivers
593 +#
594 +# CONFIG_MARVELL_PHY is not set
595 +# CONFIG_DAVICOM_PHY is not set
596 +# CONFIG_QSEMI_PHY is not set
597 +# CONFIG_LXT_PHY is not set
598 +# CONFIG_CICADA_PHY is not set
599 +# CONFIG_VITESSE_PHY is not set
600 +# CONFIG_SMSC_PHY is not set
601 +# CONFIG_BROADCOM_PHY is not set
602 +# CONFIG_FIXED_PHY is not set
603
604 #
605 # Ethernet (10 or 100Mbit)
606 #
607 CONFIG_NET_ETHERNET=y
608 -CONFIG_MII=y
609 +# CONFIG_MII is not set
610 CONFIG_MACB=y
611 # CONFIG_NETDEV_1000 is not set
612 # CONFIG_NETDEV_10000 is not set
613 @@ -625,7 +664,15 @@ CONFIG_UNIX98_PTYS=y
614 # IPMI
615 #
616 # CONFIG_IPMI_HANDLER is not set
617 -# CONFIG_WATCHDOG is not set
618 +CONFIG_WATCHDOG=y
619 +# CONFIG_WATCHDOG_NOWAYOUT is not set
620 +
621 +#
622 +# Watchdog Device Drivers
623 +#
624 +# CONFIG_SOFT_WATCHDOG is not set
625 +CONFIG_AT32AP700X_WDT=y
626 +CONFIG_AT32AP700X_WDT_TIMEOUT=2
627 # CONFIG_HW_RANDOM is not set
628 # CONFIG_RTC is not set
629 # CONFIG_GEN_RTC is not set
630 @@ -636,7 +683,42 @@ CONFIG_UNIX98_PTYS=y
631 # TPM devices
632 #
633 # CONFIG_TCG_TPM is not set
634 -# CONFIG_I2C is not set
635 +CONFIG_I2C=m
636 +CONFIG_I2C_BOARDINFO=y
637 +CONFIG_I2C_CHARDEV=m
638 +
639 +#
640 +# I2C Algorithms
641 +#
642 +CONFIG_I2C_ALGOBIT=m
643 +# CONFIG_I2C_ALGOPCF is not set
644 +# CONFIG_I2C_ALGOPCA is not set
645 +
646 +#
647 +# I2C Hardware Bus support
648 +#
649 +CONFIG_I2C_ATMELTWI=m
650 +CONFIG_I2C_ATMELTWI_BAUDRATE=100000
651 +CONFIG_I2C_GPIO=m
652 +# CONFIG_I2C_OCORES is not set
653 +# CONFIG_I2C_PARPORT_LIGHT is not set
654 +# CONFIG_I2C_SIMTEC is not set
655 +# CONFIG_I2C_STUB is not set
656 +
657 +#
658 +# Miscellaneous I2C Chip support
659 +#
660 +# CONFIG_SENSORS_DS1337 is not set
661 +# CONFIG_SENSORS_DS1374 is not set
662 +# CONFIG_SENSORS_EEPROM is not set
663 +# CONFIG_SENSORS_PCF8574 is not set
664 +# CONFIG_SENSORS_PCA9539 is not set
665 +# CONFIG_SENSORS_PCF8591 is not set
666 +# CONFIG_SENSORS_MAX6875 is not set
667 +# CONFIG_I2C_DEBUG_CORE is not set
668 +# CONFIG_I2C_DEBUG_ALGO is not set
669 +# CONFIG_I2C_DEBUG_BUS is not set
670 +# CONFIG_I2C_DEBUG_CHIP is not set
671
672 #
673 # SPI support
674 @@ -655,7 +737,7 @@ CONFIG_SPI_ATMEL=y
675 # SPI Protocol Masters
676 #
677 # CONFIG_SPI_AT25 is not set
678 -# CONFIG_SPI_SPIDEV is not set
679 +CONFIG_SPI_SPIDEV=m
680
681 #
682 # Dallas's 1-wire bus
683 @@ -706,8 +788,41 @@ CONFIG_SPI_ATMEL=y
684 #
685 # USB Gadget Support
686 #
687 -# CONFIG_USB_GADGET is not set
688 -# CONFIG_MMC is not set
689 +CONFIG_USB_GADGET=y
690 +# CONFIG_USB_GADGET_DEBUG_FILES is not set
691 +CONFIG_USB_GADGET_SELECTED=y
692 +# CONFIG_USB_GADGET_FSL_USB2 is not set
693 +# CONFIG_USB_GADGET_NET2280 is not set
694 +# CONFIG_USB_GADGET_PXA2XX is not set
695 +# CONFIG_USB_GADGET_GOKU is not set
696 +# CONFIG_USB_GADGET_LH7A40X is not set
697 +CONFIG_USB_GADGET_ATMEL_USBA=y
698 +CONFIG_USB_ATMEL_USBA=y
699 +# CONFIG_USB_GADGET_OMAP is not set
700 +# CONFIG_USB_GADGET_AT91 is not set
701 +# CONFIG_USB_GADGET_DUMMY_HCD is not set
702 +CONFIG_USB_GADGET_DUALSPEED=y
703 +CONFIG_USB_ZERO=m
704 +CONFIG_USB_ETH=m
705 +CONFIG_USB_ETH_RNDIS=y
706 +CONFIG_USB_GADGETFS=m
707 +CONFIG_USB_FILE_STORAGE=m
708 +# CONFIG_USB_FILE_STORAGE_TEST is not set
709 +CONFIG_USB_G_SERIAL=m
710 +# CONFIG_USB_MIDI_GADGET is not set
711 +CONFIG_MMC=y
712 +# CONFIG_MMC_DEBUG is not set
713 +# CONFIG_MMC_UNSAFE_RESUME is not set
714 +
715 +#
716 +# MMC/SD Card Drivers
717 +#
718 +CONFIG_MMC_BLOCK=y
719 +
720 +#
721 +# MMC/SD Host Controller Drivers
722 +#
723 +CONFIG_MMC_ATMELMCI=y
724
725 #
726 # LED devices
727 @@ -727,27 +842,62 @@ CONFIG_LEDS_TRIGGERS=y
728 CONFIG_LEDS_TRIGGER_TIMER=y
729 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
730
731 +#
732 +# InfiniBand support
733 +#
734
735 #
736 -# LED drivers
737 +# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
738 #
739
740 #
741 -# LED Triggers
742 +# Real Time Clock
743 #
744 +CONFIG_RTC_LIB=y
745 +CONFIG_RTC_CLASS=y
746 +CONFIG_RTC_HCTOSYS=y
747 +CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
748 +# CONFIG_RTC_DEBUG is not set
749
750 #
751 -# InfiniBand support
752 +# RTC interfaces
753 #
754 +CONFIG_RTC_INTF_SYSFS=y
755 +CONFIG_RTC_INTF_PROC=y
756 +CONFIG_RTC_INTF_DEV=y
757 +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
758 +# CONFIG_RTC_DRV_TEST is not set
759
760 #
761 -# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
762 +# I2C RTC drivers
763 #
764 +# CONFIG_RTC_DRV_DS1307 is not set
765 +# CONFIG_RTC_DRV_DS1672 is not set
766 +# CONFIG_RTC_DRV_MAX6900 is not set
767 +# CONFIG_RTC_DRV_RS5C372 is not set
768 +# CONFIG_RTC_DRV_ISL1208 is not set
769 +# CONFIG_RTC_DRV_X1205 is not set
770 +# CONFIG_RTC_DRV_PCF8563 is not set
771 +# CONFIG_RTC_DRV_PCF8583 is not set
772
773 #
774 -# Real Time Clock
775 +# SPI RTC drivers
776 +#
777 +# CONFIG_RTC_DRV_RS5C348 is not set
778 +# CONFIG_RTC_DRV_MAX6902 is not set
779 +
780 +#
781 +# Platform RTC drivers
782 +#
783 +# CONFIG_RTC_DRV_DS1553 is not set
784 +# CONFIG_RTC_DRV_DS1742 is not set
785 +# CONFIG_RTC_DRV_M48T86 is not set
786 +# CONFIG_RTC_DRV_V3020 is not set
787 +
788 +#
789 +# on-CPU RTC drivers
790 #
791 -# CONFIG_RTC_CLASS is not set
792 +CONFIG_RTC_DRV_AT32AP700X=y
793
794 #
795 # DMA Engine support
796 @@ -781,7 +931,8 @@ CONFIG_JBD=y
797 # CONFIG_OCFS2_FS is not set
798 # CONFIG_MINIX_FS is not set
799 # CONFIG_ROMFS_FS is not set
800 -# CONFIG_INOTIFY is not set
801 +CONFIG_INOTIFY=y
802 +CONFIG_INOTIFY_USER=y
803 # CONFIG_QUOTA is not set
804 # CONFIG_DNOTIFY is not set
805 # CONFIG_AUTOFS_FS is not set
806 @@ -936,7 +1087,7 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y
807 CONFIG_ENABLE_MUST_CHECK=y
808 CONFIG_MAGIC_SYSRQ=y
809 # CONFIG_UNUSED_SYMBOLS is not set
810 -# CONFIG_DEBUG_FS is not set
811 +CONFIG_DEBUG_FS=y
812 # CONFIG_HEADERS_CHECK is not set
813 CONFIG_DEBUG_KERNEL=y
814 # CONFIG_DEBUG_SHIRQ is not set
815 diff --git a/arch/avr32/configs/atstk1002_defconfig b/arch/avr32/configs/atstk1002_defconfig
816 index 3b977fd..3708066 100644
817 --- a/arch/avr32/configs/atstk1002_defconfig
818 +++ b/arch/avr32/configs/atstk1002_defconfig
819 @@ -1,7 +1,7 @@
820 #
821 # Automatically generated make config: don't edit
822 -# Linux kernel version: 2.6.22-rc5
823 -# Sat Jun 23 15:32:08 2007
824 +# Linux kernel version: 2.6.22.atmel.2
825 +# Thu Jul 19 13:46:47 2007
826 #
827 CONFIG_AVR32=y
828 CONFIG_GENERIC_GPIO=y
829 @@ -80,10 +80,10 @@ CONFIG_BASE_SMALL=1
830 #
831 CONFIG_MODULES=y
832 CONFIG_MODULE_UNLOAD=y
833 -# CONFIG_MODULE_FORCE_UNLOAD is not set
834 +CONFIG_MODULE_FORCE_UNLOAD=y
835 # CONFIG_MODVERSIONS is not set
836 # CONFIG_MODULE_SRCVERSION_ALL is not set
837 -# CONFIG_KMOD is not set
838 +CONFIG_KMOD=y
839
840 #
841 # Block layer
842 @@ -99,12 +99,12 @@ CONFIG_BLOCK=y
843 CONFIG_IOSCHED_NOOP=y
844 # CONFIG_IOSCHED_AS is not set
845 # CONFIG_IOSCHED_DEADLINE is not set
846 -# CONFIG_IOSCHED_CFQ is not set
847 +CONFIG_IOSCHED_CFQ=y
848 # CONFIG_DEFAULT_AS is not set
849 # CONFIG_DEFAULT_DEADLINE is not set
850 -# CONFIG_DEFAULT_CFQ is not set
851 -CONFIG_DEFAULT_NOOP=y
852 -CONFIG_DEFAULT_IOSCHED="noop"
853 +CONFIG_DEFAULT_CFQ=y
854 +# CONFIG_DEFAULT_NOOP is not set
855 +CONFIG_DEFAULT_IOSCHED="cfq"
856
857 #
858 # System Type and features
859 @@ -117,6 +117,11 @@ CONFIG_CPU_AT32AP7000=y
860 CONFIG_BOARD_ATSTK1002=y
861 CONFIG_BOARD_ATSTK1000=y
862 # CONFIG_BOARD_ATNGW100 is not set
863 +# CONFIG_BOARD_ATSTK1002_CUSTOM is not set
864 +# CONFIG_BOARD_ATSTK1002_SPI1 is not set
865 +# CONFIG_BOARD_ATSTK1002_J2_LED is not set
866 +# CONFIG_BOARD_ATSTK1002_J2_LED8 is not set
867 +# CONFIG_BOARD_ATSTK1002_J2_RGB is not set
868 CONFIG_LOADER_U_BOOT=y
869
870 #
871 @@ -125,6 +130,7 @@ CONFIG_LOADER_U_BOOT=y
872 # CONFIG_AP7000_32_BIT_SMC is not set
873 CONFIG_AP7000_16_BIT_SMC=y
874 # CONFIG_AP7000_8_BIT_SMC is not set
875 +CONFIG_GPIO_DEV=y
876 CONFIG_LOAD_ADDRESS=0x10000000
877 CONFIG_ENTRY_ADDRESS=0x90000000
878 CONFIG_PHYS_OFFSET=0x10000000
879 @@ -148,6 +154,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
880 # CONFIG_RESOURCES_64BIT is not set
881 CONFIG_ZONE_DMA_FLAG=0
882 # CONFIG_OWNERSHIP_TRACE is not set
883 +CONFIG_DW_DMAC=y
884 # CONFIG_HZ_100 is not set
885 CONFIG_HZ_250=y
886 # CONFIG_HZ_300 is not set
887 @@ -156,6 +163,27 @@ CONFIG_HZ=250
888 CONFIG_CMDLINE=""
889
890 #
891 +# Power managment options
892 +#
893 +
894 +#
895 +# CPU Frequency scaling
896 +#
897 +CONFIG_CPU_FREQ=y
898 +CONFIG_CPU_FREQ_TABLE=y
899 +# CONFIG_CPU_FREQ_DEBUG is not set
900 +CONFIG_CPU_FREQ_STAT=m
901 +# CONFIG_CPU_FREQ_STAT_DETAILS is not set
902 +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
903 +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
904 +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
905 +CONFIG_CPU_FREQ_GOV_POWERSAVE=y
906 +CONFIG_CPU_FREQ_GOV_USERSPACE=y
907 +CONFIG_CPU_FREQ_GOV_ONDEMAND=y
908 +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
909 +CONFIG_CPU_FREQ_AT32AP=y
910 +
911 +#
912 # Bus options
913 #
914 # CONFIG_ARCH_SUPPORTS_MSI is not set
915 @@ -327,6 +355,8 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2
916 #
917 # Self-contained MTD device drivers
918 #
919 +CONFIG_MTD_DATAFLASH=m
920 +# CONFIG_MTD_M25P80 is not set
921 # CONFIG_MTD_SLRAM is not set
922 # CONFIG_MTD_PHRAM is not set
923 # CONFIG_MTD_MTDRAM is not set
924 @@ -373,7 +403,7 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
925 #
926 # Misc devices
927 #
928 -# CONFIG_BLINK is not set
929 +CONFIG_ATMEL_SSC=m
930 # CONFIG_IDE is not set
931
932 #
933 @@ -397,13 +427,26 @@ CONFIG_DUMMY=y
934 # CONFIG_BONDING is not set
935 # CONFIG_EQUALIZER is not set
936 CONFIG_TUN=m
937 -# CONFIG_PHYLIB is not set
938 +CONFIG_PHYLIB=y
939 +
940 +#
941 +# MII PHY device drivers
942 +#
943 +# CONFIG_MARVELL_PHY is not set
944 +# CONFIG_DAVICOM_PHY is not set
945 +# CONFIG_QSEMI_PHY is not set
946 +CONFIG_LXT_PHY=y
947 +# CONFIG_CICADA_PHY is not set
948 +# CONFIG_VITESSE_PHY is not set
949 +# CONFIG_SMSC_PHY is not set
950 +# CONFIG_BROADCOM_PHY is not set
951 +# CONFIG_FIXED_PHY is not set
952
953 #
954 # Ethernet (10 or 100Mbit)
955 #
956 CONFIG_NET_ETHERNET=y
957 -CONFIG_MII=y
958 +# CONFIG_MII is not set
959 CONFIG_MACB=y
960 # CONFIG_NETDEV_1000 is not set
961 # CONFIG_NETDEV_10000 is not set
962 @@ -443,7 +486,42 @@ CONFIG_SLHC=m
963 #
964 # Input device support
965 #
966 -# CONFIG_INPUT is not set
967 +CONFIG_INPUT=m
968 +# CONFIG_INPUT_FF_MEMLESS is not set
969 +CONFIG_INPUT_POLLDEV=m
970 +
971 +#
972 +# Userland interfaces
973 +#
974 +CONFIG_INPUT_MOUSEDEV=m
975 +CONFIG_INPUT_MOUSEDEV_PSAUX=y
976 +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
977 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
978 +# CONFIG_INPUT_JOYDEV is not set
979 +# CONFIG_INPUT_TSDEV is not set
980 +# CONFIG_INPUT_EVDEV is not set
981 +# CONFIG_INPUT_EVBUG is not set
982 +
983 +#
984 +# Input Device Drivers
985 +#
986 +CONFIG_INPUT_KEYBOARD=y
987 +# CONFIG_KEYBOARD_ATKBD is not set
988 +# CONFIG_KEYBOARD_SUNKBD is not set
989 +# CONFIG_KEYBOARD_LKKBD is not set
990 +# CONFIG_KEYBOARD_XTKBD is not set
991 +# CONFIG_KEYBOARD_NEWTON is not set
992 +# CONFIG_KEYBOARD_STOWAWAY is not set
993 +CONFIG_KEYBOARD_GPIO=m
994 +CONFIG_INPUT_MOUSE=y
995 +# CONFIG_MOUSE_PS2 is not set
996 +# CONFIG_MOUSE_SERIAL is not set
997 +# CONFIG_MOUSE_VSXXXAA is not set
998 +CONFIG_MOUSE_GPIO=m
999 +# CONFIG_INPUT_JOYSTICK is not set
1000 +# CONFIG_INPUT_TABLET is not set
1001 +# CONFIG_INPUT_TOUCHSCREEN is not set
1002 +# CONFIG_INPUT_MISC is not set
1003
1004 #
1005 # Hardware I/O ports
1006 @@ -477,7 +555,15 @@ CONFIG_UNIX98_PTYS=y
1007 # IPMI
1008 #
1009 # CONFIG_IPMI_HANDLER is not set
1010 -# CONFIG_WATCHDOG is not set
1011 +CONFIG_WATCHDOG=y
1012 +# CONFIG_WATCHDOG_NOWAYOUT is not set
1013 +
1014 +#
1015 +# Watchdog Device Drivers
1016 +#
1017 +# CONFIG_SOFT_WATCHDOG is not set
1018 +CONFIG_AT32AP700X_WDT=y
1019 +CONFIG_AT32AP700X_WDT_TIMEOUT=2
1020 # CONFIG_HW_RANDOM is not set
1021 # CONFIG_RTC is not set
1022 # CONFIG_GEN_RTC is not set
1023 @@ -488,13 +574,61 @@ CONFIG_UNIX98_PTYS=y
1024 # TPM devices
1025 #
1026 # CONFIG_TCG_TPM is not set
1027 -# CONFIG_I2C is not set
1028 +CONFIG_I2C=m
1029 +CONFIG_I2C_BOARDINFO=y
1030 +CONFIG_I2C_CHARDEV=m
1031 +
1032 +#
1033 +# I2C Algorithms
1034 +#
1035 +CONFIG_I2C_ALGOBIT=m
1036 +# CONFIG_I2C_ALGOPCF is not set
1037 +# CONFIG_I2C_ALGOPCA is not set
1038 +
1039 +#
1040 +# I2C Hardware Bus support
1041 +#
1042 +CONFIG_I2C_ATMELTWI=m
1043 +CONFIG_I2C_ATMELTWI_BAUDRATE=100000
1044 +CONFIG_I2C_GPIO=m
1045 +# CONFIG_I2C_OCORES is not set
1046 +# CONFIG_I2C_PARPORT_LIGHT is not set
1047 +# CONFIG_I2C_SIMTEC is not set
1048 +# CONFIG_I2C_STUB is not set
1049 +
1050 +#
1051 +# Miscellaneous I2C Chip support
1052 +#
1053 +# CONFIG_SENSORS_DS1337 is not set
1054 +# CONFIG_SENSORS_DS1374 is not set
1055 +# CONFIG_SENSORS_EEPROM is not set
1056 +# CONFIG_SENSORS_PCF8574 is not set
1057 +# CONFIG_SENSORS_PCA9539 is not set
1058 +# CONFIG_SENSORS_PCF8591 is not set
1059 +# CONFIG_SENSORS_MAX6875 is not set
1060 +# CONFIG_I2C_DEBUG_CORE is not set
1061 +# CONFIG_I2C_DEBUG_ALGO is not set
1062 +# CONFIG_I2C_DEBUG_BUS is not set
1063 +# CONFIG_I2C_DEBUG_CHIP is not set
1064
1065 #
1066 # SPI support
1067 #
1068 -# CONFIG_SPI is not set
1069 -# CONFIG_SPI_MASTER is not set
1070 +CONFIG_SPI=y
1071 +# CONFIG_SPI_DEBUG is not set
1072 +CONFIG_SPI_MASTER=y
1073 +
1074 +#
1075 +# SPI Master Controller Drivers
1076 +#
1077 +CONFIG_SPI_ATMEL=y
1078 +# CONFIG_SPI_BITBANG is not set
1079 +
1080 +#
1081 +# SPI Protocol Masters
1082 +#
1083 +# CONFIG_SPI_AT25 is not set
1084 +CONFIG_SPI_SPIDEV=m
1085
1086 #
1087 # Dallas's 1-wire bus
1088 @@ -517,19 +651,91 @@ CONFIG_UNIX98_PTYS=y
1089 #
1090 # Graphics support
1091 #
1092 -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
1093 +CONFIG_BACKLIGHT_LCD_SUPPORT=y
1094 +CONFIG_LCD_CLASS_DEVICE=y
1095 +CONFIG_LCD_LTV350QV=y
1096 +# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
1097
1098 #
1099 # Display device support
1100 #
1101 # CONFIG_DISPLAY_SUPPORT is not set
1102 # CONFIG_VGASTATE is not set
1103 -# CONFIG_FB is not set
1104 +CONFIG_FB=y
1105 +# CONFIG_FIRMWARE_EDID is not set
1106 +# CONFIG_FB_DDC is not set
1107 +CONFIG_FB_CFB_FILLRECT=y
1108 +CONFIG_FB_CFB_COPYAREA=y
1109 +CONFIG_FB_CFB_IMAGEBLIT=y
1110 +# CONFIG_FB_SYS_FILLRECT is not set
1111 +# CONFIG_FB_SYS_COPYAREA is not set
1112 +# CONFIG_FB_SYS_IMAGEBLIT is not set
1113 +# CONFIG_FB_SYS_FOPS is not set
1114 +CONFIG_FB_DEFERRED_IO=y
1115 +# CONFIG_FB_SVGALIB is not set
1116 +# CONFIG_FB_MACMODES is not set
1117 +# CONFIG_FB_BACKLIGHT is not set
1118 +# CONFIG_FB_MODE_HELPERS is not set
1119 +# CONFIG_FB_TILEBLITTING is not set
1120 +
1121 +#
1122 +# Frame buffer hardware drivers
1123 +#
1124 +# CONFIG_FB_S1D13XXX is not set
1125 +CONFIG_FB_ATMEL=y
1126 +# CONFIG_FB_VIRTUAL is not set
1127 +# CONFIG_LOGO is not set
1128
1129 #
1130 # Sound
1131 #
1132 -# CONFIG_SOUND is not set
1133 +CONFIG_SOUND=m
1134 +
1135 +#
1136 +# Advanced Linux Sound Architecture
1137 +#
1138 +CONFIG_SND=m
1139 +CONFIG_SND_TIMER=m
1140 +CONFIG_SND_PCM=m
1141 +# CONFIG_SND_SEQUENCER is not set
1142 +CONFIG_SND_OSSEMUL=y
1143 +CONFIG_SND_MIXER_OSS=m
1144 +CONFIG_SND_PCM_OSS=m
1145 +CONFIG_SND_PCM_OSS_PLUGINS=y
1146 +# CONFIG_SND_DYNAMIC_MINORS is not set
1147 +# CONFIG_SND_SUPPORT_OLD_API is not set
1148 +CONFIG_SND_VERBOSE_PROCFS=y
1149 +# CONFIG_SND_VERBOSE_PRINTK is not set
1150 +# CONFIG_SND_DEBUG is not set
1151 +
1152 +#
1153 +# Generic devices
1154 +#
1155 +# CONFIG_SND_DUMMY is not set
1156 +# CONFIG_SND_MTPAV is not set
1157 +# CONFIG_SND_SERIAL_U16550 is not set
1158 +# CONFIG_SND_MPU401 is not set
1159 +
1160 +#
1161 +# SPI devices
1162 +#
1163 +CONFIG_SND_AT73C213=m
1164 +CONFIG_SND_AT73C213_TARGET_BITRATE=48000
1165 +
1166 +#
1167 +# System on Chip audio support
1168 +#
1169 +# CONFIG_SND_SOC is not set
1170 +
1171 +#
1172 +# Open Sound System
1173 +#
1174 +# CONFIG_SOUND_PRIME is not set
1175 +
1176 +#
1177 +# HID Devices
1178 +#
1179 +# CONFIG_HID is not set
1180
1181 #
1182 # USB support
1183 @@ -545,21 +751,59 @@ CONFIG_UNIX98_PTYS=y
1184 #
1185 # USB Gadget Support
1186 #
1187 -# CONFIG_USB_GADGET is not set
1188 -# CONFIG_MMC is not set
1189 +CONFIG_USB_GADGET=y
1190 +# CONFIG_USB_GADGET_DEBUG_FILES is not set
1191 +CONFIG_USB_GADGET_SELECTED=y
1192 +# CONFIG_USB_GADGET_FSL_USB2 is not set
1193 +# CONFIG_USB_GADGET_NET2280 is not set
1194 +# CONFIG_USB_GADGET_PXA2XX is not set
1195 +# CONFIG_USB_GADGET_GOKU is not set
1196 +# CONFIG_USB_GADGET_LH7A40X is not set
1197 +CONFIG_USB_GADGET_ATMEL_USBA=y
1198 +CONFIG_USB_ATMEL_USBA=y
1199 +# CONFIG_USB_GADGET_OMAP is not set
1200 +# CONFIG_USB_GADGET_AT91 is not set
1201 +# CONFIG_USB_GADGET_DUMMY_HCD is not set
1202 +CONFIG_USB_GADGET_DUALSPEED=y
1203 +CONFIG_USB_ZERO=m
1204 +CONFIG_USB_ETH=m
1205 +CONFIG_USB_ETH_RNDIS=y
1206 +CONFIG_USB_GADGETFS=m
1207 +CONFIG_USB_FILE_STORAGE=m
1208 +# CONFIG_USB_FILE_STORAGE_TEST is not set
1209 +CONFIG_USB_G_SERIAL=m
1210 +# CONFIG_USB_MIDI_GADGET is not set
1211 +CONFIG_MMC=y
1212 +# CONFIG_MMC_DEBUG is not set
1213 +# CONFIG_MMC_UNSAFE_RESUME is not set
1214 +
1215 +#
1216 +# MMC/SD Card Drivers
1217 +#
1218 +CONFIG_MMC_BLOCK=y
1219 +
1220 +#
1221 +# MMC/SD Host Controller Drivers
1222 +#
1223 +CONFIG_MMC_ATMELMCI=y
1224
1225 #
1226 # LED devices
1227 #
1228 -# CONFIG_NEW_LEDS is not set
1229 +CONFIG_NEW_LEDS=y
1230 +CONFIG_LEDS_CLASS=m
1231
1232 #
1233 # LED drivers
1234 #
1235 +CONFIG_LEDS_GPIO=m
1236
1237 #
1238 # LED Triggers
1239 #
1240 +CONFIG_LEDS_TRIGGERS=y
1241 +CONFIG_LEDS_TRIGGER_TIMER=m
1242 +CONFIG_LEDS_TRIGGER_HEARTBEAT=m
1243
1244 #
1245 # InfiniBand support
1246 @@ -572,7 +816,50 @@ CONFIG_UNIX98_PTYS=y
1247 #
1248 # Real Time Clock
1249 #
1250 -# CONFIG_RTC_CLASS is not set
1251 +CONFIG_RTC_LIB=y
1252 +CONFIG_RTC_CLASS=y
1253 +# CONFIG_RTC_HCTOSYS is not set
1254 +# CONFIG_RTC_DEBUG is not set
1255 +
1256 +#
1257 +# RTC interfaces
1258 +#
1259 +CONFIG_RTC_INTF_SYSFS=y
1260 +CONFIG_RTC_INTF_PROC=y
1261 +CONFIG_RTC_INTF_DEV=y
1262 +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
1263 +# CONFIG_RTC_DRV_TEST is not set
1264 +
1265 +#
1266 +# I2C RTC drivers
1267 +#
1268 +# CONFIG_RTC_DRV_DS1307 is not set
1269 +# CONFIG_RTC_DRV_DS1672 is not set
1270 +# CONFIG_RTC_DRV_MAX6900 is not set
1271 +# CONFIG_RTC_DRV_RS5C372 is not set
1272 +# CONFIG_RTC_DRV_ISL1208 is not set
1273 +# CONFIG_RTC_DRV_X1205 is not set
1274 +# CONFIG_RTC_DRV_PCF8563 is not set
1275 +# CONFIG_RTC_DRV_PCF8583 is not set
1276 +
1277 +#
1278 +# SPI RTC drivers
1279 +#
1280 +# CONFIG_RTC_DRV_RS5C348 is not set
1281 +# CONFIG_RTC_DRV_MAX6902 is not set
1282 +
1283 +#
1284 +# Platform RTC drivers
1285 +#
1286 +# CONFIG_RTC_DRV_DS1553 is not set
1287 +# CONFIG_RTC_DRV_DS1742 is not set
1288 +# CONFIG_RTC_DRV_M48T86 is not set
1289 +# CONFIG_RTC_DRV_V3020 is not set
1290 +
1291 +#
1292 +# on-CPU RTC drivers
1293 +#
1294 +CONFIG_RTC_DRV_AT32AP700X=y
1295
1296 #
1297 # DMA Engine support
1298 @@ -590,11 +877,14 @@ CONFIG_UNIX98_PTYS=y
1299 #
1300 # File systems
1301 #
1302 -CONFIG_EXT2_FS=m
1303 +CONFIG_EXT2_FS=y
1304 # CONFIG_EXT2_FS_XATTR is not set
1305 # CONFIG_EXT2_FS_XIP is not set
1306 -# CONFIG_EXT3_FS is not set
1307 +CONFIG_EXT3_FS=y
1308 +# CONFIG_EXT3_FS_XATTR is not set
1309 # CONFIG_EXT4DEV_FS is not set
1310 +CONFIG_JBD=y
1311 +# CONFIG_JBD_DEBUG is not set
1312 # CONFIG_REISERFS_FS is not set
1313 # CONFIG_JFS_FS is not set
1314 # CONFIG_FS_POSIX_ACL is not set
1315 @@ -609,7 +899,7 @@ CONFIG_INOTIFY_USER=y
1316 # CONFIG_DNOTIFY is not set
1317 # CONFIG_AUTOFS_FS is not set
1318 # CONFIG_AUTOFS4_FS is not set
1319 -# CONFIG_FUSE_FS is not set
1320 +CONFIG_FUSE_FS=m
1321
1322 #
1323 # CD-ROM/DVD Filesystems
1324 @@ -638,7 +928,7 @@ CONFIG_TMPFS=y
1325 # CONFIG_TMPFS_POSIX_ACL is not set
1326 # CONFIG_HUGETLB_PAGE is not set
1327 CONFIG_RAMFS=y
1328 -CONFIG_CONFIGFS_FS=m
1329 +CONFIG_CONFIGFS_FS=y
1330
1331 #
1332 # Miscellaneous filesystems
1333 @@ -683,8 +973,14 @@ CONFIG_SUNRPC=y
1334 # CONFIG_SUNRPC_BIND34 is not set
1335 # CONFIG_RPCSEC_GSS_KRB5 is not set
1336 # CONFIG_RPCSEC_GSS_SPKM3 is not set
1337 -# CONFIG_SMB_FS is not set
1338 -# CONFIG_CIFS is not set
1339 +CONFIG_SMB_FS=m
1340 +# CONFIG_SMB_NLS_DEFAULT is not set
1341 +CONFIG_CIFS=m
1342 +# CONFIG_CIFS_STATS is not set
1343 +# CONFIG_CIFS_WEAK_PW_HASH is not set
1344 +# CONFIG_CIFS_XATTR is not set
1345 +# CONFIG_CIFS_DEBUG2 is not set
1346 +# CONFIG_CIFS_EXPERIMENTAL is not set
1347 # CONFIG_NCP_FS is not set
1348 # CONFIG_CODA_FS is not set
1349 # CONFIG_AFS_FS is not set
1350 diff --git a/arch/avr32/drivers/Makefile b/arch/avr32/drivers/Makefile
1351 new file mode 100644
1352 index 0000000..b429b75
1353 --- /dev/null
1354 +++ b/arch/avr32/drivers/Makefile
1355 @@ -0,0 +1 @@
1356 +obj-$(CONFIG_DW_DMAC) += dw-dmac.o
1357 diff --git a/arch/avr32/drivers/dw-dmac.c b/arch/avr32/drivers/dw-dmac.c
1358 new file mode 100644
1359 index 0000000..224eb30
1360 --- /dev/null
1361 +++ b/arch/avr32/drivers/dw-dmac.c
1362 @@ -0,0 +1,761 @@
1363 +/*
1364 + * Driver for the Synopsys DesignWare DMA Controller
1365 + *
1366 + * Copyright (C) 2005-2006 Atmel Corporation
1367 + *
1368 + * This program is free software; you can redistribute it and/or modify
1369 + * it under the terms of the GNU General Public License version 2 as
1370 + * published by the Free Software Foundation.
1371 + */
1372 +#include <linux/clk.h>
1373 +#include <linux/device.h>
1374 +#include <linux/dma-mapping.h>
1375 +#include <linux/dmapool.h>
1376 +#include <linux/init.h>
1377 +#include <linux/interrupt.h>
1378 +#include <linux/module.h>
1379 +#include <linux/platform_device.h>
1380 +
1381 +#include <asm/dma-controller.h>
1382 +#include <asm/io.h>
1383 +
1384 +#include "dw-dmac.h"
1385 +
1386 +#define DMAC_NR_CHANNELS 3
1387 +#define DMAC_MAX_BLOCKSIZE 4095
1388 +
1389 +enum {
1390 + CH_STATE_FREE = 0,
1391 + CH_STATE_ALLOCATED,
1392 + CH_STATE_BUSY,
1393 +};
1394 +
1395 +struct dw_dma_lli {
1396 + dma_addr_t sar;
1397 + dma_addr_t dar;
1398 + dma_addr_t llp;
1399 + u32 ctllo;
1400 + u32 ctlhi;
1401 + u32 sstat;
1402 + u32 dstat;
1403 +};
1404 +
1405 +struct dw_dma_block {
1406 + struct dw_dma_lli *lli_vaddr;
1407 + dma_addr_t lli_dma_addr;
1408 +};
1409 +
1410 +struct dw_dma_channel {
1411 + unsigned int state;
1412 + int is_cyclic;
1413 + struct dma_request_sg *req_sg;
1414 + struct dma_request_cyclic *req_cyclic;
1415 + unsigned int nr_blocks;
1416 + int direction;
1417 + struct dw_dma_block *block;
1418 +};
1419 +
1420 +struct dw_dma_controller {
1421 + spinlock_t lock;
1422 + void * __iomem regs;
1423 + struct dma_pool *lli_pool;
1424 + struct clk *hclk;
1425 + struct dma_controller dma;
1426 + struct dw_dma_channel channel[DMAC_NR_CHANNELS];
1427 +};
1428 +#define to_dw_dmac(dmac) container_of(dmac, struct dw_dma_controller, dma)
1429 +
1430 +#define dmac_writel_hi(dmac, reg, value) \
1431 + __raw_writel((value), (dmac)->regs + DW_DMAC_##reg + 4)
1432 +#define dmac_readl_hi(dmac, reg) \
1433 + __raw_readl((dmac)->regs + DW_DMAC_##reg + 4)
1434 +#define dmac_writel_lo(dmac, reg, value) \
1435 + __raw_writel((value), (dmac)->regs + DW_DMAC_##reg)
1436 +#define dmac_readl_lo(dmac, reg) \
1437 + __raw_readl((dmac)->regs + DW_DMAC_##reg)
1438 +#define dmac_chan_writel_hi(dmac, chan, reg, value) \
1439 + __raw_writel((value), ((dmac)->regs + 0x58 * (chan) \
1440 + + DW_DMAC_CHAN_##reg + 4))
1441 +#define dmac_chan_readl_hi(dmac, chan, reg) \
1442 + __raw_readl((dmac)->regs + 0x58 * (chan) + DW_DMAC_CHAN_##reg + 4)
1443 +#define dmac_chan_writel_lo(dmac, chan, reg, value) \
1444 + __raw_writel((value), (dmac)->regs + 0x58 * (chan) + DW_DMAC_CHAN_##reg)
1445 +#define dmac_chan_readl_lo(dmac, chan, reg) \
1446 + __raw_readl((dmac)->regs + 0x58 * (chan) + DW_DMAC_CHAN_##reg)
1447 +#define set_channel_bit(dmac, reg, chan) \
1448 + dmac_writel_lo(dmac, reg, (1 << (chan)) | (1 << ((chan) + 8)))
1449 +#define clear_channel_bit(dmac, reg, chan) \
1450 + dmac_writel_lo(dmac, reg, (0 << (chan)) | (1 << ((chan) + 8)))
1451 +
1452 +static int dmac_alloc_channel(struct dma_controller *_dmac)
1453 +{
1454 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
1455 + struct dw_dma_channel *chan;
1456 + unsigned long flags;
1457 + int i;
1458 +
1459 + spin_lock_irqsave(&dmac->lock, flags);
1460 + for (i = 0; i < DMAC_NR_CHANNELS; i++)
1461 + if (dmac->channel[i].state == CH_STATE_FREE)
1462 + break;
1463 +
1464 + if (i < DMAC_NR_CHANNELS) {
1465 + chan = &dmac->channel[i];
1466 + chan->state = CH_STATE_ALLOCATED;
1467 + } else {
1468 + i = -EBUSY;
1469 + }
1470 +
1471 + spin_unlock_irqrestore(&dmac->lock, flags);
1472 +
1473 + return i;
1474 +}
1475 +
1476 +static void dmac_release_channel(struct dma_controller *_dmac, int channel)
1477 +{
1478 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
1479 +
1480 + BUG_ON(channel >= DMAC_NR_CHANNELS
1481 + || dmac->channel[channel].state != CH_STATE_ALLOCATED);
1482 +
1483 + dmac->channel[channel].state = CH_STATE_FREE;
1484 +}
1485 +
1486 +static struct dw_dma_block *allocate_blocks(struct dw_dma_controller *dmac,
1487 + unsigned int nr_blocks)
1488 +{
1489 + struct dw_dma_block *block;
1490 + void *p;
1491 + unsigned int i;
1492 +
1493 + block = kmalloc(nr_blocks * sizeof(*block),
1494 + GFP_KERNEL);
1495 + if (unlikely(!block))
1496 + return NULL;
1497 +
1498 + for (i = 0; i < nr_blocks; i++) {
1499 + p = dma_pool_alloc(dmac->lli_pool, GFP_KERNEL,
1500 + &block[i].lli_dma_addr);
1501 + block[i].lli_vaddr = p;
1502 + if (unlikely(!p))
1503 + goto fail;
1504 + }
1505 +
1506 + return block;
1507 +
1508 +fail:
1509 + for (i = 0; i < nr_blocks; i++) {
1510 + if (!block[i].lli_vaddr)
1511 + break;
1512 + dma_pool_free(dmac->lli_pool, block[i].lli_vaddr,
1513 + block[i].lli_dma_addr);
1514 + }
1515 + kfree(block);
1516 + return NULL;
1517 +}
1518 +
1519 +static void cleanup_channel(struct dw_dma_controller *dmac,
1520 + struct dw_dma_channel *chan)
1521 +{
1522 + unsigned int i;
1523 +
1524 + if (chan->nr_blocks > 1) {
1525 + for (i = 0; i < chan->nr_blocks; i++)
1526 + dma_pool_free(dmac->lli_pool, chan->block[i].lli_vaddr,
1527 + chan->block[i].lli_dma_addr);
1528 + kfree(chan->block);
1529 + }
1530 +
1531 + chan->state = CH_STATE_ALLOCATED;
1532 +}
1533 +
1534 +static int dmac_prepare_request_sg(struct dma_controller *_dmac,
1535 + struct dma_request_sg *req)
1536 +{
1537 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
1538 + struct dw_dma_channel *chan;
1539 + unsigned long ctlhi, ctllo, cfghi, cfglo;
1540 + unsigned long block_size;
1541 + unsigned int nr_blocks;
1542 + int ret, i, direction;
1543 + unsigned long flags;
1544 +
1545 + spin_lock_irqsave(&dmac->lock, flags);
1546 +
1547 + ret = -EINVAL;
1548 + if (req->req.channel >= DMAC_NR_CHANNELS
1549 + || dmac->channel[req->req.channel].state != CH_STATE_ALLOCATED
1550 + || req->block_size > DMAC_MAX_BLOCKSIZE) {
1551 + spin_unlock_irqrestore(&dmac->lock, flags);
1552 + return -EINVAL;
1553 + }
1554 +
1555 + chan = &dmac->channel[req->req.channel];
1556 + chan->state = CH_STATE_BUSY;
1557 + chan->req_sg = req;
1558 + chan->is_cyclic = 0;
1559 +
1560 + /*
1561 + * We have marked the channel as busy, so no need to keep the
1562 + * lock as long as we only touch the channel-specific
1563 + * registers
1564 + */
1565 + spin_unlock_irqrestore(&dmac->lock, flags);
1566 +
1567 + /*
1568 + * There may be limitations in the driver and/or the DMA
1569 + * controller that prevents us from sending a whole
1570 + * scatterlist item in one go. Taking this into account,
1571 + * calculate the number of block transfers we need to set up.
1572 + *
1573 + * FIXME: Let the peripheral driver know about the maximum
1574 + * block size we support. We really don't want to use a
1575 + * different block size than what was suggested by the
1576 + * peripheral.
1577 + *
1578 + * Each block will get its own Linked List Item (LLI) below.
1579 + */
1580 + block_size = req->block_size;
1581 + nr_blocks = req->nr_blocks;
1582 + pr_debug("block_size %lu, nr_blocks %u nr_sg = %u\n",
1583 + block_size, nr_blocks, req->nr_sg);
1584 +
1585 + BUG_ON(nr_blocks == 0);
1586 + chan->nr_blocks = nr_blocks;
1587 +
1588 + ret = -EINVAL;
1589 + cfglo = cfghi = 0;
1590 + switch (req->direction) {
1591 + case DMA_DIR_MEM_TO_PERIPH:
1592 + direction = DMA_TO_DEVICE;
1593 + cfghi = req->periph_id << (43 - 32);
1594 + break;
1595 +
1596 + case DMA_DIR_PERIPH_TO_MEM:
1597 + direction = DMA_FROM_DEVICE;
1598 + cfghi = req->periph_id << (39 - 32);
1599 + break;
1600 + default:
1601 + goto out_unclaim_channel;
1602 + }
1603 +
1604 + chan->direction = direction;
1605 +
1606 + dmac_chan_writel_hi(dmac, req->req.channel, CFG, cfghi);
1607 + dmac_chan_writel_lo(dmac, req->req.channel, CFG, cfglo);
1608 +
1609 + ctlhi = block_size >> req->width;
1610 + ctllo = ((req->direction << 20)
1611 + // | (1 << 14) | (1 << 11) // source/dest burst trans len
1612 + | (req->width << 4) | (req->width << 1)
1613 + | (1 << 0)); // interrupt enable
1614 +
1615 + if (nr_blocks == 1) {
1616 + /* Only one block: No need to use block chaining */
1617 + if (direction == DMA_TO_DEVICE) {
1618 + dmac_chan_writel_lo(dmac, req->req.channel, SAR,
1619 + req->sg->dma_address);
1620 + dmac_chan_writel_lo(dmac, req->req.channel, DAR,
1621 + req->data_reg);
1622 + ctllo |= 2 << 7; // no dst increment
1623 + } else {
1624 + dmac_chan_writel_lo(dmac, req->req.channel, SAR,
1625 + req->data_reg);
1626 + dmac_chan_writel_lo(dmac, req->req.channel, DAR,
1627 + req->sg->dma_address);
1628 + ctllo |= 2 << 9; // no src increment
1629 + }
1630 + dmac_chan_writel_lo(dmac, req->req.channel, CTL, ctllo);
1631 + dmac_chan_writel_hi(dmac, req->req.channel, CTL, ctlhi);
1632 + pr_debug("ctl hi:lo 0x%lx:%lx\n", ctlhi, ctllo);
1633 + } else {
1634 + struct dw_dma_lli *lli, *lli_prev = NULL;
1635 + int j = 0, offset = 0;
1636 +
1637 + ret = -ENOMEM;
1638 + chan->block = allocate_blocks(dmac, nr_blocks);
1639 + if (!chan->block)
1640 + goto out_unclaim_channel;
1641 +
1642 + if (direction == DMA_TO_DEVICE)
1643 + ctllo |= 1 << 28 | 1 << 27 | 2 << 7;
1644 + else
1645 + ctllo |= 1 << 28 | 1 << 27 | 2 << 9;
1646 +
1647 + /*
1648 + * Map scatterlist items to blocks. One scatterlist
1649 + * item may need more than one block for the reasons
1650 + * mentioned above.
1651 + */
1652 + for (i = 0; i < nr_blocks; i++) {
1653 + lli = chan->block[i].lli_vaddr;
1654 + if (lli_prev) {
1655 + lli_prev->llp = chan->block[i].lli_dma_addr;
1656 + pr_debug("lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
1657 + i - 1, chan->block[i - 1].lli_vaddr,
1658 + chan->block[i - 1].lli_dma_addr,
1659 + lli_prev->sar, lli_prev->dar, lli_prev->llp,
1660 + lli_prev->ctllo, lli_prev->ctlhi);
1661 + }
1662 + lli->llp = 0;
1663 + lli->ctllo = ctllo;
1664 + lli->ctlhi = ctlhi;
1665 + if (direction == DMA_TO_DEVICE) {
1666 + lli->sar = req->sg[j].dma_address + offset;
1667 + lli->dar = req->data_reg;
1668 + } else {
1669 + lli->sar = req->data_reg;
1670 + lli->dar = req->sg[j].dma_address + offset;
1671 + }
1672 + lli_prev = lli;
1673 +
1674 + offset += block_size;
1675 + if (offset > req->sg[j].length) {
1676 + j++;
1677 + offset = 0;
1678 + }
1679 + }
1680 +
1681 + pr_debug("lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
1682 + i - 1, chan->block[i - 1].lli_vaddr,
1683 + chan->block[i - 1].lli_dma_addr, lli_prev->sar,
1684 + lli_prev->dar, lli_prev->llp,
1685 + lli_prev->ctllo, lli_prev->ctlhi);
1686 +
1687 + /*
1688 + * SAR, DAR and CTL are initialized from the LLI. We
1689 + * only have to enable the LLI bits in CTL.
1690 + */
1691 + dmac_chan_writel_hi(dmac, req->req.channel, CTL, 0);
1692 + dmac_chan_writel_lo(dmac, req->req.channel, LLP,
1693 + chan->block[0].lli_dma_addr);
1694 + dmac_chan_writel_lo(dmac, req->req.channel, CTL, 1 << 28 | 1 << 27);
1695 + }
1696 +
1697 + set_channel_bit(dmac, MASK_XFER, req->req.channel);
1698 + set_channel_bit(dmac, MASK_ERROR, req->req.channel);
1699 + if (req->req.block_complete)
1700 + set_channel_bit(dmac, MASK_BLOCK, req->req.channel);
1701 + else
1702 + clear_channel_bit(dmac, MASK_BLOCK, req->req.channel);
1703 +
1704 + return 0;
1705 +
1706 +out_unclaim_channel:
1707 + chan->state = CH_STATE_ALLOCATED;
1708 + return ret;
1709 +}
1710 +
1711 +static int dmac_prepare_request_cyclic(struct dma_controller *_dmac,
1712 + struct dma_request_cyclic *req)
1713 +{
1714 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
1715 + struct dw_dma_channel *chan;
1716 + unsigned long ctlhi, ctllo, cfghi, cfglo;
1717 + unsigned long block_size;
1718 + int ret, i, direction;
1719 + unsigned long flags;
1720 +
1721 + spin_lock_irqsave(&dmac->lock, flags);
1722 +
1723 + block_size = (req->buffer_size/req->periods) >> req->width;
1724 +
1725 + ret = -EINVAL;
1726 + if (req->req.channel >= DMAC_NR_CHANNELS
1727 + || dmac->channel[req->req.channel].state != CH_STATE_ALLOCATED
1728 + || (req->periods == 0)
1729 + || block_size > DMAC_MAX_BLOCKSIZE) {
1730 + spin_unlock_irqrestore(&dmac->lock, flags);
1731 + return -EINVAL;
1732 + }
1733 +
1734 + chan = &dmac->channel[req->req.channel];
1735 + chan->state = CH_STATE_BUSY;
1736 + chan->is_cyclic = 1;
1737 + chan->req_cyclic = req;
1738 +
1739 + /*
1740 + * We have marked the channel as busy, so no need to keep the
1741 + * lock as long as we only touch the channel-specific
1742 + * registers
1743 + */
1744 + spin_unlock_irqrestore(&dmac->lock, flags);
1745 +
1746 + /*
1747 + Setup
1748 + */
1749 + BUG_ON(req->buffer_size % req->periods);
1750 + /* printk(KERN_INFO "block_size = %lu, periods = %u\n", block_size, req->periods); */
1751 +
1752 + chan->nr_blocks = req->periods;
1753 +
1754 + ret = -EINVAL;
1755 + cfglo = cfghi = 0;
1756 + switch (req->direction) {
1757 + case DMA_DIR_MEM_TO_PERIPH:
1758 + direction = DMA_TO_DEVICE;
1759 + cfghi = req->periph_id << (43 - 32);
1760 + break;
1761 +
1762 + case DMA_DIR_PERIPH_TO_MEM:
1763 + direction = DMA_FROM_DEVICE;
1764 + cfghi = req->periph_id << (39 - 32);
1765 + break;
1766 + default:
1767 + goto out_unclaim_channel;
1768 + }
1769 +
1770 + chan->direction = direction;
1771 +
1772 + dmac_chan_writel_hi(dmac, req->req.channel, CFG, cfghi);
1773 + dmac_chan_writel_lo(dmac, req->req.channel, CFG, cfglo);
1774 +
1775 + ctlhi = block_size;
1776 + ctllo = ((req->direction << 20)
1777 + | (req->width << 4) | (req->width << 1)
1778 + | (1 << 0)); // interrupt enable
1779 +
1780 + {
1781 + struct dw_dma_lli *lli = NULL, *lli_prev = NULL;
1782 +
1783 + ret = -ENOMEM;
1784 + chan->block = allocate_blocks(dmac, req->periods);
1785 + if (!chan->block)
1786 + goto out_unclaim_channel;
1787 +
1788 + if (direction == DMA_TO_DEVICE)
1789 + ctllo |= 1 << 28 | 1 << 27 | 2 << 7;
1790 + else
1791 + ctllo |= 1 << 28 | 1 << 27 | 2 << 9;
1792 +
1793 + /*
1794 + * Set up a linked list items where each period gets
1795 + * an item. The linked list item for the last period
1796 + * points back to the star of the buffer making a
1797 + * cyclic buffer.
1798 + */
1799 + for (i = 0; i < req->periods; i++) {
1800 + lli = chan->block[i].lli_vaddr;
1801 + if (lli_prev) {
1802 + lli_prev->llp = chan->block[i].lli_dma_addr;
1803 + /* printk(KERN_INFO "lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
1804 + i - 1, chan->block[i - 1].lli_vaddr,
1805 + chan->block[i - 1].lli_dma_addr,
1806 + lli_prev->sar, lli_prev->dar, lli_prev->llp,
1807 + lli_prev->ctllo, lli_prev->ctlhi);*/
1808 + }
1809 + lli->llp = 0;
1810 + lli->ctllo = ctllo;
1811 + lli->ctlhi = ctlhi;
1812 + if (direction == DMA_TO_DEVICE) {
1813 + lli->sar = req->buffer_start + i*(block_size << req->width);
1814 + lli->dar = req->data_reg;
1815 + } else {
1816 + lli->sar = req->data_reg;
1817 + lli->dar = req->buffer_start + i*(block_size << req->width);
1818 + }
1819 + lli_prev = lli;
1820 + }
1821 + lli->llp = chan->block[0].lli_dma_addr;
1822 +
1823 + /*printk(KERN_INFO "lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
1824 + i - 1, chan->block[i - 1].lli_vaddr,
1825 + chan->block[i - 1].lli_dma_addr, lli_prev->sar,
1826 + lli_prev->dar, lli_prev->llp,
1827 + lli_prev->ctllo, lli_prev->ctlhi); */
1828 +
1829 + /*
1830 + * SAR, DAR and CTL are initialized from the LLI. We
1831 + * only have to enable the LLI bits in CTL.
1832 + */
1833 + dmac_chan_writel_lo(dmac, req->req.channel, LLP,
1834 + chan->block[0].lli_dma_addr);
1835 + dmac_chan_writel_lo(dmac, req->req.channel, CTL, 1 << 28 | 1 << 27);
1836 + }
1837 +
1838 + clear_channel_bit(dmac, MASK_XFER, req->req.channel);
1839 + set_channel_bit(dmac, MASK_ERROR, req->req.channel);
1840 + if (req->req.block_complete)
1841 + set_channel_bit(dmac, MASK_BLOCK, req->req.channel);
1842 + else
1843 + clear_channel_bit(dmac, MASK_BLOCK, req->req.channel);
1844 +
1845 + return 0;
1846 +
1847 +out_unclaim_channel:
1848 + chan->state = CH_STATE_ALLOCATED;
1849 + return ret;
1850 +}
1851 +
1852 +static int dmac_start_request(struct dma_controller *_dmac,
1853 + unsigned int channel)
1854 +{
1855 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
1856 +
1857 + BUG_ON(channel >= DMAC_NR_CHANNELS);
1858 +
1859 + set_channel_bit(dmac, CH_EN, channel);
1860 +
1861 + return 0;
1862 +}
1863 +
1864 +static dma_addr_t dmac_get_current_pos(struct dma_controller *_dmac,
1865 + unsigned int channel)
1866 +{
1867 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
1868 + struct dw_dma_channel *chan;
1869 + dma_addr_t current_pos;
1870 +
1871 + BUG_ON(channel >= DMAC_NR_CHANNELS);
1872 +
1873 + chan = &dmac->channel[channel];
1874 +
1875 + switch (chan->direction) {
1876 + case DMA_TO_DEVICE:
1877 + current_pos = dmac_chan_readl_lo(dmac, channel, SAR);
1878 + break;
1879 + case DMA_FROM_DEVICE:
1880 + current_pos = dmac_chan_readl_lo(dmac, channel, DAR);
1881 + break;
1882 + default:
1883 + return 0;
1884 + }
1885 +
1886 +
1887 + if (!current_pos) {
1888 + if (chan->is_cyclic) {
1889 + current_pos = chan->req_cyclic->buffer_start;
1890 + } else {
1891 + current_pos = chan->req_sg->sg->dma_address;
1892 + }
1893 + }
1894 +
1895 + return current_pos;
1896 +}
1897 +
1898 +
1899 +static int dmac_stop_request(struct dma_controller *_dmac,
1900 + unsigned int channel)
1901 +{
1902 + struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
1903 + struct dw_dma_channel *chan;
1904 +
1905 + BUG_ON(channel >= DMAC_NR_CHANNELS);
1906 +
1907 + chan = &dmac->channel[channel];
1908 + pr_debug("stop: st%u s%08x d%08x l%08x ctl0x%08x:0x%08x\n",
1909 + chan->state, dmac_chan_readl_lo(dmac, channel, SAR),
1910 + dmac_chan_readl_lo(dmac, channel, DAR),
1911 + dmac_chan_readl_lo(dmac, channel, LLP),
1912 + dmac_chan_readl_hi(dmac, channel, CTL),
1913 + dmac_chan_readl_lo(dmac, channel, CTL));
1914 +
1915 + if (chan->state == CH_STATE_BUSY) {
1916 + clear_channel_bit(dmac, CH_EN, channel);
1917 + cleanup_channel(dmac, &dmac->channel[channel]);
1918 + }
1919 +
1920 + return 0;
1921 +}
1922 +
1923 +
1924 +static void dmac_block_complete(struct dw_dma_controller *dmac)
1925 +{
1926 + struct dw_dma_channel *chan;
1927 + unsigned long status, chanid;
1928 +
1929 + status = dmac_readl_lo(dmac, STATUS_BLOCK);
1930 +
1931 + while (status) {
1932 + struct dma_request *req;
1933 + chanid = __ffs(status);
1934 + chan = &dmac->channel[chanid];
1935 +
1936 + if (chan->is_cyclic) {
1937 + BUG_ON(!chan->req_cyclic
1938 + || !chan->req_cyclic->req.block_complete);
1939 + req = &chan->req_cyclic->req;
1940 + } else {
1941 + BUG_ON(!chan->req_sg || !chan->req_sg->req.block_complete);
1942 + req = &chan->req_sg->req;
1943 + }
1944 + dmac_writel_lo(dmac, CLEAR_BLOCK, 1 << chanid);
1945 + req->block_complete(req);
1946 + status = dmac_readl_lo(dmac, STATUS_BLOCK);
1947 + }
1948 +}
1949 +
1950 +static void dmac_xfer_complete(struct dw_dma_controller *dmac)
1951 +{
1952 + struct dw_dma_channel *chan;
1953 + struct dma_request *req;
1954 + unsigned long status, chanid;
1955 +
1956 + status = dmac_readl_lo(dmac, STATUS_XFER);
1957 +
1958 + while (status) {
1959 + chanid = __ffs(status);
1960 + chan = &dmac->channel[chanid];
1961 +
1962 + dmac_writel_lo(dmac, CLEAR_XFER, 1 << chanid);
1963 +
1964 + req = &chan->req_sg->req;
1965 + BUG_ON(!req);
1966 + cleanup_channel(dmac, chan);
1967 + if (req->xfer_complete)
1968 + req->xfer_complete(req);
1969 +
1970 + status = dmac_readl_lo(dmac, STATUS_XFER);
1971 + }
1972 +}
1973 +
1974 +static void dmac_error(struct dw_dma_controller *dmac)
1975 +{
1976 + struct dw_dma_channel *chan;
1977 + unsigned long status, chanid;
1978 +
1979 + status = dmac_readl_lo(dmac, STATUS_ERROR);
1980 +
1981 + while (status) {
1982 + struct dma_request *req;
1983 +
1984 + chanid = __ffs(status);
1985 + chan = &dmac->channel[chanid];
1986 +
1987 + dmac_writel_lo(dmac, CLEAR_ERROR, 1 << chanid);
1988 + clear_channel_bit(dmac, CH_EN, chanid);
1989 +
1990 + if (chan->is_cyclic) {
1991 + BUG_ON(!chan->req_cyclic);
1992 + req = &chan->req_cyclic->req;
1993 + } else {
1994 + BUG_ON(!chan->req_sg);
1995 + req = &chan->req_sg->req;
1996 + }
1997 +
1998 + cleanup_channel(dmac, chan);
1999 + if (req->error)
2000 + req->error(req);
2001 +
2002 + status = dmac_readl_lo(dmac, STATUS_XFER);
2003 + }
2004 +}
2005 +
2006 +static irqreturn_t dmac_interrupt(int irq, void *dev_id)
2007 +{
2008 + struct dw_dma_controller *dmac = dev_id;
2009 + unsigned long status;
2010 + int ret = IRQ_NONE;
2011 +
2012 + spin_lock(&dmac->lock);
2013 +
2014 + status = dmac_readl_lo(dmac, STATUS_INT);
2015 +
2016 + while (status) {
2017 + ret = IRQ_HANDLED;
2018 + if (status & 0x10)
2019 + dmac_error(dmac);
2020 + if (status & 0x02)
2021 + dmac_block_complete(dmac);
2022 + if (status & 0x01)
2023 + dmac_xfer_complete(dmac);
2024 +
2025 + status = dmac_readl_lo(dmac, STATUS_INT);
2026 + }
2027 +
2028 + spin_unlock(&dmac->lock);
2029 + return ret;
2030 +}
2031 +
2032 +static int __devinit dmac_probe(struct platform_device *pdev)
2033 +{
2034 + struct dw_dma_controller *dmac;
2035 + struct resource *regs;
2036 + int ret;
2037 +
2038 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2039 + if (!regs)
2040 + return -ENXIO;
2041 +
2042 + dmac = kmalloc(sizeof(*dmac), GFP_KERNEL);
2043 + if (!dmac)
2044 + return -ENOMEM;
2045 + memset(dmac, 0, sizeof(*dmac));
2046 +
2047 + dmac->hclk = clk_get(&pdev->dev, "hclk");
2048 + if (IS_ERR(dmac->hclk)) {
2049 + ret = PTR_ERR(dmac->hclk);
2050 + goto out_free_dmac;
2051 + }
2052 + clk_enable(dmac->hclk);
2053 +
2054 + ret = -ENOMEM;
2055 + dmac->lli_pool = dma_pool_create("dmac", &pdev->dev,
2056 + sizeof(struct dw_dma_lli), 4, 0);
2057 + if (!dmac->lli_pool)
2058 + goto out_disable_clk;
2059 +
2060 + spin_lock_init(&dmac->lock);
2061 + dmac->dma.dev = &pdev->dev;
2062 + dmac->dma.alloc_channel = dmac_alloc_channel;
2063 + dmac->dma.release_channel = dmac_release_channel;
2064 + dmac->dma.prepare_request_sg = dmac_prepare_request_sg;
2065 + dmac->dma.prepare_request_cyclic = dmac_prepare_request_cyclic;
2066 + dmac->dma.start_request = dmac_start_request;
2067 + dmac->dma.stop_request = dmac_stop_request;
2068 + dmac->dma.get_current_pos = dmac_get_current_pos;
2069 +
2070 + dmac->regs = ioremap(regs->start, regs->end - regs->start + 1);
2071 + if (!dmac->regs)
2072 + goto out_free_pool;
2073 +
2074 + ret = request_irq(platform_get_irq(pdev, 0), dmac_interrupt,
2075 + IRQF_SAMPLE_RANDOM, pdev->name, dmac);
2076 + if (ret)
2077 + goto out_unmap_regs;
2078 +
2079 + /* Enable the DMA controller */
2080 + dmac_writel_lo(dmac, CFG, 1);
2081 +
2082 + register_dma_controller(&dmac->dma);
2083 +
2084 + printk(KERN_INFO
2085 + "dmac%d: DesignWare DMA controller at 0x%p irq %d\n",
2086 + dmac->dma.id, dmac->regs, platform_get_irq(pdev, 0));
2087 +
2088 + return 0;
2089 +
2090 +out_unmap_regs:
2091 + iounmap(dmac->regs);
2092 +out_free_pool:
2093 + dma_pool_destroy(dmac->lli_pool);
2094 +out_disable_clk:
2095 + clk_disable(dmac->hclk);
2096 + clk_put(dmac->hclk);
2097 +out_free_dmac:
2098 + kfree(dmac);
2099 + return ret;
2100 +}
2101 +
2102 +static struct platform_driver dmac_driver = {
2103 + .probe = dmac_probe,
2104 + .driver = {
2105 + .name = "dmaca",
2106 + },
2107 +};
2108 +
2109 +static int __init dmac_init(void)
2110 +{
2111 + return platform_driver_register(&dmac_driver);
2112 +}
2113 +subsys_initcall(dmac_init);
2114 +
2115 +static void __exit dmac_exit(void)
2116 +{
2117 + platform_driver_unregister(&dmac_driver);
2118 +}
2119 +module_exit(dmac_exit);
2120 +
2121 +MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver");
2122 +MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
2123 +MODULE_LICENSE("GPL");
2124 diff --git a/arch/avr32/drivers/dw-dmac.h b/arch/avr32/drivers/dw-dmac.h
2125 new file mode 100644
2126 index 0000000..1f67921
2127 --- /dev/null
2128 +++ b/arch/avr32/drivers/dw-dmac.h
2129 @@ -0,0 +1,42 @@
2130 +/*
2131 + * Driver for the Synopsys DesignWare DMA Controller
2132 + *
2133 + * Copyright (C) 2005-2006 Atmel Corporation
2134 + *
2135 + * This program is free software; you can redistribute it and/or modify
2136 + * it under the terms of the GNU General Public License version 2 as
2137 + * published by the Free Software Foundation.
2138 + */
2139 +#ifndef __AVR32_DW_DMAC_H__
2140 +#define __AVR32_DW_DMAC_H__
2141 +
2142 +#define DW_DMAC_CFG 0x398
2143 +#define DW_DMAC_CH_EN 0x3a0
2144 +
2145 +#define DW_DMAC_STATUS_XFER 0x2e8
2146 +#define DW_DMAC_STATUS_BLOCK 0x2f0
2147 +#define DW_DMAC_STATUS_ERROR 0x308
2148 +
2149 +#define DW_DMAC_MASK_XFER 0x310
2150 +#define DW_DMAC_MASK_BLOCK 0x318
2151 +#define DW_DMAC_MASK_ERROR 0x330
2152 +
2153 +#define DW_DMAC_CLEAR_XFER 0x338
2154 +#define DW_DMAC_CLEAR_BLOCK 0x340
2155 +#define DW_DMAC_CLEAR_ERROR 0x358
2156 +
2157 +#define DW_DMAC_STATUS_INT 0x360
2158 +
2159 +#define DW_DMAC_CHAN_SAR 0x000
2160 +#define DW_DMAC_CHAN_DAR 0x008
2161 +#define DW_DMAC_CHAN_LLP 0x010
2162 +#define DW_DMAC_CHAN_CTL 0x018
2163 +#define DW_DMAC_CHAN_SSTAT 0x020
2164 +#define DW_DMAC_CHAN_DSTAT 0x028
2165 +#define DW_DMAC_CHAN_SSTATAR 0x030
2166 +#define DW_DMAC_CHAN_DSTATAR 0x038
2167 +#define DW_DMAC_CHAN_CFG 0x040
2168 +#define DW_DMAC_CHAN_SGR 0x048
2169 +#define DW_DMAC_CHAN_DSR 0x050
2170 +
2171 +#endif /* __AVR32_DW_DMAC_H__ */
2172 diff --git a/arch/avr32/kernel/Makefile b/arch/avr32/kernel/Makefile
2173 index 90e5aff..1aedaeb 100644
2174 --- a/arch/avr32/kernel/Makefile
2175 +++ b/arch/avr32/kernel/Makefile
2176 @@ -9,10 +9,6 @@ obj-y += syscall_table.o syscall-stubs.o irq.o
2177 obj-y += setup.o traps.o semaphore.o ptrace.o
2178 obj-y += signal.o sys_avr32.o process.o time.o
2179 obj-y += init_task.o switch_to.o cpu.o
2180 +obj-y += dma-controller.o
2181 obj-$(CONFIG_MODULES) += module.o avr32_ksyms.o
2182 obj-$(CONFIG_KPROBES) += kprobes.o
2183 -
2184 -USE_STANDARD_AS_RULE := true
2185 -
2186 -%.lds: %.lds.c FORCE
2187 - $(call if_changed_dep,cpp_lds_S)
2188 diff --git a/arch/avr32/kernel/dma-controller.c b/arch/avr32/kernel/dma-controller.c
2189 new file mode 100644
2190 index 0000000..fb654b3
2191 --- /dev/null
2192 +++ b/arch/avr32/kernel/dma-controller.c
2193 @@ -0,0 +1,34 @@
2194 +/*
2195 + * Preliminary DMA controller framework for AVR32
2196 + *
2197 + * Copyright (C) 2005-2006 Atmel Corporation
2198 + *
2199 + * This program is free software; you can redistribute it and/or modify
2200 + * it under the terms of the GNU General Public License version 2 as
2201 + * published by the Free Software Foundation.
2202 + */
2203 +#include <asm/dma-controller.h>
2204 +
2205 +static LIST_HEAD(controllers);
2206 +
2207 +int register_dma_controller(struct dma_controller *dmac)
2208 +{
2209 + static int next_id;
2210 +
2211 + dmac->id = next_id++;
2212 + list_add_tail(&dmac->list, &controllers);
2213 +
2214 + return 0;
2215 +}
2216 +EXPORT_SYMBOL(register_dma_controller);
2217 +
2218 +struct dma_controller *find_dma_controller(int id)
2219 +{
2220 + struct dma_controller *dmac;
2221 +
2222 + list_for_each_entry(dmac, &controllers, list)
2223 + if (dmac->id == id)
2224 + return dmac;
2225 + return NULL;
2226 +}
2227 +EXPORT_SYMBOL(find_dma_controller);
2228 diff --git a/arch/avr32/kernel/entry-avr32b.S b/arch/avr32/kernel/entry-avr32b.S
2229 index 42657f1..ccadfd9 100644
2230 --- a/arch/avr32/kernel/entry-avr32b.S
2231 +++ b/arch/avr32/kernel/entry-avr32b.S
2232 @@ -159,11 +159,18 @@ handle_vmalloc_miss:
2233
2234 .section .scall.text,"ax",@progbits
2235 system_call:
2236 +#ifdef CONFIG_PREEMPT
2237 + mask_interrupts
2238 +#endif
2239 pushm r12 /* r12_orig */
2240 stmts --sp, r0-lr
2241 - zero_fp
2242 +
2243 mfsr r0, SYSREG_RAR_SUP
2244 mfsr r1, SYSREG_RSR_SUP
2245 +#ifdef CONFIG_PREEMPT
2246 + unmask_interrupts
2247 +#endif
2248 + zero_fp
2249 stm --sp, r0-r1
2250
2251 /* check for syscall tracing */
2252 @@ -638,6 +645,13 @@ irq_level\level:
2253 stmts --sp,r0-lr
2254 mfsr r8, rar_int\level
2255 mfsr r9, rsr_int\level
2256 +
2257 +#ifdef CONFIG_PREEMPT
2258 + sub r11, pc, (. - system_call)
2259 + cp.w r11, r8
2260 + breq 4f
2261 +#endif
2262 +
2263 pushm r8-r9
2264
2265 mov r11, sp
2266 @@ -668,6 +682,16 @@ irq_level\level:
2267 sub sp, -4 /* ignore r12_orig */
2268 rete
2269
2270 +#ifdef CONFIG_PREEMPT
2271 +4: mask_interrupts
2272 + mfsr r8, rsr_int\level
2273 + sbr r8, 16
2274 + mtsr rsr_int\level, r8
2275 + ldmts sp++, r0-lr
2276 + sub sp, -4 /* ignore r12_orig */
2277 + rete
2278 +#endif
2279 +
2280 2: get_thread_info r0
2281 ld.w r1, r0[TI_flags]
2282 bld r1, TIF_CPU_GOING_TO_SLEEP
2283 diff --git a/arch/avr32/kernel/setup.c b/arch/avr32/kernel/setup.c
2284 index d08b0bc..4b4c188 100644
2285 --- a/arch/avr32/kernel/setup.c
2286 +++ b/arch/avr32/kernel/setup.c
2287 @@ -248,7 +248,7 @@ static int __init early_parse_fbmem(char *p)
2288
2289 fbmem_size = memparse(p, &p);
2290 if (*p == '@') {
2291 - fbmem_start = memparse(p, &p);
2292 + fbmem_start = memparse(p + 1, &p);
2293 ret = add_reserved_region(fbmem_start,
2294 fbmem_start + fbmem_size - 1,
2295 "Framebuffer");
2296 diff --git a/arch/avr32/kernel/vmlinux.lds.S b/arch/avr32/kernel/vmlinux.lds.S
2297 new file mode 100644
2298 index 0000000..ce9ac96
2299 --- /dev/null
2300 +++ b/arch/avr32/kernel/vmlinux.lds.S
2301 @@ -0,0 +1,143 @@
2302 +/*
2303 + * AVR32 linker script for the Linux kernel
2304 + *
2305 + * Copyright (C) 2004-2006 Atmel Corporation
2306 + *
2307 + * This program is free software; you can redistribute it and/or modify
2308 + * it under the terms of the GNU General Public License version 2 as
2309 + * published by the Free Software Foundation.
2310 + */
2311 +#define LOAD_OFFSET 0x00000000
2312 +#include <asm-generic/vmlinux.lds.h>
2313 +#include <asm/cache.h>
2314 +#include <asm/thread_info.h>
2315 +
2316 +OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
2317 +OUTPUT_ARCH(avr32)
2318 +ENTRY(_start)
2319 +
2320 +/* Big endian */
2321 +jiffies = jiffies_64 + 4;
2322 +
2323 +SECTIONS
2324 +{
2325 + . = CONFIG_ENTRY_ADDRESS;
2326 + .init : AT(ADDR(.init) - LOAD_OFFSET) {
2327 + _stext = .;
2328 + __init_begin = .;
2329 + _sinittext = .;
2330 + *(.text.reset)
2331 + *(.init.text)
2332 + /*
2333 + * .exit.text is discarded at runtime, not
2334 + * link time, to deal with references from
2335 + * __bug_table
2336 + */
2337 + *(.exit.text)
2338 + _einittext = .;
2339 + . = ALIGN(4);
2340 + __tagtable_begin = .;
2341 + *(.taglist.init)
2342 + __tagtable_end = .;
2343 + *(.init.data)
2344 + . = ALIGN(16);
2345 + __setup_start = .;
2346 + *(.init.setup)
2347 + __setup_end = .;
2348 + . = ALIGN(4);
2349 + __initcall_start = .;
2350 + INITCALLS
2351 + __initcall_end = .;
2352 + __con_initcall_start = .;
2353 + *(.con_initcall.init)
2354 + __con_initcall_end = .;
2355 + __security_initcall_start = .;
2356 + *(.security_initcall.init)
2357 + __security_initcall_end = .;
2358 +#ifdef CONFIG_BLK_DEV_INITRD
2359 + . = ALIGN(32);
2360 + __initramfs_start = .;
2361 + *(.init.ramfs)
2362 + __initramfs_end = .;
2363 +#endif
2364 + . = ALIGN(PAGE_SIZE);
2365 + __init_end = .;
2366 + }
2367 +
2368 + .text : AT(ADDR(.text) - LOAD_OFFSET) {
2369 + _evba = .;
2370 + _text = .;
2371 + *(.ex.text)
2372 + . = 0x50;
2373 + *(.tlbx.ex.text)
2374 + . = 0x60;
2375 + *(.tlbr.ex.text)
2376 + . = 0x70;
2377 + *(.tlbw.ex.text)
2378 + . = 0x100;
2379 + *(.scall.text)
2380 + *(.irq.text)
2381 + TEXT_TEXT
2382 + SCHED_TEXT
2383 + LOCK_TEXT
2384 + KPROBES_TEXT
2385 + *(.fixup)
2386 + *(.gnu.warning)
2387 + _etext = .;
2388 + } = 0xd703d703
2389 +
2390 + . = ALIGN(4);
2391 + __ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) {
2392 + __start___ex_table = .;
2393 + *(__ex_table)
2394 + __stop___ex_table = .;
2395 + }
2396 +
2397 + BUG_TABLE
2398 +
2399 + RODATA
2400 +
2401 + . = ALIGN(THREAD_SIZE);
2402 +
2403 + .data : AT(ADDR(.data) - LOAD_OFFSET) {
2404 + _data = .;
2405 + _sdata = .;
2406 + /*
2407 + * First, the init task union, aligned to an 8K boundary.
2408 + */
2409 + *(.data.init_task)
2410 +
2411 + /* Then, the cacheline aligned data */
2412 + . = ALIGN(L1_CACHE_BYTES);
2413 + *(.data.cacheline_aligned)
2414 +
2415 + /* And the rest... */
2416 + *(.data.rel*)
2417 + DATA_DATA
2418 + CONSTRUCTORS
2419 +
2420 + _edata = .;
2421 + }
2422 +
2423 +
2424 + . = ALIGN(8);
2425 + .bss : AT(ADDR(.bss) - LOAD_OFFSET) {
2426 + __bss_start = .;
2427 + *(.bss)
2428 + *(COMMON)
2429 + . = ALIGN(8);
2430 + __bss_stop = .;
2431 + _end = .;
2432 + }
2433 +
2434 + /* When something in the kernel is NOT compiled as a module, the module
2435 + * cleanup code and data are put into these segments. Both can then be
2436 + * thrown away, as cleanup code is never called unless it's a module.
2437 + */
2438 + /DISCARD/ : {
2439 + *(.exit.data)
2440 + *(.exitcall.exit)
2441 + }
2442 +
2443 + DWARF_DEBUG
2444 +}
2445 diff --git a/arch/avr32/kernel/vmlinux.lds.c b/arch/avr32/kernel/vmlinux.lds.c
2446 deleted file mode 100644
2447 index db0438f..0000000
2448 --- a/arch/avr32/kernel/vmlinux.lds.c
2449 +++ /dev/null
2450 @@ -1,142 +0,0 @@
2451 -/*
2452 - * AVR32 linker script for the Linux kernel
2453 - *
2454 - * Copyright (C) 2004-2006 Atmel Corporation
2455 - *
2456 - * This program is free software; you can redistribute it and/or modify
2457 - * it under the terms of the GNU General Public License version 2 as
2458 - * published by the Free Software Foundation.
2459 - */
2460 -#define LOAD_OFFSET 0x00000000
2461 -#include <asm-generic/vmlinux.lds.h>
2462 -
2463 -OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
2464 -OUTPUT_ARCH(avr32)
2465 -ENTRY(_start)
2466 -
2467 -/* Big endian */
2468 -jiffies = jiffies_64 + 4;
2469 -
2470 -SECTIONS
2471 -{
2472 - . = CONFIG_ENTRY_ADDRESS;
2473 - .init : AT(ADDR(.init) - LOAD_OFFSET) {
2474 - _stext = .;
2475 - __init_begin = .;
2476 - _sinittext = .;
2477 - *(.text.reset)
2478 - *(.init.text)
2479 - /*
2480 - * .exit.text is discarded at runtime, not
2481 - * link time, to deal with references from
2482 - * __bug_table
2483 - */
2484 - *(.exit.text)
2485 - _einittext = .;
2486 - . = ALIGN(4);
2487 - __tagtable_begin = .;
2488 - *(.taglist.init)
2489 - __tagtable_end = .;
2490 - *(.init.data)
2491 - . = ALIGN(16);
2492 - __setup_start = .;
2493 - *(.init.setup)
2494 - __setup_end = .;
2495 - . = ALIGN(4);
2496 - __initcall_start = .;
2497 - INITCALLS
2498 - __initcall_end = .;
2499 - __con_initcall_start = .;
2500 - *(.con_initcall.init)
2501 - __con_initcall_end = .;
2502 - __security_initcall_start = .;
2503 - *(.security_initcall.init)
2504 - __security_initcall_end = .;
2505 -#ifdef CONFIG_BLK_DEV_INITRD
2506 - . = ALIGN(32);
2507 - __initramfs_start = .;
2508 - *(.init.ramfs)
2509 - __initramfs_end = .;
2510 -#endif
2511 - . = ALIGN(4096);
2512 - __init_end = .;
2513 - }
2514 -
2515 - . = ALIGN(8192);
2516 - .text : AT(ADDR(.text) - LOAD_OFFSET) {
2517 - _evba = .;
2518 - _text = .;
2519 - *(.ex.text)
2520 - . = 0x50;
2521 - *(.tlbx.ex.text)
2522 - . = 0x60;
2523 - *(.tlbr.ex.text)
2524 - . = 0x70;
2525 - *(.tlbw.ex.text)
2526 - . = 0x100;
2527 - *(.scall.text)
2528 - *(.irq.text)
2529 - TEXT_TEXT
2530 - SCHED_TEXT
2531 - LOCK_TEXT
2532 - KPROBES_TEXT
2533 - *(.fixup)
2534 - *(.gnu.warning)
2535 - _etext = .;
2536 - } = 0xd703d703
2537 -
2538 - . = ALIGN(4);
2539 - __ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) {
2540 - __start___ex_table = .;
2541 - *(__ex_table)
2542 - __stop___ex_table = .;
2543 - }
2544 -
2545 - BUG_TABLE
2546 -
2547 - RODATA
2548 -
2549 - . = ALIGN(8192);
2550 -
2551 - .data : AT(ADDR(.data) - LOAD_OFFSET) {
2552 - _data = .;
2553 - _sdata = .;
2554 - /*
2555 - * First, the init task union, aligned to an 8K boundary.
2556 - */
2557 - *(.data.init_task)
2558 -
2559 - /* Then, the cacheline aligned data */
2560 - . = ALIGN(32);
2561 - *(.data.cacheline_aligned)
2562 -
2563 - /* And the rest... */
2564 - *(.data.rel*)
2565 - DATA_DATA
2566 - CONSTRUCTORS
2567 -
2568 - _edata = .;
2569 - }
2570 -
2571 -
2572 - . = ALIGN(8);
2573 - .bss : AT(ADDR(.bss) - LOAD_OFFSET) {
2574 - __bss_start = .;
2575 - *(.bss)
2576 - *(COMMON)
2577 - . = ALIGN(8);
2578 - __bss_stop = .;
2579 - _end = .;
2580 - }
2581 -
2582 - /* When something in the kernel is NOT compiled as a module, the module
2583 - * cleanup code and data are put into these segments. Both can then be
2584 - * thrown away, as cleanup code is never called unless it's a module.
2585 - */
2586 - /DISCARD/ : {
2587 - *(.exit.data)
2588 - *(.exitcall.exit)
2589 - }
2590 -
2591 - DWARF_DEBUG
2592 -}
2593 diff --git a/arch/avr32/mach-at32ap/Kconfig b/arch/avr32/mach-at32ap/Kconfig
2594 index eb30783..43c5b9f 100644
2595 --- a/arch/avr32/mach-at32ap/Kconfig
2596 +++ b/arch/avr32/mach-at32ap/Kconfig
2597 @@ -26,6 +26,13 @@ config AP7000_8_BIT_SMC
2598
2599 endchoice
2600
2601 +config GPIO_DEV
2602 + bool "GPIO /dev interface"
2603 + select CONFIGFS_FS
2604 + default n
2605 + help
2606 + Say `Y' to enable a /dev interface to the GPIO pins.
2607 +
2608 endmenu
2609
2610 endif # PLATFORM_AT32AP
2611 diff --git a/arch/avr32/mach-at32ap/Makefile b/arch/avr32/mach-at32ap/Makefile
2612 index a8b4450..250372a 100644
2613 --- a/arch/avr32/mach-at32ap/Makefile
2614 +++ b/arch/avr32/mach-at32ap/Makefile
2615 @@ -2,3 +2,4 @@ obj-y += at32ap.o clock.o intc.o extint.o pio.o hsmc.o
2616 obj-$(CONFIG_CPU_AT32AP7000) += at32ap7000.o
2617 obj-$(CONFIG_CPU_AT32AP7000) += time-tc.o
2618 obj-$(CONFIG_CPU_FREQ_AT32AP) += cpufreq.o
2619 +obj-$(CONFIG_GPIO_DEV) += gpio-dev.o
2620 diff --git a/arch/avr32/mach-at32ap/at32ap7000.c b/arch/avr32/mach-at32ap/at32ap7000.c
2621 index 64cc558..8375f89 100644
2622 --- a/arch/avr32/mach-at32ap/at32ap7000.c
2623 +++ b/arch/avr32/mach-at32ap/at32ap7000.c
2624 @@ -25,12 +25,6 @@
2625 #include "pio.h"
2626 #include "pm.h"
2627
2628 -/*
2629 - * We can reduce the code size a bit by using a constant here. Since
2630 - * this file is completely chip-specific, it's safe to not use
2631 - * ioremap. Generic drivers should of course never do this.
2632 - */
2633 -#define AT32_PM_BASE 0xfff00000
2634
2635 #define PBMEM(base) \
2636 { \
2637 @@ -562,6 +556,17 @@ static struct clk pico_clk = {
2638 .users = 1,
2639 };
2640
2641 +static struct resource dmaca0_resource[] = {
2642 + {
2643 + .start = 0xff200000,
2644 + .end = 0xff20ffff,
2645 + .flags = IORESOURCE_MEM,
2646 + },
2647 + IRQ(2),
2648 +};
2649 +DEFINE_DEV(dmaca, 0);
2650 +DEV_CLK(hclk, dmaca0, hsb, 10);
2651 +
2652 /* --------------------------------------------------------------------
2653 * HMATRIX
2654 * -------------------------------------------------------------------- */
2655 @@ -661,6 +666,7 @@ void __init at32_add_system_devices(void)
2656 platform_device_register(&at32_eic0_device);
2657 platform_device_register(&smc0_device);
2658 platform_device_register(&pdc_device);
2659 + platform_device_register(&dmaca0_device);
2660
2661 platform_device_register(&at32_systc0_device);
2662
2663 @@ -966,6 +972,83 @@ at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
2664 }
2665
2666 /* --------------------------------------------------------------------
2667 + * TWI
2668 + * -------------------------------------------------------------------- */
2669 +
2670 +static struct resource atmel_twi0_resource[] = {
2671 + PBMEM(0xffe00800),
2672 + IRQ(5),
2673 +};
2674 +DEFINE_DEV(atmel_twi, 0);
2675 +DEV_CLK(pclk,atmel_twi0,pba,2);
2676 +
2677 +struct platform_device *__init
2678 +at32_add_device_twi(unsigned int id)
2679 +{
2680 + struct platform_device *pdev;
2681 +
2682 + switch (id) {
2683 + case 0:
2684 + pdev = &atmel_twi0_device;
2685 + select_peripheral(PA(6), PERIPH_A, 0); /* SDA */
2686 + select_peripheral(PA(7), PERIPH_A, 0); /* SCL */
2687 + break;
2688 +
2689 + default:
2690 + return NULL;
2691 + }
2692 +
2693 + platform_device_register(pdev);
2694 + return pdev;
2695 +}
2696 +
2697 +/* --------------------------------------------------------------------
2698 + * MMC
2699 + * -------------------------------------------------------------------- */
2700 +static struct mci_platform_data atmel_mci0_data = {
2701 + .detect_pin = GPIO_PIN_NONE,
2702 + .wp_pin = GPIO_PIN_NONE,
2703 +};
2704 +static struct resource atmel_mci0_resource[] = {
2705 + PBMEM(0xfff02400),
2706 + IRQ(28),
2707 +};
2708 +DEFINE_DEV_DATA(atmel_mci, 0);
2709 +DEV_CLK(mci_clk, atmel_mci0, pbb, 9);
2710 +
2711 +struct platform_device *__init
2712 +at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
2713 +{
2714 + struct platform_device *pdev;
2715 +
2716 + switch (id) {
2717 + case 0:
2718 + pdev = &atmel_mci0_device;
2719 + select_peripheral(PA(10), PERIPH_A, 0); /* CLK */
2720 + select_peripheral(PA(11), PERIPH_A, 0); /* CMD */
2721 + select_peripheral(PA(12), PERIPH_A, 0); /* DATA0 */
2722 + select_peripheral(PA(13), PERIPH_A, 0); /* DATA1 */
2723 + select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */
2724 + select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */
2725 + break;
2726 + default:
2727 + return NULL;
2728 + }
2729 +
2730 + if (data) {
2731 + if (data->detect_pin != GPIO_PIN_NONE)
2732 + at32_select_gpio(data->detect_pin, 0);
2733 + if (data->wp_pin != GPIO_PIN_NONE)
2734 + at32_select_gpio(data->wp_pin, 0);
2735 + memcpy(pdev->dev.platform_data, data,
2736 + sizeof(struct mci_platform_data));
2737 + }
2738 +
2739 + platform_device_register(pdev);
2740 + return pdev;
2741 +}
2742 +
2743 +/* --------------------------------------------------------------------
2744 * LCDC
2745 * -------------------------------------------------------------------- */
2746 static struct atmel_lcdfb_info atmel_lcdfb0_data;
2747 @@ -1168,6 +1251,143 @@ at32_add_device_ssc(unsigned int id, unsigned int flags)
2748 }
2749
2750 /* --------------------------------------------------------------------
2751 + * USB Device Controller
2752 + * -------------------------------------------------------------------- */
2753 +static struct resource usba0_resource[] __initdata = {
2754 + {
2755 + .start = 0xff300000,
2756 + .end = 0xff3fffff,
2757 + .flags = IORESOURCE_MEM,
2758 + }, {
2759 + .start = 0xfff03000,
2760 + .end = 0xfff033ff,
2761 + .flags = IORESOURCE_MEM,
2762 + },
2763 + IRQ(31),
2764 +};
2765 +static struct clk usba0_pclk = {
2766 + .name = "pclk",
2767 + .parent = &pbb_clk,
2768 + .mode = pbb_clk_mode,
2769 + .get_rate = pbb_clk_get_rate,
2770 + .index = 12,
2771 +};
2772 +static struct clk usba0_hclk = {
2773 + .name = "hclk",
2774 + .parent = &hsb_clk,
2775 + .mode = hsb_clk_mode,
2776 + .get_rate = hsb_clk_get_rate,
2777 + .index = 6,
2778 +};
2779 +
2780 +struct platform_device *__init
2781 +at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
2782 +{
2783 + struct platform_device *pdev;
2784 +
2785 + if (id != 0)
2786 + return NULL;
2787 +
2788 + pdev = platform_device_alloc("atmel_usba_udc", 0);
2789 + if (!pdev)
2790 + return NULL;
2791 +
2792 + if (platform_device_add_resources(pdev, usba0_resource,
2793 + ARRAY_SIZE(usba0_resource)))
2794 + goto out_free_pdev;
2795 +
2796 + if (data) {
2797 + if (platform_device_add_data(pdev, data, sizeof(*data)))
2798 + goto out_free_pdev;
2799 +
2800 + if (data->vbus_pin != GPIO_PIN_NONE)
2801 + at32_select_gpio(data->vbus_pin, 0);
2802 + }
2803 +
2804 + usba0_pclk.dev = &pdev->dev;
2805 + usba0_hclk.dev = &pdev->dev;
2806 +
2807 + platform_device_add(pdev);
2808 +
2809 + return pdev;
2810 +
2811 +out_free_pdev:
2812 + platform_device_put(pdev);
2813 + return NULL;
2814 +}
2815 +
2816 +/* --------------------------------------------------------------------
2817 + * AC97C
2818 + * -------------------------------------------------------------------- */
2819 +static struct resource atmel_ac97c0_resource[] = {
2820 + PBMEM(0xfff02800),
2821 + IRQ(29),
2822 +};
2823 +DEFINE_DEV(atmel_ac97c, 0);
2824 +DEV_CLK(pclk, atmel_ac97c0, pbb, 10);
2825 +
2826 +struct platform_device *__init
2827 +at32_add_device_ac97c(unsigned int id)
2828 +{
2829 + struct platform_device *pdev;
2830 +
2831 + switch (id) {
2832 + case 0:
2833 + pdev = &atmel_ac97c0_device;
2834 + select_peripheral(PB(20), PERIPH_B, 0); /* SYNC */
2835 + select_peripheral(PB(21), PERIPH_B, 0); /* SDO */
2836 + select_peripheral(PB(22), PERIPH_B, 0); /* SDI */
2837 + select_peripheral(PB(23), PERIPH_B, 0); /* SCLK */
2838 + break;
2839 + default:
2840 + return NULL;
2841 + }
2842 +
2843 + platform_device_register(pdev);
2844 + return pdev;
2845 +}
2846 +
2847 +/* --------------------------------------------------------------------
2848 + * DAC
2849 + * -------------------------------------------------------------------- */
2850 +static struct resource abdac0_resource[] = {
2851 + PBMEM(0xfff02000),
2852 + IRQ(27),
2853 +};
2854 +DEFINE_DEV(abdac, 0);
2855 +DEV_CLK(pclk, abdac0, pbb, 8);
2856 +static struct clk abdac0_sample_clk = {
2857 + .name = "sample_clk",
2858 + .dev = &abdac0_device.dev,
2859 + .mode = genclk_mode,
2860 + .get_rate = genclk_get_rate,
2861 + .set_rate = genclk_set_rate,
2862 + .set_parent = genclk_set_parent,
2863 + .index = 6,
2864 +};
2865 +
2866 +struct platform_device *__init
2867 +at32_add_device_abdac(unsigned int id)
2868 +{
2869 + struct platform_device *pdev;
2870 +
2871 + switch (id) {
2872 + case 0:
2873 + pdev = &abdac0_device;
2874 + select_peripheral(PB(20), PERIPH_A, 0); /* DATA1 */
2875 + select_peripheral(PB(21), PERIPH_A, 0); /* DATA0 */
2876 + select_peripheral(PB(22), PERIPH_A, 0); /* DATAN1 */
2877 + select_peripheral(PB(23), PERIPH_A, 0); /* DATAN0 */
2878 + break;
2879 + default:
2880 + return NULL;
2881 + }
2882 +
2883 + platform_device_register(pdev);
2884 + return pdev;
2885 +}
2886 +
2887 +/* --------------------------------------------------------------------
2888 * GCLK
2889 * -------------------------------------------------------------------- */
2890 static struct clk gclk0 = {
2891 @@ -1230,6 +1450,7 @@ struct clk *at32_clock_list[] = {
2892 &smc0_mck,
2893 &pdc_hclk,
2894 &pdc_pclk,
2895 + &dmaca0_hclk,
2896 &pico_clk,
2897 &pio0_mck,
2898 &pio1_mck,
2899 @@ -1247,11 +1468,18 @@ struct clk *at32_clock_list[] = {
2900 &macb1_pclk,
2901 &atmel_spi0_spi_clk,
2902 &atmel_spi1_spi_clk,
2903 + &atmel_twi0_pclk,
2904 + &atmel_mci0_mci_clk,
2905 &atmel_lcdfb0_hck1,
2906 &atmel_lcdfb0_pixclk,
2907 &ssc0_pclk,
2908 &ssc1_pclk,
2909 &ssc2_pclk,
2910 + &usba0_hclk,
2911 + &usba0_pclk,
2912 + &atmel_ac97c0_pclk,
2913 + &abdac0_pclk,
2914 + &abdac0_sample_clk,
2915 &gclk0,
2916 &gclk1,
2917 &gclk2,
2918 @@ -1293,6 +1521,7 @@ void __init at32_clock_init(void)
2919 genclk_init_parent(&gclk3);
2920 genclk_init_parent(&gclk4);
2921 genclk_init_parent(&atmel_lcdfb0_pixclk);
2922 + genclk_init_parent(&abdac0_sample_clk);
2923
2924 /*
2925 * Turn on all clocks that have at least one user already, and
2926 diff --git a/arch/avr32/mach-at32ap/clock.c b/arch/avr32/mach-at32ap/clock.c
2927 index 0f8c89c..4642117 100644
2928 --- a/arch/avr32/mach-at32ap/clock.c
2929 +++ b/arch/avr32/mach-at32ap/clock.c
2930 @@ -150,3 +150,119 @@ struct clk *clk_get_parent(struct clk *clk)
2931 return clk->parent;
2932 }
2933 EXPORT_SYMBOL(clk_get_parent);
2934 +
2935 +
2936 +
2937 +#ifdef CONFIG_DEBUG_FS
2938 +
2939 +/* /sys/kernel/debug/at32ap_clk */
2940 +
2941 +#include <linux/io.h>
2942 +#include <linux/debugfs.h>
2943 +#include <linux/seq_file.h>
2944 +#include "pm.h"
2945 +
2946 +
2947 +#define NEST_DELTA 2
2948 +#define NEST_MAX 6
2949 +
2950 +struct clkinf {
2951 + struct seq_file *s;
2952 + unsigned nest;
2953 +};
2954 +
2955 +static void
2956 +dump_clock(struct clk *parent, struct clkinf *r)
2957 +{
2958 + unsigned nest = r->nest;
2959 + char buf[16 + NEST_MAX];
2960 + struct clk *clk;
2961 + unsigned i;
2962 +
2963 + /* skip clocks coupled to devices that aren't registered */
2964 + if (parent->dev && !parent->dev->bus_id[0] && !parent->users)
2965 + return;
2966 +
2967 + /* <nest spaces> name <pad to end> */
2968 + memset(buf, ' ', sizeof(buf) - 1);
2969 + buf[sizeof(buf) - 1] = 0;
2970 + i = strlen(parent->name);
2971 + memcpy(buf + nest, parent->name,
2972 + min(i, (unsigned)(sizeof(buf) - 1 - nest)));
2973 +
2974 + seq_printf(r->s, "%s%c users=%2d %-3s %9ld Hz",
2975 + buf, parent->set_parent ? '*' : ' ',
2976 + parent->users,
2977 + parent->users ? "on" : "off", /* NOTE: not-paranoid!! */
2978 + clk_get_rate(parent));
2979 + if (parent->dev)
2980 + seq_printf(r->s, ", for %s", parent->dev->bus_id);
2981 + seq_printf(r->s, "\n");
2982 +
2983 + /* cost of this scan is small, but not linear... */
2984 + r->nest = nest + NEST_DELTA;
2985 + for (i = 3; i < at32_nr_clocks; i++) {
2986 + clk = at32_clock_list[i];
2987 + if (clk->parent == parent)
2988 + dump_clock(clk, r);
2989 + }
2990 + r->nest = nest;
2991 +}
2992 +
2993 +static int clk_show(struct seq_file *s, void *unused)
2994 +{
2995 + struct clkinf r;
2996 + int i;
2997 +
2998 + /* show all the power manager registers */
2999 + seq_printf(s, "MCCTRL = %8x\n", pm_readl(MCCTRL));
3000 + seq_printf(s, "CKSEL = %8x\n", pm_readl(CKSEL));
3001 + seq_printf(s, "CPUMASK = %8x\n", pm_readl(CPU_MASK));
3002 + seq_printf(s, "HSBMASK = %8x\n", pm_readl(HSB_MASK));
3003 + seq_printf(s, "PBAMASK = %8x\n", pm_readl(PBA_MASK));
3004 + seq_printf(s, "PBBMASK = %8x\n", pm_readl(PBB_MASK));
3005 + seq_printf(s, "PLL0 = %8x\n", pm_readl(PLL0));
3006 + seq_printf(s, "PLL1 = %8x\n", pm_readl(PLL1));
3007 + seq_printf(s, "IMR = %8x\n", pm_readl(IMR));
3008 + for (i = 0; i < 8; i++) {
3009 + if (i == 5)
3010 + continue;
3011 + seq_printf(s, "GCCTRL%d = %8x\n", i, pm_readl(GCCTRL(i)));
3012 + }
3013 +
3014 + seq_printf(s, "\n");
3015 +
3016 + /* show clock tree as derived from the three oscillators
3017 + * we "know" are at the head of the list
3018 + */
3019 + r.s = s;
3020 + r.nest = 0;
3021 + dump_clock(at32_clock_list[0], &r);
3022 + dump_clock(at32_clock_list[1], &r);
3023 + dump_clock(at32_clock_list[2], &r);
3024 +
3025 + return 0;
3026 +}
3027 +
3028 +static int clk_open(struct inode *inode, struct file *file)
3029 +{
3030 + return single_open(file, clk_show, NULL);
3031 +}
3032 +
3033 +static const struct file_operations clk_operations = {
3034 + .open = clk_open,
3035 + .read = seq_read,
3036 + .llseek = seq_lseek,
3037 + .release = single_release,
3038 +};
3039 +
3040 +static int __init clk_debugfs_init(void)
3041 +{
3042 + (void) debugfs_create_file("at32ap_clk", S_IFREG | S_IRUGO,
3043 + NULL, NULL, &clk_operations);
3044 +
3045 + return 0;
3046 +}
3047 +postcore_initcall(clk_debugfs_init);
3048 +
3049 +#endif
3050 diff --git a/arch/avr32/mach-at32ap/gpio-dev.c b/arch/avr32/mach-at32ap/gpio-dev.c
3051 new file mode 100644
3052 index 0000000..8cf6d11
3053 --- /dev/null
3054 +++ b/arch/avr32/mach-at32ap/gpio-dev.c
3055 @@ -0,0 +1,573 @@
3056 +/*
3057 + * GPIO /dev and configfs interface
3058 + *
3059 + * Copyright (C) 2006-2007 Atmel Corporation
3060 + *
3061 + * This program is free software; you can redistribute it and/or modify
3062 + * it under the terms of the GNU General Public License version 2 as
3063 + * published by the Free Software Foundation.
3064 + */
3065 +#include <linux/kernel.h>
3066 +#include <linux/configfs.h>
3067 +#include <linux/cdev.h>
3068 +#include <linux/device.h>
3069 +#include <linux/fs.h>
3070 +#include <linux/interrupt.h>
3071 +#include <linux/module.h>
3072 +#include <linux/poll.h>
3073 +#include <linux/uaccess.h>
3074 +#include <linux/wait.h>
3075 +
3076 +#include <asm/gpio.h>
3077 +#include <asm/arch/portmux.h>
3078 +
3079 +#define GPIO_DEV_MAX 8
3080 +
3081 +static struct class *gpio_dev_class;
3082 +static dev_t gpio_devt;
3083 +
3084 +struct gpio_item {
3085 + spinlock_t lock;
3086 +
3087 + int enabled;
3088 + int initialized;
3089 + int port;
3090 + u32 pin_mask;
3091 + u32 oe_mask;
3092 +
3093 + /* Pin state last time we read it (for blocking reads) */
3094 + u32 pin_state;
3095 + int changed;
3096 +
3097 + wait_queue_head_t change_wq;
3098 + struct fasync_struct *async_queue;
3099 +
3100 + int id;
3101 + struct class_device *gpio_dev;
3102 + struct cdev char_dev;
3103 + struct config_item item;
3104 +};
3105 +
3106 +struct gpio_attribute {
3107 + struct configfs_attribute attr;
3108 + ssize_t (*show)(struct gpio_item *, char *);
3109 + ssize_t (*store)(struct gpio_item *, const char *, size_t);
3110 +};
3111 +
3112 +static irqreturn_t gpio_dev_interrupt(int irq, void *dev_id)
3113 +{
3114 + struct gpio_item *gpio = dev_id;
3115 + u32 old_state, new_state;
3116 +
3117 + old_state = gpio->pin_state;
3118 + new_state = at32_gpio_get_value_multiple(gpio->port, gpio->pin_mask);
3119 + gpio->pin_state = new_state;
3120 +
3121 + if (new_state != old_state) {
3122 + gpio->changed = 1;
3123 + wake_up_interruptible(&gpio->change_wq);
3124 +
3125 + if (gpio->async_queue)
3126 + kill_fasync(&gpio->async_queue, SIGIO, POLL_IN);
3127 + }
3128 +
3129 + return IRQ_HANDLED;
3130 +}
3131 +
3132 +static int gpio_dev_open(struct inode *inode, struct file *file)
3133 +{
3134 + struct gpio_item *gpio = container_of(inode->i_cdev,
3135 + struct gpio_item,
3136 + char_dev);
3137 + unsigned int irq;
3138 + unsigned int i;
3139 + int ret;
3140 +
3141 + nonseekable_open(inode, file);
3142 + config_item_get(&gpio->item);
3143 + file->private_data = gpio;
3144 +
3145 + gpio->pin_state = at32_gpio_get_value_multiple(gpio->port,
3146 + gpio->pin_mask);
3147 + gpio->changed = 1;
3148 +
3149 + for (i = 0; i < 32; i++) {
3150 + if (gpio->pin_mask & (1 << i)) {
3151 + irq = gpio_to_irq(32 * gpio->port + i);
3152 + ret = request_irq(irq, gpio_dev_interrupt, 0,
3153 + "gpio-dev", gpio);
3154 + if (ret)
3155 + goto err_irq;
3156 + }
3157 + }
3158 +
3159 + return 0;
3160 +
3161 +err_irq:
3162 + while (i--) {
3163 + if (gpio->pin_mask & (1 << i)) {
3164 + irq = gpio_to_irq(32 * gpio->port + i);
3165 + free_irq(irq, gpio);
3166 + }
3167 + }
3168 +
3169 + config_item_put(&gpio->item);
3170 +
3171 + return ret;
3172 +}
3173 +
3174 +static int gpio_dev_fasync(int fd, struct file *file, int mode)
3175 +{
3176 + struct gpio_item *gpio = file->private_data;
3177 +
3178 + return fasync_helper(fd, file, mode, &gpio->async_queue);
3179 +}
3180 +
3181 +static int gpio_dev_release(struct inode *inode, struct file *file)
3182 +{
3183 + struct gpio_item *gpio = file->private_data;
3184 + unsigned int irq;
3185 + unsigned int i;
3186 +
3187 + gpio_dev_fasync(-1, file, 0);
3188 +
3189 + for (i = 0; i < 32; i++) {
3190 + if (gpio->pin_mask & (1 << i)) {
3191 + irq = gpio_to_irq(32 * gpio->port + i);
3192 + free_irq(irq, gpio);
3193 + }
3194 + }
3195 +
3196 + config_item_put(&gpio->item);
3197 +
3198 + return 0;
3199 +}
3200 +
3201 +static unsigned int gpio_dev_poll(struct file *file, poll_table *wait)
3202 +{
3203 + struct gpio_item *gpio = file->private_data;
3204 + unsigned int mask = 0;
3205 +
3206 + poll_wait(file, &gpio->change_wq, wait);
3207 + if (gpio->changed)
3208 + mask |= POLLIN | POLLRDNORM;
3209 +
3210 + return mask;
3211 +}
3212 +
3213 +static ssize_t gpio_dev_read(struct file *file, char __user *buf,
3214 + size_t count, loff_t *offset)
3215 +{
3216 + struct gpio_item *gpio = file->private_data;
3217 + u32 value;
3218 +
3219 + spin_lock_irq(&gpio->lock);
3220 + while (!gpio->changed) {
3221 + spin_unlock_irq(&gpio->lock);
3222 +
3223 + if (file->f_flags & O_NONBLOCK)
3224 + return -EAGAIN;
3225 +
3226 + if (wait_event_interruptible(gpio->change_wq, gpio->changed))
3227 + return -ERESTARTSYS;
3228 +
3229 + spin_lock_irq(&gpio->lock);
3230 + }
3231 +
3232 + gpio->changed = 0;
3233 + value = at32_gpio_get_value_multiple(gpio->port, gpio->pin_mask);
3234 +
3235 + spin_unlock_irq(&gpio->lock);
3236 +
3237 + count = min(count, (size_t)4);
3238 + if (copy_to_user(buf, &value, count))
3239 + return -EFAULT;
3240 +
3241 + return count;
3242 +}
3243 +
3244 +static ssize_t gpio_dev_write(struct file *file, const char __user *buf,
3245 + size_t count, loff_t *offset)
3246 +{
3247 + struct gpio_item *gpio = file->private_data;
3248 + u32 value = 0;
3249 + u32 mask = ~0UL;
3250 +
3251 + count = min(count, (size_t)4);
3252 + if (copy_from_user(&value, buf, count))
3253 + return -EFAULT;
3254 +
3255 + /* Assuming big endian */
3256 + mask <<= (4 - count) * 8;
3257 + mask &= gpio->pin_mask;
3258 +
3259 + at32_gpio_set_value_multiple(gpio->port, value, mask);
3260 +
3261 + return count;
3262 +}
3263 +
3264 +static struct file_operations gpio_dev_fops = {
3265 + .owner = THIS_MODULE,
3266 + .llseek = no_llseek,
3267 + .open = gpio_dev_open,
3268 + .release = gpio_dev_release,
3269 + .fasync = gpio_dev_fasync,
3270 + .poll = gpio_dev_poll,
3271 + .read = gpio_dev_read,
3272 + .write = gpio_dev_write,
3273 +};
3274 +
3275 +static struct gpio_item *to_gpio_item(struct config_item *item)
3276 +{
3277 + return item ? container_of(item, struct gpio_item, item) : NULL;
3278 +}
3279 +
3280 +static ssize_t gpio_show_gpio_id(struct gpio_item *gpio, char *page)
3281 +{
3282 + return sprintf(page, "%d\n", gpio->port);
3283 +}
3284 +
3285 +static ssize_t gpio_store_gpio_id(struct gpio_item *gpio,
3286 + const char *page, size_t count)
3287 +{
3288 + unsigned long id;
3289 + char *p = (char *)page;
3290 + ssize_t ret = -EINVAL;
3291 +
3292 + id = simple_strtoul(p, &p, 0);
3293 + if (!p || (*p && (*p != '\n')))
3294 + return -EINVAL;
3295 +
3296 + /* Switching PIO is not allowed when live... */
3297 + spin_lock(&gpio->lock);
3298 + if (!gpio->enabled) {
3299 + ret = -ENXIO;
3300 + if (at32_gpio_port_is_valid(id)) {
3301 + gpio->port = id;
3302 + ret = count;
3303 + }
3304 + }
3305 + spin_unlock(&gpio->lock);
3306 +
3307 + return ret;
3308 +}
3309 +
3310 +static ssize_t gpio_show_pin_mask(struct gpio_item *gpio, char *page)
3311 +{
3312 + return sprintf(page, "0x%08x\n", gpio->pin_mask);
3313 +}
3314 +
3315 +static ssize_t gpio_store_pin_mask(struct gpio_item *gpio,
3316 + const char *page, size_t count)
3317 +{
3318 + u32 new_mask;
3319 + char *p = (char *)page;
3320 + ssize_t ret = -EINVAL;
3321 +
3322 + new_mask = simple_strtoul(p, &p, 0);
3323 + if (!p || (*p && (*p != '\n')))
3324 + return -EINVAL;
3325 +
3326 + /* Can't update the pin mask while live. */
3327 + spin_lock(&gpio->lock);
3328 + if (!gpio->enabled) {
3329 + gpio->oe_mask &= new_mask;
3330 + gpio->pin_mask = new_mask;
3331 + ret = count;
3332 + }
3333 + spin_unlock(&gpio->lock);
3334 +
3335 + return ret;
3336 +}
3337 +
3338 +static ssize_t gpio_show_oe_mask(struct gpio_item *gpio, char *page)
3339 +{
3340 + return sprintf(page, "0x%08x\n", gpio->oe_mask);
3341 +}
3342 +
3343 +static ssize_t gpio_store_oe_mask(struct gpio_item *gpio,
3344 + const char *page, size_t count)
3345 +{
3346 + u32 mask;
3347 + char *p = (char *)page;
3348 + ssize_t ret = -EINVAL;
3349 +
3350 + mask = simple_strtoul(p, &p, 0);
3351 + if (!p || (*p && (*p != '\n')))
3352 + return -EINVAL;
3353 +
3354 + spin_lock(&gpio->lock);
3355 + if (!gpio->enabled) {
3356 + gpio->oe_mask = mask & gpio->pin_mask;
3357 + ret = count;
3358 + }
3359 + spin_unlock(&gpio->lock);
3360 +
3361 + return ret;
3362 +}
3363 +
3364 +static ssize_t gpio_show_enabled(struct gpio_item *gpio, char *page)
3365 +{
3366 + return sprintf(page, "%d\n", gpio->enabled);
3367 +}
3368 +
3369 +static ssize_t gpio_store_enabled(struct gpio_item *gpio,
3370 + const char *page, size_t count)
3371 +{
3372 + char *p = (char *)page;
3373 + int enabled;
3374 + int ret;
3375 +
3376 + enabled = simple_strtoul(p, &p, 0);
3377 + if (!p || (*p && (*p != '\n')))
3378 + return -EINVAL;
3379 +
3380 + /* make it a boolean value */
3381 + enabled = !!enabled;
3382 +
3383 + if (gpio->enabled == enabled)
3384 + /* No change; do nothing. */
3385 + return count;
3386 +
3387 + BUG_ON(gpio->id >= GPIO_DEV_MAX);
3388 +
3389 + if (!enabled) {
3390 + class_device_unregister(gpio->gpio_dev);
3391 + cdev_del(&gpio->char_dev);
3392 + at32_deselect_pins(gpio->port, gpio->pin_mask);
3393 + gpio->initialized = 0;
3394 + } else {
3395 + if (gpio->port < 0 || !gpio->pin_mask)
3396 + return -ENODEV;
3397 + }
3398 +
3399 + /* Disallow any updates to gpio_id or pin_mask */
3400 + spin_lock(&gpio->lock);
3401 + gpio->enabled = enabled;
3402 + spin_unlock(&gpio->lock);
3403 +
3404 + if (!enabled)
3405 + return count;
3406 +
3407 + /* Now, try to allocate the pins */
3408 + ret = at32_select_gpio_pins(gpio->port, gpio->pin_mask, gpio->oe_mask);
3409 + if (ret)
3410 + goto err_alloc_pins;
3411 +
3412 + gpio->initialized = 1;
3413 +
3414 + cdev_init(&gpio->char_dev, &gpio_dev_fops);
3415 + gpio->char_dev.owner = THIS_MODULE;
3416 + ret = cdev_add(&gpio->char_dev, MKDEV(MAJOR(gpio_devt), gpio->id), 1);
3417 + if (ret < 0)
3418 + goto err_cdev_add;
3419 + gpio->gpio_dev = class_device_create(gpio_dev_class, NULL,
3420 + MKDEV(MAJOR(gpio_devt), gpio->id),
3421 + NULL,
3422 + "gpio%d", gpio->id);
3423 + if (IS_ERR(gpio->gpio_dev)) {
3424 + printk(KERN_ERR "failed to create gpio%d\n", gpio->id);
3425 + ret = PTR_ERR(gpio->gpio_dev);
3426 + goto err_class_dev;
3427 + }
3428 +
3429 + printk(KERN_INFO "created gpio%d (port%d/0x%08x) as (%d:%d)\n",
3430 + gpio->id, gpio->port, gpio->pin_mask,
3431 + MAJOR(gpio->gpio_dev->devt), MINOR(gpio->gpio_dev->devt));
3432 +
3433 + return 0;
3434 +
3435 +err_class_dev:
3436 + cdev_del(&gpio->char_dev);
3437 +err_cdev_add:
3438 + at32_deselect_pins(gpio->port, gpio->pin_mask);
3439 + gpio->initialized = 0;
3440 +err_alloc_pins:
3441 + spin_lock(&gpio->lock);
3442 + gpio->enabled = 0;
3443 + spin_unlock(&gpio->lock);
3444 +
3445 + return ret;
3446 +}
3447 +
3448 +static struct gpio_attribute gpio_item_attr_gpio_id = {
3449 + .attr = {
3450 + .ca_owner = THIS_MODULE,
3451 + .ca_name = "gpio_id",
3452 + .ca_mode = S_IRUGO | S_IWUSR,
3453 + },
3454 + .show = gpio_show_gpio_id,
3455 + .store = gpio_store_gpio_id,
3456 +};
3457 +static struct gpio_attribute gpio_item_attr_pin_mask = {
3458 + .attr = {
3459 + .ca_owner = THIS_MODULE,
3460 + .ca_name = "pin_mask",
3461 + .ca_mode = S_IRUGO | S_IWUSR,
3462 + },
3463 + .show = gpio_show_pin_mask,
3464 + .store = gpio_store_pin_mask,
3465 +};
3466 +static struct gpio_attribute gpio_item_attr_oe_mask = {
3467 + .attr = {
3468 + .ca_owner = THIS_MODULE,
3469 + .ca_name = "oe_mask",
3470 + .ca_mode = S_IRUGO | S_IWUSR,
3471 + },
3472 + .show = gpio_show_oe_mask,
3473 + .store = gpio_store_oe_mask,
3474 +};
3475 +static struct gpio_attribute gpio_item_attr_enabled = {
3476 + .attr = {
3477 + .ca_owner = THIS_MODULE,
3478 + .ca_name = "enabled",
3479 + .ca_mode = S_IRUGO | S_IWUSR,
3480 + },
3481 + .show = gpio_show_enabled,
3482 + .store = gpio_store_enabled,
3483 +};
3484 +
3485 +static struct configfs_attribute *gpio_item_attrs[] = {
3486 + &gpio_item_attr_gpio_id.attr,
3487 + &gpio_item_attr_pin_mask.attr,
3488 + &gpio_item_attr_oe_mask.attr,
3489 + &gpio_item_attr_enabled.attr,
3490 + NULL,
3491 +};
3492 +
3493 +static ssize_t gpio_show_attr(struct config_item *item,
3494 + struct configfs_attribute *attr,
3495 + char *page)
3496 +{
3497 + struct gpio_item *gpio_item = to_gpio_item(item);
3498 + struct gpio_attribute *gpio_attr
3499 + = container_of(attr, struct gpio_attribute, attr);
3500 + ssize_t ret = 0;
3501 +
3502 + if (gpio_attr->show)
3503 + ret = gpio_attr->show(gpio_item, page);
3504 + return ret;
3505 +}
3506 +
3507 +static ssize_t gpio_store_attr(struct config_item *item,
3508 + struct configfs_attribute *attr,
3509 + const char *page, size_t count)
3510 +{
3511 + struct gpio_item *gpio_item = to_gpio_item(item);
3512 + struct gpio_attribute *gpio_attr
3513 + = container_of(attr, struct gpio_attribute, attr);
3514 + ssize_t ret = -EINVAL;
3515 +
3516 + if (gpio_attr->store)
3517 + ret = gpio_attr->store(gpio_item, page, count);
3518 + return ret;
3519 +}
3520 +
3521 +static void gpio_release(struct config_item *item)
3522 +{
3523 + kfree(to_gpio_item(item));
3524 +}
3525 +
3526 +static struct configfs_item_operations gpio_item_ops = {
3527 + .release = gpio_release,
3528 + .show_attribute = gpio_show_attr,
3529 + .store_attribute = gpio_store_attr,
3530 +};
3531 +
3532 +static struct config_item_type gpio_item_type = {
3533 + .ct_item_ops = &gpio_item_ops,
3534 + .ct_attrs = gpio_item_attrs,
3535 + .ct_owner = THIS_MODULE,
3536 +};
3537 +
3538 +static struct config_item *gpio_make_item(struct config_group *group,
3539 + const char *name)
3540 +{
3541 + static int next_id;
3542 + struct gpio_item *gpio;
3543 +
3544 + if (next_id >= GPIO_DEV_MAX)
3545 + return NULL;
3546 +
3547 + gpio = kzalloc(sizeof(struct gpio_item), GFP_KERNEL);
3548 + if (!gpio)
3549 + return NULL;
3550 +
3551 + gpio->id = next_id++;
3552 + config_item_init_type_name(&gpio->item, name, &gpio_item_type);
3553 + spin_lock_init(&gpio->lock);
3554 + init_waitqueue_head(&gpio->change_wq);
3555 +
3556 + return &gpio->item;
3557 +}
3558 +
3559 +static void gpio_drop_item(struct config_group *group,
3560 + struct config_item *item)
3561 +{
3562 + struct gpio_item *gpio = to_gpio_item(item);
3563 +
3564 + spin_lock(&gpio->lock);
3565 + if (gpio->enabled) {
3566 + class_device_unregister(gpio->gpio_dev);
3567 + cdev_del(&gpio->char_dev);
3568 + }
3569 +
3570 + if (gpio->initialized) {
3571 + at32_deselect_pins(gpio->port, gpio->pin_mask);
3572 + gpio->initialized = 0;
3573 + gpio->enabled = 0;
3574 + }
3575 + spin_unlock(&gpio->lock);
3576 +}
3577 +
3578 +static struct configfs_group_operations gpio_group_ops = {
3579 + .make_item = gpio_make_item,
3580 + .drop_item = gpio_drop_item,
3581 +};
3582 +
3583 +static struct config_item_type gpio_group_type = {
3584 + .ct_group_ops = &gpio_group_ops,
3585 + .ct_owner = THIS_MODULE,
3586 +};
3587 +
3588 +static struct configfs_subsystem gpio_subsys = {
3589 + .su_group = {
3590 + .cg_item = {
3591 + .ci_namebuf = "gpio",
3592 + .ci_type = &gpio_group_type,
3593 + },
3594 + },
3595 +};
3596 +
3597 +static int __init gpio_dev_init(void)
3598 +{
3599 + int err;
3600 +
3601 + gpio_dev_class = class_create(THIS_MODULE, "gpio-dev");
3602 + if (IS_ERR(gpio_dev_class)) {
3603 + err = PTR_ERR(gpio_dev_class);
3604 + goto err_class_create;
3605 + }
3606 +
3607 + err = alloc_chrdev_region(&gpio_devt, 0, GPIO_DEV_MAX, "gpio");
3608 + if (err < 0)
3609 + goto err_alloc_chrdev;
3610 +
3611 + /* Configfs initialization */
3612 + config_group_init(&gpio_subsys.su_group);
3613 + mutex_init(&gpio_subsys.su_mutex);
3614 + err = configfs_register_subsystem(&gpio_subsys);
3615 + if (err)
3616 + goto err_register_subsys;
3617 +
3618 + return 0;
3619 +
3620 +err_register_subsys:
3621 + unregister_chrdev_region(gpio_devt, GPIO_DEV_MAX);
3622 +err_alloc_chrdev:
3623 + class_destroy(gpio_dev_class);
3624 +err_class_create:
3625 + printk(KERN_WARNING "Failed to initialize gpio /dev interface\n");
3626 + return err;
3627 +}
3628 +late_initcall(gpio_dev_init);
3629 diff --git a/arch/avr32/mach-at32ap/hsmc.c b/arch/avr32/mach-at32ap/hsmc.c
3630 index 5e22a75..704607f 100644
3631 --- a/arch/avr32/mach-at32ap/hsmc.c
3632 +++ b/arch/avr32/mach-at32ap/hsmc.c
3633 @@ -29,16 +29,25 @@ struct hsmc {
3634
3635 static struct hsmc *hsmc;
3636
3637 -int smc_set_configuration(int cs, const struct smc_config *config)
3638 +void smc_set_timing(struct smc_config *config,
3639 + const struct smc_timing *timing)
3640 {
3641 + int recover;
3642 + int cycle;
3643 +
3644 unsigned long mul;
3645 - unsigned long offset;
3646 - u32 setup, pulse, cycle, mode;
3647
3648 - if (!hsmc)
3649 - return -ENODEV;
3650 - if (cs >= NR_CHIP_SELECTS)
3651 - return -EINVAL;
3652 + /* Reset all SMC timings */
3653 + config->ncs_read_setup = 0;
3654 + config->nrd_setup = 0;
3655 + config->ncs_write_setup = 0;
3656 + config->nwe_setup = 0;
3657 + config->ncs_read_pulse = 0;
3658 + config->nrd_pulse = 0;
3659 + config->ncs_write_pulse = 0;
3660 + config->nwe_pulse = 0;
3661 + config->read_cycle = 0;
3662 + config->write_cycle = 0;
3663
3664 /*
3665 * cycles = x / T = x * f
3666 @@ -50,16 +59,102 @@ int smc_set_configuration(int cs, const struct smc_config *config)
3667
3668 #define ns2cyc(x) ((((x) * mul) + 65535) >> 16)
3669
3670 - setup = (HSMC_BF(NWE_SETUP, ns2cyc(config->nwe_setup))
3671 - | HSMC_BF(NCS_WR_SETUP, ns2cyc(config->ncs_write_setup))
3672 - | HSMC_BF(NRD_SETUP, ns2cyc(config->nrd_setup))
3673 - | HSMC_BF(NCS_RD_SETUP, ns2cyc(config->ncs_read_setup)));
3674 - pulse = (HSMC_BF(NWE_PULSE, ns2cyc(config->nwe_pulse))
3675 - | HSMC_BF(NCS_WR_PULSE, ns2cyc(config->ncs_write_pulse))
3676 - | HSMC_BF(NRD_PULSE, ns2cyc(config->nrd_pulse))
3677 - | HSMC_BF(NCS_RD_PULSE, ns2cyc(config->ncs_read_pulse)));
3678 - cycle = (HSMC_BF(NWE_CYCLE, ns2cyc(config->write_cycle))
3679 - | HSMC_BF(NRD_CYCLE, ns2cyc(config->read_cycle)));
3680 + if (timing->ncs_read_setup > 0)
3681 + config->ncs_read_setup = ns2cyc(timing->ncs_read_setup);
3682 +
3683 + if (timing->nrd_setup > 0)
3684 + config->nrd_setup = ns2cyc(timing->nrd_setup);
3685 +
3686 + if (timing->ncs_write_setup > 0)
3687 + config->ncs_write_setup = ns2cyc(timing->ncs_write_setup);
3688 +
3689 + if (timing->nwe_setup > 0)
3690 + config->nwe_setup = ns2cyc(timing->nwe_setup);
3691 +
3692 + if (timing->ncs_read_pulse > 0)
3693 + config->ncs_read_pulse = ns2cyc(timing->ncs_read_pulse);
3694 +
3695 + if (timing->nrd_pulse > 0)
3696 + config->nrd_pulse = ns2cyc(timing->nrd_pulse);
3697 +
3698 + if (timing->ncs_write_pulse > 0)
3699 + config->ncs_write_pulse = ns2cyc(timing->ncs_write_pulse);
3700 +
3701 + if (timing->nwe_pulse > 0)
3702 + config->nwe_pulse = ns2cyc(timing->nwe_pulse);
3703 +
3704 + if (timing->read_cycle > 0)
3705 + config->read_cycle = ns2cyc(timing->read_cycle);
3706 +
3707 + if (timing->write_cycle > 0)
3708 + config->write_cycle = ns2cyc(timing->write_cycle);
3709 +
3710 + /* Extend read cycle in needed */
3711 + if (timing->ncs_read_recover > 0)
3712 + recover = ns2cyc(timing->ncs_read_recover);
3713 + else
3714 + recover = 1;
3715 +
3716 + cycle = config->ncs_read_setup + config->ncs_read_pulse + recover;
3717 +
3718 + if (config->read_cycle < cycle)
3719 + config->read_cycle = cycle;
3720 +
3721 + /* Extend read cycle in needed */
3722 + if (timing->nrd_recover > 0)
3723 + recover = ns2cyc(timing->nrd_recover);
3724 + else
3725 + recover = 1;
3726 +
3727 + cycle = config->nrd_setup + config->nrd_pulse + recover;
3728 +
3729 + if (config->read_cycle < cycle)
3730 + config->read_cycle = cycle;
3731 +
3732 + /* Extend write cycle in needed */
3733 + if (timing->ncs_write_recover > 0)
3734 + recover = ns2cyc(timing->ncs_write_recover);
3735 + else
3736 + recover = 1;
3737 +
3738 + cycle = config->ncs_write_setup + config->ncs_write_pulse + recover;
3739 +
3740 + if (config->write_cycle < cycle)
3741 + config->write_cycle = cycle;
3742 +
3743 + /* Extend write cycle in needed */
3744 + if (timing->nwe_recover > 0)
3745 + recover = ns2cyc(timing->nwe_recover);
3746 + else
3747 + recover = 1;
3748 +
3749 + cycle = config->nwe_setup + config->nwe_pulse + recover;
3750 +
3751 + if (config->write_cycle < cycle)
3752 + config->write_cycle = cycle;
3753 +}
3754 +EXPORT_SYMBOL(smc_set_timing);
3755 +
3756 +int smc_set_configuration(int cs, const struct smc_config *config)
3757 +{
3758 + unsigned long offset;
3759 + u32 setup, pulse, cycle, mode;
3760 +
3761 + if (!hsmc)
3762 + return -ENODEV;
3763 + if (cs >= NR_CHIP_SELECTS)
3764 + return -EINVAL;
3765 +
3766 + setup = (HSMC_BF(NWE_SETUP, config->nwe_setup)
3767 + | HSMC_BF(NCS_WR_SETUP, config->ncs_write_setup)
3768 + | HSMC_BF(NRD_SETUP, config->nrd_setup)
3769 + | HSMC_BF(NCS_RD_SETUP, config->ncs_read_setup));
3770 + pulse = (HSMC_BF(NWE_PULSE, config->nwe_pulse)
3771 + | HSMC_BF(NCS_WR_PULSE, config->ncs_write_pulse)
3772 + | HSMC_BF(NRD_PULSE, config->nrd_pulse)
3773 + | HSMC_BF(NCS_RD_PULSE, config->ncs_read_pulse));
3774 + cycle = (HSMC_BF(NWE_CYCLE, config->write_cycle)
3775 + | HSMC_BF(NRD_CYCLE, config->read_cycle));
3776
3777 switch (config->bus_width) {
3778 case 1:
3779 diff --git a/arch/avr32/mach-at32ap/pio.c b/arch/avr32/mach-at32ap/pio.c
3780 index 1eb99b8..c978c36 100644
3781 --- a/arch/avr32/mach-at32ap/pio.c
3782 +++ b/arch/avr32/mach-at32ap/pio.c
3783 @@ -110,6 +110,10 @@ void __init at32_select_gpio(unsigned int pin, unsigned long flags)
3784 pio_writel(pio, SODR, mask);
3785 else
3786 pio_writel(pio, CODR, mask);
3787 + if (flags & AT32_GPIOF_MULTIDRV)
3788 + pio_writel(pio, MDER, mask);
3789 + else
3790 + pio_writel(pio, MDDR, mask);
3791 pio_writel(pio, PUDR, mask);
3792 pio_writel(pio, OER, mask);
3793 } else {
3794 @@ -158,6 +162,82 @@ fail:
3795 dump_stack();
3796 }
3797
3798 +#ifdef CONFIG_GPIO_DEV
3799 +
3800 +/* Gang allocators and accessors; used by the GPIO /dev driver */
3801 +int at32_gpio_port_is_valid(unsigned int port)
3802 +{
3803 + return port < MAX_NR_PIO_DEVICES && pio_dev[port].regs != NULL;
3804 +}
3805 +
3806 +int at32_select_gpio_pins(unsigned int port, u32 pins, u32 oe_mask)
3807 +{
3808 + struct pio_device *pio;
3809 + u32 old, new;
3810 +
3811 + pio = &pio_dev[port];
3812 + BUG_ON(port > ARRAY_SIZE(pio_dev) || !pio->regs || (oe_mask & ~pins));
3813 +
3814 + /* Try to allocate the pins */
3815 + do {
3816 + old = pio->pinmux_mask;
3817 + if (old & pins)
3818 + return -EBUSY;
3819 +
3820 + new = old | pins;
3821 + } while (cmpxchg(&pio->pinmux_mask, old, new) != old);
3822 +
3823 + /* That went well, now configure the port */
3824 + pio_writel(pio, OER, oe_mask);
3825 + pio_writel(pio, PER, pins);
3826 +
3827 + return 0;
3828 +}
3829 +
3830 +void at32_deselect_pins(unsigned int port, u32 pins)
3831 +{
3832 + struct pio_device *pio;
3833 + u32 old, new;
3834 +
3835 + pio = &pio_dev[port];
3836 + BUG_ON(port > ARRAY_SIZE(pio_dev) || !pio->regs);
3837 +
3838 + /* Return to a "safe" mux configuration */
3839 + pio_writel(pio, PUER, pins);
3840 + pio_writel(pio, ODR, pins);
3841 +
3842 + /* Deallocate the pins */
3843 + do {
3844 + old = pio->pinmux_mask;
3845 + new = old & ~pins;
3846 + } while (cmpxchg(&pio->pinmux_mask, old, new) != old);
3847 +}
3848 +
3849 +u32 at32_gpio_get_value_multiple(unsigned int port, u32 pins)
3850 +{
3851 + struct pio_device *pio;
3852 +
3853 + pio = &pio_dev[port];
3854 + BUG_ON(port > ARRAY_SIZE(pio_dev) || !pio->regs);
3855 +
3856 + return pio_readl(pio, PDSR) & pins;
3857 +}
3858 +
3859 +void at32_gpio_set_value_multiple(unsigned int port, u32 value, u32 mask)
3860 +{
3861 + struct pio_device *pio;
3862 +
3863 + pio = &pio_dev[port];
3864 + BUG_ON(port > ARRAY_SIZE(pio_dev) || !pio->regs);
3865 +
3866 + /* No atomic updates for now... */
3867 + pio_writel(pio, CODR, ~value & mask);
3868 + pio_writel(pio, SODR, value & mask);
3869 +}
3870 +
3871 +#endif /* CONFIG_GPIO_DEV */
3872 +
3873 +
3874 /*--------------------------------------------------------------------------*/
3875
3876 /* GPIO API */
3877 diff --git a/arch/avr32/mach-at32ap/pm.h b/arch/avr32/mach-at32ap/pm.h
3878 index a1f8ace..47efd0d 100644
3879 --- a/arch/avr32/mach-at32ap/pm.h
3880 +++ b/arch/avr32/mach-at32ap/pm.h
3881 @@ -4,6 +4,14 @@
3882 #ifndef __ARCH_AVR32_MACH_AT32AP_PM_H__
3883 #define __ARCH_AVR32_MACH_AT32AP_PM_H__
3884
3885 +/*
3886 + * We can reduce the code size a bit by using a constant here. Since
3887 + * this file is only used on AVR32 AP CPUs with segmentation enabled,
3888 + * it's safe to not use ioremap. Generic drivers should of course
3889 + * never do this.
3890 + */
3891 +#define AT32_PM_BASE 0xfff00000
3892 +
3893 /* PM register offsets */
3894 #define PM_MCCTRL 0x0000
3895 #define PM_CKSEL 0x0004
3896 diff --git a/arch/avr32/mm/dma-coherent.c b/arch/avr32/mm/dma-coherent.c
3897 index 099212d..26f29c6 100644
3898 --- a/arch/avr32/mm/dma-coherent.c
3899 +++ b/arch/avr32/mm/dma-coherent.c
3900 @@ -41,6 +41,13 @@ static struct page *__dma_alloc(struct device *dev, size_t size,
3901 struct page *page, *free, *end;
3902 int order;
3903
3904 + /* Following is a work-around (a.k.a. hack) to prevent pages
3905 + * with __GFP_COMP being passed to split_page() which cannot
3906 + * handle them. The real problem is that this flag probably
3907 + * should be 0 on AVR32 as it is not supported on this
3908 + * platform--see CONFIG_HUGETLB_PAGE. */
3909 + gfp &= ~(__GFP_COMP);
3910 +
3911 size = PAGE_ALIGN(size);
3912 order = get_order(size);
3913
3914 diff --git a/arch/avr32/mm/init.c b/arch/avr32/mm/init.c
3915 index 82cf708..480760b 100644
3916 --- a/arch/avr32/mm/init.c
3917 +++ b/arch/avr32/mm/init.c
3918 @@ -224,19 +224,9 @@ void free_initmem(void)
3919
3920 #ifdef CONFIG_BLK_DEV_INITRD
3921
3922 -static int keep_initrd;
3923 -
3924 void free_initrd_mem(unsigned long start, unsigned long end)
3925 {
3926 - if (!keep_initrd)
3927 - free_area(start, end, "initrd");
3928 -}
3929 -
3930 -static int __init keepinitrd_setup(char *__unused)
3931 -{
3932 - keep_initrd = 1;
3933 - return 1;
3934 + free_area(start, end, "initrd");
3935 }
3936
3937 -__setup("keepinitrd", keepinitrd_setup);
3938 #endif
3939 diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
3940 index 9f3a4cd..6f5bcd6 100644
3941 --- a/drivers/i2c/busses/Kconfig
3942 +++ b/drivers/i2c/busses/Kconfig
3943 @@ -80,6 +80,14 @@ config I2C_AT91
3944 This supports the use of the I2C interface on Atmel AT91
3945 processors.
3946
3947 +config I2C_ATMELTWI
3948 + tristate "Atmel Two-Wire Interface (TWI)"
3949 + depends on I2C && (ARCH_AT91 || PLATFORM_AT32AP)
3950 + help
3951 + Atmel on-chip TWI controller. Say Y if you have an AT32 or
3952 + AT91-based device and want to use its built-in TWI
3953 + functionality.
3954 +
3955 config I2C_AU1550
3956 tristate "Au1550/Au1200 SMBus interface"
3957 depends on SOC_AU1550 || SOC_AU1200
3958 diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
3959 index 5b752e4..e4644a8 100644
3960 --- a/drivers/i2c/busses/Makefile
3961 +++ b/drivers/i2c/busses/Makefile
3962 @@ -52,6 +52,7 @@ obj-$(CONFIG_I2C_VIAPRO) += i2c-viapro.o
3963 obj-$(CONFIG_I2C_VOODOO3) += i2c-voodoo3.o
3964 obj-$(CONFIG_SCx200_ACB) += scx200_acb.o
3965 obj-$(CONFIG_SCx200_I2C) += scx200_i2c.o
3966 +obj-$(CONFIG_I2C_ATMELTWI) += i2c-atmeltwi.o
3967
3968 ifeq ($(CONFIG_I2C_DEBUG_BUS),y)
3969 EXTRA_CFLAGS += -DDEBUG
3970 diff --git a/drivers/i2c/busses/i2c-atmeltwi.c b/drivers/i2c/busses/i2c-atmeltwi.c
3971 new file mode 100644
3972 index 0000000..3f78b31
3973 --- /dev/null
3974 +++ b/drivers/i2c/busses/i2c-atmeltwi.c
3975 @@ -0,0 +1,436 @@
3976 +/*
3977 + * i2c Support for Atmel's Two-Wire Interface (TWI)
3978 + *
3979 + * Based on the work of Copyright (C) 2004 Rick Bronson
3980 + * Converted to 2.6 by Andrew Victor <andrew at sanpeople.com>
3981 + * Ported to AVR32 and heavily modified by Espen Krangnes
3982 + * <ekrangnes at atmel.com>
3983 + *
3984 + * Copyright (C) 2006 Atmel Corporation
3985 + *
3986 + * Borrowed heavily from the original work by:
3987 + * Copyright (C) 2000 Philip Edelbrock <phil at stimpy.netroedge.com>
3988 + *
3989 + * Partialy rewriten by Karel Hojdar <cmkaho at seznam.cz>
3990 + * bugs removed, interrupt routine markedly rewritten
3991 + *
3992 + * This program is free software; you can redistribute it and/or modify
3993 + * it under the terms of the GNU General Public License as published by
3994 + * the Free Software Foundation; either version 2 of the License, or
3995 + * (at your option) any later version.
3996 + */
3997 +#undef VERBOSE_DEBUG
3998 +
3999 +#include <linux/module.h>
4000 +#include <linux/slab.h>
4001 +#include <linux/i2c.h>
4002 +#include <linux/init.h>
4003 +#include <linux/clk.h>
4004 +#include <linux/err.h>
4005 +#include <linux/interrupt.h>
4006 +#include <linux/platform_device.h>
4007 +#include <linux/completion.h>
4008 +#include <linux/io.h>
4009 +
4010 +#include "i2c-atmeltwi.h"
4011 +
4012 +static unsigned int baudrate = 100 * 1000;
4013 +module_param(baudrate, uint, S_IRUGO);
4014 +MODULE_PARM_DESC(baudrate, "The TWI baudrate");
4015 +
4016 +
4017 +struct atmel_twi {
4018 + void __iomem *regs;
4019 + struct i2c_adapter adapter;
4020 + struct clk *pclk;
4021 + struct completion comp;
4022 + u32 mask;
4023 + u8 *buf;
4024 + u16 len;
4025 + u16 acks_left;
4026 + int status;
4027 + unsigned int irq;
4028 +
4029 +};
4030 +#define to_atmel_twi(adap) container_of(adap, struct atmel_twi, adapter)
4031 +
4032 +/*
4033 + * (Re)Initialize the TWI hardware registers.
4034 + */
4035 +static int twi_hwinit(struct atmel_twi *twi)
4036 +{
4037 + unsigned long cdiv, ckdiv = 0;
4038 +
4039 + /* REVISIT: wait till SCL is high before resetting; otherwise,
4040 + * some versions will wedge forever.
4041 + */
4042 +
4043 + twi_writel(twi, IDR, ~0UL);
4044 + twi_writel(twi, CR, TWI_BIT(SWRST)); /*Reset peripheral*/
4045 + twi_readl(twi, SR);
4046 +
4047 + cdiv = (clk_get_rate(twi->pclk) / (2 * baudrate)) - 4;
4048 +
4049 + while (cdiv > 255) {
4050 + ckdiv++;
4051 + cdiv = cdiv >> 1;
4052 + }
4053 +
4054 + /* REVISIT: there are various errata to consider re CDIV and CHDIV
4055 + * here, at least on at91 parts.
4056 + */
4057 +
4058 + if (ckdiv > 7)
4059 + return -EINVAL;
4060 + else
4061 + twi_writel(twi, CWGR, TWI_BF(CKDIV, ckdiv)
4062 + | TWI_BF(CHDIV, cdiv)
4063 + | TWI_BF(CLDIV, cdiv));
4064 + return 0;
4065 +}
4066 +
4067 +/*
4068 + * Waits for the i2c status register to set the specified bitmask
4069 + * Returns 0 if timed out ... ~100ms is much longer than the SMBus
4070 + * limit, but I2C has no limit at all.
4071 + */
4072 +static int twi_complete(struct atmel_twi *twi, u32 mask)
4073 +{
4074 + int timeout = msecs_to_jiffies(100);
4075 +
4076 + mask |= TWI_BIT(TXCOMP);
4077 + twi->mask = mask | TWI_BIT(NACK) | TWI_BIT(OVRE);
4078 + init_completion(&twi->comp);
4079 +
4080 + twi_writel(twi, IER, mask);
4081 +
4082 + if (!wait_for_completion_timeout(&twi->comp, timeout)) {
4083 + /* RESET TWI interface */
4084 + twi_writel(twi, CR, TWI_BIT(SWRST));
4085 +
4086 + /* Reinitialize TWI */
4087 + twi_hwinit(twi);
4088 +
4089 + return -ETIMEDOUT;
4090 + }
4091 + return 0;
4092 +}
4093 +
4094 +/*
4095 + * Generic i2c master transfer entrypoint.
4096 + */
4097 +static int twi_xfer(struct i2c_adapter *adap, struct i2c_msg *pmsg, int num)
4098 +{
4099 + struct atmel_twi *twi = to_atmel_twi(adap);
4100 + int i;
4101 +
4102 + dev_dbg(&adap->dev, "twi_xfer: processing %d messages:\n", num);
4103 +
4104 + twi->status = 0;
4105 + for (i = 0; i < num; i++, pmsg++) {
4106 + twi->len = pmsg->len;
4107 + twi->buf = pmsg->buf;
4108 + twi->acks_left = pmsg->len;
4109 + twi_writel(twi, MMR, TWI_BF(DADR, pmsg->addr) |
4110 + (pmsg->flags & I2C_M_RD ? TWI_BIT(MREAD) : 0));
4111 + twi_writel(twi, IADR, TWI_BF(IADR, pmsg->addr));
4112 +
4113 + dev_dbg(&adap->dev,
4114 + "#%d: %s %d byte%s %s dev 0x%02x\n",
4115 + i,
4116 + pmsg->flags & I2C_M_RD ? "reading" : "writing",
4117 + pmsg->len,
4118 + pmsg->len > 1 ? "s" : "",
4119 + pmsg->flags & I2C_M_RD ? "from" : "to", pmsg->addr);
4120 +
4121 + /* enable */
4122 + twi_writel(twi, CR, TWI_BIT(MSEN));
4123 +
4124 + if (pmsg->flags & I2C_M_RD) {
4125 + /* cleanup after previous RX overruns */
4126 + while (twi_readl(twi, SR) & TWI_BIT(RXRDY))
4127 + twi_readl(twi, RHR);
4128 +
4129 + if (twi->len == 1)
4130 + twi_writel(twi, CR,
4131 + TWI_BIT(START) | TWI_BIT(STOP));
4132 + else
4133 + twi_writel(twi, CR, TWI_BIT(START));
4134 +
4135 + if (twi_complete(twi, TWI_BIT(RXRDY)) == -ETIMEDOUT) {
4136 + dev_dbg(&adap->dev, "RX[%d] timeout. "
4137 + "Stopped with %d bytes left\n",
4138 + i, twi->acks_left);
4139 + return -ETIMEDOUT;
4140 + }
4141 + } else {
4142 + twi_writel(twi, THR, twi->buf[0]);
4143 + twi->acks_left--;
4144 + /* REVISIT: some chips don't start automagically:
4145 + * twi_writel(twi, CR, TWI_BIT(START));
4146 + */
4147 + if (twi_complete(twi, TWI_BIT(TXRDY)) == -ETIMEDOUT) {
4148 + dev_dbg(&adap->dev, "TX[%d] timeout. "
4149 + "Stopped with %d bytes left\n",
4150 + i, twi->acks_left);
4151 + return -ETIMEDOUT;
4152 + }
4153 + /* REVISIT: an erratum workaround may be needed here;
4154 + * see sam9261 "STOP not generated" (START either).
4155 + */
4156 + }
4157 +
4158 + /* Disable TWI interface */
4159 + twi_writel(twi, CR, TWI_BIT(MSDIS));
4160 +
4161 + if (twi->status)
4162 + return twi->status;
4163 +
4164 + /* WARNING: This driver lies about properly supporting
4165 + * repeated start, or it would *ALWAYS* return here. It
4166 + * has issued a STOP. Continuing is a false claim -- that
4167 + * a second (or third, etc.) message is part of the same
4168 + * "combined" (no STOPs between parts) message.
4169 + */
4170 +
4171 + } /* end cur msg */
4172 +
4173 + return i;
4174 +}
4175 +
4176 +
4177 +static irqreturn_t twi_interrupt(int irq, void *dev_id)
4178 +{
4179 + struct atmel_twi *twi = dev_id;
4180 + int status = twi_readl(twi, SR);
4181 +
4182 + /* Save state for later debug prints */
4183 + int old_status = status;
4184 +
4185 + if (twi->mask & status) {
4186 +
4187 + status &= twi->mask;
4188 +
4189 + if (status & TWI_BIT(RXRDY)) {
4190 + if ((status & TWI_BIT(OVRE)) && twi->acks_left) {
4191 + /* Note weakness in fault reporting model:
4192 + * we can't say "the first N of these data
4193 + * bytes are valid".
4194 + */
4195 + dev_err(&twi->adapter.dev,
4196 + "OVERRUN RX! %04x, lost %d\n",
4197 + old_status, twi->acks_left);
4198 + twi->acks_left = 0;
4199 + twi_writel(twi, CR, TWI_BIT(STOP));
4200 + twi->status = -EOVERFLOW;
4201 + } else if (twi->acks_left > 0) {
4202 + twi->buf[twi->len - twi->acks_left] =
4203 + twi_readl(twi, RHR);
4204 + twi->acks_left--;
4205 + }
4206 + if (status & TWI_BIT(TXCOMP))
4207 + goto done;
4208 + if (twi->acks_left == 1)
4209 + twi_writel(twi, CR, TWI_BIT(STOP));
4210 +
4211 + } else if (status & (TWI_BIT(NACK) | TWI_BIT(TXCOMP))) {
4212 + goto done;
4213 +
4214 + } else if (status & TWI_BIT(TXRDY)) {
4215 + if (twi->acks_left > 0) {
4216 + twi->acks_left--;
4217 + twi_writel(twi, THR,
4218 + twi->buf[twi->len - twi->acks_left]);
4219 + } else
4220 + twi_writel(twi, CR, TWI_BIT(STOP));
4221 + }
4222 +
4223 + if (twi->acks_left == 0)
4224 + twi_writel(twi, IDR, ~TWI_BIT(TXCOMP));
4225 + }
4226 +
4227 + /* enabling this message helps trigger overruns/underruns ... */
4228 + dev_vdbg(&twi->adapter.dev,
4229 + "ISR: SR 0x%04X, mask 0x%04X, acks %i\n",
4230 + old_status,
4231 + twi->acks_left ? twi->mask : TWI_BIT(TXCOMP),
4232 + twi->acks_left);
4233 +
4234 + return IRQ_HANDLED;
4235 +
4236 +done:
4237 + /* Note weak fault reporting model: we can't report how many
4238 + * bytes we sent before the NAK, or let upper layers choose
4239 + * whether to continue. The I2C stack doesn't allow that...
4240 + */
4241 + if (status & TWI_BIT(NACK)) {
4242 + dev_dbg(&twi->adapter.dev, "NACK received! %d to go\n",
4243 + twi->acks_left);
4244 + twi->status = -EPIPE;
4245 +
4246 + /* TX underrun morphs automagically into a premature STOP;
4247 + * we'll probably observe UVRE even when it's not documented.
4248 + */
4249 + } else if (twi->acks_left && (twi->mask & TWI_BIT(TXRDY))) {
4250 + dev_err(&twi->adapter.dev, "UNDERRUN TX! %04x, %d to go\n",
4251 + old_status, twi->acks_left);
4252 + twi->status = -ENOSR;
4253 + }
4254 +
4255 + twi_writel(twi, IDR, ~0UL);
4256 + complete(&twi->comp);
4257 +
4258 + dev_dbg(&twi->adapter.dev, "ISR: SR 0x%04X, acks %i --> %d\n",
4259 + old_status, twi->acks_left, twi->status);
4260 +
4261 + return IRQ_HANDLED;
4262 +}
4263 +
4264 +
4265 +/*
4266 + * Return list of supported functionality.
4267 + *
4268 + * NOTE: see warning above about repeated starts; this driver is falsely
4269 + * claiming to support "combined" transfers. The mid-message STOPs mean
4270 + * some slaves will never work with this driver. (Use i2c-gpio...)
4271 + */
4272 +static u32 twi_func(struct i2c_adapter *adapter)
4273 +{
4274 + return (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL)
4275 + & ~I2C_FUNC_SMBUS_QUICK;
4276 +}
4277 +
4278 +static struct i2c_algorithm twi_algorithm = {
4279 + .master_xfer = twi_xfer,
4280 + .functionality = twi_func,
4281 +};
4282 +
4283 +/*
4284 + * Main initialization routine.
4285 + */
4286 +static int __init twi_probe(struct platform_device *pdev)
4287 +{
4288 + struct atmel_twi *twi;
4289 + struct resource *regs;
4290 + struct clk *pclk;
4291 + struct i2c_adapter *adapter;
4292 + int rc, irq;
4293 +
4294 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4295 + if (!regs)
4296 + return -ENXIO;
4297 +
4298 + pclk = clk_get(&pdev->dev, "pclk");
4299 + if (IS_ERR(pclk))
4300 + return PTR_ERR(pclk);
4301 + clk_enable(pclk);
4302 +
4303 + rc = -ENOMEM;
4304 + twi = kzalloc(sizeof(struct atmel_twi), GFP_KERNEL);
4305 + if (!twi) {
4306 + dev_dbg(&pdev->dev, "can't allocate interface!\n");
4307 + goto err_alloc_twi;
4308 + }
4309 +
4310 + twi->pclk = pclk;
4311 + twi->regs = ioremap(regs->start, regs->end - regs->start + 1);
4312 + if (!twi->regs)
4313 + goto err_ioremap;
4314 +
4315 + irq = platform_get_irq(pdev, 0);
4316 + rc = request_irq(irq, twi_interrupt, 0, "twi", twi);
4317 + if (rc) {
4318 + dev_dbg(&pdev->dev, "can't bind irq!\n");
4319 + goto err_irq;
4320 + }
4321 + twi->irq = irq;
4322 +
4323 + rc = twi_hwinit(twi);
4324 + if (rc) {
4325 + dev_err(&pdev->dev, "Unable to set baudrate\n");
4326 + goto err_hw_init;
4327 + }
4328 +
4329 + adapter = &twi->adapter;
4330 + sprintf(adapter->name, "TWI");
4331 + adapter->algo = &twi_algorithm;
4332 + adapter->class = I2C_CLASS_ALL;
4333 + adapter->nr = pdev->id;
4334 + adapter->dev.parent = &pdev->dev;
4335 +
4336 + platform_set_drvdata(pdev, twi);
4337 +
4338 + rc = i2c_add_numbered_adapter(adapter);
4339 + if (rc) {
4340 + dev_dbg(&pdev->dev, "Adapter %s registration failed\n",
4341 + adapter->name);
4342 + goto err_register;
4343 + }
4344 +
4345 + dev_info(&pdev->dev,
4346 + "Atmel TWI/I2C adapter (baudrate %dk) at 0x%08lx.\n",
4347 + baudrate/1000, (unsigned long)regs->start);
4348 +
4349 + return 0;
4350 +
4351 +
4352 +err_register:
4353 + platform_set_drvdata(pdev, NULL);
4354 +
4355 +err_hw_init:
4356 + free_irq(irq, twi);
4357 +
4358 +err_irq:
4359 + iounmap(twi->regs);
4360 +
4361 +err_ioremap:
4362 + kfree(twi);
4363 +
4364 +err_alloc_twi:
4365 + clk_disable(pclk);
4366 + clk_put(pclk);
4367 +
4368 + return rc;
4369 +}
4370 +
4371 +static int __exit twi_remove(struct platform_device *pdev)
4372 +{
4373 + struct atmel_twi *twi = platform_get_drvdata(pdev);
4374 + int res;
4375 +
4376 + platform_set_drvdata(pdev, NULL);
4377 + res = i2c_del_adapter(&twi->adapter);
4378 + twi_writel(twi, CR, TWI_BIT(MSDIS));
4379 + iounmap(twi->regs);
4380 + clk_disable(twi->pclk);
4381 + clk_put(twi->pclk);
4382 + free_irq(twi->irq, twi);
4383 + kfree(twi);
4384 +
4385 + return res;
4386 +}
4387 +
4388 +static struct platform_driver twi_driver = {
4389 + .remove = __exit_p(twi_remove),
4390 + .driver = {
4391 + .name = "atmel_twi",
4392 + .owner = THIS_MODULE,
4393 + },
4394 +};
4395 +
4396 +static int __init atmel_twi_init(void)
4397 +{
4398 + return platform_driver_probe(&twi_driver, twi_probe);
4399 +}
4400 +
4401 +static void __exit atmel_twi_exit(void)
4402 +{
4403 + platform_driver_unregister(&twi_driver);
4404 +}
4405 +
4406 +module_init(atmel_twi_init);
4407 +module_exit(atmel_twi_exit);
4408 +
4409 +MODULE_AUTHOR("Espen Krangnes");
4410 +MODULE_DESCRIPTION("I2C driver for Atmel TWI");
4411 +MODULE_LICENSE("GPL");
4412 diff --git a/drivers/i2c/busses/i2c-atmeltwi.h b/drivers/i2c/busses/i2c-atmeltwi.h
4413 new file mode 100644
4414 index 0000000..1aca065
4415 --- /dev/null
4416 +++ b/drivers/i2c/busses/i2c-atmeltwi.h
4417 @@ -0,0 +1,117 @@
4418 +/*
4419 + * Register definitions for the Atmel Two-Wire Interface
4420 + */
4421 +
4422 +#ifndef __ATMELTWI_H__
4423 +#define __ATMELTWI_H__
4424 +
4425 +/* TWI register offsets */
4426 +#define TWI_CR 0x0000
4427 +#define TWI_MMR 0x0004
4428 +#define TWI_SMR 0x0008
4429 +#define TWI_IADR 0x000c
4430 +#define TWI_CWGR 0x0010
4431 +#define TWI_SR 0x0020
4432 +#define TWI_IER 0x0024
4433 +#define TWI_IDR 0x0028
4434 +#define TWI_IMR 0x002c
4435 +#define TWI_RHR 0x0030
4436 +#define TWI_THR 0x0034
4437 +
4438 +/* Bitfields in CR */
4439 +#define TWI_START_OFFSET 0
4440 +#define TWI_START_SIZE 1
4441 +#define TWI_STOP_OFFSET 1
4442 +#define TWI_STOP_SIZE 1
4443 +#define TWI_MSEN_OFFSET 2
4444 +#define TWI_MSEN_SIZE 1
4445 +#define TWI_MSDIS_OFFSET 3
4446 +#define TWI_MSDIS_SIZE 1
4447 +#define TWI_SVEN_OFFSET 4
4448 +#define TWI_SVEN_SIZE 1
4449 +#define TWI_SVDIS_OFFSET 5
4450 +#define TWI_SVDIS_SIZE 1
4451 +#define TWI_SWRST_OFFSET 7
4452 +#define TWI_SWRST_SIZE 1
4453 +
4454 +/* Bitfields in MMR */
4455 +#define TWI_IADRSZ_OFFSET 8
4456 +#define TWI_IADRSZ_SIZE 2
4457 +#define TWI_MREAD_OFFSET 12
4458 +#define TWI_MREAD_SIZE 1
4459 +#define TWI_DADR_OFFSET 16
4460 +#define TWI_DADR_SIZE 7
4461 +
4462 +/* Bitfields in SMR */
4463 +#define TWI_SADR_OFFSET 16
4464 +#define TWI_SADR_SIZE 7
4465 +
4466 +/* Bitfields in IADR */
4467 +#define TWI_IADR_OFFSET 0
4468 +#define TWI_IADR_SIZE 24
4469 +
4470 +/* Bitfields in CWGR */
4471 +#define TWI_CLDIV_OFFSET 0
4472 +#define TWI_CLDIV_SIZE 8
4473 +#define TWI_CHDIV_OFFSET 8
4474 +#define TWI_CHDIV_SIZE 8
4475 +#define TWI_CKDIV_OFFSET 16
4476 +#define TWI_CKDIV_SIZE 3
4477 +
4478 +/* Bitfields in SR */
4479 +#define TWI_TXCOMP_OFFSET 0
4480 +#define TWI_TXCOMP_SIZE 1
4481 +#define TWI_RXRDY_OFFSET 1
4482 +#define TWI_RXRDY_SIZE 1
4483 +#define TWI_TXRDY_OFFSET 2
4484 +#define TWI_TXRDY_SIZE 1
4485 +#define TWI_SVDIR_OFFSET 3
4486 +#define TWI_SVDIR_SIZE 1
4487 +#define TWI_SVACC_OFFSET 4
4488 +#define TWI_SVACC_SIZE 1
4489 +#define TWI_GCACC_OFFSET 5
4490 +#define TWI_GCACC_SIZE 1
4491 +#define TWI_OVRE_OFFSET 6
4492 +#define TWI_OVRE_SIZE 1
4493 +#define TWI_UNRE_OFFSET 7
4494 +#define TWI_UNRE_SIZE 1
4495 +#define TWI_NACK_OFFSET 8
4496 +#define TWI_NACK_SIZE 1
4497 +#define TWI_ARBLST_OFFSET 9
4498 +#define TWI_ARBLST_SIZE 1
4499 +
4500 +/* Bitfields in RHR */
4501 +#define TWI_RXDATA_OFFSET 0
4502 +#define TWI_RXDATA_SIZE 8
4503 +
4504 +/* Bitfields in THR */
4505 +#define TWI_TXDATA_OFFSET 0
4506 +#define TWI_TXDATA_SIZE 8
4507 +
4508 +/* Constants for IADRSZ */
4509 +#define TWI_IADRSZ_NO_ADDR 0
4510 +#define TWI_IADRSZ_ONE_BYTE 1
4511 +#define TWI_IADRSZ_TWO_BYTES 2
4512 +#define TWI_IADRSZ_THREE_BYTES 3
4513 +
4514 +/* Bit manipulation macros */
4515 +#define TWI_BIT(name) \
4516 + (1 << TWI_##name##_OFFSET)
4517 +#define TWI_BF(name, value) \
4518 + (((value) & ((1 << TWI_##name##_SIZE) - 1)) \
4519 + << TWI_##name##_OFFSET)
4520 +#define TWI_BFEXT(name, value) \
4521 + (((value) >> TWI_##name##_OFFSET) \
4522 + & ((1 << TWI_##name##_SIZE) - 1))
4523 +#define TWI_BFINS(name, value, old) \
4524 + (((old) & ~(((1 << TWI_##name##_SIZE) - 1) \
4525 + << TWI_##name##_OFFSET)) \
4526 + | TWI_BF(name, (value)))
4527 +
4528 +/* Register access macros */
4529 +#define twi_readl(port, reg) \
4530 + __raw_readl((port)->regs + TWI_##reg)
4531 +#define twi_writel(port, reg, value) \
4532 + __raw_writel((value), (port)->regs + TWI_##reg)
4533 +
4534 +#endif /* __ATMELTWI_H__ */
4535 diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
4536 index 73e248f..9e848cc 100644
4537 --- a/drivers/misc/Kconfig
4538 +++ b/drivers/misc/Kconfig
4539 @@ -202,5 +202,14 @@ config THINKPAD_ACPI_BAY
4540
4541 If you are not sure, say Y here.
4542
4543 +config ATMEL_SSC
4544 + tristate "Device driver for Atmel SSC peripheral"
4545 + depends on AVR32 || ARCH_AT91
4546 + ---help---
4547 + This option enables device driver support for Atmel Syncronized
4548 + Serial Communication peripheral (SSC).
4549 +
4550 + The SSC peripheral supports a wide variety of serial frame based
4551 + communications, i.e. I2S, SPI, etc.
4552
4553 endif # MISC_DEVICES
4554 diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
4555 index b5ce0e3..40d8ed1 100644
4556 --- a/drivers/misc/Makefile
4557 +++ b/drivers/misc/Makefile
4558 @@ -15,3 +15,4 @@ obj-$(CONFIG_SGI_IOC4) += ioc4.o
4559 obj-$(CONFIG_SONY_LAPTOP) += sony-laptop.o
4560 obj-$(CONFIG_THINKPAD_ACPI) += thinkpad_acpi.o
4561 obj-$(CONFIG_EEPROM_93CX6) += eeprom_93cx6.o
4562 +obj-$(CONFIG_ATMEL_SSC) += atmel-ssc.o
4563 diff --git a/drivers/misc/atmel-ssc.c b/drivers/misc/atmel-ssc.c
4564 new file mode 100644
4565 index 0000000..058ccac
4566 --- /dev/null
4567 +++ b/drivers/misc/atmel-ssc.c
4568 @@ -0,0 +1,174 @@
4569 +/*
4570 + * Atmel SSC driver
4571 + *
4572 + * Copyright (C) 2007 Atmel Corporation
4573 + *
4574 + * This program is free software; you can redistribute it and/or modify
4575 + * it under the terms of the GNU General Public License version 2 as
4576 + * published by the Free Software Foundation.
4577 + */
4578 +
4579 +#include <linux/platform_device.h>
4580 +#include <linux/list.h>
4581 +#include <linux/clk.h>
4582 +#include <linux/err.h>
4583 +#include <linux/io.h>
4584 +#include <linux/list.h>
4585 +#include <linux/spinlock.h>
4586 +#include <linux/atmel-ssc.h>
4587 +
4588 +/* Serialize access to ssc_list and user count */
4589 +static DEFINE_SPINLOCK(user_lock);
4590 +static LIST_HEAD(ssc_list);
4591 +
4592 +struct ssc_device *ssc_request(unsigned int ssc_num)
4593 +{
4594 + int ssc_valid = 0;
4595 + struct ssc_device *ssc;
4596 +
4597 + spin_lock(&user_lock);
4598 + list_for_each_entry(ssc, &ssc_list, list) {
4599 + if (ssc->pdev->id == ssc_num) {
4600 + ssc_valid = 1;
4601 + break;
4602 + }
4603 + }
4604 +
4605 + if (!ssc_valid) {
4606 + spin_unlock(&user_lock);
4607 + dev_dbg(&ssc->pdev->dev, "could not find requested device\n");
4608 + return ERR_PTR(-ENODEV);
4609 + }
4610 +
4611 + if (ssc->user) {
4612 + spin_unlock(&user_lock);
4613 + dev_dbg(&ssc->pdev->dev, "module busy\n");
4614 + return ERR_PTR(-EBUSY);
4615 + }
4616 + ssc->user++;
4617 + spin_unlock(&user_lock);
4618 +
4619 + clk_enable(ssc->clk);
4620 +
4621 + return ssc;
4622 +}
4623 +EXPORT_SYMBOL(ssc_request);
4624 +
4625 +void ssc_free(struct ssc_device *ssc)
4626 +{
4627 + spin_lock(&user_lock);
4628 + if (ssc->user) {
4629 + ssc->user--;
4630 + clk_disable(ssc->clk);
4631 + } else {
4632 + dev_dbg(&ssc->pdev->dev, "device already free\n");
4633 + }
4634 + spin_unlock(&user_lock);
4635 +}
4636 +EXPORT_SYMBOL(ssc_free);
4637 +
4638 +static int __init ssc_probe(struct platform_device *pdev)
4639 +{
4640 + int retval = 0;
4641 + struct resource *regs;
4642 + struct ssc_device *ssc;
4643 +
4644 + ssc = kzalloc(sizeof(struct ssc_device), GFP_KERNEL);
4645 + if (!ssc) {
4646 + dev_dbg(&pdev->dev, "out of memory\n");
4647 + retval = -ENOMEM;
4648 + goto out;
4649 + }
4650 +
4651 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4652 + if (!regs) {
4653 + dev_dbg(&pdev->dev, "no mmio resource defined\n");
4654 + retval = -ENXIO;
4655 + goto out_free;
4656 + }
4657 +
4658 + ssc->clk = clk_get(&pdev->dev, "pclk");
4659 + if (IS_ERR(ssc->clk)) {
4660 + dev_dbg(&pdev->dev, "no pclk clock defined\n");
4661 + retval = -ENXIO;
4662 + goto out_free;
4663 + }
4664 +
4665 + ssc->pdev = pdev;
4666 + ssc->regs = ioremap(regs->start, regs->end - regs->start + 1);
4667 + if (!ssc->regs) {
4668 + dev_dbg(&pdev->dev, "ioremap failed\n");
4669 + retval = -EINVAL;
4670 + goto out_clk;
4671 + }
4672 +
4673 + /* disable all interrupts */
4674 + clk_enable(ssc->clk);
4675 + ssc_writel(ssc->regs, IDR, ~0UL);
4676 + ssc_readl(ssc->regs, SR);
4677 + clk_disable(ssc->clk);
4678 +
4679 + ssc->irq = platform_get_irq(pdev, 0);
4680 + if (!ssc->irq) {
4681 + dev_dbg(&pdev->dev, "could not get irq\n");
4682 + retval = -ENXIO;
4683 + goto out_unmap;
4684 + }
4685 +
4686 + spin_lock(&user_lock);
4687 + list_add_tail(&ssc->list, &ssc_list);
4688 + spin_unlock(&user_lock);
4689 +
4690 + platform_set_drvdata(pdev, ssc);
4691 +
4692 + dev_info(&pdev->dev, "Atmel SSC device at 0x%p (irq %d)\n",
4693 + ssc->regs, ssc->irq);
4694 +
4695 + goto out;
4696 +
4697 +out_unmap:
4698 + iounmap(ssc->regs);
4699 +out_clk:
4700 + clk_put(ssc->clk);
4701 +out_free:
4702 + kfree(ssc);
4703 +out:
4704 + return retval;
4705 +}
4706 +
4707 +static int __devexit ssc_remove(struct platform_device *pdev)
4708 +{
4709 + struct ssc_device *ssc = platform_get_drvdata(pdev);
4710 +
4711 + spin_lock(&user_lock);
4712 + iounmap(ssc->regs);
4713 + clk_put(ssc->clk);
4714 + list_del(&ssc->list);
4715 + kfree(ssc);
4716 + spin_unlock(&user_lock);
4717 +
4718 + return 0;
4719 +}
4720 +
4721 +static struct platform_driver ssc_driver = {
4722 + .remove = __devexit_p(ssc_remove),
4723 + .driver = {
4724 + .name = "ssc",
4725 + },
4726 +};
4727 +
4728 +static int __init ssc_init(void)
4729 +{
4730 + return platform_driver_probe(&ssc_driver, ssc_probe);
4731 +}
4732 +module_init(ssc_init);
4733 +
4734 +static void __exit ssc_exit(void)
4735 +{
4736 + platform_driver_unregister(&ssc_driver);
4737 +}
4738 +module_exit(ssc_exit);
4739 +
4740 +MODULE_AUTHOR("Hans-Christian Egtvedt <hcegtvedt@atmel.com>");
4741 +MODULE_DESCRIPTION("SSC driver for Atmel AVR32 and AT91");
4742 +MODULE_LICENSE("GPL");
4743 diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
4744 index e23082f..1de1716 100644
4745 --- a/drivers/mmc/host/Kconfig
4746 +++ b/drivers/mmc/host/Kconfig
4747 @@ -74,6 +74,16 @@ config MMC_AT91
4748
4749 If unsure, say N.
4750
4751 +config MMC_ATMELMCI
4752 + tristate "Atmel Multimedia Card Interface support"
4753 + depends on AVR32 && MMC
4754 + help
4755 + This selects the Atmel Multimedia Card Interface. If you have
4756 + a AT91 (ARM) or AT32 (AVR32) platform with a Multimedia Card
4757 + slot, say Y or M here.
4758 +
4759 + If unsure, say N.
4760 +
4761 config MMC_IMX
4762 tristate "Motorola i.MX Multimedia Card Interface support"
4763 depends on ARCH_IMX
4764 diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
4765 index 6685f64..4b8e6e2 100644
4766 --- a/drivers/mmc/host/Makefile
4767 +++ b/drivers/mmc/host/Makefile
4768 @@ -14,5 +14,6 @@ obj-$(CONFIG_MMC_WBSD) += wbsd.o
4769 obj-$(CONFIG_MMC_AU1X) += au1xmmc.o
4770 obj-$(CONFIG_MMC_OMAP) += omap.o
4771 obj-$(CONFIG_MMC_AT91) += at91_mci.o
4772 +obj-$(CONFIG_MMC_ATMELMCI) += atmel-mci.o
4773 obj-$(CONFIG_MMC_TIFM_SD) += tifm_sd.o
4774
4775 diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
4776 new file mode 100644
4777 index 0000000..45323c9
4778 --- /dev/null
4779 +++ b/drivers/mmc/host/atmel-mci.c
4780 @@ -0,0 +1,1161 @@
4781 +/*
4782 + * Atmel MultiMedia Card Interface driver
4783 + *
4784 + * Copyright (C) 2004-2006 Atmel Corporation
4785 + *
4786 + * This program is free software; you can redistribute it and/or modify
4787 + * it under the terms of the GNU General Public License version 2 as
4788 + * published by the Free Software Foundation.
4789 + */
4790 +#include <linux/blkdev.h>
4791 +#include <linux/clk.h>
4792 +#include <linux/device.h>
4793 +#include <linux/dma-mapping.h>
4794 +#include <linux/init.h>
4795 +#include <linux/interrupt.h>
4796 +#include <linux/ioport.h>
4797 +#include <linux/module.h>
4798 +#include <linux/platform_device.h>
4799 +
4800 +#include <linux/mmc/host.h>
4801 +
4802 +#include <asm/dma-controller.h>
4803 +#include <asm/io.h>
4804 +#include <asm/arch/board.h>
4805 +#include <asm/arch/gpio.h>
4806 +
4807 +#include "atmel-mci.h"
4808 +
4809 +#define DRIVER_NAME "atmel_mci"
4810 +
4811 +#define MCI_DATA_ERROR_FLAGS (MCI_BIT(DCRCE) | MCI_BIT(DTOE) | \
4812 + MCI_BIT(OVRE) | MCI_BIT(UNRE))
4813 +
4814 +enum {
4815 + EVENT_CMD_COMPLETE = 0,
4816 + EVENT_DATA_COMPLETE,
4817 + EVENT_DATA_ERROR,
4818 + EVENT_STOP_SENT,
4819 + EVENT_STOP_COMPLETE,
4820 + EVENT_DMA_ERROR,
4821 + EVENT_CARD_DETECT,
4822 +};
4823 +
4824 +struct atmel_mci_dma {
4825 + struct dma_request_sg req;
4826 + unsigned short rx_periph_id;
4827 + unsigned short tx_periph_id;
4828 +};
4829 +
4830 +struct atmel_mci {
4831 + struct mmc_host *mmc;
4832 + void __iomem *regs;
4833 + struct atmel_mci_dma dma;
4834 +
4835 + struct mmc_request *mrq;
4836 + struct mmc_command *cmd;
4837 + struct mmc_data *data;
4838 +
4839 + u32 cmd_status;
4840 + u32 data_status;
4841 + u32 stop_status;
4842 + u32 stop_cmdr;
4843 +
4844 + struct tasklet_struct tasklet;
4845 + unsigned long pending_events;
4846 + unsigned long completed_events;
4847 +
4848 + int present;
4849 + int detect_pin;
4850 + int wp_pin;
4851 +
4852 + unsigned long bus_hz;
4853 + unsigned long mapbase;
4854 + struct clk *mck;
4855 + struct platform_device *pdev;
4856 +
4857 +#ifdef CONFIG_DEBUG_FS
4858 + struct dentry *debugfs_root;
4859 + struct dentry *debugfs_regs;
4860 + struct dentry *debugfs_req;
4861 + struct dentry *debugfs_pending_events;
4862 + struct dentry *debugfs_completed_events;
4863 +#endif
4864 +};
4865 +
4866 +/* Those printks take an awful lot of time... */
4867 +#ifndef DEBUG
4868 +static unsigned int fmax = 15000000U;
4869 +#else
4870 +static unsigned int fmax = 1000000U;
4871 +#endif
4872 +module_param(fmax, uint, 0444);
4873 +MODULE_PARM_DESC(fmax, "Max frequency in Hz of the MMC bus clock");
4874 +
4875 +/* Test bit macros for completed events */
4876 +#define mci_cmd_is_complete(host) \
4877 + test_bit(EVENT_CMD_COMPLETE, &host->completed_events)
4878 +#define mci_data_is_complete(host) \
4879 + test_bit(EVENT_DATA_COMPLETE, &host->completed_events)
4880 +#define mci_data_error_is_complete(host) \
4881 + test_bit(EVENT_DATA_ERROR, &host->completed_events)
4882 +#define mci_stop_sent_is_complete(host) \
4883 + test_bit(EVENT_STOP_SENT, &host->completed_events)
4884 +#define mci_stop_is_complete(host) \
4885 + test_bit(EVENT_STOP_COMPLETE, &host->completed_events)
4886 +#define mci_dma_error_is_complete(host) \
4887 + test_bit(EVENT_DMA_ERROR, &host->completed_events)
4888 +#define mci_card_detect_is_complete(host) \
4889 + test_bit(EVENT_CARD_DETECT, &host->completed_events)
4890 +
4891 +/* Test and clear bit macros for pending events */
4892 +#define mci_clear_cmd_is_pending(host) \
4893 + test_and_clear_bit(EVENT_CMD_COMPLETE, &host->pending_events)
4894 +#define mci_clear_data_is_pending(host) \
4895 + test_and_clear_bit(EVENT_DATA_COMPLETE, &host->pending_events)
4896 +#define mci_clear_data_error_is_pending(host) \
4897 + test_and_clear_bit(EVENT_DATA_ERROR, &host->pending_events)
4898 +#define mci_clear_stop_sent_is_pending(host) \
4899 + test_and_clear_bit(EVENT_STOP_SENT, &host->pending_events)
4900 +#define mci_clear_stop_is_pending(host) \
4901 + test_and_clear_bit(EVENT_STOP_COMPLETE, &host->pending_events)
4902 +#define mci_clear_dma_error_is_pending(host) \
4903 + test_and_clear_bit(EVENT_DMA_ERROR, &host->pending_events)
4904 +#define mci_clear_card_detect_is_pending(host) \
4905 + test_and_clear_bit(EVENT_CARD_DETECT, &host->pending_events)
4906 +
4907 +/* Test and set bit macros for completed events */
4908 +#define mci_set_cmd_is_completed(host) \
4909 + test_and_set_bit(EVENT_CMD_COMPLETE, &host->completed_events)
4910 +#define mci_set_data_is_completed(host) \
4911 + test_and_set_bit(EVENT_DATA_COMPLETE, &host->completed_events)
4912 +#define mci_set_data_error_is_completed(host) \
4913 + test_and_set_bit(EVENT_DATA_ERROR, &host->completed_events)
4914 +#define mci_set_stop_sent_is_completed(host) \
4915 + test_and_set_bit(EVENT_STOP_SENT, &host->completed_events)
4916 +#define mci_set_stop_is_completed(host) \
4917 + test_and_set_bit(EVENT_STOP_COMPLETE, &host->completed_events)
4918 +#define mci_set_dma_error_is_completed(host) \
4919 + test_and_set_bit(EVENT_DMA_ERROR, &host->completed_events)
4920 +#define mci_set_card_detect_is_completed(host) \
4921 + test_and_set_bit(EVENT_CARD_DETECT, &host->completed_events)
4922 +
4923 +/* Set bit macros for completed events */
4924 +#define mci_set_cmd_complete(host) \
4925 + set_bit(EVENT_CMD_COMPLETE, &host->completed_events)
4926 +#define mci_set_data_complete(host) \
4927 + set_bit(EVENT_DATA_COMPLETE, &host->completed_events)
4928 +#define mci_set_data_error_complete(host) \
4929 + set_bit(EVENT_DATA_ERROR, &host->completed_events)
4930 +#define mci_set_stop_sent_complete(host) \
4931 + set_bit(EVENT_STOP_SENT, &host->completed_events)
4932 +#define mci_set_stop_complete(host) \
4933 + set_bit(EVENT_STOP_COMPLETE, &host->completed_events)
4934 +#define mci_set_dma_error_complete(host) \
4935 + set_bit(EVENT_DMA_ERROR, &host->completed_events)
4936 +#define mci_set_card_detect_complete(host) \
4937 + set_bit(EVENT_CARD_DETECT, &host->completed_events)
4938 +
4939 +/* Set bit macros for pending events */
4940 +#define mci_set_cmd_pending(host) \
4941 + set_bit(EVENT_CMD_COMPLETE, &host->pending_events)
4942 +#define mci_set_data_pending(host) \
4943 + set_bit(EVENT_DATA_COMPLETE, &host->pending_events)
4944 +#define mci_set_data_error_pending(host) \
4945 + set_bit(EVENT_DATA_ERROR, &host->pending_events)
4946 +#define mci_set_stop_sent_pending(host) \
4947 + set_bit(EVENT_STOP_SENT, &host->pending_events)
4948 +#define mci_set_stop_pending(host) \
4949 + set_bit(EVENT_STOP_COMPLETE, &host->pending_events)
4950 +#define mci_set_dma_error_pending(host) \
4951 + set_bit(EVENT_DMA_ERROR, &host->pending_events)
4952 +#define mci_set_card_detect_pending(host) \
4953 + set_bit(EVENT_CARD_DETECT, &host->pending_events)
4954 +
4955 +/* Clear bit macros for pending events */
4956 +#define mci_clear_cmd_pending(host) \
4957 + clear_bit(EVENT_CMD_COMPLETE, &host->pending_events)
4958 +#define mci_clear_data_pending(host) \
4959 + clear_bit(EVENT_DATA_COMPLETE, &host->pending_events)
4960 +#define mci_clear_data_error_pending(host) \
4961 + clear_bit(EVENT_DATA_ERROR, &host->pending_events)
4962 +#define mci_clear_stop_sent_pending(host) \
4963 + clear_bit(EVENT_STOP_SENT, &host->pending_events)
4964 +#define mci_clear_stop_pending(host) \
4965 + clear_bit(EVENT_STOP_COMPLETE, &host->pending_events)
4966 +#define mci_clear_dma_error_pending(host) \
4967 + clear_bit(EVENT_DMA_ERROR, &host->pending_events)
4968 +#define mci_clear_card_detect_pending(host) \
4969 + clear_bit(EVENT_CARD_DETECT, &host->pending_events)
4970 +
4971 +
4972 +#ifdef CONFIG_DEBUG_FS
4973 +#include <linux/debugfs.h>
4974 +
4975 +#define DBG_REQ_BUF_SIZE (4096 - sizeof(unsigned int))
4976 +
4977 +struct req_dbg_data {
4978 + unsigned int nbytes;
4979 + char str[DBG_REQ_BUF_SIZE];
4980 +};
4981 +
4982 +static int req_dbg_open(struct inode *inode, struct file *file)
4983 +{
4984 + struct atmel_mci *host;
4985 + struct mmc_request *mrq;
4986 + struct mmc_command *cmd, *stop;
4987 + struct mmc_data *data;
4988 + struct req_dbg_data *priv;
4989 + char *str;
4990 + unsigned long n = 0;
4991 +
4992 + priv = kzalloc(DBG_REQ_BUF_SIZE, GFP_KERNEL);
4993 + if (!priv)
4994 + return -ENOMEM;
4995 + str = priv->str;
4996 +
4997 + mutex_lock(&inode->i_mutex);
4998 + host = inode->i_private;
4999 +
5000 + spin_lock_irq(&host->mmc->lock);
5001 + mrq = host->mrq;
5002 + if (mrq) {
5003 + cmd = mrq->cmd;
5004 + data = mrq->data;
5005 + stop = mrq->stop;
5006 + n = snprintf(str, DBG_REQ_BUF_SIZE,
5007 + "CMD%u(0x%x) %x %x %x %x %x (err %u)\n",
5008 + cmd->opcode, cmd->arg, cmd->flags,
5009 + cmd->resp[0], cmd->resp[1], cmd->resp[2],
5010 + cmd->resp[3], cmd->error);
5011 + if (n < DBG_REQ_BUF_SIZE && data)
5012 + n += snprintf(str + n, DBG_REQ_BUF_SIZE - n,
5013 + "DATA %u * %u (%u) %x (err %u)\n",
5014 + data->blocks, data->blksz,
5015 + data->bytes_xfered, data->flags,
5016 + data->error);
5017 + if (n < DBG_REQ_BUF_SIZE && stop)
5018 + n += snprintf(str + n, DBG_REQ_BUF_SIZE - n,
5019 + "CMD%u(0x%x) %x %x %x %x %x (err %u)\n",
5020 + stop->opcode, stop->arg, stop->flags,
5021 + stop->resp[0], stop->resp[1],
5022 + stop->resp[2], stop->resp[3],
5023 + stop->error);
5024 + }
5025 + spin_unlock_irq(&host->mmc->lock);
5026 + mutex_unlock(&inode->i_mutex);
5027 +
5028 + priv->nbytes = min(n, DBG_REQ_BUF_SIZE);
5029 + file->private_data = priv;
5030 +
5031 + return 0;
5032 +}
5033 +
5034 +static ssize_t req_dbg_read(struct file *file, char __user *buf,
5035 + size_t nbytes, loff_t *ppos)
5036 +{
5037 + struct req_dbg_data *priv = file->private_data;
5038 +
5039 + return simple_read_from_buffer(buf, nbytes, ppos,
5040 + priv->str, priv->nbytes);
5041 +}
5042 +
5043 +static int req_dbg_release(struct inode *inode, struct file *file)
5044 +{
5045 + kfree(file->private_data);
5046 + return 0;
5047 +}
5048 +
5049 +static const struct file_operations req_dbg_fops = {
5050 + .owner = THIS_MODULE,
5051 + .open = req_dbg_open,
5052 + .llseek = no_llseek,
5053 + .read = req_dbg_read,
5054 + .release = req_dbg_release,
5055 +};
5056 +
5057 +static int regs_dbg_open(struct inode *inode, struct file *file)
5058 +{
5059 + struct atmel_mci *host;
5060 + unsigned int i;
5061 + u32 *data;
5062 + int ret = -ENOMEM;
5063 +
5064 + mutex_lock(&inode->i_mutex);
5065 + host = inode->i_private;
5066 + data = kmalloc(inode->i_size, GFP_KERNEL);
5067 + if (!data)
5068 + goto out;
5069 +
5070 + spin_lock_irq(&host->mmc->lock);
5071 + for (i = 0; i < inode->i_size / 4; i++)
5072 + data[i] = __raw_readl(host->regs + i * 4);
5073 + spin_unlock_irq(&host->mmc->lock);
5074 +
5075 + file->private_data = data;
5076 + ret = 0;
5077 +
5078 +out:
5079 + mutex_unlock(&inode->i_mutex);
5080 +
5081 + return ret;
5082 +}
5083 +
5084 +static ssize_t regs_dbg_read(struct file *file, char __user *buf,
5085 + size_t nbytes, loff_t *ppos)
5086 +{
5087 + struct inode *inode = file->f_dentry->d_inode;
5088 + int ret;
5089 +
5090 + mutex_lock(&inode->i_mutex);
5091 + ret = simple_read_from_buffer(buf, nbytes, ppos,
5092 + file->private_data,
5093 + file->f_dentry->d_inode->i_size);
5094 + mutex_unlock(&inode->i_mutex);
5095 +
5096 + return ret;
5097 +}
5098 +
5099 +static int regs_dbg_release(struct inode *inode, struct file *file)
5100 +{
5101 + kfree(file->private_data);
5102 + return 0;
5103 +}
5104 +
5105 +static const struct file_operations regs_dbg_fops = {
5106 + .owner = THIS_MODULE,
5107 + .open = regs_dbg_open,
5108 + .llseek = generic_file_llseek,
5109 + .read = regs_dbg_read,
5110 + .release = regs_dbg_release,
5111 +};
5112 +
5113 +static void atmci_init_debugfs(struct atmel_mci *host)
5114 +{
5115 + struct mmc_host *mmc;
5116 + struct dentry *root, *regs;
5117 + struct resource *res;
5118 +
5119 + mmc = host->mmc;
5120 + root = debugfs_create_dir(mmc_hostname(mmc), NULL);
5121 + if (IS_ERR(root) || !root)
5122 + goto err_root;
5123 + host->debugfs_root = root;
5124 +
5125 + regs = debugfs_create_file("regs", 0400, root, host, &regs_dbg_fops);
5126 + if (!regs)
5127 + goto err_regs;
5128 +
5129 + res = platform_get_resource(host->pdev, IORESOURCE_MEM, 0);
5130 + regs->d_inode->i_size = res->end - res->start + 1;
5131 + host->debugfs_regs = regs;
5132 +
5133 + host->debugfs_req = debugfs_create_file("req", 0400, root,
5134 + host, &req_dbg_fops);
5135 + if (!host->debugfs_req)
5136 + goto err_req;
5137 +
5138 + host->debugfs_pending_events
5139 + = debugfs_create_u32("pending_events", 0400, root,
5140 + (u32 *)&host->pending_events);
5141 + if (!host->debugfs_pending_events)
5142 + goto err_pending_events;
5143 +
5144 + host->debugfs_completed_events
5145 + = debugfs_create_u32("completed_events", 0400, root,
5146 + (u32 *)&host->completed_events);
5147 + if (!host->debugfs_completed_events)
5148 + goto err_completed_events;
5149 +
5150 + return;
5151 +
5152 +err_completed_events:
5153 + debugfs_remove(host->debugfs_pending_events);
5154 +err_pending_events:
5155 + debugfs_remove(host->debugfs_req);
5156 +err_req:
5157 + debugfs_remove(host->debugfs_regs);
5158 +err_regs:
5159 + debugfs_remove(host->debugfs_root);
5160 +err_root:
5161 + host->debugfs_root = NULL;
5162 + dev_err(&host->pdev->dev,
5163 + "failed to initialize debugfs for %s\n",
5164 + mmc_hostname(mmc));
5165 +}
5166 +
5167 +static void atmci_cleanup_debugfs(struct atmel_mci *host)
5168 +{
5169 + if (host->debugfs_root) {
5170 + debugfs_remove(host->debugfs_completed_events);
5171 + debugfs_remove(host->debugfs_pending_events);
5172 + debugfs_remove(host->debugfs_req);
5173 + debugfs_remove(host->debugfs_regs);
5174 + debugfs_remove(host->debugfs_root);
5175 + host->debugfs_root = NULL;
5176 + }
5177 +}
5178 +#else
5179 +static inline void atmci_init_debugfs(struct atmel_mci *host)
5180 +{
5181 +
5182 +}
5183 +
5184 +static inline void atmci_cleanup_debugfs(struct atmel_mci *host)
5185 +{
5186 +
5187 +}
5188 +#endif /* CONFIG_DEBUG_FS */
5189 +
5190 +static inline unsigned int ns_to_clocks(struct atmel_mci *host,
5191 + unsigned int ns)
5192 +{
5193 + return (ns * (host->bus_hz / 1000000) + 999) / 1000;
5194 +}
5195 +
5196 +static void atmci_set_timeout(struct atmel_mci *host,
5197 + struct mmc_data *data)
5198 +{
5199 + static unsigned dtomul_to_shift[] = {
5200 + 0, 4, 7, 8, 10, 12, 16, 20
5201 + };
5202 + unsigned timeout;
5203 + unsigned dtocyc, dtomul;
5204 +
5205 + timeout = ns_to_clocks(host, data->timeout_ns) + data->timeout_clks;
5206 +
5207 + for (dtomul = 0; dtomul < 8; dtomul++) {
5208 + unsigned shift = dtomul_to_shift[dtomul];
5209 + dtocyc = (timeout + (1 << shift) - 1) >> shift;
5210 + if (dtocyc < 15)
5211 + break;
5212 + }
5213 +
5214 + if (dtomul >= 8) {
5215 + dtomul = 7;
5216 + dtocyc = 15;
5217 + }
5218 +
5219 + dev_dbg(&host->mmc->class_dev, "setting timeout to %u cycles\n",
5220 + dtocyc << dtomul_to_shift[dtomul]);
5221 + mci_writel(host, DTOR, (MCI_BF(DTOMUL, dtomul)
5222 + | MCI_BF(DTOCYC, dtocyc)));
5223 +}
5224 +
5225 +/*
5226 + * Return mask with command flags to be enabled for this command.
5227 + */
5228 +static u32 atmci_prepare_command(struct mmc_host *mmc,
5229 + struct mmc_command *cmd)
5230 +{
5231 + u32 cmdr;
5232 +
5233 + cmd->error = MMC_ERR_NONE;
5234 +
5235 + cmdr = MCI_BF(CMDNB, cmd->opcode);
5236 +
5237 + if (cmd->flags & MMC_RSP_PRESENT) {
5238 + if (cmd->flags & MMC_RSP_136)
5239 + cmdr |= MCI_BF(RSPTYP, MCI_RSPTYP_136_BIT);
5240 + else
5241 + cmdr |= MCI_BF(RSPTYP, MCI_RSPTYP_48_BIT);
5242 + }
5243 +
5244 + /*
5245 + * This should really be MAXLAT_5 for CMD2 and ACMD41, but
5246 + * it's too difficult to determine whether this is an ACMD or
5247 + * not. Better make it 64.
5248 + */
5249 + cmdr |= MCI_BIT(MAXLAT);
5250 +
5251 + if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
5252 + cmdr |= MCI_BIT(OPDCMD);
5253 +
5254 + dev_dbg(&mmc->class_dev,
5255 + "cmd: op %02x arg %08x flags %08x, cmdflags %08lx\n",
5256 + cmd->opcode, cmd->arg, cmd->flags, (unsigned long)cmdr);
5257 +
5258 + return cmdr;
5259 +}
5260 +
5261 +static void atmci_start_command(struct atmel_mci *host,
5262 + struct mmc_command *cmd,
5263 + u32 cmd_flags)
5264 +{
5265 + WARN_ON(host->cmd);
5266 + host->cmd = cmd;
5267 +
5268 + mci_writel(host, ARGR, cmd->arg);
5269 + mci_writel(host, CMDR, cmd_flags);
5270 +
5271 + if (cmd->data)
5272 + dma_start_request(host->dma.req.req.dmac,
5273 + host->dma.req.req.channel);
5274 +}
5275 +
5276 +/*
5277 + * Returns a mask of flags to be set in the command register when the
5278 + * command to start the transfer is to be sent.
5279 + */
5280 +static u32 atmci_prepare_data(struct mmc_host *mmc, struct mmc_data *data)
5281 +{
5282 + struct atmel_mci *host = mmc_priv(mmc);
5283 + u32 cmd_flags;
5284 +
5285 + WARN_ON(host->data);
5286 + host->data = data;
5287 +
5288 + atmci_set_timeout(host, data);
5289 + mci_writel(host, BLKR, (MCI_BF(BCNT, data->blocks)
5290 + | MCI_BF(BLKLEN, data->blksz)));
5291 + host->dma.req.block_size = data->blksz;
5292 + host->dma.req.nr_blocks = data->blocks;
5293 +
5294 + cmd_flags = MCI_BF(TRCMD, MCI_TRCMD_START_TRANS);
5295 + if (data->flags & MMC_DATA_STREAM)
5296 + cmd_flags |= MCI_BF(TRTYP, MCI_TRTYP_STREAM);
5297 + else if (data->blocks > 1)
5298 + cmd_flags |= MCI_BF(TRTYP, MCI_TRTYP_MULTI_BLOCK);
5299 + else
5300 + cmd_flags |= MCI_BF(TRTYP, MCI_TRTYP_BLOCK);
5301 +
5302 + if (data->flags & MMC_DATA_READ) {
5303 + cmd_flags |= MCI_BIT(TRDIR);
5304 + host->dma.req.nr_sg
5305 + = dma_map_sg(&host->pdev->dev, data->sg,
5306 + data->sg_len, DMA_FROM_DEVICE);
5307 + host->dma.req.periph_id = host->dma.rx_periph_id;
5308 + host->dma.req.direction = DMA_DIR_PERIPH_TO_MEM;
5309 + host->dma.req.data_reg = host->mapbase + MCI_RDR;
5310 + } else {
5311 + host->dma.req.nr_sg
5312 + = dma_map_sg(&host->pdev->dev, data->sg,
5313 + data->sg_len, DMA_TO_DEVICE);
5314 + host->dma.req.periph_id = host->dma.tx_periph_id;
5315 + host->dma.req.direction = DMA_DIR_MEM_TO_PERIPH;
5316 + host->dma.req.data_reg = host->mapbase + MCI_TDR;
5317 + }
5318 + host->dma.req.sg = data->sg;
5319 +
5320 + dma_prepare_request_sg(host->dma.req.req.dmac, &host->dma.req);
5321 +
5322 + return cmd_flags;
5323 +}
5324 +
5325 +static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
5326 +{
5327 + struct atmel_mci *host = mmc_priv(mmc);
5328 + struct mmc_data *data = mrq->data;
5329 + u32 iflags;
5330 + u32 cmdflags = 0;
5331 +
5332 + iflags = mci_readl(host, IMR);
5333 + if (iflags)
5334 + dev_warn(&mmc->class_dev, "WARNING: IMR=0x%08x\n",
5335 + mci_readl(host, IMR));
5336 +
5337 + WARN_ON(host->mrq != NULL);
5338 + host->mrq = mrq;
5339 + host->pending_events = 0;
5340 + host->completed_events = 0;
5341 +
5342 + iflags = MCI_BIT(CMDRDY);
5343 + cmdflags = atmci_prepare_command(mmc, mrq->cmd);
5344 +
5345 + if (mrq->stop) {
5346 + WARN_ON(!data);
5347 +
5348 + host->stop_cmdr = atmci_prepare_command(mmc, mrq->stop);
5349 + host->stop_cmdr |= MCI_BF(TRCMD, MCI_TRCMD_STOP_TRANS);
5350 + if (!(data->flags & MMC_DATA_WRITE))
5351 + host->stop_cmdr |= MCI_BIT(TRDIR);
5352 + if (data->flags & MMC_DATA_STREAM)
5353 + host->stop_cmdr |= MCI_BF(TRTYP, MCI_TRTYP_STREAM);
5354 + else
5355 + host->stop_cmdr |= MCI_BF(TRTYP, MCI_TRTYP_MULTI_BLOCK);
5356 + }
5357 + if (data) {
5358 + cmdflags |= atmci_prepare_data(mmc, data);
5359 + iflags |= MCI_DATA_ERROR_FLAGS;
5360 + }
5361 +
5362 + atmci_start_command(host, mrq->cmd, cmdflags);
5363 + mci_writel(host, IER, iflags);
5364 +}
5365 +
5366 +static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
5367 +{
5368 + struct atmel_mci *host = mmc_priv(mmc);
5369 + u32 mr;
5370 +
5371 + if (ios->clock) {
5372 + u32 clkdiv;
5373 +
5374 + /* Set clock rate */
5375 + clkdiv = host->bus_hz / (2 * ios->clock) - 1;
5376 + if (clkdiv > 255) {
5377 + dev_warn(&mmc->class_dev,
5378 + "clock %u too slow; using %lu\n",
5379 + ios->clock, host->bus_hz / (2 * 256));
5380 + clkdiv = 255;
5381 + }
5382 +
5383 + mr = mci_readl(host, MR);
5384 + mr = MCI_BFINS(CLKDIV, clkdiv, mr)
5385 + | MCI_BIT(WRPROOF) | MCI_BIT(RDPROOF);
5386 + mci_writel(host, MR, mr);
5387 +
5388 + /* Enable the MCI controller */
5389 + mci_writel(host, CR, MCI_BIT(MCIEN));
5390 + } else {
5391 + /* Disable the MCI controller */
5392 + mci_writel(host, CR, MCI_BIT(MCIDIS));
5393 + }
5394 +
5395 + switch (ios->bus_width) {
5396 + case MMC_BUS_WIDTH_1:
5397 + mci_writel(host, SDCR, 0);
5398 + break;
5399 + case MMC_BUS_WIDTH_4:
5400 + mci_writel(host, SDCR, MCI_BIT(SDCBUS));
5401 + break;
5402 + }
5403 +
5404 + switch (ios->power_mode) {
5405 + case MMC_POWER_ON:
5406 + /* Send init sequence (74 clock cycles) */
5407 + mci_writel(host, IDR, ~0UL);
5408 + mci_writel(host, CMDR, MCI_BF(SPCMD, MCI_SPCMD_INIT_CMD));
5409 + while (!(mci_readl(host, SR) & MCI_BIT(CMDRDY)))
5410 + cpu_relax();
5411 + break;
5412 + default:
5413 + /*
5414 + * TODO: None of the currently available AVR32-based
5415 + * boards allow MMC power to be turned off. Implement
5416 + * power control when this can be tested properly.
5417 + */
5418 + break;
5419 + }
5420 +}
5421 +
5422 +static int atmci_get_ro(struct mmc_host *mmc)
5423 +{
5424 + int read_only = 0;
5425 + struct atmel_mci *host = mmc_priv(mmc);
5426 +
5427 + if (host->wp_pin >= 0) {
5428 + read_only = gpio_get_value(host->wp_pin);
5429 + dev_dbg(&mmc->class_dev, "card is %s\n",
5430 + read_only ? "read-only" : "read-write");
5431 + } else {
5432 + dev_dbg(&mmc->class_dev,
5433 + "no pin for checking read-only switch."
5434 + " Assuming write-enable.\n");
5435 + }
5436 +
5437 + return read_only;
5438 +}
5439 +
5440 +static struct mmc_host_ops atmci_ops = {
5441 + .request = atmci_request,
5442 + .set_ios = atmci_set_ios,
5443 + .get_ro = atmci_get_ro,
5444 +};
5445 +
5446 +static void atmci_request_end(struct mmc_host *mmc, struct mmc_request *mrq)
5447 +{
5448 + struct atmel_mci *host = mmc_priv(mmc);
5449 +
5450 + WARN_ON(host->cmd || host->data);
5451 + host->mrq = NULL;
5452 +
5453 + mmc_request_done(mmc, mrq);
5454 +}
5455 +
5456 +static void send_stop_cmd(struct mmc_host *mmc, struct mmc_data *data,
5457 + u32 flags)
5458 +{
5459 + struct atmel_mci *host = mmc_priv(mmc);
5460 +
5461 + atmci_start_command(host, data->stop, host->stop_cmdr | flags);
5462 + mci_writel(host, IER, MCI_BIT(CMDRDY));
5463 +}
5464 +
5465 +static void atmci_data_complete(struct atmel_mci *host, struct mmc_data *data)
5466 +{
5467 + host->data = NULL;
5468 + dma_unmap_sg(&host->pdev->dev, data->sg, host->dma.req.nr_sg,
5469 + ((data->flags & MMC_DATA_WRITE)
5470 + ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
5471 +
5472 + /*
5473 + * Data might complete before command for very short transfers
5474 + * (like READ_SCR)
5475 + */
5476 + if (mci_cmd_is_complete(host)
5477 + && (!data->stop || mci_stop_is_complete(host)))
5478 + atmci_request_end(host->mmc, data->mrq);
5479 +}
5480 +
5481 +static void atmci_command_complete(struct atmel_mci *host,
5482 + struct mmc_command *cmd, u32 status)
5483 +{
5484 + if (status & MCI_BIT(RTOE))
5485 + cmd->error = MMC_ERR_TIMEOUT;
5486 + else if ((cmd->flags & MMC_RSP_CRC)
5487 + && (status & MCI_BIT(RCRCE)))
5488 + cmd->error = MMC_ERR_BADCRC;
5489 + else if (status & (MCI_BIT(RINDE) | MCI_BIT(RDIRE) | MCI_BIT(RENDE)))
5490 + cmd->error = MMC_ERR_FAILED;
5491 +
5492 + if (cmd->error != MMC_ERR_NONE) {
5493 + dev_dbg(&host->mmc->class_dev,
5494 + "command error: op=0x%x status=0x%08x\n",
5495 + cmd->opcode, status);
5496 +
5497 + if (cmd->data) {
5498 + dma_stop_request(host->dma.req.req.dmac,
5499 + host->dma.req.req.channel);
5500 + mci_writel(host, IDR, MCI_BIT(NOTBUSY)
5501 + | MCI_DATA_ERROR_FLAGS);
5502 + host->data = NULL;
5503 + }
5504 + }
5505 +}
5506 +
5507 +static void atmci_tasklet_func(unsigned long priv)
5508 +{
5509 + struct mmc_host *mmc = (struct mmc_host *)priv;
5510 + struct atmel_mci *host = mmc_priv(mmc);
5511 + struct mmc_request *mrq = host->mrq;
5512 + struct mmc_data *data = host->data;
5513 +
5514 + dev_vdbg(&mmc->class_dev,
5515 + "tasklet: pending/completed/mask %lx/%lx/%x\n",
5516 + host->pending_events, host->completed_events,
5517 + mci_readl(host, IMR));
5518 +
5519 + if (mci_clear_cmd_is_pending(host)) {
5520 + mci_set_cmd_complete(host);
5521 + atmci_command_complete(host, mrq->cmd, host->cmd_status);
5522 + if (!host->data || mci_data_is_complete(host)
5523 + || mci_data_error_is_complete(host))
5524 + atmci_request_end(mmc, mrq);
5525 + }
5526 + if (mci_clear_stop_is_pending(host)) {
5527 + mci_set_stop_complete(host);
5528 + atmci_command_complete(host, mrq->stop, host->stop_status);
5529 + if (mci_data_is_complete(host)
5530 + || mci_data_error_is_complete(host))
5531 + atmci_request_end(mmc, mrq);
5532 + }
5533 + if (mci_clear_dma_error_is_pending(host)) {
5534 + mci_set_dma_error_complete(host);
5535 + mci_clear_data_pending(host);
5536 +
5537 + /* DMA controller got bus error => invalid address */
5538 + data->error = MMC_ERR_INVALID;
5539 +
5540 + dev_dbg(&mmc->class_dev, "dma error after %u bytes xfered\n",
5541 + host->data->bytes_xfered);
5542 +
5543 + if (data->stop
5544 + && !mci_set_stop_sent_is_completed(host))
5545 + /* TODO: Check if card is still present */
5546 + send_stop_cmd(host->mmc, data, 0);
5547 +
5548 + atmci_data_complete(host, data);
5549 + }
5550 + if (mci_clear_data_error_is_pending(host)) {
5551 + u32 status = host->data_status;
5552 +
5553 + mci_set_data_error_complete(host);
5554 + mci_clear_data_pending(host);
5555 +
5556 + dma_stop_request(host->dma.req.req.dmac,
5557 + host->dma.req.req.channel);
5558 +
5559 + if (status & MCI_BIT(DCRCE)) {
5560 + dev_dbg(&mmc->class_dev, "data CRC error\n");
5561 + data->error = MMC_ERR_BADCRC;
5562 + } else if (status & MCI_BIT(DTOE)) {
5563 + dev_dbg(&mmc->class_dev, "data timeout error\n");
5564 + data->error = MMC_ERR_TIMEOUT;
5565 + } else {
5566 + dev_dbg(&mmc->class_dev, "data FIFO error\n");
5567 + data->error = MMC_ERR_FIFO;
5568 + }
5569 + dev_dbg(&mmc->class_dev, "bytes xfered: %u\n",
5570 + data->bytes_xfered);
5571 +
5572 + if (data->stop
5573 + && !mci_set_stop_sent_is_completed(host))
5574 + /* TODO: Check if card is still present */
5575 + send_stop_cmd(host->mmc, data, 0);
5576 +
5577 + atmci_data_complete(host, data);
5578 + }
5579 + if (mci_clear_data_is_pending(host)) {
5580 + mci_set_data_complete(host);
5581 + data->bytes_xfered = data->blocks * data->blksz;
5582 + atmci_data_complete(host, data);
5583 + }
5584 + if (mci_clear_card_detect_is_pending(host)) {
5585 + /* Reset controller if card is gone */
5586 + if (!host->present) {
5587 + mci_writel(host, CR, MCI_BIT(SWRST));
5588 + mci_writel(host, IDR, ~0UL);
5589 + mci_writel(host, CR, MCI_BIT(MCIEN));
5590 + }
5591 +
5592 + /* Clean up queue if present */
5593 + if (mrq) {
5594 + if (!mci_cmd_is_complete(host))
5595 + mrq->cmd->error = MMC_ERR_TIMEOUT;
5596 + if (mrq->data && !mci_data_is_complete(host)
5597 + && !mci_data_error_is_complete(host)) {
5598 + dma_stop_request(host->dma.req.req.dmac,
5599 + host->dma.req.req.channel);
5600 + host->data->error = MMC_ERR_TIMEOUT;
5601 + atmci_data_complete(host, data);
5602 + }
5603 + if (mrq->stop && !mci_stop_is_complete(host))
5604 + mrq->stop->error = MMC_ERR_TIMEOUT;
5605 +
5606 + host->cmd = NULL;
5607 + atmci_request_end(mmc, mrq);
5608 + }
5609 + mmc_detect_change(host->mmc, msecs_to_jiffies(100));
5610 + }
5611 +}
5612 +
5613 +static void atmci_cmd_interrupt(struct mmc_host *mmc, u32 status)
5614 +{
5615 + struct atmel_mci *host = mmc_priv(mmc);
5616 + struct mmc_command *cmd = host->cmd;
5617 +
5618 + /*
5619 + * Read the response now so that we're free to send a new
5620 + * command immediately.
5621 + */
5622 + cmd->resp[0] = mci_readl(host, RSPR);
5623 + cmd->resp[1] = mci_readl(host, RSPR);
5624 + cmd->resp[2] = mci_readl(host, RSPR);
5625 + cmd->resp[3] = mci_readl(host, RSPR);
5626 +
5627 + mci_writel(host, IDR, MCI_BIT(CMDRDY));
5628 + host->cmd = NULL;
5629 +
5630 + if (mci_stop_sent_is_complete(host)) {
5631 + host->stop_status = status;
5632 + mci_set_stop_pending(host);
5633 + } else {
5634 + host->cmd_status = status;
5635 + mci_set_cmd_pending(host);
5636 + }
5637 +
5638 + tasklet_schedule(&host->tasklet);
5639 +}
5640 +
5641 +static void atmci_xfer_complete(struct dma_request *_req)
5642 +{
5643 + struct dma_request_sg *req = to_dma_request_sg(_req);
5644 + struct atmel_mci_dma *dma;
5645 + struct atmel_mci *host;
5646 + struct mmc_data *data;
5647 +
5648 + dma = container_of(req, struct atmel_mci_dma, req);
5649 + host = container_of(dma, struct atmel_mci, dma);
5650 + data = host->data;
5651 +
5652 + if (data->stop && !mci_set_stop_sent_is_completed(host))
5653 + send_stop_cmd(host->mmc, data, 0);
5654 +
5655 + /*
5656 + * Regardless of what the documentation says, we have to wait
5657 + * for NOTBUSY even after block read operations.
5658 + *
5659 + * When the DMA transfer is complete, the controller may still
5660 + * be reading the CRC from the card, i.e. the data transfer is
5661 + * still in progress and we haven't seen all the potential
5662 + * error bits yet.
5663 + */
5664 + mci_writel(host, IER, MCI_BIT(NOTBUSY));
5665 +}
5666 +
5667 +static void atmci_dma_error(struct dma_request *_req)
5668 +{
5669 + struct dma_request_sg *req = to_dma_request_sg(_req);
5670 + struct atmel_mci_dma *dma;
5671 + struct atmel_mci *host;
5672 +
5673 + dma = container_of(req, struct atmel_mci_dma, req);
5674 + host = container_of(dma, struct atmel_mci, dma);
5675 +
5676 + mci_writel(host, IDR, (MCI_BIT(NOTBUSY)
5677 + | MCI_DATA_ERROR_FLAGS));
5678 +
5679 + mci_set_dma_error_pending(host);
5680 + tasklet_schedule(&host->tasklet);
5681 +}
5682 +
5683 +static irqreturn_t atmci_interrupt(int irq, void *dev_id)
5684 +{
5685 + struct mmc_host *mmc = dev_id;
5686 + struct atmel_mci *host = mmc_priv(mmc);
5687 + u32 status, mask, pending;
5688 +
5689 + spin_lock(&mmc->lock);
5690 +
5691 + status = mci_readl(host, SR);
5692 + mask = mci_readl(host, IMR);
5693 + pending = status & mask;
5694 +
5695 + do {
5696 + if (pending & MCI_DATA_ERROR_FLAGS) {
5697 + mci_writel(host, IDR, (MCI_BIT(NOTBUSY)
5698 + | MCI_DATA_ERROR_FLAGS));
5699 + host->data_status = status;
5700 + mci_set_data_error_pending(host);
5701 + tasklet_schedule(&host->tasklet);
5702 + break;
5703 + }
5704 + if (pending & MCI_BIT(CMDRDY))
5705 + atmci_cmd_interrupt(mmc, status);
5706 + if (pending & MCI_BIT(NOTBUSY)) {
5707 + mci_writel(host, IDR, (MCI_BIT(NOTBUSY)
5708 + | MCI_DATA_ERROR_FLAGS));
5709 + mci_set_data_pending(host);
5710 + tasklet_schedule(&host->tasklet);
5711 + }
5712 +
5713 + status = mci_readl(host, SR);
5714 + mask = mci_readl(host, IMR);
5715 + pending = status & mask;
5716 + } while (pending);
5717 +
5718 + spin_unlock(&mmc->lock);
5719 +
5720 + return IRQ_HANDLED;
5721 +}
5722 +
5723 +static irqreturn_t atmci_detect_change(int irq, void *dev_id)
5724 +{
5725 + struct mmc_host *mmc = dev_id;
5726 + struct atmel_mci *host = mmc_priv(mmc);
5727 +
5728 + int present = !gpio_get_value(irq_to_gpio(irq));
5729 +
5730 + if (present != host->present) {
5731 + dev_dbg(&mmc->class_dev, "card %s\n",
5732 + present ? "inserted" : "removed");
5733 + host->present = present;
5734 + mci_set_card_detect_pending(host);
5735 + tasklet_schedule(&host->tasklet);
5736 + }
5737 + return IRQ_HANDLED;
5738 +}
5739 +
5740 +static int __devinit atmci_probe(struct platform_device *pdev)
5741 +{
5742 + struct mci_platform_data *board;
5743 + struct atmel_mci *host;
5744 + struct mmc_host *mmc;
5745 + struct resource *regs;
5746 + int irq;
5747 + int ret;
5748 +
5749 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5750 + if (!regs)
5751 + return -ENXIO;
5752 + irq = platform_get_irq(pdev, 0);
5753 + if (irq < 0)
5754 + return irq;
5755 +
5756 + board = pdev->dev.platform_data;
5757 +
5758 + mmc = mmc_alloc_host(sizeof(struct atmel_mci), &pdev->dev);
5759 + if (!mmc)
5760 + return -ENOMEM;
5761 +
5762 + host = mmc_priv(mmc);
5763 + host->pdev = pdev;
5764 + host->mmc = mmc;
5765 + if (board) {
5766 + host->detect_pin = board->detect_pin;
5767 + host->wp_pin = board->wp_pin;
5768 + } else {
5769 + host->detect_pin = -1;
5770 + host->detect_pin = -1;
5771 + }
5772 +
5773 + host->mck = clk_get(&pdev->dev, "mci_clk");
5774 + if (IS_ERR(host->mck)) {
5775 + ret = PTR_ERR(host->mck);
5776 + goto out_free_host;
5777 + }
5778 + clk_enable(host->mck);
5779 +
5780 + ret = -ENOMEM;
5781 + host->regs = ioremap(regs->start, regs->end - regs->start + 1);
5782 + if (!host->regs)
5783 + goto out_disable_clk;
5784 +
5785 + host->bus_hz = clk_get_rate(host->mck);
5786 + host->mapbase = regs->start;
5787 +
5788 + mmc->ops = &atmci_ops;
5789 + mmc->f_min = (host->bus_hz + 511) / 512;
5790 + mmc->f_max = min((unsigned int)(host->bus_hz / 2), fmax);
5791 + mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
5792 + mmc->caps |= MMC_CAP_4_BIT_DATA;
5793 +
5794 + tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)mmc);
5795 +
5796 + ret = request_irq(irq, atmci_interrupt, 0, "mmci", mmc);
5797 + if (ret)
5798 + goto out_unmap;
5799 +
5800 + /* Assume card is present if we don't have a detect pin */
5801 + host->present = 1;
5802 + if (host->detect_pin >= 0) {
5803 + if (gpio_request(host->detect_pin, "mmc_detect")) {
5804 + dev_dbg(&mmc->class_dev, "no detect pin available\n");
5805 + host->detect_pin = -1;
5806 + } else {
5807 + host->present = !gpio_get_value(host->detect_pin);
5808 + }
5809 + }
5810 + if (host->wp_pin >= 0) {
5811 + if (gpio_request(host->wp_pin, "mmc_wp")) {
5812 + dev_dbg(&mmc->class_dev, "no WP pin available\n");
5813 + host->wp_pin = -1;
5814 + }
5815 + }
5816 +
5817 + /* TODO: Get this information from platform data */
5818 + ret = -ENOMEM;
5819 + host->dma.req.req.dmac = find_dma_controller(0);
5820 + if (!host->dma.req.req.dmac) {
5821 + dev_dbg(&mmc->class_dev, "no DMA controller available\n");
5822 + goto out_free_irq;
5823 + }
5824 + ret = dma_alloc_channel(host->dma.req.req.dmac);
5825 + if (ret < 0) {
5826 + dev_dbg(&mmc->class_dev, "unable to allocate DMA channel\n");
5827 + goto out_free_irq;
5828 + }
5829 + host->dma.req.req.channel = ret;
5830 + host->dma.req.width = DMA_WIDTH_32BIT;
5831 + host->dma.req.req.xfer_complete = atmci_xfer_complete;
5832 + host->dma.req.req.block_complete = NULL; // atmci_block_complete;
5833 + host->dma.req.req.error = atmci_dma_error;
5834 + host->dma.rx_periph_id = 0;
5835 + host->dma.tx_periph_id = 1;
5836 +
5837 + mci_writel(host, CR, MCI_BIT(SWRST));
5838 + mci_writel(host, IDR, ~0UL);
5839 +
5840 + platform_set_drvdata(pdev, host);
5841 +
5842 + mmc_add_host(mmc);
5843 +
5844 + if (host->detect_pin >= 0) {
5845 + ret = request_irq(gpio_to_irq(host->detect_pin),
5846 + atmci_detect_change,
5847 + IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
5848 + DRIVER_NAME, mmc);
5849 + if (ret) {
5850 + dev_dbg(&mmc->class_dev,
5851 + "could not request IRQ %d for detect pin\n",
5852 + gpio_to_irq(host->detect_pin));
5853 + gpio_free(host->detect_pin);
5854 + host->detect_pin = -1;
5855 + }
5856 + }
5857 +
5858 + dev_info(&mmc->class_dev, "Atmel MCI controller at 0x%08lx irq %d\n",
5859 + host->mapbase, irq);
5860 +
5861 + atmci_init_debugfs(host);
5862 +
5863 + return 0;
5864 +
5865 +out_free_irq:
5866 + if (host->detect_pin >= 0)
5867 + gpio_free(host->detect_pin);
5868 + if (host->wp_pin >= 0)
5869 + gpio_free(host->wp_pin);
5870 + free_irq(irq, mmc);
5871 +out_unmap:
5872 + iounmap(host->regs);
5873 +out_disable_clk:
5874 + clk_disable(host->mck);
5875 + clk_put(host->mck);
5876 +out_free_host:
5877 + mmc_free_host(mmc);
5878 + return ret;
5879 +}
5880 +
5881 +static int __devexit atmci_remove(struct platform_device *pdev)
5882 +{
5883 + struct atmel_mci *host = platform_get_drvdata(pdev);
5884 +
5885 + platform_set_drvdata(pdev, NULL);
5886 +
5887 + if (host) {
5888 + atmci_cleanup_debugfs(host);
5889 +
5890 + if (host->detect_pin >= 0) {
5891 + free_irq(gpio_to_irq(host->detect_pin), host->mmc);
5892 + cancel_delayed_work(&host->mmc->detect);
5893 + gpio_free(host->detect_pin);
5894 + }
5895 +
5896 + mmc_remove_host(host->mmc);
5897 +
5898 + mci_writel(host, IDR, ~0UL);
5899 + mci_writel(host, CR, MCI_BIT(MCIDIS));
5900 + mci_readl(host, SR);
5901 +
5902 + dma_release_channel(host->dma.req.req.dmac,
5903 + host->dma.req.req.channel);
5904 +
5905 + if (host->wp_pin >= 0)
5906 + gpio_free(host->wp_pin);
5907 +
5908 + free_irq(platform_get_irq(pdev, 0), host->mmc);
5909 + iounmap(host->regs);
5910 +
5911 + clk_disable(host->mck);
5912 + clk_put(host->mck);
5913 +
5914 + mmc_free_host(host->mmc);
5915 + }
5916 + return 0;
5917 +}
5918 +
5919 +static struct platform_driver atmci_driver = {
5920 + .probe = atmci_probe,
5921 + .remove = __devexit_p(atmci_remove),
5922 + .driver = {
5923 + .name = DRIVER_NAME,
5924 + },
5925 +};
5926 +
5927 +static int __init atmci_init(void)
5928 +{
5929 + return platform_driver_register(&atmci_driver);
5930 +}
5931 +
5932 +static void __exit atmci_exit(void)
5933 +{
5934 + platform_driver_unregister(&atmci_driver);
5935 +}
5936 +
5937 +module_init(atmci_init);
5938 +module_exit(atmci_exit);
5939 +
5940 +MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
5941 +MODULE_LICENSE("GPL");
5942 diff --git a/drivers/mmc/host/atmel-mci.h b/drivers/mmc/host/atmel-mci.h
5943 new file mode 100644
5944 index 0000000..60d15c4
5945 --- /dev/null
5946 +++ b/drivers/mmc/host/atmel-mci.h
5947 @@ -0,0 +1,192 @@
5948 +/*
5949 + * Atmel MultiMedia Card Interface driver
5950 + *
5951 + * Copyright (C) 2004-2006 Atmel Corporation
5952 + *
5953 + * This program is free software; you can redistribute it and/or modify
5954 + * it under the terms of the GNU General Public License version 2 as
5955 + * published by the Free Software Foundation.
5956 + */
5957 +#ifndef __DRIVERS_MMC_ATMEL_MCI_H__
5958 +#define __DRIVERS_MMC_ATMEL_MCI_H__
5959 +
5960 +/* MCI register offsets */
5961 +#define MCI_CR 0x0000
5962 +#define MCI_MR 0x0004
5963 +#define MCI_DTOR 0x0008
5964 +#define MCI_SDCR 0x000c
5965 +#define MCI_ARGR 0x0010
5966 +#define MCI_CMDR 0x0014
5967 +#define MCI_BLKR 0x0018
5968 +#define MCI_RSPR 0x0020
5969 +#define MCI_RSPR1 0x0024
5970 +#define MCI_RSPR2 0x0028
5971 +#define MCI_RSPR3 0x002c
5972 +#define MCI_RDR 0x0030
5973 +#define MCI_TDR 0x0034
5974 +#define MCI_SR 0x0040
5975 +#define MCI_IER 0x0044
5976 +#define MCI_IDR 0x0048
5977 +#define MCI_IMR 0x004c
5978 +
5979 +/* Bitfields in CR */
5980 +#define MCI_MCIEN_OFFSET 0
5981 +#define MCI_MCIEN_SIZE 1
5982 +#define MCI_MCIDIS_OFFSET 1
5983 +#define MCI_MCIDIS_SIZE 1
5984 +#define MCI_PWSEN_OFFSET 2
5985 +#define MCI_PWSEN_SIZE 1
5986 +#define MCI_PWSDIS_OFFSET 3
5987 +#define MCI_PWSDIS_SIZE 1
5988 +#define MCI_SWRST_OFFSET 7
5989 +#define MCI_SWRST_SIZE 1
5990 +
5991 +/* Bitfields in MR */
5992 +#define MCI_CLKDIV_OFFSET 0
5993 +#define MCI_CLKDIV_SIZE 8
5994 +#define MCI_PWSDIV_OFFSET 8
5995 +#define MCI_PWSDIV_SIZE 3
5996 +#define MCI_RDPROOF_OFFSET 11
5997 +#define MCI_RDPROOF_SIZE 1
5998 +#define MCI_WRPROOF_OFFSET 12
5999 +#define MCI_WRPROOF_SIZE 1
6000 +#define MCI_DMAPADV_OFFSET 14
6001 +#define MCI_DMAPADV_SIZE 1
6002 +#define MCI_BLKLEN_OFFSET 16
6003 +#define MCI_BLKLEN_SIZE 16
6004 +
6005 +/* Bitfields in DTOR */
6006 +#define MCI_DTOCYC_OFFSET 0
6007 +#define MCI_DTOCYC_SIZE 4
6008 +#define MCI_DTOMUL_OFFSET 4
6009 +#define MCI_DTOMUL_SIZE 3
6010 +
6011 +/* Bitfields in SDCR */
6012 +#define MCI_SDCSEL_OFFSET 0
6013 +#define MCI_SDCSEL_SIZE 4
6014 +#define MCI_SDCBUS_OFFSET 7
6015 +#define MCI_SDCBUS_SIZE 1
6016 +
6017 +/* Bitfields in ARGR */
6018 +#define MCI_ARG_OFFSET 0
6019 +#define MCI_ARG_SIZE 32
6020 +
6021 +/* Bitfields in CMDR */
6022 +#define MCI_CMDNB_OFFSET 0
6023 +#define MCI_CMDNB_SIZE 6
6024 +#define MCI_RSPTYP_OFFSET 6
6025 +#define MCI_RSPTYP_SIZE 2
6026 +#define MCI_SPCMD_OFFSET 8
6027 +#define MCI_SPCMD_SIZE 3
6028 +#define MCI_OPDCMD_OFFSET 11
6029 +#define MCI_OPDCMD_SIZE 1
6030 +#define MCI_MAXLAT_OFFSET 12
6031 +#define MCI_MAXLAT_SIZE 1
6032 +#define MCI_TRCMD_OFFSET 16
6033 +#define MCI_TRCMD_SIZE 2
6034 +#define MCI_TRDIR_OFFSET 18
6035 +#define MCI_TRDIR_SIZE 1
6036 +#define MCI_TRTYP_OFFSET 19
6037 +#define MCI_TRTYP_SIZE 2
6038 +
6039 +/* Bitfields in BLKR */
6040 +#define MCI_BCNT_OFFSET 0
6041 +#define MCI_BCNT_SIZE 16
6042 +
6043 +/* Bitfields in RSPRn */
6044 +#define MCI_RSP_OFFSET 0
6045 +#define MCI_RSP_SIZE 32
6046 +
6047 +/* Bitfields in SR/IER/IDR/IMR */
6048 +#define MCI_CMDRDY_OFFSET 0
6049 +#define MCI_CMDRDY_SIZE 1
6050 +#define MCI_RXRDY_OFFSET 1
6051 +#define MCI_RXRDY_SIZE 1
6052 +#define MCI_TXRDY_OFFSET 2
6053 +#define MCI_TXRDY_SIZE 1
6054 +#define MCI_BLKE_OFFSET 3
6055 +#define MCI_BLKE_SIZE 1
6056 +#define MCI_DTIP_OFFSET 4
6057 +#define MCI_DTIP_SIZE 1
6058 +#define MCI_NOTBUSY_OFFSET 5
6059 +#define MCI_NOTBUSY_SIZE 1
6060 +#define MCI_ENDRX_OFFSET 6
6061 +#define MCI_ENDRX_SIZE 1
6062 +#define MCI_ENDTX_OFFSET 7
6063 +#define MCI_ENDTX_SIZE 1
6064 +#define MCI_RXBUFF_OFFSET 14
6065 +#define MCI_RXBUFF_SIZE 1
6066 +#define MCI_TXBUFE_OFFSET 15
6067 +#define MCI_TXBUFE_SIZE 1
6068 +#define MCI_RINDE_OFFSET 16
6069 +#define MCI_RINDE_SIZE 1
6070 +#define MCI_RDIRE_OFFSET 17
6071 +#define MCI_RDIRE_SIZE 1
6072 +#define MCI_RCRCE_OFFSET 18
6073 +#define MCI_RCRCE_SIZE 1
6074 +#define MCI_RENDE_OFFSET 19
6075 +#define MCI_RENDE_SIZE 1
6076 +#define MCI_RTOE_OFFSET 20
6077 +#define MCI_RTOE_SIZE 1
6078 +#define MCI_DCRCE_OFFSET 21
6079 +#define MCI_DCRCE_SIZE 1
6080 +#define MCI_DTOE_OFFSET 22
6081 +#define MCI_DTOE_SIZE 1
6082 +#define MCI_OVRE_OFFSET 30
6083 +#define MCI_OVRE_SIZE 1
6084 +#define MCI_UNRE_OFFSET 31
6085 +#define MCI_UNRE_SIZE 1
6086 +
6087 +/* Constants for DTOMUL */
6088 +#define MCI_DTOMUL_1_CYCLE 0
6089 +#define MCI_DTOMUL_16_CYCLES 1
6090 +#define MCI_DTOMUL_128_CYCLES 2
6091 +#define MCI_DTOMUL_256_CYCLES 3
6092 +#define MCI_DTOMUL_1024_CYCLES 4
6093 +#define MCI_DTOMUL_4096_CYCLES 5
6094 +#define MCI_DTOMUL_65536_CYCLES 6
6095 +#define MCI_DTOMUL_1048576_CYCLES 7
6096 +
6097 +/* Constants for RSPTYP */
6098 +#define MCI_RSPTYP_NO_RESP 0
6099 +#define MCI_RSPTYP_48_BIT 1
6100 +#define MCI_RSPTYP_136_BIT 2
6101 +
6102 +/* Constants for SPCMD */
6103 +#define MCI_SPCMD_NO_SPEC_CMD 0
6104 +#define MCI_SPCMD_INIT_CMD 1
6105 +#define MCI_SPCMD_SYNC_CMD 2
6106 +#define MCI_SPCMD_INT_CMD 4
6107 +#define MCI_SPCMD_INT_RESP 5
6108 +
6109 +/* Constants for TRCMD */
6110 +#define MCI_TRCMD_NO_TRANS 0
6111 +#define MCI_TRCMD_START_TRANS 1
6112 +#define MCI_TRCMD_STOP_TRANS 2
6113 +
6114 +/* Constants for TRTYP */
6115 +#define MCI_TRTYP_BLOCK 0
6116 +#define MCI_TRTYP_MULTI_BLOCK 1
6117 +#define MCI_TRTYP_STREAM 2
6118 +
6119 +/* Bit manipulation macros */
6120 +#define MCI_BIT(name) \
6121 + (1 << MCI_##name##_OFFSET)
6122 +#define MCI_BF(name,value) \
6123 + (((value) & ((1 << MCI_##name##_SIZE) - 1)) \
6124 + << MCI_##name##_OFFSET)
6125 +#define MCI_BFEXT(name,value) \
6126 + (((value) >> MCI_##name##_OFFSET) \
6127 + & ((1 << MCI_##name##_SIZE) - 1))
6128 +#define MCI_BFINS(name,value,old) \
6129 + (((old) & ~(((1 << MCI_##name##_SIZE) - 1) \
6130 + << MCI_##name##_OFFSET)) \
6131 + | MCI_BF(name,value))
6132 +
6133 +/* Register access macros */
6134 +#define mci_readl(port,reg) \
6135 + __raw_readl((port)->regs + MCI_##reg)
6136 +#define mci_writel(port,reg,value) \
6137 + __raw_writel((value), (port)->regs + MCI_##reg)
6138 +
6139 +#endif /* __DRIVERS_MMC_ATMEL_MCI_H__ */
6140 diff --git a/drivers/mtd/chips/cfi_cmdset_0001.c b/drivers/mtd/chips/cfi_cmdset_0001.c
6141 index 2f19fa7..94304ca 100644
6142 --- a/drivers/mtd/chips/cfi_cmdset_0001.c
6143 +++ b/drivers/mtd/chips/cfi_cmdset_0001.c
6144 @@ -50,6 +50,7 @@
6145 #define I82802AC 0x00ac
6146 #define MANUFACTURER_ST 0x0020
6147 #define M50LPW080 0x002F
6148 +#define AT49BV640D 0x02de
6149
6150 static int cfi_intelext_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
6151 static int cfi_intelext_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
6152 @@ -156,6 +157,47 @@ static void cfi_tell_features(struct cfi_pri_intelext *extp)
6153 }
6154 #endif
6155
6156 +/* Atmel chips don't use the same PRI format as Intel chips */
6157 +static void fixup_convert_atmel_pri(struct mtd_info *mtd, void *param)
6158 +{
6159 + struct map_info *map = mtd->priv;
6160 + struct cfi_private *cfi = map->fldrv_priv;
6161 + struct cfi_pri_intelext *extp = cfi->cmdset_priv;
6162 + struct cfi_pri_atmel atmel_pri;
6163 + uint32_t features = 0;
6164 +
6165 + /* Reverse byteswapping */
6166 + extp->FeatureSupport = cpu_to_le32(extp->FeatureSupport);
6167 + extp->BlkStatusRegMask = cpu_to_le16(extp->BlkStatusRegMask);
6168 + extp->ProtRegAddr = cpu_to_le16(extp->ProtRegAddr);
6169 +
6170 + memcpy(&atmel_pri, extp, sizeof(atmel_pri));
6171 + memset((char *)extp + 5, 0, sizeof(*extp) - 5);
6172 +
6173 + printk(KERN_ERR "atmel Features: %02x\n", atmel_pri.Features);
6174 +
6175 + if (atmel_pri.Features & 0x01) /* chip erase supported */
6176 + features |= (1<<0);
6177 + if (atmel_pri.Features & 0x02) /* erase suspend supported */
6178 + features |= (1<<1);
6179 + if (atmel_pri.Features & 0x04) /* program suspend supported */
6180 + features |= (1<<2);
6181 + if (atmel_pri.Features & 0x08) /* simultaneous operations supported */
6182 + features |= (1<<9);
6183 + if (atmel_pri.Features & 0x20) /* page mode read supported */
6184 + features |= (1<<7);
6185 + if (atmel_pri.Features & 0x40) /* queued erase supported */
6186 + features |= (1<<4);
6187 + if (atmel_pri.Features & 0x80) /* Protection bits supported */
6188 + features |= (1<<6);
6189 +
6190 + extp->FeatureSupport = features;
6191 +
6192 + /* burst write mode not supported */
6193 + cfi->cfiq->BufWriteTimeoutTyp = 0;
6194 + cfi->cfiq->BufWriteTimeoutMax = 0;
6195 +}
6196 +
6197 #ifdef CMDSET0001_DISABLE_ERASE_SUSPEND_ON_WRITE
6198 /* Some Intel Strata Flash prior to FPO revision C has bugs in this area */
6199 static void fixup_intel_strataflash(struct mtd_info *mtd, void* param)
6200 @@ -233,6 +275,7 @@ static void fixup_use_powerup_lock(struct mtd_info *mtd, void *param)
6201 }
6202
6203 static struct cfi_fixup cfi_fixup_table[] = {
6204 + { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri, NULL },
6205 #ifdef CMDSET0001_DISABLE_ERASE_SUSPEND_ON_WRITE
6206 { CFI_MFR_ANY, CFI_ID_ANY, fixup_intel_strataflash, NULL },
6207 #endif
6208 diff --git a/drivers/mtd/chips/cfi_cmdset_0002.c b/drivers/mtd/chips/cfi_cmdset_0002.c
6209 index 1f64458..205977b 100644
6210 --- a/drivers/mtd/chips/cfi_cmdset_0002.c
6211 +++ b/drivers/mtd/chips/cfi_cmdset_0002.c
6212 @@ -185,6 +185,10 @@ static void fixup_convert_atmel_pri(struct mtd_info *mtd, void *param)
6213 extp->TopBottom = 2;
6214 else
6215 extp->TopBottom = 3;
6216 +
6217 + /* burst write mode not supported */
6218 + cfi->cfiq->BufWriteTimeoutTyp = 0;
6219 + cfi->cfiq->BufWriteTimeoutMax = 0;
6220 }
6221
6222 static void fixup_use_secsi(struct mtd_info *mtd, void *param)
6223 @@ -217,6 +221,7 @@ static void fixup_use_atmel_lock(struct mtd_info *mtd, void *param)
6224 }
6225
6226 static struct cfi_fixup cfi_fixup_table[] = {
6227 + { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri, NULL },
6228 #ifdef AMD_BOOTLOC_BUG
6229 { CFI_MFR_AMD, CFI_ID_ANY, fixup_amd_bootblock, NULL },
6230 #endif
6231 @@ -229,7 +234,6 @@ static struct cfi_fixup cfi_fixup_table[] = {
6232 #if !FORCE_WORD_WRITE
6233 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_write_buffers, NULL, },
6234 #endif
6235 - { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri, NULL },
6236 { 0, 0, NULL, NULL }
6237 };
6238 static struct cfi_fixup jedec_fixup_table[] = {
6239 diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c
6240 index b046974..bc90604 100644
6241 --- a/drivers/spi/atmel_spi.c
6242 +++ b/drivers/spi/atmel_spi.c
6243 @@ -491,8 +491,8 @@ static int atmel_spi_setup(struct spi_device *spi)
6244 csr |= SPI_BIT(NCPHA);
6245
6246 /* TODO: DLYBS and DLYBCT */
6247 - csr |= SPI_BF(DLYBS, 10);
6248 - csr |= SPI_BF(DLYBCT, 10);
6249 + csr |= SPI_BF(DLYBS, 0);
6250 + csr |= SPI_BF(DLYBCT, 0);
6251
6252 /* chipselect must have been muxed as GPIO (e.g. in board setup) */
6253 npcs_pin = (unsigned int)spi->controller_data;
6254 diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
6255 index 767aed5..f81d08d 100644
6256 --- a/drivers/usb/gadget/Kconfig
6257 +++ b/drivers/usb/gadget/Kconfig
6258 @@ -67,6 +67,17 @@ config USB_GADGET_DEBUG_FILES
6259 driver on a new board. Enable these files by choosing "Y"
6260 here. If in doubt, or to conserve kernel memory, say "N".
6261
6262 +config USB_GADGET_DEBUG_FS
6263 + boolean "Debugging information files in debugfs"
6264 + depends on USB_GADGET && DEBUG_FS
6265 + help
6266 + Some of the drivers in the "gadget" framework can expose
6267 + debugging information in files under /sys/kernel/debug/.
6268 + The information in these files may help when you're
6269 + troubleshooting or bringing up a driver on a new board.
6270 + Enable these files by choosing "Y" here. If in doubt, or
6271 + to conserve kernel memory, say "N".
6272 +
6273 config USB_GADGET_SELECTED
6274 boolean
6275
6276 @@ -103,6 +114,20 @@ config USB_AMD5536UDC
6277 default USB_GADGET
6278 select USB_GADGET_SELECTED
6279
6280 +config USB_GADGET_ATMEL_USBA
6281 + boolean "Atmel USBA"
6282 + select USB_GADGET_DUALSPEED
6283 + depends on AVR32
6284 + help
6285 + USBA is the integrated high-speed USB Device controller on
6286 + the AT32AP700x processors from Atmel.
6287 +
6288 +config USB_ATMEL_USBA
6289 + tristate
6290 + depends on USB_GADGET_ATMEL_USBA
6291 + default USB_GADGET
6292 + select USB_GADGET_SELECTED
6293 +
6294 config USB_GADGET_FSL_USB2
6295 boolean "Freescale Highspeed USB DR Peripheral Controller"
6296 depends on MPC834x || PPC_MPC831x
6297 @@ -228,7 +253,6 @@ config USB_LH7A40X
6298 default USB_GADGET
6299 select USB_GADGET_SELECTED
6300
6301 -
6302 config USB_GADGET_OMAP
6303 boolean "OMAP USB Device Controller"
6304 depends on ARCH_OMAP
6305 diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
6306 index 1bc0f03..904e57b 100644
6307 --- a/drivers/usb/gadget/Makefile
6308 +++ b/drivers/usb/gadget/Makefile
6309 @@ -14,6 +14,7 @@ obj-$(CONFIG_USB_OMAP) += omap_udc.o
6310 obj-$(CONFIG_USB_LH7A40X) += lh7a40x_udc.o
6311 obj-$(CONFIG_USB_S3C2410) += s3c2410_udc.o
6312 obj-$(CONFIG_USB_AT91) += at91_udc.o
6313 +obj-$(CONFIG_USB_ATMEL_USBA) += atmel_usba_udc.o
6314 obj-$(CONFIG_USB_FSL_USB2) += fsl_usb2_udc.o
6315 obj-$(CONFIG_USB_M66592) += m66592-udc.o
6316
6317 diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c
6318 new file mode 100644
6319 index 0000000..e35362d
6320 --- /dev/null
6321 +++ b/drivers/usb/gadget/atmel_usba_udc.c
6322 @@ -0,0 +1,2038 @@
6323 +/*
6324 + * Driver for the Atmel USBA high speed USB device controller
6325 + *
6326 + * Copyright (C) 2005-2007 Atmel Corporation
6327 + *
6328 + * This program is free software; you can redistribute it and/or modify
6329 + * it under the terms of the GNU General Public License version 2 as
6330 + * published by the Free Software Foundation.
6331 + */
6332 +#include <linux/clk.h>
6333 +#include <linux/module.h>
6334 +#include <linux/init.h>
6335 +#include <linux/interrupt.h>
6336 +#include <linux/io.h>
6337 +#include <linux/device.h>
6338 +#include <linux/dma-mapping.h>
6339 +#include <linux/list.h>
6340 +#include <linux/platform_device.h>
6341 +#include <linux/usb/ch9.h>
6342 +#include <linux/usb_gadget.h>
6343 +#include <linux/delay.h>
6344 +
6345 +#include <asm/gpio.h>
6346 +#include <asm/arch/board.h>
6347 +
6348 +#include "atmel_usba_udc.h"
6349 +
6350 +
6351 +static struct usba_udc the_udc;
6352 +
6353 +#ifdef CONFIG_USB_GADGET_DEBUG_FS
6354 +#include <linux/debugfs.h>
6355 +#include <linux/uaccess.h>
6356 +
6357 +static int queue_dbg_open(struct inode *inode, struct file *file)
6358 +{
6359 + struct usba_ep *ep = inode->i_private;
6360 + struct usba_request *req, *req_copy;
6361 + struct list_head *queue_data;
6362 +
6363 + queue_data = kmalloc(sizeof(*queue_data), GFP_KERNEL);
6364 + if (!queue_data)
6365 + return -ENOMEM;
6366 + INIT_LIST_HEAD(queue_data);
6367 +
6368 + spin_lock_irq(&ep->udc->lock);
6369 + list_for_each_entry(req, &ep->queue, queue) {
6370 + req_copy = kmalloc(sizeof(*req_copy), GFP_ATOMIC);
6371 + if (!req_copy)
6372 + goto fail;
6373 + memcpy(req_copy, req, sizeof(*req_copy));
6374 + list_add_tail(&req_copy->queue, queue_data);
6375 + }
6376 + spin_unlock_irq(&ep->udc->lock);
6377 +
6378 + file->private_data = queue_data;
6379 + return 0;
6380 +
6381 +fail:
6382 + spin_unlock_irq(&ep->udc->lock);
6383 + list_for_each_entry_safe(req, req_copy, queue_data, queue) {
6384 + list_del(&req->queue);
6385 + kfree(req);
6386 + }
6387 + kfree(queue_data);
6388 + return -ENOMEM;
6389 +}
6390 +
6391 +/*
6392 + * bbbbbbbb llllllll IZS sssss nnnn FDL\n\0
6393 + *
6394 + * b: buffer address
6395 + * l: buffer length
6396 + * I/i: interrupt/no interrupt
6397 + * Z/z: zero/no zero
6398 + * S/s: short ok/short not ok
6399 + * s: status
6400 + * n: nr_packets
6401 + * F/f: submitted/not submitted to FIFO
6402 + * D/d: using/not using DMA
6403 + * L/l: last transaction/not last transaction
6404 + */
6405 +static ssize_t queue_dbg_read(struct file *file, char __user *buf,
6406 + size_t nbytes, loff_t *ppos)
6407 +{
6408 + struct list_head *queue = file->private_data;
6409 + struct usba_request *req, *tmp_req;
6410 + size_t len, remaining, actual = 0;
6411 + char tmpbuf[38];
6412 +
6413 + if (!access_ok(VERIFY_WRITE, buf, nbytes))
6414 + return -EFAULT;
6415 +
6416 + mutex_lock(&file->f_dentry->d_inode->i_mutex);
6417 + list_for_each_entry_safe(req, tmp_req, queue, queue) {
6418 + len = snprintf(tmpbuf, sizeof(tmpbuf),
6419 + "%8p %08x %c%c%c %5d %c%c%c\n",
6420 + req->req.buf, req->req.length,
6421 + req->req.no_interrupt ? 'i' : 'I',
6422 + req->req.zero ? 'Z' : 'z',
6423 + req->req.short_not_ok ? 's' : 'S',
6424 + req->req.status,
6425 + req->submitted ? 'F' : 'f',
6426 + req->using_dma ? 'D' : 'd',
6427 + req->last_transaction ? 'L' : 'l');
6428 + len = min(len, sizeof(tmpbuf));
6429 + if (len > nbytes)
6430 + break;
6431 +
6432 + list_del(&req->queue);
6433 + kfree(req);
6434 +
6435 + remaining = __copy_to_user(buf, tmpbuf, len);
6436 + actual += len - remaining;
6437 + if (remaining)
6438 + break;
6439 +
6440 + nbytes -= len;
6441 + buf += len;
6442 + }
6443 + mutex_unlock(&file->f_dentry->d_inode->i_mutex);
6444 +
6445 + return actual;
6446 +}
6447 +
6448 +static int queue_dbg_release(struct inode *inode, struct file *file)
6449 +{
6450 + struct list_head *queue_data = file->private_data;
6451 + struct usba_request *req, *tmp_req;
6452 +
6453 + list_for_each_entry_safe(req, tmp_req, queue_data, queue) {
6454 + list_del(&req->queue);
6455 + kfree(req);
6456 + }
6457 + kfree(queue_data);
6458 + return 0;
6459 +}
6460 +
6461 +static int regs_dbg_open(struct inode *inode, struct file *file)
6462 +{
6463 + struct usba_udc *udc;
6464 + unsigned int i;
6465 + u32 *data;
6466 + int ret = -ENOMEM;
6467 +
6468 + mutex_lock(&inode->i_mutex);
6469 + udc = inode->i_private;
6470 + data = kmalloc(inode->i_size, GFP_KERNEL);
6471 + if (!data)
6472 + goto out;
6473 +
6474 + spin_lock_irq(&udc->lock);
6475 + for (i = 0; i < inode->i_size / 4; i++)
6476 + data[i] = __raw_readl(udc->regs + i * 4);
6477 + spin_unlock_irq(&udc->lock);
6478 +
6479 + file->private_data = data;
6480 + ret = 0;
6481 +
6482 +out:
6483 + mutex_unlock(&inode->i_mutex);
6484 +
6485 + return ret;
6486 +}
6487 +
6488 +static ssize_t regs_dbg_read(struct file *file, char __user *buf,
6489 + size_t nbytes, loff_t *ppos)
6490 +{
6491 + struct inode *inode = file->f_dentry->d_inode;
6492 + int ret;
6493 +
6494 + mutex_lock(&inode->i_mutex);
6495 + ret = simple_read_from_buffer(buf, nbytes, ppos,
6496 + file->private_data,
6497 + file->f_dentry->d_inode->i_size);
6498 + mutex_unlock(&inode->i_mutex);
6499 +
6500 + return ret;
6501 +}
6502 +
6503 +static int regs_dbg_release(struct inode *inode, struct file *file)
6504 +{
6505 + kfree(file->private_data);
6506 + return 0;
6507 +}
6508 +
6509 +const struct file_operations queue_dbg_fops = {
6510 + .owner = THIS_MODULE,
6511 + .open = queue_dbg_open,
6512 + .llseek = no_llseek,
6513 + .read = queue_dbg_read,
6514 + .release = queue_dbg_release,
6515 +};
6516 +
6517 +const struct file_operations regs_dbg_fops = {
6518 + .owner = THIS_MODULE,
6519 + .open = regs_dbg_open,
6520 + .llseek = generic_file_llseek,
6521 + .read = regs_dbg_read,
6522 + .release = regs_dbg_release,
6523 +};
6524 +
6525 +static void usba_ep_init_debugfs(struct usba_udc *udc,
6526 + struct usba_ep *ep)
6527 +{
6528 + struct dentry *ep_root;
6529 +
6530 + ep_root = debugfs_create_dir(ep->ep.name, udc->debugfs_root);
6531 + if (!ep_root)
6532 + goto err_root;
6533 + ep->debugfs_dir = ep_root;
6534 +
6535 + ep->debugfs_queue = debugfs_create_file("queue", 0400, ep_root,
6536 + ep, &queue_dbg_fops);
6537 + if (!ep->debugfs_queue)
6538 + goto err_queue;
6539 +
6540 + if (ep->can_dma) {
6541 + ep->debugfs_dma_status
6542 + = debugfs_create_u32("dma_status", 0400, ep_root,
6543 + &ep->last_dma_status);
6544 + if (!ep->debugfs_dma_status)
6545 + goto err_dma_status;
6546 + }
6547 + if (ep_is_control(ep)) {
6548 + ep->debugfs_state
6549 + = debugfs_create_u32("state", 0400, ep_root,
6550 + &ep->state);
6551 + if (!ep->debugfs_state)
6552 + goto err_state;
6553 + }
6554 +
6555 + return;
6556 +
6557 +err_state:
6558 + if (ep->can_dma)
6559 + debugfs_remove(ep->debugfs_dma_status);
6560 +err_dma_status:
6561 + debugfs_remove(ep->debugfs_queue);
6562 +err_queue:
6563 + debugfs_remove(ep_root);
6564 +err_root:
6565 + dev_err(&ep->udc->pdev->dev,
6566 + "failed to create debugfs directory for %s\n", ep->ep.name);
6567 +}
6568 +
6569 +static void usba_ep_cleanup_debugfs(struct usba_ep *ep)
6570 +{
6571 + debugfs_remove(ep->debugfs_queue);
6572 + debugfs_remove(ep->debugfs_dma_status);
6573 + debugfs_remove(ep->debugfs_state);
6574 + debugfs_remove(ep->debugfs_dir);
6575 + ep->debugfs_dma_status = NULL;
6576 + ep->debugfs_dir = NULL;
6577 +}
6578 +
6579 +static void usba_init_debugfs(struct usba_udc *udc)
6580 +{
6581 + struct dentry *root, *regs;
6582 + struct resource *regs_resource;
6583 +
6584 + root = debugfs_create_dir(udc->gadget.name, NULL);
6585 + if (IS_ERR(root) || !root)
6586 + goto err_root;
6587 + udc->debugfs_root = root;
6588 +
6589 + regs = debugfs_create_file("regs", 0400, root, udc, &regs_dbg_fops);
6590 + if (!regs)
6591 + goto err_regs;
6592 +
6593 + regs_resource = platform_get_resource(udc->pdev, IORESOURCE_MEM,
6594 + CTRL_IOMEM_ID);
6595 + regs->d_inode->i_size = regs_resource->end - regs_resource->start + 1;
6596 + udc->debugfs_regs = regs;
6597 +
6598 + usba_ep_init_debugfs(udc, to_usba_ep(udc->gadget.ep0));
6599 +
6600 + return;
6601 +
6602 +err_regs:
6603 + debugfs_remove(root);
6604 +err_root:
6605 + udc->debugfs_root = NULL;
6606 + dev_err(&udc->pdev->dev, "debugfs is not available\n");
6607 +}
6608 +
6609 +static void usba_cleanup_debugfs(struct usba_udc *udc)
6610 +{
6611 + usba_ep_cleanup_debugfs(to_usba_ep(udc->gadget.ep0));
6612 + debugfs_remove(udc->debugfs_regs);
6613 + debugfs_remove(udc->debugfs_root);
6614 + udc->debugfs_regs = NULL;
6615 + udc->debugfs_root = NULL;
6616 +}
6617 +#else
6618 +static inline void usba_ep_init_debugfs(struct usba_udc *udc,
6619 + struct usba_ep *ep)
6620 +{
6621 +
6622 +}
6623 +
6624 +static inline void usba_ep_cleanup_debugfs(struct usba_ep *ep)
6625 +{
6626 +
6627 +}
6628 +
6629 +static inline void usba_init_debugfs(struct usba_udc *udc)
6630 +{
6631 +
6632 +}
6633 +
6634 +static inline void usba_cleanup_debugfs(struct usba_udc *udc)
6635 +{
6636 +
6637 +}
6638 +#endif
6639 +
6640 +static int vbus_is_present(struct usba_udc *udc)
6641 +{
6642 + if (udc->vbus_pin != -1)
6643 + return gpio_get_value(udc->vbus_pin);
6644 +
6645 + /* No Vbus detection: Assume always present */
6646 + return 1;
6647 +}
6648 +
6649 +static void copy_to_fifo(void __iomem *fifo, const void *buf, int len)
6650 +{
6651 + unsigned long tmp;
6652 +
6653 + DBG(DBG_FIFO, "copy to FIFO (len %d):\n", len);
6654 + for (; len > 0; len -= 4, buf += 4, fifo += 4) {
6655 + tmp = *(unsigned long *)buf;
6656 + if (len >= 4) {
6657 + DBG(DBG_FIFO, " -> %08lx\n", tmp);
6658 + __raw_writel(tmp, fifo);
6659 + } else {
6660 + do {
6661 + DBG(DBG_FIFO, " -> %02lx\n", tmp >> 24);
6662 + __raw_writeb(tmp >> 24, fifo);
6663 + fifo++;
6664 + tmp <<= 8;
6665 + } while (--len);
6666 + break;
6667 + }
6668 + }
6669 +}
6670 +
6671 +static void copy_from_fifo(void *buf, void __iomem *fifo, int len)
6672 +{
6673 + union {
6674 + unsigned long *w;
6675 + unsigned char *b;
6676 + } p;
6677 + unsigned long tmp;
6678 +
6679 + DBG(DBG_FIFO, "copy from FIFO (len %d):\n", len);
6680 + for (p.w = buf; len > 0; len -= 4, p.w++, fifo += 4) {
6681 + if (len >= 4) {
6682 + tmp = __raw_readl(fifo);
6683 + *p.w = tmp;
6684 + DBG(DBG_FIFO, " -> %08lx\n", tmp);
6685 + } else {
6686 + do {
6687 + tmp = __raw_readb(fifo);
6688 + *p.b = tmp;
6689 + DBG(DBG_FIFO, " -> %02lx\n", tmp);
6690 + fifo++, p.b++;
6691 + } while (--len);
6692 + }
6693 + }
6694 +}
6695 +
6696 +static void next_fifo_transaction(struct usba_ep *ep, struct usba_request *req)
6697 +{
6698 + unsigned int transaction_len;
6699 +
6700 + transaction_len = req->req.length - req->req.actual;
6701 + req->last_transaction = 1;
6702 + if (transaction_len > ep->ep.maxpacket) {
6703 + transaction_len = ep->ep.maxpacket;
6704 + req->last_transaction = 0;
6705 + } else if (transaction_len == ep->ep.maxpacket && req->req.zero)
6706 + req->last_transaction = 0;
6707 +
6708 + DBG(DBG_QUEUE, "%s: submit_transaction, req %p (length %d)%s\n",
6709 + ep->ep.name, req, transaction_len,
6710 + req->last_transaction ? ", done" : "");
6711 +
6712 + copy_to_fifo(ep->fifo, req->req.buf + req->req.actual, transaction_len);
6713 + usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
6714 + req->req.actual += transaction_len;
6715 +}
6716 +
6717 +static void submit_request(struct usba_ep *ep, struct usba_request *req)
6718 +{
6719 + DBG(DBG_QUEUE, "%s: submit_request: req %p (length %d)\n",
6720 + ep->ep.name, req, req->req.length);
6721 +
6722 + req->req.actual = 0;
6723 + req->submitted = 1;
6724 +
6725 + if (req->using_dma) {
6726 + if (req->req.length == 0) {
6727 + usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
6728 + return;
6729 + }
6730 +
6731 + if (req->req.zero)
6732 + usba_ep_writel(ep, CTL_ENB, USBA_SHORT_PACKET);
6733 + else
6734 + usba_ep_writel(ep, CTL_DIS, USBA_SHORT_PACKET);
6735 +
6736 + usba_dma_writel(ep, ADDRESS, req->req.dma);
6737 + usba_dma_writel(ep, CONTROL, req->ctrl);
6738 + } else {
6739 + next_fifo_transaction(ep, req);
6740 + if (req->last_transaction) {
6741 + usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
6742 + usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
6743 + } else {
6744 + usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
6745 + usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
6746 + }
6747 + }
6748 +}
6749 +
6750 +static void submit_next_request(struct usba_ep *ep)
6751 +{
6752 + struct usba_request *req;
6753 +
6754 + if (list_empty(&ep->queue)) {
6755 + usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY | USBA_RX_BK_RDY);
6756 + return;
6757 + }
6758 +
6759 + req = list_entry(ep->queue.next, struct usba_request, queue);
6760 + if (!req->submitted)
6761 + submit_request(ep, req);
6762 +}
6763 +
6764 +static void send_status(struct usba_udc *udc, struct usba_ep *ep)
6765 +{
6766 + ep->state = STATUS_STAGE_IN;
6767 + usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
6768 + usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
6769 +}
6770 +
6771 +static void receive_data(struct usba_ep *ep)
6772 +{
6773 + struct usba_udc *udc = ep->udc;
6774 + struct usba_request *req;
6775 + unsigned long status;
6776 + unsigned int bytecount, nr_busy;
6777 + int is_complete = 0;
6778 +
6779 + status = usba_ep_readl(ep, STA);
6780 + nr_busy = USBA_BFEXT(BUSY_BANKS, status);
6781 +
6782 + DBG(DBG_QUEUE, "receive data: nr_busy=%u\n", nr_busy);
6783 +
6784 + while (nr_busy > 0) {
6785 + if (list_empty(&ep->queue)) {
6786 + usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
6787 + break;
6788 + }
6789 + req = list_entry(ep->queue.next,
6790 + struct usba_request, queue);
6791 +
6792 + bytecount = USBA_BFEXT(BYTE_COUNT, status);
6793 +
6794 + if (status & (1 << 31))
6795 + is_complete = 1;
6796 + if (req->req.actual + bytecount >= req->req.length) {
6797 + is_complete = 1;
6798 + bytecount = req->req.length - req->req.actual;
6799 + }
6800 +
6801 + copy_from_fifo(req->req.buf + req->req.actual,
6802 + ep->fifo, bytecount);
6803 + req->req.actual += bytecount;
6804 +
6805 + usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
6806 +
6807 + if (is_complete) {
6808 + DBG(DBG_QUEUE, "%s: request done\n", ep->ep.name);
6809 + req->req.status = 0;
6810 + list_del_init(&req->queue);
6811 + usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
6812 + spin_unlock(&udc->lock);
6813 + req->req.complete(&ep->ep, &req->req);
6814 + spin_lock(&udc->lock);
6815 + }
6816 +
6817 + status = usba_ep_readl(ep, STA);
6818 + nr_busy = USBA_BFEXT(BUSY_BANKS, status);
6819 +
6820 + if (is_complete && ep_is_control(ep)) {
6821 + send_status(udc, ep);
6822 + break;
6823 + }
6824 + }
6825 +}
6826 +
6827 +static void
6828 +request_complete(struct usba_ep *ep, struct usba_request *req, int status)
6829 +{
6830 + struct usba_udc *udc = ep->udc;
6831 +
6832 + WARN_ON(!list_empty(&req->queue));
6833 +
6834 + if (req->req.status == -EINPROGRESS)
6835 + req->req.status = status;
6836 +
6837 + if (req->mapped) {
6838 + dma_unmap_single(
6839 + &udc->pdev->dev, req->req.dma, req->req.length,
6840 + ep->is_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
6841 + req->req.dma = DMA_ADDR_INVALID;
6842 + req->mapped = 0;
6843 + }
6844 +
6845 + DBG(DBG_GADGET | DBG_REQ,
6846 + "%s: req %p complete: status %d, actual %u\n",
6847 + ep->ep.name, req, req->req.status, req->req.actual);
6848 +
6849 + spin_unlock(&udc->lock);
6850 + req->req.complete(&ep->ep, &req->req);
6851 + spin_lock(&udc->lock);
6852 +}
6853 +
6854 +static void
6855 +request_complete_list(struct usba_ep *ep, struct list_head *list, int status)
6856 +{
6857 + struct usba_request *req, *tmp_req;
6858 +
6859 + list_for_each_entry_safe(req, tmp_req, list, queue) {
6860 + list_del_init(&req->queue);
6861 + request_complete(ep, req, status);
6862 + }
6863 +}
6864 +
6865 +static int
6866 +usba_ep_enable(struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc)
6867 +{
6868 + struct usba_ep *ep = to_usba_ep(_ep);
6869 + struct usba_udc *udc = ep->udc;
6870 + unsigned long flags, ept_cfg, maxpacket;
6871 + unsigned int nr_trans;
6872 +
6873 + DBG(DBG_GADGET, "%s: ep_enable: desc=%p\n", ep->ep.name, desc);
6874 +
6875 + maxpacket = le16_to_cpu(desc->wMaxPacketSize) & 0x7ff;
6876 +
6877 + if (((desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK) != ep->index)
6878 + || ep->index == 0
6879 + || desc->bDescriptorType != USB_DT_ENDPOINT
6880 + || maxpacket == 0
6881 + || maxpacket > ep->fifo_size) {
6882 + DBG(DBG_ERR, "ep_enable: Invalid argument");
6883 + return -EINVAL;
6884 + }
6885 +
6886 + ep->is_isoc = 0;
6887 + ep->is_in = 0;
6888 +
6889 + if (maxpacket <= 8)
6890 + ept_cfg = USBA_BF(EPT_SIZE, USBA_EPT_SIZE_8);
6891 + else
6892 + /* LSB is bit 1, not 0 */
6893 + ept_cfg = USBA_BF(EPT_SIZE, fls(maxpacket - 1) - 3);
6894 +
6895 + DBG(DBG_HW, "%s: EPT_SIZE = %lu (maxpacket = %lu)\n",
6896 + ep->ep.name, ept_cfg, maxpacket);
6897 +
6898 + if ((desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) {
6899 + ep->is_in = 1;
6900 + ept_cfg |= USBA_EPT_DIR_IN;
6901 + }
6902 +
6903 + switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
6904 + case USB_ENDPOINT_XFER_CONTROL:
6905 + ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL);
6906 + ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE);
6907 + break;
6908 + case USB_ENDPOINT_XFER_ISOC:
6909 + if (!ep->can_isoc) {
6910 + DBG(DBG_ERR, "ep_enable: %s is not isoc capable\n",
6911 + ep->ep.name);
6912 + return -EINVAL;
6913 + }
6914 +
6915 + /*
6916 + * Bits 11:12 specify number of _additional_
6917 + * transactions per microframe.
6918 + */
6919 + nr_trans = ((le16_to_cpu(desc->wMaxPacketSize) >> 11) & 3) + 1;
6920 + if (nr_trans > 3)
6921 + return -EINVAL;
6922 +
6923 + ep->is_isoc = 1;
6924 + ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_ISO);
6925 +
6926 + /*
6927 + * Do triple-buffering on high-bandwidth iso endpoints.
6928 + */
6929 + if (nr_trans > 1 && ep->nr_banks == 3)
6930 + ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_TRIPLE);
6931 + else
6932 + ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE);
6933 + ept_cfg |= USBA_BF(NB_TRANS, nr_trans);
6934 + break;
6935 + case USB_ENDPOINT_XFER_BULK:
6936 + ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK);
6937 + ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE);
6938 + break;
6939 + case USB_ENDPOINT_XFER_INT:
6940 + ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_INT);
6941 + ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE);
6942 + break;
6943 + }
6944 +
6945 + spin_lock_irqsave(&ep->udc->lock, flags);
6946 +
6947 + if (ep->desc) {
6948 + spin_unlock_irqrestore(&ep->udc->lock, flags);
6949 + DBG(DBG_ERR, "ep%d already enabled\n", ep->index);
6950 + return -EBUSY;
6951 + }
6952 +
6953 + ep->desc = desc;
6954 + ep->ep.maxpacket = maxpacket;
6955 +
6956 + usba_ep_writel(ep, CFG, ept_cfg);
6957 + usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
6958 +
6959 + if (ep->can_dma) {
6960 + u32 ctrl;
6961 +
6962 + usba_writel(udc, INT_ENB,
6963 + (usba_readl(udc, INT_ENB)
6964 + | USBA_BF(EPT_INT, 1 << ep->index)
6965 + | USBA_BF(DMA_INT, 1 << ep->index)));
6966 + ctrl = USBA_AUTO_VALID | USBA_INTDIS_DMA;
6967 + usba_ep_writel(ep, CTL_ENB, ctrl);
6968 + } else {
6969 + usba_writel(udc, INT_ENB,
6970 + (usba_readl(udc, INT_ENB)
6971 + | USBA_BF(EPT_INT, 1 << ep->index)));
6972 + }
6973 +
6974 + spin_unlock_irqrestore(&udc->lock, flags);
6975 +
6976 + DBG(DBG_HW, "EPT_CFG%d after init: %#08lx\n", ep->index,
6977 + (unsigned long)usba_ep_readl(ep, CFG));
6978 + DBG(DBG_HW, "INT_ENB after init: %#08lx\n",
6979 + (unsigned long)usba_readl(udc, INT_ENB));
6980 +
6981 + return 0;
6982 +}
6983 +
6984 +static int usba_ep_disable(struct usb_ep *_ep)
6985 +{
6986 + struct usba_ep *ep = to_usba_ep(_ep);
6987 + struct usba_udc *udc = ep->udc;
6988 + LIST_HEAD(req_list);
6989 + unsigned long flags;
6990 +
6991 + DBG(DBG_GADGET, "ep_disable: %s\n", ep->ep.name);
6992 +
6993 + spin_lock_irqsave(&udc->lock, flags);
6994 +
6995 + if (!ep->desc) {
6996 + spin_unlock_irqrestore(&udc->lock, flags);
6997 + DBG(DBG_ERR, "ep_disable: %s not enabled\n", ep->ep.name);
6998 + return -EINVAL;
6999 + }
7000 + ep->desc = NULL;
7001 +
7002 + list_splice_init(&ep->queue, &req_list);
7003 + if (ep->can_dma) {
7004 + usba_dma_writel(ep, CONTROL, 0);
7005 + usba_dma_writel(ep, ADDRESS, 0);
7006 + usba_dma_readl(ep, STATUS);
7007 + }
7008 + usba_ep_writel(ep, CTL_DIS, USBA_EPT_ENABLE);
7009 + usba_writel(udc, INT_ENB,
7010 + usba_readl(udc, INT_ENB)
7011 + & ~USBA_BF(EPT_INT, 1 << ep->index));
7012 +
7013 + request_complete_list(ep, &req_list, -ESHUTDOWN);
7014 +
7015 + spin_unlock_irqrestore(&udc->lock, flags);
7016 +
7017 + return 0;
7018 +}
7019 +
7020 +static struct usb_request *
7021 +usba_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
7022 +{
7023 + struct usba_request *req;
7024 +
7025 + DBG(DBG_GADGET, "ep_alloc_request: %p, 0x%x\n", _ep, gfp_flags);
7026 +
7027 + req = kzalloc(sizeof(*req), gfp_flags);
7028 + if (!req)
7029 + return NULL;
7030 +
7031 + INIT_LIST_HEAD(&req->queue);
7032 + req->req.dma = DMA_ADDR_INVALID;
7033 +
7034 + return &req->req;
7035 +}
7036 +
7037 +static void
7038 +usba_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
7039 +{
7040 + struct usba_request *req = to_usba_req(_req);
7041 +
7042 + DBG(DBG_GADGET, "ep_free_request: %p, %p\n", _ep, _req);
7043 +
7044 + kfree(req);
7045 +}
7046 +
7047 +static int queue_dma(struct usba_udc *udc, struct usba_ep *ep,
7048 + struct usba_request *req, gfp_t gfp_flags)
7049 +{
7050 + unsigned long flags;
7051 + int ret;
7052 +
7053 + DBG(DBG_DMA, "%s: req l/%u d/%08x %c%c%c\n",
7054 + ep->ep.name, req->req.length, req->req.dma,
7055 + req->req.zero ? 'Z' : 'z',
7056 + req->req.short_not_ok ? 'S' : 's',
7057 + req->req.no_interrupt ? 'I' : 'i');
7058 +
7059 + if (req->req.length > 0x10000) {
7060 + /* Lengths from 0 to 65536 (inclusive) are supported */
7061 + DBG(DBG_ERR, "invalid request length %u\n", req->req.length);
7062 + return -EINVAL;
7063 + }
7064 +
7065 + req->using_dma = 1;
7066 +
7067 + if (req->req.dma == DMA_ADDR_INVALID) {
7068 + req->req.dma = dma_map_single(
7069 + &udc->pdev->dev, req->req.buf, req->req.length,
7070 + ep->is_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
7071 + req->mapped = 1;
7072 + } else {
7073 + dma_sync_single_for_device(
7074 + &udc->pdev->dev, req->req.dma, req->req.length,
7075 + ep->is_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
7076 + req->mapped = 0;
7077 + }
7078 +
7079 + req->ctrl = USBA_BF(DMA_BUF_LEN, req->req.length)
7080 + | USBA_DMA_CH_EN | USBA_DMA_END_BUF_IE
7081 + | USBA_DMA_END_TR_EN | USBA_DMA_END_TR_IE;
7082 +
7083 + if (ep->is_in)
7084 + req->ctrl |= USBA_DMA_END_BUF_EN;
7085 +
7086 + /*
7087 + * Add this request to the queue and submit for DMA if
7088 + * possible. Check if we're still alive first -- we may have
7089 + * received a reset since last time we checked.
7090 + */
7091 + ret = -ESHUTDOWN;
7092 + spin_lock_irqsave(&udc->lock, flags);
7093 + if (ep->desc) {
7094 + if (list_empty(&ep->queue))
7095 + submit_request(ep, req);
7096 +
7097 + list_add_tail(&req->queue, &ep->queue);
7098 + ret = 0;
7099 + }
7100 + spin_unlock_irqrestore(&udc->lock, flags);
7101 +
7102 + return ret;
7103 +}
7104 +
7105 +static int
7106 +usba_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
7107 +{
7108 + struct usba_request *req = to_usba_req(_req);
7109 + struct usba_ep *ep = to_usba_ep(_ep);
7110 + struct usba_udc *udc = ep->udc;
7111 + unsigned long flags;
7112 + int ret;
7113 +
7114 + DBG(DBG_GADGET | DBG_QUEUE | DBG_REQ, "%s: queue req %p, len %u\n",
7115 + ep->ep.name, req, _req->length);
7116 +
7117 + if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN || !ep->desc)
7118 + return -ESHUTDOWN;
7119 +
7120 + req->submitted = 0;
7121 + req->using_dma = 0;
7122 + req->last_transaction = 0;
7123 +
7124 + _req->status = -EINPROGRESS;
7125 + _req->actual = 0;
7126 +
7127 + if (ep->can_dma)
7128 + return queue_dma(udc, ep, req, gfp_flags);
7129 +
7130 + /* May have received a reset since last time we checked */
7131 + ret = -ESHUTDOWN;
7132 + spin_lock_irqsave(&udc->lock, flags);
7133 + if (ep->desc) {
7134 + list_add_tail(&req->queue, &ep->queue);
7135 +
7136 + if (ep->is_in || (ep_is_control(ep)
7137 + && (ep->state == DATA_STAGE_IN
7138 + || ep->state == STATUS_STAGE_IN)))
7139 + usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
7140 + else
7141 + usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY);
7142 + ret = 0;
7143 + }
7144 + spin_unlock_irqrestore(&udc->lock, flags);
7145 +
7146 + return ret;
7147 +}
7148 +
7149 +static void
7150 +usba_update_req(struct usba_ep *ep, struct usba_request *req, u32 status)
7151 +{
7152 + req->req.actual = req->req.length - USBA_BFEXT(DMA_BUF_LEN, status);
7153 +}
7154 +
7155 +static int stop_dma(struct usba_ep *ep, u32 *pstatus)
7156 +{
7157 + unsigned int timeout;
7158 + u32 status;
7159 +
7160 + /*
7161 + * Stop the DMA controller. When writing both CH_EN
7162 + * and LINK to 0, the other bits are not affected.
7163 + */
7164 + usba_dma_writel(ep, CONTROL, 0);
7165 +
7166 + /* Wait for the FIFO to empty */
7167 + for (timeout = 40; timeout; --timeout) {
7168 + status = usba_dma_readl(ep, STATUS);
7169 + if (!(status & USBA_DMA_CH_EN))
7170 + break;
7171 + udelay(1);
7172 + }
7173 +
7174 + if (pstatus)
7175 + *pstatus = status;
7176 +
7177 + if (timeout == 0) {
7178 + dev_err(&ep->udc->pdev->dev,
7179 + "%s: timed out waiting for DMA FIFO to empty\n",
7180 + ep->ep.name);
7181 + return -ETIMEDOUT;
7182 + }
7183 +
7184 + return 0;
7185 +}
7186 +
7187 +static int usba_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
7188 +{
7189 + struct usba_ep *ep = to_usba_ep(_ep);
7190 + struct usba_udc *udc = ep->udc;
7191 + struct usba_request *req = to_usba_req(_req);
7192 + unsigned long flags;
7193 + u32 status;
7194 +
7195 + DBG(DBG_GADGET | DBG_QUEUE, "ep_dequeue: %s, req %p\n",
7196 + ep->ep.name, req);
7197 +
7198 + spin_lock_irqsave(&udc->lock, flags);
7199 +
7200 + if (req->using_dma) {
7201 + /*
7202 + * If this request is currently being transferred,
7203 + * stop the DMA controller and reset the FIFO.
7204 + */
7205 + if (ep->queue.next == &req->queue) {
7206 + status = usba_dma_readl(ep, STATUS);
7207 + if (status & USBA_DMA_CH_EN)
7208 + stop_dma(ep, &status);
7209 +
7210 +#ifdef CONFIG_USB_GADGET_DEBUG_FS
7211 + ep->last_dma_status = status;
7212 +#endif
7213 +
7214 + usba_writel(udc, EPT_RST, 1 << ep->index);
7215 +
7216 + usba_update_req(ep, req, status);
7217 + }
7218 + }
7219 +
7220 + /*
7221 + * Errors should stop the queue from advancing until the
7222 + * completion function returns.
7223 + */
7224 + list_del_init(&req->queue);
7225 +
7226 + request_complete(ep, req, -ECONNRESET);
7227 +
7228 + /* Process the next request if any */
7229 + submit_next_request(ep);
7230 + spin_unlock_irqrestore(&udc->lock, flags);
7231 +
7232 + return 0;
7233 +}
7234 +
7235 +static int usba_ep_set_halt(struct usb_ep *_ep, int value)
7236 +{
7237 + struct usba_ep *ep = to_usba_ep(_ep);
7238 + struct usba_udc *udc = ep->udc;
7239 + unsigned long flags;
7240 + int ret = 0;
7241 +
7242 + DBG(DBG_GADGET, "endpoint %s: %s HALT\n", ep->ep.name,
7243 + value ? "set" : "clear");
7244 +
7245 + if (!ep->desc) {
7246 + DBG(DBG_ERR, "Attempted to halt uninitialized ep %s\n",
7247 + ep->ep.name);
7248 + return -ENODEV;
7249 + }
7250 + if (ep->is_isoc) {
7251 + DBG(DBG_ERR, "Attempted to halt isochronous ep %s\n",
7252 + ep->ep.name);
7253 + return -ENOTTY;
7254 + }
7255 +
7256 + spin_lock_irqsave(&udc->lock, flags);
7257 +
7258 + /*
7259 + * We can't halt IN endpoints while there are still data to be
7260 + * transferred
7261 + */
7262 + if (!list_empty(&ep->queue)
7263 + || ((value && ep->is_in && (usba_ep_readl(ep, STA)
7264 + & USBA_BF(BUSY_BANKS, -1L))))) {
7265 + ret = -EAGAIN;
7266 + } else {
7267 + if (value)
7268 + usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL);
7269 + else
7270 + usba_ep_writel(ep, CLR_STA,
7271 + USBA_FORCE_STALL | USBA_TOGGLE_CLR);
7272 + usba_ep_readl(ep, STA);
7273 + }
7274 +
7275 + spin_unlock_irqrestore(&udc->lock, flags);
7276 +
7277 + return ret;
7278 +}
7279 +
7280 +static int usba_ep_fifo_status(struct usb_ep *_ep)
7281 +{
7282 + struct usba_ep *ep = to_usba_ep(_ep);
7283 +
7284 + return USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
7285 +}
7286 +
7287 +static void usba_ep_fifo_flush(struct usb_ep *_ep)
7288 +{
7289 + struct usba_ep *ep = to_usba_ep(_ep);
7290 + struct usba_udc *udc = ep->udc;
7291 +
7292 + usba_writel(udc, EPT_RST, 1 << ep->index);
7293 +}
7294 +
7295 +static const struct usb_ep_ops usba_ep_ops = {
7296 + .enable = usba_ep_enable,
7297 + .disable = usba_ep_disable,
7298 + .alloc_request = usba_ep_alloc_request,
7299 + .free_request = usba_ep_free_request,
7300 + .queue = usba_ep_queue,
7301 + .dequeue = usba_ep_dequeue,
7302 + .set_halt = usba_ep_set_halt,
7303 + .fifo_status = usba_ep_fifo_status,
7304 + .fifo_flush = usba_ep_fifo_flush,
7305 +};
7306 +
7307 +static int usba_udc_get_frame(struct usb_gadget *gadget)
7308 +{
7309 + struct usba_udc *udc = to_usba_udc(gadget);
7310 +
7311 + return USBA_BFEXT(FRAME_NUMBER, usba_readl(udc, FNUM));
7312 +}
7313 +
7314 +static const struct usb_gadget_ops usba_udc_ops = {
7315 + .get_frame = usba_udc_get_frame,
7316 +};
7317 +
7318 +#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
7319 +{ \
7320 + .ep = { \
7321 + .ops = &usba_ep_ops, \
7322 + .name = nam, \
7323 + .maxpacket = maxpkt, \
7324 + }, \
7325 + .udc = &the_udc, \
7326 + .queue = LIST_HEAD_INIT(usba_ep[idx].queue), \
7327 + .fifo_size = maxpkt, \
7328 + .nr_banks = maxbk, \
7329 + .index = idx, \
7330 + .can_dma = dma, \
7331 + .can_isoc = isoc, \
7332 +}
7333 +
7334 +static struct usba_ep usba_ep[] = {
7335 + EP("ep0", 0, 64, 1, 0, 0),
7336 + EP("ep1in-bulk", 1, 512, 2, 1, 1),
7337 + EP("ep2out-bulk", 2, 512, 2, 1, 1),
7338 + EP("ep3in-int", 3, 64, 3, 1, 0),
7339 + EP("ep4out-int", 4, 64, 3, 1, 0),
7340 + EP("ep5in-iso", 5, 1024, 3, 1, 1),
7341 + EP("ep6out-iso", 6, 1024, 3, 1, 1),
7342 +};
7343 +#undef EP
7344 +
7345 +static struct usb_endpoint_descriptor usba_ep0_desc = {
7346 + .bLength = USB_DT_ENDPOINT_SIZE,
7347 + .bDescriptorType = USB_DT_ENDPOINT,
7348 + .bEndpointAddress = 0,
7349 + .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
7350 + .wMaxPacketSize = __constant_cpu_to_le16(64),
7351 + /* FIXME: I have no idea what to put here */
7352 + .bInterval = 1,
7353 +};
7354 +
7355 +static void nop_release(struct device *dev)
7356 +{
7357 +
7358 +}
7359 +
7360 +static struct usba_udc the_udc = {
7361 + .gadget = {
7362 + .ops = &usba_udc_ops,
7363 + .ep0 = &usba_ep[0].ep,
7364 + .ep_list = LIST_HEAD_INIT(the_udc.gadget.ep_list),
7365 + .is_dualspeed = 1,
7366 + .name = "atmel_usba_udc",
7367 + .dev = {
7368 + .bus_id = "gadget",
7369 + .release = nop_release,
7370 + },
7371 + },
7372 +
7373 + .lock = SPIN_LOCK_UNLOCKED,
7374 +};
7375 +
7376 +/*
7377 + * Called with interrupts disabled and udc->lock held.
7378 + */
7379 +static void reset_all_endpoints(struct usba_udc *udc)
7380 +{
7381 + struct usba_ep *ep;
7382 + struct usba_request *req, *tmp_req;
7383 +
7384 + usba_writel(udc, EPT_RST, ~0UL);
7385 +
7386 + ep = to_usba_ep(udc->gadget.ep0);
7387 + list_for_each_entry_safe(req, tmp_req, &ep->queue, queue) {
7388 + list_del_init(&req->queue);
7389 + request_complete(ep, req, -ECONNRESET);
7390 + }
7391 +
7392 + list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
7393 + if (ep->desc)
7394 + usba_ep_disable(&ep->ep);
7395 + }
7396 +}
7397 +
7398 +static struct usba_ep *get_ep_by_addr(struct usba_udc *udc, u16 wIndex)
7399 +{
7400 + struct usba_ep *ep;
7401 +
7402 + if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
7403 + return to_usba_ep(udc->gadget.ep0);
7404 +
7405 + list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
7406 + u8 bEndpointAddress;
7407 +
7408 + if (!ep->desc)
7409 + continue;
7410 + bEndpointAddress = ep->desc->bEndpointAddress;
7411 + if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
7412 + continue;
7413 + if ((bEndpointAddress & USB_ENDPOINT_NUMBER_MASK)
7414 + == (wIndex & USB_ENDPOINT_NUMBER_MASK))
7415 + return ep;
7416 + }
7417 +
7418 + return NULL;
7419 +}
7420 +
7421 +/* Called with interrupts disabled and udc->lock held */
7422 +static inline void set_protocol_stall(struct usba_udc *udc, struct usba_ep *ep)
7423 +{
7424 + usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL);
7425 + ep->state = WAIT_FOR_SETUP;
7426 +}
7427 +
7428 +static inline int is_stalled(struct usba_udc *udc, struct usba_ep *ep)
7429 +{
7430 + if (usba_ep_readl(ep, STA) & USBA_FORCE_STALL)
7431 + return 1;
7432 + return 0;
7433 +}
7434 +
7435 +static inline void set_address(struct usba_udc *udc, unsigned int addr)
7436 +{
7437 + u32 regval;
7438 +
7439 + DBG(DBG_BUS, "setting address %u...\n", addr);
7440 + regval = usba_readl(udc, CTRL);
7441 + regval = USBA_BFINS(DEV_ADDR, addr, regval);
7442 + usba_writel(udc, CTRL, regval);
7443 +}
7444 +
7445 +static int do_test_mode(struct usba_udc *udc)
7446 +{
7447 + static const char test_packet_buffer[] = {
7448 + /* JKJKJKJK * 9 */
7449 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7450 + /* JJKKJJKK * 8 */
7451 + 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
7452 + /* JJKKJJKK * 8 */
7453 + 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
7454 + /* JJJJJJJKKKKKKK * 8 */
7455 + 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
7456 + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
7457 + /* JJJJJJJK * 8 */
7458 + 0x7F, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD,
7459 + /* {JKKKKKKK * 10}, JK */
7460 + 0xFC, 0x7E, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD, 0x7E
7461 + };
7462 + struct usba_ep *ep;
7463 + struct device *dev = &udc->pdev->dev;
7464 + int test_mode;
7465 +
7466 + test_mode = udc->test_mode;
7467 +
7468 + /* Start from a clean slate */
7469 + reset_all_endpoints(udc);
7470 +
7471 + switch (test_mode) {
7472 + case 0x0100:
7473 + /* Test_J */
7474 + usba_writel(udc, TST, USBA_TST_J_MODE);
7475 + dev_info(dev, "Entering Test_J mode...\n");
7476 + break;
7477 + case 0x0200:
7478 + /* Test_K */
7479 + usba_writel(udc, TST, USBA_TST_K_MODE);
7480 + dev_info(dev, "Entering Test_K mode...\n");
7481 + break;
7482 + case 0x0300:
7483 + /*
7484 + * Test_SE0_NAK: Force high-speed mode and set up ep0
7485 + * for Bulk IN transfers
7486 + */
7487 + ep = &usba_ep[0];
7488 + usba_writel(udc, TST,
7489 + USBA_BF(SPEED_CFG, USBA_SPEED_CFG_FORCE_HIGH));
7490 + usba_ep_writel(ep, CFG,
7491 + USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
7492 + | USBA_EPT_DIR_IN
7493 + | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
7494 + | USBA_BF(BK_NUMBER, 1));
7495 + if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) {
7496 + set_protocol_stall(udc, ep);
7497 + dev_err(dev, "Test_SE0_NAK: ep0 not mapped\n");
7498 + } else {
7499 + usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
7500 + dev_info(dev, "Entering Test_SE0_NAK mode...\n");
7501 + }
7502 + break;
7503 + case 0x0400:
7504 + /* Test_Packet */
7505 + ep = &usba_ep[0];
7506 + usba_ep_writel(ep, CFG,
7507 + USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
7508 + | USBA_EPT_DIR_IN
7509 + | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
7510 + | USBA_BF(BK_NUMBER, 1));
7511 + if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) {
7512 + set_protocol_stall(udc, ep);
7513 + dev_err(dev, "Test_Packet: ep0 not mapped\n");
7514 + } else {
7515 + usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
7516 + usba_writel(udc, TST, USBA_TST_PKT_MODE);
7517 + copy_to_fifo(ep->fifo, test_packet_buffer,
7518 + sizeof(test_packet_buffer));
7519 + usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
7520 + dev_info(dev, "Entering Test_Packet mode...\n");
7521 + }
7522 + break;
7523 + default:
7524 + dev_err(dev, "Invalid test mode: 0x%04x\n", test_mode);
7525 + return -EINVAL;
7526 + }
7527 +
7528 + return 0;
7529 +}
7530 +
7531 +/* Avoid overly long expressions */
7532 +static inline bool feature_is_dev_remote_wakeup(struct usb_ctrlrequest *crq)
7533 +{
7534 + if (crq->wValue == __constant_cpu_to_le16(USB_DEVICE_REMOTE_WAKEUP))
7535 + return true;
7536 + return false;
7537 +}
7538 +
7539 +static inline bool feature_is_dev_test_mode(struct usb_ctrlrequest *crq)
7540 +{
7541 + if (crq->wValue == __constant_cpu_to_le16(USB_DEVICE_TEST_MODE))
7542 + return true;
7543 + return false;
7544 +}
7545 +
7546 +static inline bool feature_is_ep_halt(struct usb_ctrlrequest *crq)
7547 +{
7548 + if (crq->wValue == __constant_cpu_to_le16(USB_ENDPOINT_HALT))
7549 + return true;
7550 + return false;
7551 +}
7552 +
7553 +static int handle_ep0_setup(struct usba_udc *udc, struct usba_ep *ep,
7554 + struct usb_ctrlrequest *crq)
7555 +{
7556 + int retval = 0;;
7557 +
7558 + switch (crq->bRequest) {
7559 + case USB_REQ_GET_STATUS: {
7560 + u16 status;
7561 +
7562 + if (crq->bRequestType == (USB_DIR_IN | USB_RECIP_DEVICE)) {
7563 + /* Self-powered, no remote wakeup */
7564 + status = __constant_cpu_to_le16(1 << 0);
7565 + } else if (crq->bRequestType
7566 + == (USB_DIR_IN | USB_RECIP_INTERFACE)) {
7567 + status = __constant_cpu_to_le16(0);
7568 + } else if (crq->bRequestType
7569 + == (USB_DIR_IN | USB_RECIP_ENDPOINT)) {
7570 + struct usba_ep *target;
7571 +
7572 + target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
7573 + if (!target)
7574 + goto stall;
7575 +
7576 + status = 0;
7577 + if (is_stalled(udc, target))
7578 + status |= __constant_cpu_to_le16(1);
7579 + } else
7580 + goto delegate;
7581 +
7582 + /* Write directly to the FIFO. No queueing is done. */
7583 + if (crq->wLength != __constant_cpu_to_le16(sizeof(status)))
7584 + goto stall;
7585 + ep->state = DATA_STAGE_IN;
7586 + __raw_writew(status, ep->fifo);
7587 + usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
7588 + break;
7589 + }
7590 +
7591 + case USB_REQ_CLEAR_FEATURE: {
7592 + if (crq->bRequestType == USB_RECIP_DEVICE) {
7593 + if (feature_is_dev_remote_wakeup(crq)) {
7594 + /* TODO: Handle REMOTE_WAKEUP */
7595 + } else {
7596 + /* Can't CLEAR_FEATURE TEST_MODE */
7597 + goto stall;
7598 + }
7599 + } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
7600 + struct usba_ep *target;
7601 +
7602 + if (crq->wLength != __constant_cpu_to_le16(0)
7603 + || !feature_is_ep_halt(crq))
7604 + goto stall;
7605 + target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
7606 + if (!target)
7607 + goto stall;
7608 +
7609 + usba_ep_writel(target, CLR_STA, USBA_FORCE_STALL);
7610 + if (target->index != 0)
7611 + usba_ep_writel(target, CLR_STA,
7612 + USBA_TOGGLE_CLR);
7613 + } else {
7614 + goto delegate;
7615 + }
7616 +
7617 + send_status(udc, ep);
7618 + break;
7619 + }
7620 +
7621 + case USB_REQ_SET_FEATURE: {
7622 + if (crq->bRequestType == USB_RECIP_DEVICE) {
7623 + if (feature_is_dev_test_mode(crq)) {
7624 + send_status(udc, ep);
7625 + ep->state = STATUS_STAGE_TEST;
7626 + udc->test_mode = le16_to_cpu(crq->wIndex);
7627 + return 0;
7628 + } else if (feature_is_dev_remote_wakeup(crq)) {
7629 + /* TODO: Handle REMOTE_WAKEUP */
7630 + } else {
7631 + goto stall;
7632 + }
7633 + } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
7634 + struct usba_ep *target;
7635 +
7636 + if (crq->wLength != __constant_cpu_to_le16(0)
7637 + || !feature_is_ep_halt(crq))
7638 + goto stall;
7639 +
7640 + target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
7641 + if (!target)
7642 + goto stall;
7643 +
7644 + usba_ep_writel(target, SET_STA, USBA_FORCE_STALL);
7645 + } else
7646 + goto delegate;
7647 +
7648 + send_status(udc, ep);
7649 + break;
7650 + }
7651 +
7652 + case USB_REQ_SET_ADDRESS:
7653 + if (crq->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE))
7654 + goto delegate;
7655 +
7656 + set_address(udc, le16_to_cpu(crq->wValue));
7657 + send_status(udc, ep);
7658 + ep->state = STATUS_STAGE_ADDR;
7659 + break;
7660 +
7661 + default:
7662 +delegate:
7663 + spin_unlock(&udc->lock);
7664 + retval = udc->driver->setup(&udc->gadget, crq);
7665 + spin_lock(&udc->lock);
7666 + }
7667 +
7668 + return retval;
7669 +
7670 +stall:
7671 + printk(KERN_ERR
7672 + "udc: %s: Invalid setup request: %02x.%02x v%04x i%04x l%d, "
7673 + "halting endpoint...\n",
7674 + ep->ep.name, crq->bRequestType, crq->bRequest,
7675 + le16_to_cpu(crq->wValue), le16_to_cpu(crq->wIndex),
7676 + le16_to_cpu(crq->wLength));
7677 + set_protocol_stall(udc, ep);
7678 + return -1;
7679 +}
7680 +
7681 +static void usba_control_irq(struct usba_udc *udc, struct usba_ep *ep)
7682 +{
7683 + struct usba_request *req;
7684 + u32 epstatus;
7685 + u32 epctrl;
7686 +
7687 +restart:
7688 + epstatus = usba_ep_readl(ep, STA);
7689 + epctrl = usba_ep_readl(ep, CTL);
7690 +
7691 + DBG(DBG_INT, "%s [%d]: s/%08x c/%08x\n",
7692 + ep->ep.name, ep->state, epstatus, epctrl);
7693 +
7694 + req = NULL;
7695 + if (!list_empty(&ep->queue))
7696 + req = list_entry(ep->queue.next,
7697 + struct usba_request, queue);
7698 +
7699 + if ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) {
7700 + if (req->submitted)
7701 + next_fifo_transaction(ep, req);
7702 + else
7703 + submit_request(ep, req);
7704 +
7705 + if (req->last_transaction) {
7706 + usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
7707 + usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
7708 + }
7709 + goto restart;
7710 + }
7711 + if ((epstatus & epctrl) & USBA_TX_COMPLETE) {
7712 + usba_ep_writel(ep, CLR_STA, USBA_TX_COMPLETE);
7713 +
7714 + switch (ep->state) {
7715 + case DATA_STAGE_IN:
7716 + usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY);
7717 + usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
7718 + ep->state = STATUS_STAGE_OUT;
7719 + break;
7720 + case STATUS_STAGE_ADDR:
7721 + /* Activate our new address */
7722 + usba_writel(udc, CTRL, (usba_readl(udc, CTRL)
7723 + | USBA_FADDR_EN));
7724 + usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
7725 + ep->state = WAIT_FOR_SETUP;
7726 + break;
7727 + case STATUS_STAGE_IN:
7728 + if (req) {
7729 + list_del_init(&req->queue);
7730 + request_complete(ep, req, 0);
7731 + submit_next_request(ep);
7732 + }
7733 + usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
7734 + ep->state = WAIT_FOR_SETUP;
7735 + break;
7736 + case STATUS_STAGE_TEST:
7737 + usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
7738 + ep->state = WAIT_FOR_SETUP;
7739 + if (do_test_mode(udc))
7740 + set_protocol_stall(udc, ep);
7741 + break;
7742 + default:
7743 + printk(KERN_ERR
7744 + "udc: %s: TXCOMP: Invalid endpoint state %d, "
7745 + "halting endpoint...\n",
7746 + ep->ep.name, ep->state);
7747 + set_protocol_stall(udc, ep);
7748 + break;
7749 + }
7750 +
7751 + goto restart;
7752 + }
7753 + if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
7754 + switch (ep->state) {
7755 + case STATUS_STAGE_OUT:
7756 + usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
7757 + usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
7758 +
7759 + if (req) {
7760 + list_del_init(&req->queue);
7761 + request_complete(ep, req, 0);
7762 + }
7763 + ep->state = WAIT_FOR_SETUP;
7764 + break;
7765 +
7766 + case DATA_STAGE_OUT:
7767 + receive_data(ep);
7768 + break;
7769 +
7770 + default:
7771 + usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
7772 + usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
7773 + printk(KERN_ERR
7774 + "udc: %s: RXRDY: Invalid endpoint state %d, "
7775 + "halting endpoint...\n",
7776 + ep->ep.name, ep->state);
7777 + set_protocol_stall(udc, ep);
7778 + break;
7779 + }
7780 +
7781 + goto restart;
7782 + }
7783 + if (epstatus & USBA_RX_SETUP) {
7784 + union {
7785 + struct usb_ctrlrequest crq;
7786 + unsigned long data[2];
7787 + } crq;
7788 + unsigned int pkt_len;
7789 + int ret;
7790 +
7791 + if (ep->state != WAIT_FOR_SETUP) {
7792 + /*
7793 + * Didn't expect a SETUP packet at this
7794 + * point. Clean up any pending requests (which
7795 + * may be successful).
7796 + */
7797 + int status = -EPROTO;
7798 +
7799 + /*
7800 + * RXRDY and TXCOMP are dropped when SETUP
7801 + * packets arrive. Just pretend we received
7802 + * the status packet.
7803 + */
7804 + if (ep->state == STATUS_STAGE_OUT
7805 + || ep->state == STATUS_STAGE_IN) {
7806 + usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
7807 + status = 0;
7808 + }
7809 +
7810 + if (req) {
7811 + list_del_init(&req->queue);
7812 + request_complete(ep, req, status);
7813 + }
7814 + }
7815 +
7816 + pkt_len = USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
7817 + DBG(DBG_HW, "Packet length: %u\n", pkt_len);
7818 + if (pkt_len != sizeof(crq)) {
7819 + printk(KERN_WARNING "udc: Invalid packet length %u "
7820 + "(expected %lu)\n", pkt_len, sizeof(crq));
7821 + set_protocol_stall(udc, ep);
7822 + return;
7823 + }
7824 +
7825 + DBG(DBG_FIFO, "Copying ctrl request from 0x%p:\n", ep->fifo);
7826 + copy_from_fifo(crq.data, ep->fifo, sizeof(crq));
7827 +
7828 + /* Free up one bank in the FIFO so that we can
7829 + * generate or receive a reply right away. */
7830 + usba_ep_writel(ep, CLR_STA, USBA_RX_SETUP);
7831 +
7832 + /* printk(KERN_DEBUG "setup: %d: %02x.%02x\n",
7833 + ep->state, crq.crq.bRequestType,
7834 + crq.crq.bRequest); */
7835 +
7836 + if (crq.crq.bRequestType & USB_DIR_IN) {
7837 + /*
7838 + * The USB 2.0 spec states that "if wLength is
7839 + * zero, there is no data transfer phase."
7840 + * However, testusb #14 seems to actually
7841 + * expect a data phase even if wLength = 0...
7842 + */
7843 + ep->state = DATA_STAGE_IN;
7844 + } else {
7845 + if (crq.crq.wLength != __constant_cpu_to_le16(0))
7846 + ep->state = DATA_STAGE_OUT;
7847 + else
7848 + ep->state = STATUS_STAGE_IN;
7849 + }
7850 +
7851 + ret = -1;
7852 + if (ep->index == 0)
7853 + ret = handle_ep0_setup(udc, ep, &crq.crq);
7854 + else {
7855 + spin_unlock(&udc->lock);
7856 + ret = udc->driver->setup(&udc->gadget, &crq.crq);
7857 + spin_lock(&udc->lock);
7858 + }
7859 +
7860 + DBG(DBG_BUS, "req %02x.%02x, length %d, state %d, ret %d\n",
7861 + crq.crq.bRequestType, crq.crq.bRequest,
7862 + le16_to_cpu(crq.crq.wLength), ep->state, ret);
7863 +
7864 + if (ret < 0) {
7865 + /* Let the host know that we failed */
7866 + set_protocol_stall(udc, ep);
7867 + }
7868 + }
7869 +}
7870 +
7871 +static void usba_ep_irq(struct usba_udc *udc, struct usba_ep *ep)
7872 +{
7873 + struct usba_request *req;
7874 + u32 epstatus;
7875 + u32 epctrl;
7876 +
7877 + epstatus = usba_ep_readl(ep, STA);
7878 + epctrl = usba_ep_readl(ep, CTL);
7879 +
7880 + DBG(DBG_INT, "%s: interrupt, status: 0x%08x\n", ep->ep.name, epstatus);
7881 +
7882 + while ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) {
7883 + DBG(DBG_BUS, "%s: TX PK ready\n", ep->ep.name);
7884 +
7885 + if (list_empty(&ep->queue)) {
7886 + dev_warn(&udc->pdev->dev, "ep_irq: queue empty\n");
7887 + usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
7888 + return;
7889 + }
7890 +
7891 + req = list_entry(ep->queue.next, struct usba_request, queue);
7892 +
7893 + if (req->using_dma) {
7894 + /* Send a zero-length packet */
7895 + usba_ep_writel(ep, SET_STA,
7896 + USBA_TX_PK_RDY);
7897 + usba_ep_writel(ep, CTL_DIS,
7898 + USBA_TX_PK_RDY);
7899 + list_del_init(&req->queue);
7900 + submit_next_request(ep);
7901 + request_complete(ep, req, 0);
7902 + } else {
7903 + if (req->submitted)
7904 + next_fifo_transaction(ep, req);
7905 + else
7906 + submit_request(ep, req);
7907 +
7908 + if (req->last_transaction) {
7909 + list_del_init(&req->queue);
7910 + submit_next_request(ep);
7911 + request_complete(ep, req, 0);
7912 + }
7913 + }
7914 +
7915 + epstatus = usba_ep_readl(ep, STA);
7916 + epctrl = usba_ep_readl(ep, CTL);
7917 + }
7918 + if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
7919 + DBG(DBG_BUS, "%s: RX data ready\n", ep->ep.name);
7920 + receive_data(ep);
7921 + usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
7922 + }
7923 +}
7924 +
7925 +static void usba_dma_irq(struct usba_udc *udc, struct usba_ep *ep)
7926 +{
7927 + struct usba_request *req;
7928 + u32 status, control, pending;
7929 +
7930 + status = usba_dma_readl(ep, STATUS);
7931 + control = usba_dma_readl(ep, CONTROL);
7932 +#ifdef CONFIG_USB_GADGET_DEBUG_FS
7933 + ep->last_dma_status = status;
7934 +#endif
7935 + pending = status & control;
7936 + DBG(DBG_INT | DBG_DMA, "dma irq, s/%#08x, c/%#08x\n", status, control);
7937 +
7938 + if (status & USBA_DMA_CH_EN) {
7939 + dev_err(&udc->pdev->dev,
7940 + "DMA_CH_EN is set after transfer is finished!\n");
7941 + dev_err(&udc->pdev->dev,
7942 + "status=%#08x, pending=%#08x, control=%#08x\n",
7943 + status, pending, control);
7944 +
7945 + /*
7946 + * try to pretend nothing happened. We might have to
7947 + * do something here...
7948 + */
7949 + }
7950 +
7951 + if (list_empty(&ep->queue))
7952 + /* Might happen if a reset comes along at the right moment */
7953 + return;
7954 +
7955 + if (pending & (USBA_DMA_END_TR_ST | USBA_DMA_END_BUF_ST)) {
7956 + req = list_entry(ep->queue.next, struct usba_request, queue);
7957 + usba_update_req(ep, req, status);
7958 +
7959 + list_del_init(&req->queue);
7960 + submit_next_request(ep);
7961 + request_complete(ep, req, 0);
7962 + }
7963 +}
7964 +
7965 +static irqreturn_t usba_udc_irq(int irq, void *devid)
7966 +{
7967 + struct usba_udc *udc = devid;
7968 + u32 status;
7969 + u32 dma_status;
7970 + u32 ep_status;
7971 +
7972 + spin_lock(&udc->lock);
7973 +
7974 + status = usba_readl(udc, INT_STA);
7975 + DBG(DBG_INT, "irq, status=%#08x\n", status);
7976 +
7977 + if (status & USBA_DET_SUSPEND) {
7978 + usba_writel(udc, INT_CLR, USBA_DET_SUSPEND);
7979 + DBG(DBG_BUS, "Suspend detected\n");
7980 + if (udc->gadget.speed != USB_SPEED_UNKNOWN
7981 + && udc->driver && udc->driver->suspend) {
7982 + spin_unlock(&udc->lock);
7983 + udc->driver->suspend(&udc->gadget);
7984 + spin_lock(&udc->lock);
7985 + }
7986 + }
7987 +
7988 + if (status & USBA_WAKE_UP) {
7989 + usba_writel(udc, INT_CLR, USBA_WAKE_UP);
7990 + DBG(DBG_BUS, "Wake Up CPU detected\n");
7991 + }
7992 +
7993 + if (status & USBA_END_OF_RESUME) {
7994 + usba_writel(udc, INT_CLR, USBA_END_OF_RESUME);
7995 + DBG(DBG_BUS, "Resume detected\n");
7996 + if (udc->gadget.speed != USB_SPEED_UNKNOWN
7997 + && udc->driver && udc->driver->resume) {
7998 + spin_unlock(&udc->lock);
7999 + udc->driver->resume(&udc->gadget);
8000 + spin_lock(&udc->lock);
8001 + }
8002 + }
8003 +
8004 + dma_status = USBA_BFEXT(DMA_INT, status);
8005 + if (dma_status) {
8006 + int i;
8007 +
8008 + for (i = 1; i < USBA_NR_ENDPOINTS; i++)
8009 + if (dma_status & (1 << i))
8010 + usba_dma_irq(udc, &usba_ep[i]);
8011 + }
8012 +
8013 + ep_status = USBA_BFEXT(EPT_INT, status);
8014 + if (ep_status) {
8015 + int i;
8016 +
8017 + for (i = 0; i < USBA_NR_ENDPOINTS; i++)
8018 + if (ep_status & (1 << i)) {
8019 + if (ep_is_control(&usba_ep[i]))
8020 + usba_control_irq(udc, &usba_ep[i]);
8021 + else
8022 + usba_ep_irq(udc, &usba_ep[i]);
8023 + }
8024 + }
8025 +
8026 + if (status & USBA_END_OF_RESET) {
8027 + struct usba_ep *ep0;
8028 +
8029 + usba_writel(udc, INT_CLR, USBA_END_OF_RESET);
8030 + reset_all_endpoints(udc);
8031 +
8032 + if (status & USBA_HIGH_SPEED) {
8033 + DBG(DBG_BUS, "High-speed bus reset detected\n");
8034 + udc->gadget.speed = USB_SPEED_HIGH;
8035 + } else {
8036 + DBG(DBG_BUS, "Full-speed bus reset detected\n");
8037 + udc->gadget.speed = USB_SPEED_FULL;
8038 + }
8039 +
8040 + ep0 = &usba_ep[0];
8041 + ep0->desc = &usba_ep0_desc;
8042 + ep0->state = WAIT_FOR_SETUP;
8043 + usba_ep_writel(ep0, CFG,
8044 + (USBA_BF(EPT_SIZE, EP0_EPT_SIZE)
8045 + | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL)
8046 + | USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE)));
8047 + usba_ep_writel(ep0, CTL_ENB,
8048 + USBA_EPT_ENABLE | USBA_RX_SETUP);
8049 + usba_writel(udc, INT_ENB,
8050 + (usba_readl(udc, INT_ENB)
8051 + | USBA_BF(EPT_INT, 1)
8052 + | USBA_DET_SUSPEND
8053 + | USBA_END_OF_RESUME));
8054 +
8055 + if (!(usba_ep_readl(ep0, CFG) & USBA_EPT_MAPPED))
8056 + dev_warn(&udc->pdev->dev,
8057 + "WARNING: EP0 configuration is invalid!\n");
8058 + }
8059 +
8060 + spin_unlock(&udc->lock);
8061 +
8062 + return IRQ_HANDLED;
8063 +}
8064 +
8065 +static irqreturn_t usba_vbus_irq(int irq, void *devid)
8066 +{
8067 + struct usba_udc *udc = devid;
8068 + int vbus;
8069 +
8070 + /* debounce */
8071 + udelay(10);
8072 +
8073 + spin_lock(&udc->lock);
8074 +
8075 + /* May happen if Vbus pin toggles during probe() */
8076 + if (!udc->driver)
8077 + goto out;
8078 +
8079 + vbus = gpio_get_value(udc->vbus_pin);
8080 + if (vbus != udc->vbus_prev) {
8081 + if (vbus) {
8082 + usba_writel(udc, CTRL, USBA_EN_USBA);
8083 + usba_writel(udc, INT_ENB, USBA_END_OF_RESET);
8084 + } else {
8085 + udc->gadget.speed = USB_SPEED_UNKNOWN;
8086 + reset_all_endpoints(udc);
8087 + usba_writel(udc, CTRL, 0);
8088 + spin_unlock(&udc->lock);
8089 + udc->driver->disconnect(&udc->gadget);
8090 + spin_lock(&udc->lock);
8091 + }
8092 + udc->vbus_prev = vbus;
8093 + }
8094 +
8095 +out:
8096 + spin_unlock(&udc->lock);
8097 +
8098 + return IRQ_HANDLED;
8099 +}
8100 +
8101 +int usb_gadget_register_driver(struct usb_gadget_driver *driver)
8102 +{
8103 + struct usba_udc *udc = &the_udc;
8104 + unsigned long flags;
8105 + int ret;
8106 +
8107 + if (!udc->pdev)
8108 + return -ENODEV;
8109 +
8110 + spin_lock_irqsave(&udc->lock, flags);
8111 + if (udc->driver) {
8112 + spin_unlock_irqrestore(&udc->lock, flags);
8113 + return -EBUSY;
8114 + }
8115 +
8116 + udc->driver = driver;
8117 + udc->gadget.dev.driver = &driver->driver;
8118 + spin_unlock_irqrestore(&udc->lock, flags);
8119 +
8120 + clk_enable(udc->pclk);
8121 + clk_enable(udc->hclk);
8122 +
8123 + ret = driver->bind(&udc->gadget);
8124 + if (ret) {
8125 + DBG(DBG_ERR, "Could not bind to driver %s: error %d\n",
8126 + driver->driver.name, ret);
8127 + goto err_driver_bind;
8128 + }
8129 +
8130 + DBG(DBG_GADGET, "registered driver `%s'\n", driver->driver.name);
8131 +
8132 + udc->vbus_prev = 0;
8133 + if (udc->vbus_pin != -1)
8134 + enable_irq(gpio_to_irq(udc->vbus_pin));
8135 +
8136 + /* If Vbus is present, enable the controller and wait for reset */
8137 + spin_lock_irqsave(&udc->lock, flags);
8138 + if (vbus_is_present(udc) && udc->vbus_prev == 0) {
8139 + usba_writel(udc, CTRL, USBA_EN_USBA);
8140 + usba_writel(udc, INT_ENB, USBA_END_OF_RESET);
8141 + }
8142 + spin_unlock_irqrestore(&udc->lock, flags);
8143 +
8144 + return 0;
8145 +
8146 +err_driver_bind:
8147 + udc->driver = NULL;
8148 + udc->gadget.dev.driver = NULL;
8149 + return ret;
8150 +}
8151 +EXPORT_SYMBOL(usb_gadget_register_driver);
8152 +
8153 +int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
8154 +{
8155 + struct usba_udc *udc = &the_udc;
8156 + unsigned long flags;
8157 +
8158 + if (!udc->pdev)
8159 + return -ENODEV;
8160 + if (driver != udc->driver)
8161 + return -EINVAL;
8162 +
8163 + if (udc->vbus_pin != -1)
8164 + disable_irq(gpio_to_irq(udc->vbus_pin));
8165 +
8166 + spin_lock_irqsave(&udc->lock, flags);
8167 + udc->gadget.speed = USB_SPEED_UNKNOWN;
8168 + reset_all_endpoints(udc);
8169 + spin_unlock_irqrestore(&udc->lock, flags);
8170 +
8171 + /* This will also disable the DP pullup */
8172 + usba_writel(udc, CTRL, 0);
8173 +
8174 + driver->unbind(&udc->gadget);
8175 + udc->gadget.dev.driver = NULL;
8176 + udc->driver = NULL;
8177 +
8178 + clk_disable(udc->hclk);
8179 + clk_disable(udc->pclk);
8180 +
8181 + DBG(DBG_GADGET, "unregistered driver `%s'\n", driver->driver.name);
8182 +
8183 + return 0;
8184 +}
8185 +EXPORT_SYMBOL(usb_gadget_unregister_driver);
8186 +
8187 +static int __init usba_udc_probe(struct platform_device *pdev)
8188 +{
8189 + struct usba_platform_data *pdata = pdev->dev.platform_data;
8190 + struct resource *regs, *fifo;
8191 + struct clk *pclk, *hclk;
8192 + struct usba_udc *udc = &the_udc;
8193 + int irq, ret, i;
8194 +
8195 + regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
8196 + fifo = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
8197 + if (!regs || !fifo)
8198 + return -ENXIO;
8199 +
8200 + irq = platform_get_irq(pdev, 0);
8201 + if (irq < 0)
8202 + return irq;
8203 +
8204 + pclk = clk_get(&pdev->dev, "pclk");
8205 + if (IS_ERR(pclk))
8206 + return PTR_ERR(pclk);
8207 + hclk = clk_get(&pdev->dev, "hclk");
8208 + if (IS_ERR(hclk)) {
8209 + ret = PTR_ERR(hclk);
8210 + goto err_get_hclk;
8211 + }
8212 +
8213 + udc->pdev = pdev;
8214 + udc->pclk = pclk;
8215 + udc->hclk = hclk;
8216 + udc->vbus_pin = -1;
8217 +
8218 + ret = -ENOMEM;
8219 + udc->regs = ioremap(regs->start, regs->end - regs->start + 1);
8220 + if (!udc->regs) {
8221 + dev_err(&pdev->dev, "Unable to map I/O memory, aborting.\n");
8222 + goto err_map_regs;
8223 + }
8224 + dev_info(&pdev->dev, "MMIO registers at 0x%08lx mapped at %p\n",
8225 + (unsigned long)regs->start, udc->regs);
8226 + udc->fifo = ioremap(fifo->start, fifo->end - fifo->start + 1);
8227 + if (!udc->fifo) {
8228 + dev_err(&pdev->dev, "Unable to map FIFO, aborting.\n");
8229 + goto err_map_fifo;
8230 + }
8231 + dev_info(&pdev->dev, "FIFO at 0x%08lx mapped at %p\n",
8232 + (unsigned long)fifo->start, udc->fifo);
8233 +
8234 + device_initialize(&udc->gadget.dev);
8235 + udc->gadget.dev.parent = &pdev->dev;
8236 + udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
8237 +
8238 + platform_set_drvdata(pdev, udc);
8239 +
8240 + /* Make sure we start from a clean slate */
8241 + clk_enable(pclk);
8242 + usba_writel(udc, CTRL, 0);
8243 + clk_disable(pclk);
8244 +
8245 + INIT_LIST_HEAD(&usba_ep[0].ep.ep_list);
8246 + usba_ep[0].ep_regs = udc->regs + USBA_EPT_BASE(0);
8247 + usba_ep[0].dma_regs = udc->regs + USBA_DMA_BASE(0);
8248 + usba_ep[0].fifo = udc->fifo + USBA_FIFO_BASE(0);
8249 + for (i = 1; i < ARRAY_SIZE(usba_ep); i++) {
8250 + struct usba_ep *ep = &usba_ep[i];
8251 +
8252 + ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
8253 + ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
8254 + ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
8255 +
8256 + list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
8257 + }
8258 +
8259 + ret = request_irq(irq, usba_udc_irq, 0, "atmel_usba_udc", udc);
8260 + if (ret) {
8261 + dev_err(&pdev->dev, "Cannot request irq %d (error %d)\n",
8262 + irq, ret);
8263 + goto err_request_irq;
8264 + }
8265 + udc->irq = irq;
8266 +
8267 + ret = device_add(&udc->gadget.dev);
8268 + if (ret) {
8269 + dev_dbg(&pdev->dev, "Could not add gadget: %d\n", ret);
8270 + goto err_device_add;
8271 + }
8272 +
8273 + if (pdata && pdata->vbus_pin != GPIO_PIN_NONE) {
8274 + if (!gpio_request(pdata->vbus_pin, "atmel_usba_udc")) {
8275 + udc->vbus_pin = pdata->vbus_pin;
8276 +
8277 + ret = request_irq(gpio_to_irq(udc->vbus_pin),
8278 + usba_vbus_irq, 0,
8279 + "atmel_usba_udc", udc);
8280 + if (ret) {
8281 + gpio_free(udc->vbus_pin);
8282 + udc->vbus_pin = -1;
8283 + dev_warn(&udc->pdev->dev,
8284 + "failed to request vbus irq; "
8285 + "assuming always on\n");
8286 + } else {
8287 + disable_irq(gpio_to_irq(udc->vbus_pin));
8288 + }
8289 + }
8290 + }
8291 +
8292 + usba_init_debugfs(udc);
8293 + for (i = 1; i < ARRAY_SIZE(usba_ep); i++)
8294 + usba_ep_init_debugfs(udc, &usba_ep[i]);
8295 +
8296 + return 0;
8297 +
8298 +err_device_add:
8299 + free_irq(irq, udc);
8300 +err_request_irq:
8301 + iounmap(udc->fifo);
8302 +err_map_fifo:
8303 + iounmap(udc->regs);
8304 +err_map_regs:
8305 + clk_put(hclk);
8306 +err_get_hclk:
8307 + clk_put(pclk);
8308 +
8309 + platform_set_drvdata(pdev, NULL);
8310 +
8311 + return ret;
8312 +}
8313 +
8314 +static int __exit usba_udc_remove(struct platform_device *pdev)
8315 +{
8316 + struct usba_udc *udc;
8317 + int i;
8318 +
8319 + udc = platform_get_drvdata(pdev);
8320 +
8321 + for (i = 1; i < ARRAY_SIZE(usba_ep); i++)
8322 + usba_ep_cleanup_debugfs(&usba_ep[i]);
8323 + usba_cleanup_debugfs(udc);
8324 +
8325 + if (udc->vbus_pin != -1)
8326 + gpio_free(udc->vbus_pin);
8327 +
8328 + free_irq(udc->irq, udc);
8329 + iounmap(udc->fifo);
8330 + iounmap(udc->regs);
8331 + clk_put(udc->hclk);
8332 + clk_put(udc->pclk);
8333 +
8334 + device_unregister(&udc->gadget.dev);
8335 +
8336 + return 0;
8337 +}
8338 +
8339 +static struct platform_driver udc_driver = {
8340 + .remove = __exit_p(usba_udc_remove),
8341 + .driver = {
8342 + .name = "atmel_usba_udc",
8343 + },
8344 +};
8345 +
8346 +static int __init udc_init(void)
8347 +{
8348 + return platform_driver_probe(&udc_driver, usba_udc_probe);
8349 +}
8350 +module_init(udc_init);
8351 +
8352 +static void __exit udc_exit(void)
8353 +{
8354 + platform_driver_unregister(&udc_driver);
8355 +}
8356 +module_exit(udc_exit);
8357 +
8358 +MODULE_DESCRIPTION("Atmel USBA UDC driver");
8359 +MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
8360 +MODULE_LICENSE("GPL");
8361 diff --git a/drivers/usb/gadget/atmel_usba_udc.h b/drivers/usb/gadget/atmel_usba_udc.h
8362 new file mode 100644
8363 index 0000000..f4f0f8b
8364 --- /dev/null
8365 +++ b/drivers/usb/gadget/atmel_usba_udc.h
8366 @@ -0,0 +1,350 @@
8367 +/*
8368 + * Driver for the Atmel USBA high speed USB device controller
8369 + *
8370 + * Copyright (C) 2005-2007 Atmel Corporation
8371 + *
8372 + * This program is free software; you can redistribute it and/or modify
8373 + * it under the terms of the GNU General Public License version 2 as
8374 + * published by the Free Software Foundation.
8375 + */
8376 +#ifndef __LINUX_USB_GADGET_USBA_UDC_H__
8377 +#define __LINUX_USB_GADGET_USBA_UDC_H__
8378 +
8379 +/* USB register offsets */
8380 +#define USBA_CTRL 0x0000
8381 +#define USBA_FNUM 0x0004
8382 +#define USBA_INT_ENB 0x0010
8383 +#define USBA_INT_STA 0x0014
8384 +#define USBA_INT_CLR 0x0018
8385 +#define USBA_EPT_RST 0x001c
8386 +#define USBA_TST 0x00e0
8387 +
8388 +/* USB endpoint register offsets */
8389 +#define USBA_EPT_CFG 0x0000
8390 +#define USBA_EPT_CTL_ENB 0x0004
8391 +#define USBA_EPT_CTL_DIS 0x0008
8392 +#define USBA_EPT_CTL 0x000c
8393 +#define USBA_EPT_SET_STA 0x0014
8394 +#define USBA_EPT_CLR_STA 0x0018
8395 +#define USBA_EPT_STA 0x001c
8396 +
8397 +/* USB DMA register offsets */
8398 +#define USBA_DMA_NXT_DSC 0x0000
8399 +#define USBA_DMA_ADDRESS 0x0004
8400 +#define USBA_DMA_CONTROL 0x0008
8401 +#define USBA_DMA_STATUS 0x000c
8402 +
8403 +/* Bitfields in CTRL */
8404 +#define USBA_DEV_ADDR_OFFSET 0
8405 +#define USBA_DEV_ADDR_SIZE 7
8406 +#define USBA_FADDR_EN (1 << 7)
8407 +#define USBA_EN_USBA (1 << 8)
8408 +#define USBA_DETACH (1 << 9)
8409 +#define USBA_REMOTE_WAKE_UP (1 << 10)
8410 +
8411 +/* Bitfields in FNUM */
8412 +#define USBA_MICRO_FRAME_NUM_OFFSET 0
8413 +#define USBA_MICRO_FRAME_NUM_SIZE 3
8414 +#define USBA_FRAME_NUMBER_OFFSET 3
8415 +#define USBA_FRAME_NUMBER_SIZE 11
8416 +#define USBA_FRAME_NUM_ERROR (1 << 31)
8417 +
8418 +/* Bitfields in INT_ENB/INT_STA/INT_CLR */
8419 +#define USBA_HIGH_SPEED (1 << 0)
8420 +#define USBA_DET_SUSPEND (1 << 1)
8421 +#define USBA_MICRO_SOF (1 << 2)
8422 +#define USBA_SOF (1 << 3)
8423 +#define USBA_END_OF_RESET (1 << 4)
8424 +#define USBA_WAKE_UP (1 << 5)
8425 +#define USBA_END_OF_RESUME (1 << 6)
8426 +#define USBA_UPSTREAM_RESUME (1 << 7)
8427 +#define USBA_EPT_INT_OFFSET 8
8428 +#define USBA_EPT_INT_SIZE 16
8429 +#define USBA_DMA_INT_OFFSET 24
8430 +#define USBA_DMA_INT_SIZE 8
8431 +
8432 +/* Bitfields in EPT_RST */
8433 +#define USBA_RST_OFFSET 0
8434 +#define USBA_RST_SIZE 16
8435 +
8436 +/* Bitfields in USBA_TST */
8437 +#define USBA_SPEED_CFG_OFFSET 0
8438 +#define USBA_SPEED_CFG_SIZE 2
8439 +#define USBA_TST_J_MODE (1 << 2)
8440 +#define USBA_TST_K_MODE (1 << 3)
8441 +#define USBA_TST_PKT_MODE (1 << 4)
8442 +#define USBA_OPMODE2 (1 << 5)
8443 +
8444 +/* Bitfields in EPT_CFG */
8445 +#define USBA_EPT_SIZE_OFFSET 0
8446 +#define USBA_EPT_SIZE_SIZE 3
8447 +#define USBA_EPT_DIR_IN (1 << 3)
8448 +#define USBA_EPT_TYPE_OFFSET 4
8449 +#define USBA_EPT_TYPE_SIZE 2
8450 +#define USBA_BK_NUMBER_OFFSET 6
8451 +#define USBA_BK_NUMBER_SIZE 2
8452 +#define USBA_NB_TRANS_OFFSET 8
8453 +#define USBA_NB_TRANS_SIZE 2
8454 +#define USBA_EPT_MAPPED (1 << 31)
8455 +
8456 +/* Bitfields in EPT_CTL/EPT_CTL_ENB/EPT_CTL_DIS */
8457 +#define USBA_EPT_ENABLE (1 << 0)
8458 +#define USBA_AUTO_VALID (1 << 1)
8459 +#define USBA_INTDIS_DMA (1 << 3)
8460 +#define USBA_NYET_DIS (1 << 4)
8461 +#define USBA_DATAX_RX (1 << 6)
8462 +#define USBA_MDATA_RX (1 << 7)
8463 +/* Bits 8-15 and 31 enable interrupts for respective bits in EPT_STA */
8464 +#define USBA_BUSY_BANK_IE (1 << 18)
8465 +
8466 +/* Bitfields in EPT_SET_STA/EPT_CLR_STA/EPT_STA */
8467 +#define USBA_FORCE_STALL (1 << 5)
8468 +#define USBA_TOGGLE_CLR (1 << 6)
8469 +#define USBA_TOGGLE_SEQ_OFFSET 6
8470 +#define USBA_TOGGLE_SEQ_SIZE 2
8471 +#define USBA_ERR_OVFLW (1 << 8)
8472 +#define USBA_RX_BK_RDY (1 << 9)
8473 +#define USBA_KILL_BANK (1 << 9)
8474 +#define USBA_TX_COMPLETE (1 << 10)
8475 +#define USBA_TX_PK_RDY (1 << 11)
8476 +#define USBA_ISO_ERR_TRANS (1 << 11)
8477 +#define USBA_RX_SETUP (1 << 12)
8478 +#define USBA_ISO_ERR_FLOW (1 << 12)
8479 +#define USBA_STALL_SENT (1 << 13)
8480 +#define USBA_ISO_ERR_CRC (1 << 13)
8481 +#define USBA_ISO_ERR_NBTRANS (1 << 13)
8482 +#define USBA_NAK_IN (1 << 14)
8483 +#define USBA_ISO_ERR_FLUSH (1 << 14)
8484 +#define USBA_NAK_OUT (1 << 15)
8485 +#define USBA_CURRENT_BANK_OFFSET 16
8486 +#define USBA_CURRENT_BANK_SIZE 2
8487 +#define USBA_BUSY_BANKS_OFFSET 18
8488 +#define USBA_BUSY_BANKS_SIZE 2
8489 +#define USBA_BYTE_COUNT_OFFSET 20
8490 +#define USBA_BYTE_COUNT_SIZE 11
8491 +#define USBA_SHORT_PACKET (1 << 31)
8492 +
8493 +/* Bitfields in DMA_CONTROL */
8494 +#define USBA_DMA_CH_EN (1 << 0)
8495 +#define USBA_DMA_LINK (1 << 1)
8496 +#define USBA_DMA_END_TR_EN (1 << 2)
8497 +#define USBA_DMA_END_BUF_EN (1 << 3)
8498 +#define USBA_DMA_END_TR_IE (1 << 4)
8499 +#define USBA_DMA_END_BUF_IE (1 << 5)
8500 +#define USBA_DMA_DESC_LOAD_IE (1 << 6)
8501 +#define USBA_DMA_BURST_LOCK (1 << 7)
8502 +#define USBA_DMA_BUF_LEN_OFFSET 16
8503 +#define USBA_DMA_BUF_LEN_SIZE 16
8504 +
8505 +/* Bitfields in DMA_STATUS */
8506 +#define USBA_DMA_CH_ACTIVE (1 << 1)
8507 +#define USBA_DMA_END_TR_ST (1 << 4)
8508 +#define USBA_DMA_END_BUF_ST (1 << 5)
8509 +#define USBA_DMA_DESC_LOAD_ST (1 << 6)
8510 +
8511 +/* Constants for SPEED_CFG */
8512 +#define USBA_SPEED_CFG_NORMAL 0
8513 +#define USBA_SPEED_CFG_FORCE_HIGH 2
8514 +#define USBA_SPEED_CFG_FORCE_FULL 3
8515 +
8516 +/* Constants for EPT_SIZE */
8517 +#define USBA_EPT_SIZE_8 0
8518 +#define USBA_EPT_SIZE_16 1
8519 +#define USBA_EPT_SIZE_32 2
8520 +#define USBA_EPT_SIZE_64 3
8521 +#define USBA_EPT_SIZE_128 4
8522 +#define USBA_EPT_SIZE_256 5
8523 +#define USBA_EPT_SIZE_512 6
8524 +#define USBA_EPT_SIZE_1024 7
8525 +
8526 +/* Constants for EPT_TYPE */
8527 +#define USBA_EPT_TYPE_CONTROL 0
8528 +#define USBA_EPT_TYPE_ISO 1
8529 +#define USBA_EPT_TYPE_BULK 2
8530 +#define USBA_EPT_TYPE_INT 3
8531 +
8532 +/* Constants for BK_NUMBER */
8533 +#define USBA_BK_NUMBER_ZERO 0
8534 +#define USBA_BK_NUMBER_ONE 1
8535 +#define USBA_BK_NUMBER_DOUBLE 2
8536 +#define USBA_BK_NUMBER_TRIPLE 3
8537 +
8538 +/* Bit manipulation macros */
8539 +#define USBA_BF(name, value) \
8540 + (((value) & ((1 << USBA_##name##_SIZE) - 1)) \
8541 + << USBA_##name##_OFFSET)
8542 +#define USBA_BFEXT(name, value) \
8543 + (((value) >> USBA_##name##_OFFSET) \
8544 + & ((1 << USBA_##name##_SIZE) - 1))
8545 +#define USBA_BFINS(name, value, old) \
8546 + (((old) & ~(((1 << USBA_##name##_SIZE) - 1) \
8547 + << USBA_##name##_OFFSET)) \
8548 + | USBA_BF(name, value))
8549 +
8550 +/* Register access macros */
8551 +#define usba_readl(udc, reg) \
8552 + __raw_readl((udc)->regs + USBA_##reg)
8553 +#define usba_writel(udc, reg, value) \
8554 + __raw_writel((value), (udc)->regs + USBA_##reg)
8555 +#define usba_ep_readl(ep, reg) \
8556 + __raw_readl((ep)->ep_regs + USBA_EPT_##reg)
8557 +#define usba_ep_writel(ep, reg, value) \
8558 + __raw_writel((value), (ep)->ep_regs + USBA_EPT_##reg)
8559 +#define usba_dma_readl(ep, reg) \
8560 + __raw_readl((ep)->dma_regs + USBA_DMA_##reg)
8561 +#define usba_dma_writel(ep, reg, value) \
8562 + __raw_writel((value), (ep)->dma_regs + USBA_DMA_##reg)
8563 +
8564 +/* Calculate base address for a given endpoint or DMA controller */
8565 +#define USBA_EPT_BASE(x) (0x100 + (x) * 0x20)
8566 +#define USBA_DMA_BASE(x) (0x300 + (x) * 0x10)
8567 +#define USBA_FIFO_BASE(x) ((x) << 16)
8568 +
8569 +/* Synth parameters */
8570 +#define USBA_NR_ENDPOINTS 7
8571 +
8572 +#define EP0_FIFO_SIZE 64
8573 +#define EP0_EPT_SIZE USBA_EPT_SIZE_64
8574 +#define EP0_NR_BANKS 1
8575 +
8576 +/*
8577 + * REVISIT: Try to eliminate this value. Can we rely on req->mapped to
8578 + * provide this information?
8579 + */
8580 +#define DMA_ADDR_INVALID (~(dma_addr_t)0)
8581 +
8582 +#define FIFO_IOMEM_ID 0
8583 +#define CTRL_IOMEM_ID 1
8584 +
8585 +#ifdef DEBUG
8586 +#define DBG_ERR 0x0001 /* report all error returns */
8587 +#define DBG_HW 0x0002 /* debug hardware initialization */
8588 +#define DBG_GADGET 0x0004 /* calls to/from gadget driver */
8589 +#define DBG_INT 0x0008 /* interrupts */
8590 +#define DBG_BUS 0x0010 /* report changes in bus state */
8591 +#define DBG_QUEUE 0x0020 /* debug request queue processing */
8592 +#define DBG_FIFO 0x0040 /* debug FIFO contents */
8593 +#define DBG_DMA 0x0080 /* debug DMA handling */
8594 +#define DBG_REQ 0x0100 /* print out queued request length */
8595 +#define DBG_ALL 0xffff
8596 +#define DBG_NONE 0x0000
8597 +
8598 +#define DEBUG_LEVEL (DBG_ERR)
8599 +#define DBG(level, fmt, ...) \
8600 + do { \
8601 + if ((level) & DEBUG_LEVEL) \
8602 + printk(KERN_DEBUG "udc: " fmt, ## __VA_ARGS__); \
8603 + } while (0)
8604 +#else
8605 +#define DBG(level, fmt...)
8606 +#endif
8607 +
8608 +enum usba_ctrl_state {
8609 + WAIT_FOR_SETUP,
8610 + DATA_STAGE_IN,
8611 + DATA_STAGE_OUT,
8612 + STATUS_STAGE_IN,
8613 + STATUS_STAGE_OUT,
8614 + STATUS_STAGE_ADDR,
8615 + STATUS_STAGE_TEST,
8616 +};
8617 +/*
8618 + EP_STATE_IDLE,
8619 + EP_STATE_SETUP,
8620 + EP_STATE_IN_DATA,
8621 + EP_STATE_OUT_DATA,
8622 + EP_STATE_SET_ADDR_STATUS,
8623 + EP_STATE_RX_STATUS,
8624 + EP_STATE_TX_STATUS,
8625 + EP_STATE_HALT,
8626 +*/
8627 +
8628 +struct usba_dma_desc {
8629 + dma_addr_t next;
8630 + dma_addr_t addr;
8631 + u32 ctrl;
8632 +};
8633 +
8634 +struct usba_ep {
8635 + int state;
8636 + void __iomem *ep_regs;
8637 + void __iomem *dma_regs;
8638 + void __iomem *fifo;
8639 + struct usb_ep ep;
8640 + struct usba_udc *udc;
8641 +
8642 + struct list_head queue;
8643 + const struct usb_endpoint_descriptor *desc;
8644 +
8645 + u16 fifo_size;
8646 + u8 nr_banks;
8647 + u8 index;
8648 + unsigned int can_dma:1;
8649 + unsigned int can_isoc:1;
8650 + unsigned int is_isoc:1;
8651 + unsigned int is_in:1;
8652 +
8653 +#ifdef CONFIG_USB_GADGET_DEBUG_FS
8654 + u32 last_dma_status;
8655 + struct dentry *debugfs_dir;
8656 + struct dentry *debugfs_queue;
8657 + struct dentry *debugfs_dma_status;
8658 + struct dentry *debugfs_state;
8659 +#endif
8660 +};
8661 +
8662 +struct usba_request {
8663 + struct usb_request req;
8664 + struct list_head queue;
8665 +
8666 + u32 ctrl;
8667 +
8668 + unsigned int submitted:1;
8669 + unsigned int last_transaction:1;
8670 + unsigned int using_dma:1;
8671 + unsigned int mapped:1;
8672 +};
8673 +
8674 +struct usba_udc {
8675 + /* Protect hw registers from concurrent modifications */
8676 + spinlock_t lock;
8677 +
8678 + void __iomem *regs;
8679 + void __iomem *fifo;
8680 +
8681 + struct usb_gadget gadget;
8682 + struct usb_gadget_driver *driver;
8683 + struct platform_device *pdev;
8684 + int irq;
8685 + int vbus_pin;
8686 + struct clk *pclk;
8687 + struct clk *hclk;
8688 +
8689 + int test_mode;
8690 + int vbus_prev;
8691 +
8692 +#ifdef CONFIG_USB_GADGET_DEBUG_FS
8693 + struct dentry *debugfs_root;
8694 + struct dentry *debugfs_regs;
8695 +#endif
8696 +};
8697 +
8698 +static inline struct usba_ep *to_usba_ep(struct usb_ep *ep)
8699 +{
8700 + return container_of(ep, struct usba_ep, ep);
8701 +}
8702 +
8703 +static inline struct usba_request *to_usba_req(struct usb_request *req)
8704 +{
8705 + return container_of(req, struct usba_request, req);
8706 +}
8707 +
8708 +static inline struct usba_udc *to_usba_udc(struct usb_gadget *gadget)
8709 +{
8710 + return container_of(gadget, struct usba_udc, gadget);
8711 +}
8712 +
8713 +#define ep_is_control(ep) ((ep)->index == 0)
8714 +#define ep_is_idle(ep) ((ep)->state == EP_STATE_IDLE)
8715 +
8716 +#endif /* __LINUX_USB_GADGET_USBA_UDC_H */
8717 diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
8718 index 235b618..bb361ab 100644
8719 --- a/drivers/video/atmel_lcdfb.c
8720 +++ b/drivers/video/atmel_lcdfb.c
8721 @@ -37,7 +37,9 @@
8722 #endif
8723
8724 #if defined(CONFIG_ARCH_AT91)
8725 -#define ATMEL_LCDFB_FBINFO_DEFAULT FBINFO_DEFAULT
8726 +#define ATMEL_LCDFB_FBINFO_DEFAULT (FBINFO_DEFAULT \
8727 + | FBINFO_PARTIAL_PAN_OK \
8728 + | FBINFO_HWACCEL_YPAN)
8729
8730 static inline void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo,
8731 struct fb_var_screeninfo *var)
8732 @@ -74,7 +76,7 @@ static struct fb_fix_screeninfo atmel_lcdfb_fix __initdata = {
8733 .type = FB_TYPE_PACKED_PIXELS,
8734 .visual = FB_VISUAL_TRUECOLOR,
8735 .xpanstep = 0,
8736 - .ypanstep = 0,
8737 + .ypanstep = 1,
8738 .ywrapstep = 0,
8739 .accel = FB_ACCEL_NONE,
8740 };
8741 diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig
8742 index 2580f5f..b6f936a 100644
8743 --- a/drivers/video/backlight/Kconfig
8744 +++ b/drivers/video/backlight/Kconfig
8745 @@ -24,6 +24,18 @@ config LCD_CLASS_DEVICE
8746 To have support for your specific LCD panel you will have to
8747 select the proper drivers which depend on this option.
8748
8749 +config LCD_LTV350QV
8750 + tristate "Samsung LTV350QV LCD Panel"
8751 + depends on LCD_CLASS_DEVICE && SPI_MASTER
8752 + default n
8753 + help
8754 + If you have a Samsung LTV350QV LCD panel, say y to include a
8755 + power control driver for it. The panel starts up in power
8756 + off state, so you need this driver in order to see any
8757 + output.
8758 +
8759 + The LTV350QV panel is present on all ATSTK1000 boards.
8760 +
8761 #
8762 # Backlight
8763 #
8764 diff --git a/drivers/video/backlight/Makefile b/drivers/video/backlight/Makefile
8765 index c6e2266..965a78b 100644
8766 --- a/drivers/video/backlight/Makefile
8767 +++ b/drivers/video/backlight/Makefile
8768 @@ -1,6 +1,8 @@
8769 # Backlight & LCD drivers
8770
8771 obj-$(CONFIG_LCD_CLASS_DEVICE) += lcd.o
8772 +obj-$(CONFIG_LCD_LTV350QV) += ltv350qv.o
8773 +
8774 obj-$(CONFIG_BACKLIGHT_CLASS_DEVICE) += backlight.o
8775 obj-$(CONFIG_BACKLIGHT_CORGI) += corgi_bl.o
8776 obj-$(CONFIG_BACKLIGHT_HP680) += hp680_bl.o
8777 diff --git a/drivers/video/backlight/ltv350qv.c b/drivers/video/backlight/ltv350qv.c
8778 new file mode 100644
8779 index 0000000..751dc53
8780 --- /dev/null
8781 +++ b/drivers/video/backlight/ltv350qv.c
8782 @@ -0,0 +1,339 @@
8783 +/*
8784 + * Power control for Samsung LTV350QV Quarter VGA LCD Panel
8785 + *
8786 + * Copyright (C) 2006, 2007 Atmel Corporation
8787 + *
8788 + * This program is free software; you can redistribute it and/or modify
8789 + * it under the terms of the GNU General Public License version 2 as
8790 + * published by the Free Software Foundation.
8791 + */
8792 +#include <linux/delay.h>
8793 +#include <linux/err.h>
8794 +#include <linux/fb.h>
8795 +#include <linux/init.h>
8796 +#include <linux/lcd.h>
8797 +#include <linux/module.h>
8798 +#include <linux/spi/spi.h>
8799 +
8800 +#include "ltv350qv.h"
8801 +
8802 +#define POWER_IS_ON(pwr) ((pwr) <= FB_BLANK_NORMAL)
8803 +
8804 +struct ltv350qv {
8805 + struct spi_device *spi;
8806 + u8 *buffer;
8807 + int power;
8808 + struct lcd_device *ld;
8809 +};
8810 +
8811 +/*
8812 + * The power-on and power-off sequences are taken from the
8813 + * LTV350QV-F04 data sheet from Samsung. The register definitions are
8814 + * taken from the S6F2002 command list also from Samsung. Both
8815 + * documents are distributed with the AVR32 Linux BSP CD from Atmel.
8816 + *
8817 + * There's still some voodoo going on here, but it's a lot better than
8818 + * in the first incarnation of the driver where all we had was the raw
8819 + * numbers from the initialization sequence.
8820 + */
8821 +static int ltv350qv_write_reg(struct ltv350qv *lcd, u8 reg, u16 val)
8822 +{
8823 + struct spi_message msg;
8824 + struct spi_transfer index_xfer = {
8825 + .len = 3,
8826 + .cs_change = 1,
8827 + };
8828 + struct spi_transfer value_xfer = {
8829 + .len = 3,
8830 + };
8831 +
8832 + spi_message_init(&msg);
8833 +
8834 + /* register index */
8835 + lcd->buffer[0] = LTV_OPC_INDEX;
8836 + lcd->buffer[1] = 0x00;
8837 + lcd->buffer[2] = reg & 0x7f;
8838 + index_xfer.tx_buf = lcd->buffer;
8839 + spi_message_add_tail(&index_xfer, &msg);
8840 +
8841 + /* register value */
8842 + lcd->buffer[4] = LTV_OPC_DATA;
8843 + lcd->buffer[5] = val >> 8;
8844 + lcd->buffer[6] = val;
8845 + value_xfer.tx_buf = lcd->buffer + 4;
8846 + spi_message_add_tail(&value_xfer, &msg);
8847 +
8848 + return spi_sync(lcd->spi, &msg);
8849 +}
8850 +
8851 +/* The comments are taken straight from the data sheet */
8852 +static int ltv350qv_power_on(struct ltv350qv *lcd)
8853 +{
8854 + int ret;
8855 +
8856 + /* Power On Reset Display off State */
8857 + if (ltv350qv_write_reg(lcd, LTV_PWRCTL1, 0x0000))
8858 + goto err;
8859 + msleep(15);
8860 +
8861 + /* Power Setting Function 1 */
8862 + if (ltv350qv_write_reg(lcd, LTV_PWRCTL1, LTV_VCOM_DISABLE))
8863 + goto err;
8864 + if (ltv350qv_write_reg(lcd, LTV_PWRCTL2, LTV_VCOML_ENABLE))
8865 + goto err_power1;
8866 +
8867 + /* Power Setting Function 2 */
8868 + if (ltv350qv_write_reg(lcd, LTV_PWRCTL1,
8869 + LTV_VCOM_DISABLE | LTV_DRIVE_CURRENT(5)
8870 + | LTV_SUPPLY_CURRENT(5)))
8871 + goto err_power2;
8872 +
8873 + msleep(55);
8874 +
8875 + /* Instruction Setting */
8876 + ret = ltv350qv_write_reg(lcd, LTV_IFCTL,
8877 + LTV_NMD | LTV_REV | LTV_NL(0x1d));
8878 + ret |= ltv350qv_write_reg(lcd, LTV_DATACTL,
8879 + LTV_DS_SAME | LTV_CHS_480
8880 + | LTV_DF_RGB | LTV_RGB_BGR);
8881 + ret |= ltv350qv_write_reg(lcd, LTV_ENTRY_MODE,
8882 + LTV_VSPL_ACTIVE_LOW
8883 + | LTV_HSPL_ACTIVE_LOW
8884 + | LTV_DPL_SAMPLE_RISING
8885 + | LTV_EPL_ACTIVE_LOW
8886 + | LTV_SS_RIGHT_TO_LEFT);
8887 + ret |= ltv350qv_write_reg(lcd, LTV_GATECTL1, LTV_CLW(3));
8888 + ret |= ltv350qv_write_reg(lcd, LTV_GATECTL2,
8889 + LTV_NW_INV_1LINE | LTV_FWI(3));
8890 + ret |= ltv350qv_write_reg(lcd, LTV_VBP, 0x000a);
8891 + ret |= ltv350qv_write_reg(lcd, LTV_HBP, 0x0021);
8892 + ret |= ltv350qv_write_reg(lcd, LTV_SOTCTL, LTV_SDT(3) | LTV_EQ(0));
8893 + ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(0), 0x0103);
8894 + ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(1), 0x0301);
8895 + ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(2), 0x1f0f);
8896 + ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(3), 0x1f0f);
8897 + ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(4), 0x0707);
8898 + ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(5), 0x0307);
8899 + ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(6), 0x0707);
8900 + ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(7), 0x0000);
8901 + ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(8), 0x0004);
8902 + ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(9), 0x0000);
8903 + if (ret)
8904 + goto err_settings;
8905 +
8906 + /* Wait more than 2 frames */
8907 + msleep(20);
8908 +
8909 + /* Display On Sequence */
8910 + ret = ltv350qv_write_reg(lcd, LTV_PWRCTL1,
8911 + LTV_VCOM_DISABLE | LTV_VCOMOUT_ENABLE
8912 + | LTV_POWER_ON | LTV_DRIVE_CURRENT(5)
8913 + | LTV_SUPPLY_CURRENT(5));
8914 + ret |= ltv350qv_write_reg(lcd, LTV_GATECTL2,
8915 + LTV_NW_INV_1LINE | LTV_DSC | LTV_FWI(3));
8916 + if (ret)
8917 + goto err_disp_on;
8918 +
8919 + /* Display should now be ON. Phew. */
8920 + return 0;
8921 +
8922 +err_disp_on:
8923 + /*
8924 + * Try to recover. Error handling probably isn't very useful
8925 + * at this point, just make a best effort to switch the panel
8926 + * off.
8927 + */
8928 + ltv350qv_write_reg(lcd, LTV_PWRCTL1,
8929 + LTV_VCOM_DISABLE | LTV_DRIVE_CURRENT(5)
8930 + | LTV_SUPPLY_CURRENT(5));
8931 + ltv350qv_write_reg(lcd, LTV_GATECTL2,
8932 + LTV_NW_INV_1LINE | LTV_FWI(3));
8933 +err_settings:
8934 +err_power2:
8935 +err_power1:
8936 + ltv350qv_write_reg(lcd, LTV_PWRCTL2, 0x0000);
8937 + msleep(1);
8938 +err:
8939 + ltv350qv_write_reg(lcd, LTV_PWRCTL1, LTV_VCOM_DISABLE);
8940 + return -EIO;
8941 +}
8942 +
8943 +static int ltv350qv_power_off(struct ltv350qv *lcd)
8944 +{
8945 + int ret;
8946 +
8947 + /* Display Off Sequence */
8948 + ret = ltv350qv_write_reg(lcd, LTV_PWRCTL1,
8949 + LTV_VCOM_DISABLE
8950 + | LTV_DRIVE_CURRENT(5)
8951 + | LTV_SUPPLY_CURRENT(5));
8952 + ret |= ltv350qv_write_reg(lcd, LTV_GATECTL2,
8953 + LTV_NW_INV_1LINE | LTV_FWI(3));
8954 +
8955 + /* Power down setting 1 */
8956 + ret |= ltv350qv_write_reg(lcd, LTV_PWRCTL2, 0x0000);
8957 +
8958 + /* Wait at least 1 ms */
8959 + msleep(1);
8960 +
8961 + /* Power down setting 2 */
8962 + ret |= ltv350qv_write_reg(lcd, LTV_PWRCTL1, LTV_VCOM_DISABLE);
8963 +
8964 + /*
8965 + * No point in trying to recover here. If we can't switch the
8966 + * panel off, what are we supposed to do other than inform the
8967 + * user about the failure?
8968 + */
8969 + if (ret)
8970 + return -EIO;
8971 +
8972 + /* Display power should now be OFF */
8973 + return 0;
8974 +}
8975 +
8976 +static int ltv350qv_power(struct ltv350qv *lcd, int power)
8977 +{
8978 + int ret = 0;
8979 +
8980 + if (POWER_IS_ON(power) && !POWER_IS_ON(lcd->power))
8981 + ret = ltv350qv_power_on(lcd);
8982 + else if (!POWER_IS_ON(power) && POWER_IS_ON(lcd->power))
8983 + ret = ltv350qv_power_off(lcd);
8984 +
8985 + if (!ret)
8986 + lcd->power = power;
8987 +
8988 + return ret;
8989 +}
8990 +
8991 +static int ltv350qv_set_power(struct lcd_device *ld, int power)
8992 +{
8993 + struct ltv350qv *lcd;
8994 +
8995 + lcd = lcd_get_data(ld);
8996 + return ltv350qv_power(lcd, power);
8997 +}
8998 +
8999 +static int ltv350qv_get_power(struct lcd_device *ld)
9000 +{
9001 + struct ltv350qv *lcd;
9002 +
9003 + lcd = lcd_get_data(ld);
9004 + return lcd->power;
9005 +}
9006 +
9007 +static struct lcd_ops ltv_ops = {
9008 + .get_power = ltv350qv_get_power,
9009 + .set_power = ltv350qv_set_power,
9010 +};
9011 +
9012 +static int __devinit ltv350qv_probe(struct spi_device *spi)
9013 +{
9014 + struct ltv350qv *lcd;
9015 + struct lcd_device *ld;
9016 + int ret;
9017 +
9018 + lcd = kzalloc(sizeof(struct ltv350qv), GFP_KERNEL);
9019 + if (!lcd)
9020 + return -ENOMEM;
9021 +
9022 + lcd->spi = spi;
9023 + lcd->power = FB_BLANK_POWERDOWN;
9024 + lcd->buffer = kzalloc(8, GFP_KERNEL);
9025 +
9026 + ld = lcd_device_register("ltv350qv", &spi->dev, lcd, &ltv_ops);
9027 + if (IS_ERR(ld)) {
9028 + ret = PTR_ERR(ld);
9029 + goto out_free_lcd;
9030 + }
9031 + lcd->ld = ld;
9032 +
9033 + ret = ltv350qv_power(lcd, FB_BLANK_UNBLANK);
9034 + if (ret)
9035 + goto out_unregister;
9036 +
9037 + dev_set_drvdata(&spi->dev, lcd);
9038 +
9039 + return 0;
9040 +
9041 +out_unregister:
9042 + lcd_device_unregister(ld);
9043 +out_free_lcd:
9044 + kfree(lcd);
9045 + return ret;
9046 +}
9047 +
9048 +static int __devexit ltv350qv_remove(struct spi_device *spi)
9049 +{
9050 + struct ltv350qv *lcd = dev_get_drvdata(&spi->dev);
9051 +
9052 + ltv350qv_power(lcd, FB_BLANK_POWERDOWN);
9053 + lcd_device_unregister(lcd->ld);
9054 + kfree(lcd);
9055 +
9056 + return 0;
9057 +}
9058 +
9059 +#ifdef CONFIG_PM
9060 +static int ltv350qv_suspend(struct spi_device *spi,
9061 + pm_message_t state, u32 level)
9062 +{
9063 + struct ltv350qv *lcd = dev_get_drvdata(&spi->dev);
9064 +
9065 + if (level == SUSPEND_POWER_DOWN)
9066 + return ltv350qv_power(lcd, FB_BLANK_POWERDOWN);
9067 +
9068 + return 0;
9069 +}
9070 +
9071 +static int ltv350qv_resume(struct spi_device *spi, u32 level)
9072 +{
9073 + struct ltv350qv *lcd = dev_get_drvdata(&spi->dev);
9074 +
9075 + if (level == RESUME_POWER_ON)
9076 + return ltv350qv_power(lcd, FB_BLANK_UNBLANK);
9077 +
9078 + return 0;
9079 +}
9080 +#else
9081 +#define ltv350qv_suspend NULL
9082 +#define ltv350qv_resume NULL
9083 +#endif
9084 +
9085 +/* Power down all displays on reboot, poweroff or halt */
9086 +static void ltv350qv_shutdown(struct spi_device *spi)
9087 +{
9088 + struct ltv350qv *lcd = dev_get_drvdata(&spi->dev);
9089 +
9090 + ltv350qv_power(lcd, FB_BLANK_POWERDOWN);
9091 +}
9092 +
9093 +static struct spi_driver ltv350qv_driver = {
9094 + .driver = {
9095 + .name = "ltv350qv",
9096 + .bus = &spi_bus_type,
9097 + .owner = THIS_MODULE,
9098 + },
9099 +
9100 + .probe = ltv350qv_probe,
9101 + .remove = __devexit_p(ltv350qv_remove),
9102 + .shutdown = ltv350qv_shutdown,
9103 + .suspend = ltv350qv_suspend,
9104 + .resume = ltv350qv_resume,
9105 +};
9106 +
9107 +static int __init ltv350qv_init(void)
9108 +{
9109 + return spi_register_driver(&ltv350qv_driver);
9110 +}
9111 +
9112 +static void __exit ltv350qv_exit(void)
9113 +{
9114 + spi_unregister_driver(&ltv350qv_driver);
9115 +}
9116 +module_init(ltv350qv_init);
9117 +module_exit(ltv350qv_exit);
9118 +
9119 +MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
9120 +MODULE_DESCRIPTION("Samsung LTV350QV LCD Driver");
9121 +MODULE_LICENSE("GPL");
9122 diff --git a/drivers/video/backlight/ltv350qv.h b/drivers/video/backlight/ltv350qv.h
9123 new file mode 100644
9124 index 0000000..189112e
9125 --- /dev/null
9126 +++ b/drivers/video/backlight/ltv350qv.h
9127 @@ -0,0 +1,95 @@
9128 +/*
9129 + * Register definitions for Samsung LTV350QV Quarter VGA LCD Panel
9130 + *
9131 + * Copyright (C) 2006, 2007 Atmel Corporation
9132 + *
9133 + * This program is free software; you can redistribute it and/or modify
9134 + * it under the terms of the GNU General Public License version 2 as
9135 + * published by the Free Software Foundation.
9136 + */
9137 +#ifndef __LTV350QV_H
9138 +#define __LTV350QV_H
9139 +
9140 +#define LTV_OPC_INDEX 0x74
9141 +#define LTV_OPC_DATA 0x76
9142 +
9143 +#define LTV_ID 0x00 /* ID Read */
9144 +#define LTV_IFCTL 0x01 /* Display Interface Control */
9145 +#define LTV_DATACTL 0x02 /* Display Data Control */
9146 +#define LTV_ENTRY_MODE 0x03 /* Entry Mode */
9147 +#define LTV_GATECTL1 0x04 /* Gate Control 1 */
9148 +#define LTV_GATECTL2 0x05 /* Gate Control 2 */
9149 +#define LTV_VBP 0x06 /* Vertical Back Porch */
9150 +#define LTV_HBP 0x07 /* Horizontal Back Porch */
9151 +#define LTV_SOTCTL 0x08 /* Source Output Timing Control */
9152 +#define LTV_PWRCTL1 0x09 /* Power Control 1 */
9153 +#define LTV_PWRCTL2 0x0a /* Power Control 2 */
9154 +#define LTV_GAMMA(x) (0x10 + (x)) /* Gamma control */
9155 +
9156 +/* Bit definitions for LTV_IFCTL */
9157 +#define LTV_IM (1 << 15)
9158 +#define LTV_NMD (1 << 14)
9159 +#define LTV_SSMD (1 << 13)
9160 +#define LTV_REV (1 << 7)
9161 +#define LTV_NL(x) (((x) & 0x001f) << 0)
9162 +
9163 +/* Bit definitions for LTV_DATACTL */
9164 +#define LTV_DS_SAME (0 << 12)
9165 +#define LTV_DS_D_TO_S (1 << 12)
9166 +#define LTV_DS_S_TO_D (2 << 12)
9167 +#define LTV_CHS_384 (0 << 9)
9168 +#define LTV_CHS_480 (1 << 9)
9169 +#define LTV_CHS_492 (2 << 9)
9170 +#define LTV_DF_RGB (0 << 6)
9171 +#define LTV_DF_RGBX (1 << 6)
9172 +#define LTV_DF_XRGB (2 << 6)
9173 +#define LTV_RGB_RGB (0 << 2)
9174 +#define LTV_RGB_BGR (1 << 2)
9175 +#define LTV_RGB_GRB (2 << 2)
9176 +#define LTV_RGB_RBG (3 << 2)
9177 +
9178 +/* Bit definitions for LTV_ENTRY_MODE */
9179 +#define LTV_VSPL_ACTIVE_LOW (0 << 15)
9180 +#define LTV_VSPL_ACTIVE_HIGH (1 << 15)
9181 +#define LTV_HSPL_ACTIVE_LOW (0 << 14)
9182 +#define LTV_HSPL_ACTIVE_HIGH (1 << 14)
9183 +#define LTV_DPL_SAMPLE_RISING (0 << 13)
9184 +#define LTV_DPL_SAMPLE_FALLING (1 << 13)
9185 +#define LTV_EPL_ACTIVE_LOW (0 << 12)
9186 +#define LTV_EPL_ACTIVE_HIGH (1 << 12)
9187 +#define LTV_SS_LEFT_TO_RIGHT (0 << 8)
9188 +#define LTV_SS_RIGHT_TO_LEFT (1 << 8)
9189 +#define LTV_STB (1 << 1)
9190 +
9191 +/* Bit definitions for LTV_GATECTL1 */
9192 +#define LTV_CLW(x) (((x) & 0x0007) << 12)
9193 +#define LTV_GAON (1 << 5)
9194 +#define LTV_SDR (1 << 3)
9195 +
9196 +/* Bit definitions for LTV_GATECTL2 */
9197 +#define LTV_NW_INV_FRAME (0 << 14)
9198 +#define LTV_NW_INV_1LINE (1 << 14)
9199 +#define LTV_NW_INV_2LINE (2 << 14)
9200 +#define LTV_DSC (1 << 12)
9201 +#define LTV_GIF (1 << 8)
9202 +#define LTV_FHN (1 << 7)
9203 +#define LTV_FTI(x) (((x) & 0x0003) << 4)
9204 +#define LTV_FWI(x) (((x) & 0x0003) << 0)
9205 +
9206 +/* Bit definitions for LTV_SOTCTL */
9207 +#define LTV_SDT(x) (((x) & 0x0007) << 10)
9208 +#define LTV_EQ(x) (((x) & 0x0007) << 2)
9209 +
9210 +/* Bit definitions for LTV_PWRCTL1 */
9211 +#define LTV_VCOM_DISABLE (1 << 14)
9212 +#define LTV_VCOMOUT_ENABLE (1 << 11)
9213 +#define LTV_POWER_ON (1 << 9)
9214 +#define LTV_DRIVE_CURRENT(x) (((x) & 0x0007) << 4) /* 0=off, 5=max */
9215 +#define LTV_SUPPLY_CURRENT(x) (((x) & 0x0007) << 0) /* 0=off, 5=max */
9216 +
9217 +/* Bit definitions for LTV_PWRCTL2 */
9218 +#define LTV_VCOML_ENABLE (1 << 13)
9219 +#define LTV_VCOML_VOLTAGE(x) (((x) & 0x001f) << 8) /* 0=1V, 31=-1V */
9220 +#define LTV_VCOMH_VOLTAGE(x) (((x) & 0x001f) << 0) /* 0=3V, 31=4.5V */
9221 +
9222 +#endif /* __LTV350QV_H */
9223 diff --git a/include/asm-avr32/arch-at32ap/board.h b/include/asm-avr32/arch-at32ap/board.h
9224 index 0215965..e1318e0 100644
9225 --- a/include/asm-avr32/arch-at32ap/board.h
9226 +++ b/include/asm-avr32/arch-at32ap/board.h
9227 @@ -6,6 +6,8 @@
9228
9229 #include <linux/types.h>
9230
9231 +#define GPIO_PIN_NONE (-1)
9232 +
9233 /* Add basic devices: system manager, interrupt controller, portmuxes, etc. */
9234 void at32_add_system_devices(void);
9235
9236 @@ -31,11 +33,26 @@ struct spi_board_info;
9237 struct platform_device *
9238 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n);
9239
9240 +struct platform_device *at32_add_device_twi(unsigned int id);
9241 +
9242 +struct mci_platform_data {
9243 + int detect_pin;
9244 + int wp_pin;
9245 +};
9246 +struct platform_device *
9247 +at32_add_device_mci(unsigned int id, struct mci_platform_data *data);
9248 +
9249 struct atmel_lcdfb_info;
9250 struct platform_device *
9251 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
9252 unsigned long fbmem_start, unsigned long fbmem_len);
9253
9254 +struct usba_platform_data {
9255 + int vbus_pin;
9256 +};
9257 +struct platform_device *
9258 +at32_add_device_usba(unsigned int id, struct usba_platform_data *data);
9259 +
9260 /* depending on what's hooked up, not all SSC pins will be used */
9261 #define ATMEL_SSC_TK 0x01
9262 #define ATMEL_SSC_TF 0x02
9263 @@ -50,4 +67,7 @@ at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
9264 struct platform_device *
9265 at32_add_device_ssc(unsigned int id, unsigned int flags);
9266
9267 +struct platform_device *at32_add_device_ac97c(unsigned int id);
9268 +struct platform_device *at32_add_device_abdac(unsigned int id);
9269 +
9270 #endif /* __ASM_ARCH_BOARD_H */
9271 diff --git a/include/asm-avr32/arch-at32ap/portmux.h b/include/asm-avr32/arch-at32ap/portmux.h
9272 index 9930871..135e034 100644
9273 --- a/include/asm-avr32/arch-at32ap/portmux.h
9274 +++ b/include/asm-avr32/arch-at32ap/portmux.h
9275 @@ -19,10 +19,23 @@
9276 #define AT32_GPIOF_OUTPUT 0x00000002 /* (OUT) Enable output driver */
9277 #define AT32_GPIOF_HIGH 0x00000004 /* (OUT) Set output high */
9278 #define AT32_GPIOF_DEGLITCH 0x00000008 /* (IN) Filter glitches */
9279 +#define AT32_GPIOF_MULTIDRV 0x00000010 /* Enable multidriver option */
9280
9281 void at32_select_periph(unsigned int pin, unsigned int periph,
9282 unsigned long flags);
9283 void at32_select_gpio(unsigned int pin, unsigned long flags);
9284 void at32_reserve_pin(unsigned int pin);
9285
9286 +#ifdef CONFIG_GPIO_DEV
9287 +
9288 +/* Gang allocators and accessors; used by the GPIO /dev driver */
9289 +int at32_gpio_port_is_valid(unsigned int port);
9290 +int at32_select_gpio_pins(unsigned int port, u32 pins, u32 oe_mask);
9291 +void at32_deselect_pins(unsigned int port, u32 pins);
9292 +
9293 +u32 at32_gpio_get_value_multiple(unsigned int port, u32 pins);
9294 +void at32_gpio_set_value_multiple(unsigned int port, u32 value, u32 mask);
9295 +
9296 +#endif /* CONFIG_GPIO_DEV */
9297 +
9298 #endif /* __ASM_ARCH_PORTMUX_H__ */
9299 diff --git a/include/asm-avr32/arch-at32ap/smc.h b/include/asm-avr32/arch-at32ap/smc.h
9300 index 07152b7..c98eea4 100644
9301 --- a/include/asm-avr32/arch-at32ap/smc.h
9302 +++ b/include/asm-avr32/arch-at32ap/smc.h
9303 @@ -15,22 +15,50 @@
9304 /*
9305 * All timing parameters are in nanoseconds.
9306 */
9307 +struct smc_timing {
9308 + /* Delay from address valid to assertion of given strobe */
9309 + int ncs_read_setup;
9310 + int nrd_setup;
9311 + int ncs_write_setup;
9312 + int nwe_setup;
9313 +
9314 + /* Pulse length of given strobe */
9315 + int ncs_read_pulse;
9316 + int nrd_pulse;
9317 + int ncs_write_pulse;
9318 + int nwe_pulse;
9319 +
9320 + /* Total cycle length of given operation */
9321 + int read_cycle;
9322 + int write_cycle;
9323 +
9324 + /* Minimal recovery times, will extend cycle if needed */
9325 + int ncs_read_recover;
9326 + int nrd_recover;
9327 + int ncs_write_recover;
9328 + int nwe_recover;
9329 +};
9330 +
9331 +/*
9332 + * All timing parameters are in clock cycles.
9333 + */
9334 struct smc_config {
9335 +
9336 /* Delay from address valid to assertion of given strobe */
9337 - u16 ncs_read_setup;
9338 - u16 nrd_setup;
9339 - u16 ncs_write_setup;
9340 - u16 nwe_setup;
9341 + u8 ncs_read_setup;
9342 + u8 nrd_setup;
9343 + u8 ncs_write_setup;
9344 + u8 nwe_setup;
9345
9346 /* Pulse length of given strobe */
9347 - u16 ncs_read_pulse;
9348 - u16 nrd_pulse;
9349 - u16 ncs_write_pulse;
9350 - u16 nwe_pulse;
9351 + u8 ncs_read_pulse;
9352 + u8 nrd_pulse;
9353 + u8 ncs_write_pulse;
9354 + u8 nwe_pulse;
9355
9356 /* Total cycle length of given operation */
9357 - u16 read_cycle;
9358 - u16 write_cycle;
9359 + u8 read_cycle;
9360 + u8 write_cycle;
9361
9362 /* Bus width in bytes */
9363 u8 bus_width;
9364 @@ -76,6 +104,9 @@ struct smc_config {
9365 unsigned int tdf_mode:1;
9366 };
9367
9368 +extern void smc_set_timing(struct smc_config *config,
9369 + const struct smc_timing *timing);
9370 +
9371 extern int smc_set_configuration(int cs, const struct smc_config *config);
9372 extern struct smc_config *smc_get_configuration(int cs);
9373
9374 diff --git a/include/asm-avr32/dma-controller.h b/include/asm-avr32/dma-controller.h
9375 new file mode 100644
9376 index 0000000..56a4965
9377 --- /dev/null
9378 +++ b/include/asm-avr32/dma-controller.h
9379 @@ -0,0 +1,166 @@
9380 +/*
9381 + * Copyright (C) 2005-2006 Atmel Corporation
9382 + *
9383 + * This program is free software; you can redistribute it and/or modify
9384 + * it under the terms of the GNU General Public License version 2 as
9385 + * published by the Free Software Foundation.
9386 + */
9387 +#ifndef __ASM_AVR32_DMA_CONTROLLER_H
9388 +#define __ASM_AVR32_DMA_CONTROLLER_H
9389 +
9390 +#include <linux/device.h>
9391 +
9392 +#define DMA_DIR_MEM_TO_MEM 0x0000
9393 +#define DMA_DIR_MEM_TO_PERIPH 0x0001
9394 +#define DMA_DIR_PERIPH_TO_MEM 0x0002
9395 +#define DMA_DIR_PERIPH_TO_PERIPH 0x0003
9396 +
9397 +#define DMA_WIDTH_8BIT 0
9398 +#define DMA_WIDTH_16BIT 1
9399 +#define DMA_WIDTH_32BIT 2
9400 +
9401 +struct dma_request {
9402 + struct dma_controller *dmac;
9403 + struct list_head list;
9404 +
9405 + unsigned short channel;
9406 +
9407 + void (*xfer_complete)(struct dma_request *req);
9408 + void (*block_complete)(struct dma_request *req);
9409 + void (*error)(struct dma_request *req);
9410 +};
9411 +
9412 +struct dma_request_sg {
9413 + struct dma_request req;
9414 +
9415 + int nr_sg;
9416 + struct scatterlist *sg;
9417 + unsigned long block_size;
9418 + unsigned int nr_blocks;
9419 +
9420 + dma_addr_t data_reg;
9421 + unsigned short periph_id;
9422 +
9423 + unsigned char direction;
9424 + unsigned char width;
9425 +};
9426 +#define to_dma_request_sg(_req) \
9427 + container_of(_req, struct dma_request_sg, req)
9428 +
9429 +struct dma_request_cyclic {
9430 + struct dma_request req;
9431 +
9432 + int periods;
9433 + unsigned long buffer_size;
9434 +
9435 + dma_addr_t buffer_start;
9436 + dma_addr_t data_reg;
9437 +
9438 + unsigned short periph_id;
9439 + unsigned char direction;
9440 + unsigned char width;
9441 +
9442 + void *dev_id;
9443 +};
9444 +#define to_dma_request_cyclic(_req) \
9445 + container_of(_req, struct dma_request_cyclic, req)
9446 +
9447 +struct dma_request_memcpy {
9448 + struct dma_request req;
9449 +
9450 + dma_addr_t src_addr;
9451 + unsigned int src_width;
9452 + unsigned int src_stride;
9453 +
9454 + dma_addr_t dst_addr;
9455 + unsigned int dst_width;
9456 + unsigned int dst_stride;
9457 +
9458 + size_t length;
9459 +
9460 + unsigned short src_reverse:1;
9461 + unsigned short dst_reverse:1;
9462 +};
9463 +#define to_dma_request_memcpy(_req) \
9464 + container_of(_req, struct dma_request_memcpy, req)
9465 +
9466 +struct dma_controller {
9467 + struct list_head list;
9468 + int id;
9469 + struct device *dev;
9470 +
9471 + int (*alloc_channel)(struct dma_controller *dmac);
9472 + void (*release_channel)(struct dma_controller *dmac,
9473 + int channel);
9474 + int (*prepare_request_sg)(struct dma_controller *dmac,
9475 + struct dma_request_sg *req);
9476 + int (*prepare_request_cyclic)(struct dma_controller *dmac,
9477 + struct dma_request_cyclic *req);
9478 + int (*prepare_request_memcpy)(struct dma_controller *dmac,
9479 + struct dma_request_memcpy *req);
9480 + int (*start_request)(struct dma_controller *dmac,
9481 + unsigned int channel);
9482 + int (*stop_request)(struct dma_controller *dmac,
9483 + unsigned int channel);
9484 + dma_addr_t (*get_current_pos)(struct dma_controller *dmac,
9485 + unsigned int channel);
9486 +};
9487 +
9488 +static inline int
9489 +dma_alloc_channel(struct dma_controller *dmac)
9490 +{
9491 + return dmac->alloc_channel(dmac);
9492 +}
9493 +
9494 +static inline void
9495 +dma_release_channel(struct dma_controller *dmac, int chan)
9496 +{
9497 + dmac->release_channel(dmac, chan);
9498 +}
9499 +
9500 +static inline int
9501 +dma_prepare_request_sg(struct dma_controller *dmac,
9502 + struct dma_request_sg *req)
9503 +{
9504 + return dmac->prepare_request_sg(dmac, req);
9505 +}
9506 +
9507 +static inline int
9508 +dma_prepare_request_cyclic(struct dma_controller *dmac,
9509 + struct dma_request_cyclic *req)
9510 +{
9511 + return dmac->prepare_request_cyclic(dmac, req);
9512 +}
9513 +
9514 +static inline int
9515 +dma_prepare_request_memcpy(struct dma_controller *dmac,
9516 + struct dma_request_memcpy *req)
9517 +{
9518 + return dmac->prepare_request_memcpy(dmac, req);
9519 +}
9520 +
9521 +static inline int
9522 +dma_start_request(struct dma_controller *dmac,
9523 + unsigned int channel)
9524 +{
9525 + return dmac->start_request(dmac, channel);
9526 +}
9527 +
9528 +static inline int
9529 +dma_stop_request(struct dma_controller *dmac,
9530 + unsigned int channel)
9531 +{
9532 + return dmac->stop_request(dmac, channel);
9533 +}
9534 +
9535 +static inline dma_addr_t
9536 +dma_get_current_pos(struct dma_controller *dmac,
9537 + unsigned int channel)
9538 +{
9539 + return dmac->get_current_pos(dmac, channel);
9540 +}
9541 +
9542 +extern int register_dma_controller(struct dma_controller *dmac);
9543 +extern struct dma_controller *find_dma_controller(int id);
9544 +
9545 +#endif /* __ASM_AVR32_DMA_CONTROLLER_H */
9546 diff --git a/include/asm-avr32/dma-mapping.h b/include/asm-avr32/dma-mapping.h
9547 index 21bb60b..81e3426 100644
9548 --- a/include/asm-avr32/dma-mapping.h
9549 +++ b/include/asm-avr32/dma-mapping.h
9550 @@ -264,7 +264,11 @@ static inline void
9551 dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
9552 size_t size, enum dma_data_direction direction)
9553 {
9554 - dma_cache_sync(dev, bus_to_virt(dma_handle), size, direction);
9555 + /*
9556 + * No need to do anything since the CPU isn't supposed to
9557 + * touch this memory after we flushed it at mapping- or
9558 + * sync-for-device time.
9559 + */
9560 }
9561
9562 static inline void
9563 @@ -309,12 +313,11 @@ static inline void
9564 dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
9565 int nents, enum dma_data_direction direction)
9566 {
9567 - int i;
9568 -
9569 - for (i = 0; i < nents; i++) {
9570 - dma_cache_sync(dev, page_address(sg[i].page) + sg[i].offset,
9571 - sg[i].length, direction);
9572 - }
9573 + /*
9574 + * No need to do anything since the CPU isn't supposed to
9575 + * touch this memory after we flushed it at mapping- or
9576 + * sync-for-device time.
9577 + */
9578 }
9579
9580 static inline void
9581 diff --git a/include/asm-avr32/system.h b/include/asm-avr32/system.h
9582 index a8236ba..dc2d527 100644
9583 --- a/include/asm-avr32/system.h
9584 +++ b/include/asm-avr32/system.h
9585 @@ -73,11 +73,16 @@ extern struct task_struct *__switch_to(struct task_struct *,
9586
9587 extern void __xchg_called_with_bad_pointer(void);
9588
9589 -#ifdef __CHECKER__
9590 -extern unsigned long __builtin_xchg(void *ptr, unsigned long x);
9591 -#endif
9592 +static inline unsigned long xchg_u32(u32 val, volatile u32 *m)
9593 +{
9594 + u32 ret;
9595
9596 -#define xchg_u32(val, m) __builtin_xchg((void *)m, val)
9597 + asm volatile("xchg %[ret], %[m], %[val]"
9598 + : [ret] "=&r"(ret), "=m"(*m)
9599 + : "m"(*m), [m] "r"(m), [val] "r"(val)
9600 + : "memory");
9601 + return ret;
9602 +}
9603
9604 static inline unsigned long __xchg(unsigned long x,
9605 volatile void *ptr,
9606 diff --git a/include/asm-avr32/unistd.h b/include/asm-avr32/unistd.h
9607 index 3b4e35b..de09009 100644
9608 --- a/include/asm-avr32/unistd.h
9609 +++ b/include/asm-avr32/unistd.h
9610 @@ -303,6 +303,19 @@
9611 #ifdef __KERNEL__
9612 #define NR_syscalls 282
9613
9614 +/* Old stuff */
9615 +#define __IGNORE_uselib
9616 +#define __IGNORE_mmap
9617 +
9618 +/* NUMA stuff */
9619 +#define __IGNORE_mbind
9620 +#define __IGNORE_get_mempolicy
9621 +#define __IGNORE_set_mempolicy
9622 +#define __IGNORE_migrate_pages
9623 +#define __IGNORE_move_pages
9624 +
9625 +/* SMP stuff */
9626 +#define __IGNORE_getcpu
9627
9628 #define __ARCH_WANT_IPC_PARSE_VERSION
9629 #define __ARCH_WANT_STAT64
9630 diff --git a/include/linux/atmel-ssc.h b/include/linux/atmel-ssc.h
9631 new file mode 100644
9632 index 0000000..0602339
9633 --- /dev/null
9634 +++ b/include/linux/atmel-ssc.h
9635 @@ -0,0 +1,312 @@
9636 +#ifndef __INCLUDE_ATMEL_SSC_H
9637 +#define __INCLUDE_ATMEL_SSC_H
9638 +
9639 +#include <linux/platform_device.h>
9640 +#include <linux/list.h>
9641 +
9642 +struct ssc_device {
9643 + struct list_head list;
9644 + void __iomem *regs;
9645 + struct platform_device *pdev;
9646 + struct clk *clk;
9647 + int user;
9648 + int irq;
9649 +};
9650 +
9651 +struct ssc_device * __must_check ssc_request(unsigned int ssc_num);
9652 +void ssc_free(struct ssc_device *ssc);
9653 +
9654 +/* SSC register offsets */
9655 +
9656 +/* SSC Control Register */
9657 +#define SSC_CR 0x00000000
9658 +#define SSC_CR_RXDIS_SIZE 1
9659 +#define SSC_CR_RXDIS_OFFSET 1
9660 +#define SSC_CR_RXEN_SIZE 1
9661 +#define SSC_CR_RXEN_OFFSET 0
9662 +#define SSC_CR_SWRST_SIZE 1
9663 +#define SSC_CR_SWRST_OFFSET 15
9664 +#define SSC_CR_TXDIS_SIZE 1
9665 +#define SSC_CR_TXDIS_OFFSET 9
9666 +#define SSC_CR_TXEN_SIZE 1
9667 +#define SSC_CR_TXEN_OFFSET 8
9668 +
9669 +/* SSC Clock Mode Register */
9670 +#define SSC_CMR 0x00000004
9671 +#define SSC_CMR_DIV_SIZE 12
9672 +#define SSC_CMR_DIV_OFFSET 0
9673 +
9674 +/* SSC Receive Clock Mode Register */
9675 +#define SSC_RCMR 0x00000010
9676 +#define SSC_RCMR_CKG_SIZE 2
9677 +#define SSC_RCMR_CKG_OFFSET 6
9678 +#define SSC_RCMR_CKI_SIZE 1
9679 +#define SSC_RCMR_CKI_OFFSET 5
9680 +#define SSC_RCMR_CKO_SIZE 3
9681 +#define SSC_RCMR_CKO_OFFSET 2
9682 +#define SSC_RCMR_CKS_SIZE 2
9683 +#define SSC_RCMR_CKS_OFFSET 0
9684 +#define SSC_RCMR_PERIOD_SIZE 8
9685 +#define SSC_RCMR_PERIOD_OFFSET 24
9686 +#define SSC_RCMR_START_SIZE 4
9687 +#define SSC_RCMR_START_OFFSET 8
9688 +#define SSC_RCMR_STOP_SIZE 1
9689 +#define SSC_RCMR_STOP_OFFSET 12
9690 +#define SSC_RCMR_STTDLY_SIZE 8
9691 +#define SSC_RCMR_STTDLY_OFFSET 16
9692 +
9693 +/* SSC Receive Frame Mode Register */
9694 +#define SSC_RFMR 0x00000014
9695 +#define SSC_RFMR_DATLEN_SIZE 5
9696 +#define SSC_RFMR_DATLEN_OFFSET 0
9697 +#define SSC_RFMR_DATNB_SIZE 4
9698 +#define SSC_RFMR_DATNB_OFFSET 8
9699 +#define SSC_RFMR_FSEDGE_SIZE 1
9700 +#define SSC_RFMR_FSEDGE_OFFSET 24
9701 +#define SSC_RFMR_FSLEN_SIZE 4
9702 +#define SSC_RFMR_FSLEN_OFFSET 16
9703 +#define SSC_RFMR_FSOS_SIZE 4
9704 +#define SSC_RFMR_FSOS_OFFSET 20
9705 +#define SSC_RFMR_LOOP_SIZE 1
9706 +#define SSC_RFMR_LOOP_OFFSET 5
9707 +#define SSC_RFMR_MSBF_SIZE 1
9708 +#define SSC_RFMR_MSBF_OFFSET 7
9709 +
9710 +/* SSC Transmit Clock Mode Register */
9711 +#define SSC_TCMR 0x00000018
9712 +#define SSC_TCMR_CKG_SIZE 2
9713 +#define SSC_TCMR_CKG_OFFSET 6
9714 +#define SSC_TCMR_CKI_SIZE 1
9715 +#define SSC_TCMR_CKI_OFFSET 5
9716 +#define SSC_TCMR_CKO_SIZE 3
9717 +#define SSC_TCMR_CKO_OFFSET 2
9718 +#define SSC_TCMR_CKS_SIZE 2
9719 +#define SSC_TCMR_CKS_OFFSET 0
9720 +#define SSC_TCMR_PERIOD_SIZE 8
9721 +#define SSC_TCMR_PERIOD_OFFSET 24
9722 +#define SSC_TCMR_START_SIZE 4
9723 +#define SSC_TCMR_START_OFFSET 8
9724 +#define SSC_TCMR_STTDLY_SIZE 8
9725 +#define SSC_TCMR_STTDLY_OFFSET 16
9726 +
9727 +/* SSC Transmit Frame Mode Register */
9728 +#define SSC_TFMR 0x0000001c
9729 +#define SSC_TFMR_DATDEF_SIZE 1
9730 +#define SSC_TFMR_DATDEF_OFFSET 5
9731 +#define SSC_TFMR_DATLEN_SIZE 5
9732 +#define SSC_TFMR_DATLEN_OFFSET 0
9733 +#define SSC_TFMR_DATNB_SIZE 4
9734 +#define SSC_TFMR_DATNB_OFFSET 8
9735 +#define SSC_TFMR_FSDEN_SIZE 1
9736 +#define SSC_TFMR_FSDEN_OFFSET 23
9737 +#define SSC_TFMR_FSEDGE_SIZE 1
9738 +#define SSC_TFMR_FSEDGE_OFFSET 24
9739 +#define SSC_TFMR_FSLEN_SIZE 4
9740 +#define SSC_TFMR_FSLEN_OFFSET 16
9741 +#define SSC_TFMR_FSOS_SIZE 3
9742 +#define SSC_TFMR_FSOS_OFFSET 20
9743 +#define SSC_TFMR_MSBF_SIZE 1
9744 +#define SSC_TFMR_MSBF_OFFSET 7
9745 +
9746 +/* SSC Receive Hold Register */
9747 +#define SSC_RHR 0x00000020
9748 +#define SSC_RHR_RDAT_SIZE 32
9749 +#define SSC_RHR_RDAT_OFFSET 0
9750 +
9751 +/* SSC Transmit Hold Register */
9752 +#define SSC_THR 0x00000024
9753 +#define SSC_THR_TDAT_SIZE 32
9754 +#define SSC_THR_TDAT_OFFSET 0
9755 +
9756 +/* SSC Receive Sync. Holding Register */
9757 +#define SSC_RSHR 0x00000030
9758 +#define SSC_RSHR_RSDAT_SIZE 16
9759 +#define SSC_RSHR_RSDAT_OFFSET 0
9760 +
9761 +/* SSC Transmit Sync. Holding Register */
9762 +#define SSC_TSHR 0x00000034
9763 +#define SSC_TSHR_TSDAT_SIZE 16
9764 +#define SSC_TSHR_RSDAT_OFFSET 0
9765 +
9766 +/* SSC Receive Compare 0 Register */
9767 +#define SSC_RC0R 0x00000038
9768 +#define SSC_RC0R_CP0_SIZE 16
9769 +#define SSC_RC0R_CP0_OFFSET 0
9770 +
9771 +/* SSC Receive Compare 1 Register */
9772 +#define SSC_RC1R 0x0000003c
9773 +#define SSC_RC1R_CP1_SIZE 16
9774 +#define SSC_RC1R_CP1_OFFSET 0
9775 +
9776 +/* SSC Status Register */
9777 +#define SSC_SR 0x00000040
9778 +#define SSC_SR_CP0_SIZE 1
9779 +#define SSC_SR_CP0_OFFSET 8
9780 +#define SSC_SR_CP1_SIZE 1
9781 +#define SSC_SR_CP1_OFFSET 9
9782 +#define SSC_SR_ENDRX_SIZE 1
9783 +#define SSC_SR_ENDRX_OFFSET 6
9784 +#define SSC_SR_ENDTX_SIZE 1
9785 +#define SSC_SR_ENDTX_OFFSET 2
9786 +#define SSC_SR_OVRUN_SIZE 1
9787 +#define SSC_SR_OVRUN_OFFSET 5
9788 +#define SSC_SR_RXBUFF_SIZE 1
9789 +#define SSC_SR_RXBUFF_OFFSET 7
9790 +#define SSC_SR_RXEN_SIZE 1
9791 +#define SSC_SR_RXEN_OFFSET 17
9792 +#define SSC_SR_RXRDY_SIZE 1
9793 +#define SSC_SR_RXRDY_OFFSET 4
9794 +#define SSC_SR_RXSYN_SIZE 1
9795 +#define SSC_SR_RXSYN_OFFSET 11
9796 +#define SSC_SR_TXBUFE_SIZE 1
9797 +#define SSC_SR_TXBUFE_OFFSET 3
9798 +#define SSC_SR_TXEMPTY_SIZE 1
9799 +#define SSC_SR_TXEMPTY_OFFSET 1
9800 +#define SSC_SR_TXEN_SIZE 1
9801 +#define SSC_SR_TXEN_OFFSET 16
9802 +#define SSC_SR_TXRDY_SIZE 1
9803 +#define SSC_SR_TXRDY_OFFSET 0
9804 +#define SSC_SR_TXSYN_SIZE 1
9805 +#define SSC_SR_TXSYN_OFFSET 10
9806 +
9807 +/* SSC Interrupt Enable Register */
9808 +#define SSC_IER 0x00000044
9809 +#define SSC_IER_CP0_SIZE 1
9810 +#define SSC_IER_CP0_OFFSET 8
9811 +#define SSC_IER_CP1_SIZE 1
9812 +#define SSC_IER_CP1_OFFSET 9
9813 +#define SSC_IER_ENDRX_SIZE 1
9814 +#define SSC_IER_ENDRX_OFFSET 6
9815 +#define SSC_IER_ENDTX_SIZE 1
9816 +#define SSC_IER_ENDTX_OFFSET 2
9817 +#define SSC_IER_OVRUN_SIZE 1
9818 +#define SSC_IER_OVRUN_OFFSET 5
9819 +#define SSC_IER_RXBUFF_SIZE 1
9820 +#define SSC_IER_RXBUFF_OFFSET 7
9821 +#define SSC_IER_RXRDY_SIZE 1
9822 +#define SSC_IER_RXRDY_OFFSET 4
9823 +#define SSC_IER_RXSYN_SIZE 1
9824 +#define SSC_IER_RXSYN_OFFSET 11
9825 +#define SSC_IER_TXBUFE_SIZE 1
9826 +#define SSC_IER_TXBUFE_OFFSET 3
9827 +#define SSC_IER_TXEMPTY_SIZE 1
9828 +#define SSC_IER_TXEMPTY_OFFSET 1
9829 +#define SSC_IER_TXRDY_SIZE 1
9830 +#define SSC_IER_TXRDY_OFFSET 0
9831 +#define SSC_IER_TXSYN_SIZE 1
9832 +#define SSC_IER_TXSYN_OFFSET 10
9833 +
9834 +/* SSC Interrupt Disable Register */
9835 +#define SSC_IDR 0x00000048
9836 +#define SSC_IDR_CP0_SIZE 1
9837 +#define SSC_IDR_CP0_OFFSET 8
9838 +#define SSC_IDR_CP1_SIZE 1
9839 +#define SSC_IDR_CP1_OFFSET 9
9840 +#define SSC_IDR_ENDRX_SIZE 1
9841 +#define SSC_IDR_ENDRX_OFFSET 6
9842 +#define SSC_IDR_ENDTX_SIZE 1
9843 +#define SSC_IDR_ENDTX_OFFSET 2
9844 +#define SSC_IDR_OVRUN_SIZE 1
9845 +#define SSC_IDR_OVRUN_OFFSET 5
9846 +#define SSC_IDR_RXBUFF_SIZE 1
9847 +#define SSC_IDR_RXBUFF_OFFSET 7
9848 +#define SSC_IDR_RXRDY_SIZE 1
9849 +#define SSC_IDR_RXRDY_OFFSET 4
9850 +#define SSC_IDR_RXSYN_SIZE 1
9851 +#define SSC_IDR_RXSYN_OFFSET 11
9852 +#define SSC_IDR_TXBUFE_SIZE 1
9853 +#define SSC_IDR_TXBUFE_OFFSET 3
9854 +#define SSC_IDR_TXEMPTY_SIZE 1
9855 +#define SSC_IDR_TXEMPTY_OFFSET 1
9856 +#define SSC_IDR_TXRDY_SIZE 1
9857 +#define SSC_IDR_TXRDY_OFFSET 0
9858 +#define SSC_IDR_TXSYN_SIZE 1
9859 +#define SSC_IDR_TXSYN_OFFSET 10
9860 +
9861 +/* SSC Interrupt Mask Register */
9862 +#define SSC_IMR 0x0000004c
9863 +#define SSC_IMR_CP0_SIZE 1
9864 +#define SSC_IMR_CP0_OFFSET 8
9865 +#define SSC_IMR_CP1_SIZE 1
9866 +#define SSC_IMR_CP1_OFFSET 9
9867 +#define SSC_IMR_ENDRX_SIZE 1
9868 +#define SSC_IMR_ENDRX_OFFSET 6
9869 +#define SSC_IMR_ENDTX_SIZE 1
9870 +#define SSC_IMR_ENDTX_OFFSET 2
9871 +#define SSC_IMR_OVRUN_SIZE 1
9872 +#define SSC_IMR_OVRUN_OFFSET 5
9873 +#define SSC_IMR_RXBUFF_SIZE 1
9874 +#define SSC_IMR_RXBUFF_OFFSET 7
9875 +#define SSC_IMR_RXRDY_SIZE 1
9876 +#define SSC_IMR_RXRDY_OFFSET 4
9877 +#define SSC_IMR_RXSYN_SIZE 1
9878 +#define SSC_IMR_RXSYN_OFFSET 11
9879 +#define SSC_IMR_TXBUFE_SIZE 1
9880 +#define SSC_IMR_TXBUFE_OFFSET 3
9881 +#define SSC_IMR_TXEMPTY_SIZE 1
9882 +#define SSC_IMR_TXEMPTY_OFFSET 1
9883 +#define SSC_IMR_TXRDY_SIZE 1
9884 +#define SSC_IMR_TXRDY_OFFSET 0
9885 +#define SSC_IMR_TXSYN_SIZE 1
9886 +#define SSC_IMR_TXSYN_OFFSET 10
9887 +
9888 +/* SSC PDC Receive Pointer Register */
9889 +#define SSC_PDC_RPR 0x00000100
9890 +
9891 +/* SSC PDC Receive Counter Register */
9892 +#define SSC_PDC_RCR 0x00000104
9893 +
9894 +/* SSC PDC Transmit Pointer Register */
9895 +#define SSC_PDC_TPR 0x00000108
9896 +
9897 +/* SSC PDC Receive Next Pointer Register */
9898 +#define SSC_PDC_RNPR 0x00000110
9899 +
9900 +/* SSC PDC Receive Next Counter Register */
9901 +#define SSC_PDC_RNCR 0x00000114
9902 +
9903 +/* SSC PDC Transmit Counter Register */
9904 +#define SSC_PDC_TCR 0x0000010c
9905 +
9906 +/* SSC PDC Transmit Next Pointer Register */
9907 +#define SSC_PDC_TNPR 0x00000118
9908 +
9909 +/* SSC PDC Transmit Next Counter Register */
9910 +#define SSC_PDC_TNCR 0x0000011c
9911 +
9912 +/* SSC PDC Transfer Control Register */
9913 +#define SSC_PDC_PTCR 0x00000120
9914 +#define SSC_PDC_PTCR_RXTDIS_SIZE 1
9915 +#define SSC_PDC_PTCR_RXTDIS_OFFSET 1
9916 +#define SSC_PDC_PTCR_RXTEN_SIZE 1
9917 +#define SSC_PDC_PTCR_RXTEN_OFFSET 0
9918 +#define SSC_PDC_PTCR_TXTDIS_SIZE 1
9919 +#define SSC_PDC_PTCR_TXTDIS_OFFSET 9
9920 +#define SSC_PDC_PTCR_TXTEN_SIZE 1
9921 +#define SSC_PDC_PTCR_TXTEN_OFFSET 8
9922 +
9923 +/* SSC PDC Transfer Status Register */
9924 +#define SSC_PDC_PTSR 0x00000124
9925 +#define SSC_PDC_PTSR_RXTEN_SIZE 1
9926 +#define SSC_PDC_PTSR_RXTEN_OFFSET 0
9927 +#define SSC_PDC_PTSR_TXTEN_SIZE 1
9928 +#define SSC_PDC_PTSR_TXTEN_OFFSET 8
9929 +
9930 +/* Bit manipulation macros */
9931 +#define SSC_BIT(name) \
9932 + (1 << SSC_##name##_OFFSET)
9933 +#define SSC_BF(name, value) \
9934 + (((value) & ((1 << SSC_##name##_SIZE) - 1)) \
9935 + << SSC_##name##_OFFSET)
9936 +#define SSC_BFEXT(name, value) \
9937 + (((value) >> SSC_##name##_OFFSET) \
9938 + & ((1 << SSC_##name##_SIZE) - 1))
9939 +#define SSC_BFINS(name, value, old) \
9940 + (((old) & ~(((1 << SSC_##name##_SIZE) - 1) \
9941 + << SSC_##name##_OFFSET)) | SSC_BF(name, value))
9942 +
9943 +/* Register access macros */
9944 +#define ssc_readl(base, reg) __raw_readl(base + SSC_##reg)
9945 +#define ssc_writel(base, reg, value) __raw_writel((value), base + SSC_##reg)
9946 +
9947 +#endif /* __INCLUDE_ATMEL_SSC_H */
9948 diff --git a/include/linux/spi/at73c213.h b/include/linux/spi/at73c213.h
9949 new file mode 100644
9950 index 0000000..0f20a70
9951 --- /dev/null
9952 +++ b/include/linux/spi/at73c213.h
9953 @@ -0,0 +1,25 @@
9954 +/*
9955 + * Board-specific data used to set up AT73c213 audio DAC driver.
9956 + */
9957 +
9958 +#ifndef __LINUX_SPI_AT73C213_H
9959 +#define __LINUX_SPI_AT73C213_H
9960 +
9961 +/**
9962 + * at73c213_board_info - how the external DAC is wired to the device.
9963 + *
9964 + * @ssc_id: SSC platform_driver id the DAC shall use to stream the audio.
9965 + * @dac_clk: the external clock used to provide master clock to the DAC.
9966 + * @shortname: a short discription for the DAC, seen by userspace tools.
9967 + *
9968 + * This struct contains the configuration of the hardware connection to the
9969 + * external DAC. The DAC needs a master clock and a I2S audio stream. It also
9970 + * provides a name which is used to identify it in userspace tools.
9971 + */
9972 +struct at73c213_board_info {
9973 + int ssc_id;
9974 + struct clk *dac_clk;
9975 + char shortname[32];
9976 +};
9977 +
9978 +#endif /* __LINUX_SPI_AT73C213_H */
9979 diff --git a/scripts/checkstack.pl b/scripts/checkstack.pl
9980 index f7844f6..6631586 100755
9981 --- a/scripts/checkstack.pl
9982 +++ b/scripts/checkstack.pl
9983 @@ -12,6 +12,7 @@
9984 # sh64 port by Paul Mundt
9985 # Random bits by Matt Mackall <mpm@selenic.com>
9986 # M68k port by Geert Uytterhoeven and Andreas Schwab
9987 +# AVR32 port by Haavard Skinnemoen <hskinnemoen@atmel.com>
9988 #
9989 # Usage:
9990 # objdump -d vmlinux | stackcheck.pl [arch]
9991 @@ -37,6 +38,10 @@ my (@stack, $re, $x, $xs);
9992 if ($arch eq 'arm') {
9993 #c0008ffc: e24dd064 sub sp, sp, #100 ; 0x64
9994 $re = qr/.*sub.*sp, sp, #(([0-9]{2}|[3-9])[0-9]{2})/o;
9995 + } elsif ($arch eq 'avr32') {
9996 + #8000008a: 20 1d sub sp,4
9997 + #80000ca8: fa cd 05 b0 sub sp,sp,1456
9998 + $re = qr/^.*sub.*sp.*,([0-9]{1,8})/o;
9999 } elsif ($arch =~ /^i[3456]86$/) {
10000 #c0105234: 81 ec ac 05 00 00 sub $0x5ac,%esp
10001 $re = qr/^.*[as][du][db] \$(0x$x{1,8}),\%esp$/o;
10002 diff --git a/sound/Kconfig b/sound/Kconfig
10003 index e48b9b3..29a9979 100644
10004 --- a/sound/Kconfig
10005 +++ b/sound/Kconfig
10006 @@ -63,6 +63,12 @@ source "sound/aoa/Kconfig"
10007
10008 source "sound/arm/Kconfig"
10009
10010 +source "sound/avr32/Kconfig"
10011 +
10012 +if SPI
10013 +source "sound/spi/Kconfig"
10014 +endif
10015 +
10016 source "sound/mips/Kconfig"
10017
10018 source "sound/sh/Kconfig"
10019 diff --git a/sound/Makefile b/sound/Makefile
10020 index 3ead922..e655df7 100644
10021 --- a/sound/Makefile
10022 +++ b/sound/Makefile
10023 @@ -5,7 +5,8 @@ obj-$(CONFIG_SOUND) += soundcore.o
10024 obj-$(CONFIG_SOUND_PRIME) += sound_firmware.o
10025 obj-$(CONFIG_SOUND_PRIME) += oss/
10026 obj-$(CONFIG_DMASOUND) += oss/
10027 -obj-$(CONFIG_SND) += core/ i2c/ drivers/ isa/ pci/ ppc/ arm/ sh/ synth/ usb/ sparc/ parisc/ pcmcia/ mips/ soc/
10028 +obj-$(CONFIG_SND) += core/ i2c/ drivers/ isa/ pci/ ppc/ arm/ avr32/ sh/ synth/ usb/ sparc/ spi/ parisc/ pcmcia/ mips/ soc/
10029 +
10030 obj-$(CONFIG_SND_AOA) += aoa/
10031
10032 # This one must be compilable even if sound is configured out
10033 diff --git a/sound/avr32/Kconfig b/sound/avr32/Kconfig
10034 new file mode 100644
10035 index 0000000..17d1d91
10036 --- /dev/null
10037 +++ b/sound/avr32/Kconfig
10038 @@ -0,0 +1,11 @@
10039 +menu "AVR32 devices"
10040 + depends on SND != n && AVR32
10041 +
10042 +config SND_ATMEL_AC97
10043 + tristate "Atmel AC97 Controller Driver"
10044 + select SND_PCM
10045 + select SND_AC97_CODEC
10046 + help
10047 + ALSA sound driver for the Atmel AC97 controller.
10048 +
10049 +endmenu
10050 diff --git a/sound/avr32/Makefile b/sound/avr32/Makefile
10051 new file mode 100644
10052 index 0000000..5d87d0e
10053 --- /dev/null
10054 +++ b/sound/avr32/Makefile
10055 @@ -0,0 +1,3 @@
10056 +snd-atmel-ac97-objs := ac97c.o
10057 +
10058 +obj-$(CONFIG_SND_ATMEL_AC97) += snd-atmel-ac97.o
10059 diff --git a/sound/avr32/ac97c.c b/sound/avr32/ac97c.c
10060 new file mode 100644
10061 index 0000000..0ec0b1c
10062 --- /dev/null
10063 +++ b/sound/avr32/ac97c.c
10064 @@ -0,0 +1,914 @@
10065 +/*
10066 + * Driver for the Atmel AC97 controller
10067 + *
10068 + * Copyright (C) 2005-2007 Atmel Corporation
10069 + *
10070 + * This program is free software; you can redistribute it and/or modify it
10071 + * under the terms of the GNU General Public License version 2 as published by
10072 + * the Free Software Foundation.
10073 + */
10074 +#include <linux/clk.h>
10075 +#include <linux/delay.h>
10076 +#include <linux/dma-mapping.h>
10077 +#include <linux/init.h>
10078 +#include <linux/interrupt.h>
10079 +#include <linux/module.h>
10080 +#include <linux/platform_device.h>
10081 +#include <linux/mutex.h>
10082 +#include <linux/io.h>
10083 +
10084 +#include <sound/driver.h>
10085 +#include <sound/core.h>
10086 +#include <sound/initval.h>
10087 +#include <sound/pcm.h>
10088 +#include <sound/pcm_params.h>
10089 +#include <sound/ac97_codec.h>
10090 +#include <sound/memalloc.h>
10091 +
10092 +#include <asm/dma-controller.h>
10093 +
10094 +#include "ac97c.h"
10095 +
10096 +/* Serialize access to opened */
10097 +static DEFINE_MUTEX(opened_mutex);
10098 +
10099 +struct atmel_ac97_dma_info {
10100 + struct dma_request_cyclic req_tx;
10101 + struct dma_request_cyclic req_rx;
10102 + unsigned short rx_periph_id;
10103 + unsigned short tx_periph_id;
10104 +};
10105 +
10106 +struct atmel_ac97 {
10107 + /* Serialize access to opened */
10108 + spinlock_t lock;
10109 + void __iomem *regs;
10110 + struct snd_pcm_substream *playback_substream;
10111 + struct snd_pcm_substream *capture_substream;
10112 + struct snd_card *card;
10113 + struct snd_pcm *pcm;
10114 + struct snd_ac97 *ac97;
10115 + struct snd_ac97_bus *ac97_bus;
10116 + int opened;
10117 + int period;
10118 + u64 cur_format;
10119 + unsigned int cur_rate;
10120 + struct clk *mck;
10121 + struct platform_device *pdev;
10122 + struct atmel_ac97_dma_info dma;
10123 +};
10124 +
10125 +#define get_chip(card) ((struct atmel_ac97 *)(card)->private_data)
10126 +
10127 +#define ac97c_writel(chip, reg, val) \
10128 + __raw_writel((val), (chip)->regs + AC97C_##reg)
10129 +#define ac97c_readl(chip, reg) \
10130 + __raw_readl((chip)->regs + AC97C_##reg)
10131 +
10132 +/*
10133 + * PCM part
10134 + */
10135 +static struct snd_pcm_hardware snd_atmel_ac97_playback_hw = {
10136 + .info = (SNDRV_PCM_INFO_INTERLEAVED
10137 + | SNDRV_PCM_INFO_MMAP
10138 + | SNDRV_PCM_INFO_MMAP_VALID
10139 + | SNDRV_PCM_INFO_BLOCK_TRANSFER
10140 + | SNDRV_PCM_INFO_JOINT_DUPLEX),
10141 + .formats = (SNDRV_PCM_FMTBIT_S16_BE
10142 + | SNDRV_PCM_FMTBIT_S16_LE),
10143 + .rates = (SNDRV_PCM_RATE_CONTINUOUS),
10144 + .rate_min = 4000,
10145 + .rate_max = 48000,
10146 + .channels_min = 1,
10147 + .channels_max = 6,
10148 + .buffer_bytes_max = 64*1024,
10149 + .period_bytes_min = 512,
10150 + .period_bytes_max = 4095,
10151 + .periods_min = 8,
10152 + .periods_max = 1024,
10153 +};
10154 +
10155 +static struct snd_pcm_hardware snd_atmel_ac97_capture_hw = {
10156 + .info = (SNDRV_PCM_INFO_INTERLEAVED
10157 + | SNDRV_PCM_INFO_MMAP
10158 + | SNDRV_PCM_INFO_MMAP_VALID
10159 + | SNDRV_PCM_INFO_BLOCK_TRANSFER
10160 + | SNDRV_PCM_INFO_JOINT_DUPLEX),
10161 + .formats = (SNDRV_PCM_FMTBIT_S16_BE
10162 + | SNDRV_PCM_FMTBIT_S16_LE),
10163 + .rates = (SNDRV_PCM_RATE_CONTINUOUS),
10164 + .rate_min = 4000,
10165 + .rate_max = 48000,
10166 + .channels_min = 1,
10167 + .channels_max = 2,
10168 + .buffer_bytes_max = 64*1024,
10169 + .period_bytes_min = 512,
10170 + .period_bytes_max = 4095,
10171 + .periods_min = 8,
10172 + .periods_max = 1024,
10173 +};
10174 +
10175 +/*
10176 + * PCM functions
10177 + */
10178 +static int
10179 +snd_atmel_ac97_playback_open(struct snd_pcm_substream *substream)
10180 +{
10181 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
10182 + struct snd_pcm_runtime *runtime = substream->runtime;
10183 +
10184 + mutex_lock(&opened_mutex);
10185 + chip->opened++;
10186 + runtime->hw = snd_atmel_ac97_playback_hw;
10187 + if (chip->cur_rate) {
10188 + runtime->hw.rate_min = chip->cur_rate;
10189 + runtime->hw.rate_max = chip->cur_rate;
10190 + }
10191 + if (chip->cur_format)
10192 + runtime->hw.formats = (1ULL << chip->cur_format);
10193 + mutex_unlock(&opened_mutex);
10194 + chip->playback_substream = substream;
10195 + chip->period = 0;
10196 + return 0;
10197 +}
10198 +
10199 +static int
10200 +snd_atmel_ac97_capture_open(struct snd_pcm_substream *substream)
10201 +{
10202 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
10203 + struct snd_pcm_runtime *runtime = substream->runtime;
10204 +
10205 + mutex_lock(&opened_mutex);
10206 + chip->opened++;
10207 + runtime->hw = snd_atmel_ac97_capture_hw;
10208 + if (chip->cur_rate) {
10209 + runtime->hw.rate_min = chip->cur_rate;
10210 + runtime->hw.rate_max = chip->cur_rate;
10211 + }
10212 + if (chip->cur_format)
10213 + runtime->hw.formats = (1ULL << chip->cur_format);
10214 + mutex_unlock(&opened_mutex);
10215 + chip->capture_substream = substream;
10216 + chip->period = 0;
10217 + return 0;
10218 +}
10219 +
10220 +static int snd_atmel_ac97_playback_close(struct snd_pcm_substream *substream)
10221 +{
10222 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
10223 + mutex_lock(&opened_mutex);
10224 + chip->opened--;
10225 + if (!chip->opened) {
10226 + chip->cur_rate = 0;
10227 + chip->cur_format = 0;
10228 + }
10229 + mutex_unlock(&opened_mutex);
10230 + return 0;
10231 +}
10232 +
10233 +static int snd_atmel_ac97_capture_close(struct snd_pcm_substream *substream)
10234 +{
10235 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
10236 + mutex_lock(&opened_mutex);
10237 + chip->opened--;
10238 + if (!chip->opened) {
10239 + chip->cur_rate = 0;
10240 + chip->cur_format = 0;
10241 + }
10242 + mutex_unlock(&opened_mutex);
10243 + return 0;
10244 +}
10245 +
10246 +static int
10247 +snd_atmel_ac97_playback_hw_params(struct snd_pcm_substream *substream,
10248 + struct snd_pcm_hw_params *hw_params)
10249 +{
10250 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
10251 + int err;
10252 +
10253 + err = snd_pcm_lib_malloc_pages(substream,
10254 + params_buffer_bytes(hw_params));
10255 + if (err < 0)
10256 + return err;
10257 +
10258 + /* Set restrictions to params */
10259 + mutex_lock(&opened_mutex);
10260 + chip->cur_rate = params_rate(hw_params);
10261 + chip->cur_format = params_format(hw_params);
10262 + mutex_unlock(&opened_mutex);
10263 +
10264 + return 0;
10265 +}
10266 +
10267 +static int
10268 +snd_atmel_ac97_capture_hw_params(struct snd_pcm_substream *substream,
10269 + struct snd_pcm_hw_params *hw_params)
10270 +{
10271 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
10272 + int err;
10273 +
10274 + err = snd_pcm_lib_malloc_pages(substream,
10275 + params_buffer_bytes(hw_params));
10276 + if (err < 0)
10277 + return err;
10278 +
10279 + /* Set restrictions to params */
10280 + mutex_lock(&opened_mutex);
10281 + chip->cur_rate = params_rate(hw_params);
10282 + chip->cur_format = params_format(hw_params);
10283 + mutex_unlock(&opened_mutex);
10284 +
10285 + return 0;
10286 +}
10287 +
10288 +static int snd_atmel_ac97_playback_hw_free(struct snd_pcm_substream *substream)
10289 +{
10290 + return snd_pcm_lib_free_pages(substream);
10291 +}
10292 +
10293 +static int snd_atmel_ac97_capture_hw_free(struct snd_pcm_substream *substream)
10294 +{
10295 +
10296 + return snd_pcm_lib_free_pages(substream);
10297 +}
10298 +
10299 +static int snd_atmel_ac97_playback_prepare(struct snd_pcm_substream *substream)
10300 +{
10301 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
10302 + struct platform_device *pdev = chip->pdev;
10303 + struct snd_pcm_runtime *runtime = substream->runtime;
10304 + int block_size = frames_to_bytes(runtime, runtime->period_size);
10305 + unsigned long word = 0;
10306 + unsigned long buffer_size = 0;
10307 +
10308 + dma_sync_single_for_device(&pdev->dev, runtime->dma_addr,
10309 + block_size * 2, DMA_TO_DEVICE);
10310 +
10311 + /* Assign slots to channels */
10312 + switch (substream->runtime->channels) {
10313 + case 1:
10314 + word |= AC97C_CH_ASSIGN(PCM_LEFT, A);
10315 + break;
10316 + case 2:
10317 + /* Assign Left and Right slot to Channel A */
10318 + word |= AC97C_CH_ASSIGN(PCM_LEFT, A)
10319 + | AC97C_CH_ASSIGN(PCM_RIGHT, A);
10320 + break;
10321 + default:
10322 + /* TODO: support more than two channels */
10323 + return -EINVAL;
10324 + break;
10325 + }
10326 + ac97c_writel(chip, OCA, word);
10327 +
10328 + /* Configure sample format and size */
10329 + word = AC97C_CMR_PDCEN | AC97C_CMR_SIZE_16;
10330 +
10331 + switch (runtime->format) {
10332 + case SNDRV_PCM_FORMAT_S16_LE:
10333 + word |= AC97C_CMR_CEM_LITTLE;
10334 + break;
10335 + case SNDRV_PCM_FORMAT_S16_BE: /* fall through */
10336 + default:
10337 + word &= ~AC97C_CMR_CEM_LITTLE;
10338 + break;
10339 + }
10340 +
10341 + ac97c_writel(chip, CAMR, word);
10342 +
10343 + /* Set variable rate if needed */
10344 + if (runtime->rate != 48000) {
10345 + word = ac97c_readl(chip, MR);
10346 + word |= AC97C_MR_VRA;
10347 + ac97c_writel(chip, MR, word);
10348 + } else {
10349 + /* Clear Variable Rate Bit */
10350 + word = ac97c_readl(chip, MR);
10351 + word &= ~AC97C_MR_VRA;
10352 + ac97c_writel(chip, MR, word);
10353 + }
10354 +
10355 + /* Set rate */
10356 + snd_ac97_set_rate(chip->ac97, AC97_PCM_FRONT_DAC_RATE, runtime->rate);
10357 +
10358 + buffer_size = frames_to_bytes(runtime, runtime->period_size) *
10359 + runtime->periods;
10360 +
10361 + chip->dma.req_tx.buffer_size = buffer_size;
10362 + chip->dma.req_tx.periods = runtime->periods;
10363 +
10364 + BUG_ON(chip->dma.req_tx.buffer_size !=
10365 + (chip->dma.req_tx.periods *
10366 + frames_to_bytes(runtime, runtime->period_size)));
10367 +
10368 + chip->dma.req_tx.buffer_start = runtime->dma_addr;
10369 + chip->dma.req_tx.data_reg = (dma_addr_t)(chip->regs + AC97C_CATHR + 2);
10370 + chip->dma.req_tx.periph_id = chip->dma.tx_periph_id;
10371 + chip->dma.req_tx.direction = DMA_DIR_MEM_TO_PERIPH;
10372 + chip->dma.req_tx.width = DMA_WIDTH_16BIT;
10373 + chip->dma.req_tx.dev_id = chip;
10374 +
10375 + return 0;
10376 +}
10377 +
10378 +static int snd_atmel_ac97_capture_prepare(struct snd_pcm_substream *substream)
10379 +{
10380 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
10381 + struct platform_device *pdev = chip->pdev;
10382 + struct snd_pcm_runtime *runtime = substream->runtime;
10383 + int block_size = frames_to_bytes(runtime, runtime->period_size);
10384 + unsigned long word = 0;
10385 + unsigned long buffer_size = 0;
10386 +
10387 + dma_sync_single_for_device(&pdev->dev, runtime->dma_addr,
10388 + block_size * 2, DMA_FROM_DEVICE);
10389 +
10390 + /* Assign slots to channels */
10391 + switch (substream->runtime->channels) {
10392 + case 1:
10393 + word |= AC97C_CH_ASSIGN(PCM_LEFT, A);
10394 + break;
10395 + case 2:
10396 + /* Assign Left and Right slot to Channel A */
10397 + word |= AC97C_CH_ASSIGN(PCM_LEFT, A)
10398 + | AC97C_CH_ASSIGN(PCM_RIGHT, A);
10399 + break;
10400 + default:
10401 + /* TODO: support more than two channels */
10402 + return -EINVAL;
10403 + break;
10404 + }
10405 + ac97c_writel(chip, ICA, word);
10406 +
10407 + /* Configure sample format and size */
10408 + word = AC97C_CMR_PDCEN | AC97C_CMR_SIZE_16;
10409 +
10410 + switch (runtime->format) {
10411 + case SNDRV_PCM_FORMAT_S16_LE:
10412 + word |= AC97C_CMR_CEM_LITTLE;
10413 + break;
10414 + case SNDRV_PCM_FORMAT_S16_BE:
10415 + default:
10416 + word &= ~(AC97C_CMR_CEM_LITTLE);
10417 + break;
10418 + }
10419 +
10420 + ac97c_writel(chip, CAMR, word);
10421 +
10422 + /* Set variable rate if needed */
10423 + if (runtime->rate != 48000) {
10424 + word = ac97c_readl(chip, MR);
10425 + word |= AC97C_MR_VRA;
10426 + ac97c_writel(chip, MR, word);
10427 + } else {
10428 + /* Clear Variable Rate Bit */
10429 + word = ac97c_readl(chip, MR);
10430 + word &= ~(AC97C_MR_VRA);
10431 + ac97c_writel(chip, MR, word);
10432 + }
10433 +
10434 + /* Set rate */
10435 + snd_ac97_set_rate(chip->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate);
10436 +
10437 + buffer_size = frames_to_bytes(runtime, runtime->period_size) *
10438 + runtime->periods;
10439 +
10440 + chip->dma.req_rx.buffer_size = buffer_size;
10441 + chip->dma.req_rx.periods = runtime->periods;
10442 +
10443 + BUG_ON(chip->dma.req_rx.buffer_size !=
10444 + (chip->dma.req_rx.periods *
10445 + frames_to_bytes(runtime, runtime->period_size)));
10446 +
10447 + chip->dma.req_rx.buffer_start = runtime->dma_addr;
10448 + chip->dma.req_rx.data_reg = (dma_addr_t)(chip->regs + AC97C_CARHR + 2);
10449 + chip->dma.req_rx.periph_id = chip->dma.rx_periph_id;
10450 + chip->dma.req_rx.direction = DMA_DIR_PERIPH_TO_MEM;
10451 + chip->dma.req_rx.width = DMA_WIDTH_16BIT;
10452 + chip->dma.req_rx.dev_id = chip;
10453 +
10454 + return 0;
10455 +}
10456 +
10457 + static int
10458 +snd_atmel_ac97_playback_trigger(struct snd_pcm_substream *substream, int cmd)
10459 +{
10460 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
10461 + unsigned long camr;
10462 + int flags, err = 0;
10463 +
10464 + spin_lock_irqsave(&chip->lock, flags);
10465 + camr = ac97c_readl(chip, CAMR);
10466 +
10467 + switch (cmd) {
10468 + case SNDRV_PCM_TRIGGER_START:
10469 + err = dma_prepare_request_cyclic(chip->dma.req_tx.req.dmac,
10470 + &chip->dma.req_tx);
10471 + dma_start_request(chip->dma.req_tx.req.dmac,
10472 + chip->dma.req_tx.req.channel);
10473 + camr |= AC97C_CMR_CENA;
10474 + break;
10475 + case SNDRV_PCM_TRIGGER_STOP:
10476 + err = dma_stop_request(chip->dma.req_tx.req.dmac,
10477 + chip->dma.req_tx.req.channel);
10478 + if (chip->opened <= 1)
10479 + camr &= ~AC97C_CMR_CENA;
10480 + break;
10481 + default:
10482 + err = -EINVAL;
10483 + break;
10484 + }
10485 +
10486 + ac97c_writel(chip, CAMR, camr);
10487 +
10488 + spin_unlock_irqrestore(&chip->lock, flags);
10489 + return err;
10490 +}
10491 +
10492 + static int
10493 +snd_atmel_ac97_capture_trigger(struct snd_pcm_substream *substream, int cmd)
10494 +{
10495 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
10496 + unsigned long camr;
10497 + int flags, err = 0;
10498 +
10499 + spin_lock_irqsave(&chip->lock, flags);
10500 + camr = ac97c_readl(chip, CAMR);
10501 +
10502 + switch (cmd) {
10503 + case SNDRV_PCM_TRIGGER_START:
10504 + err = dma_prepare_request_cyclic(chip->dma.req_rx.req.dmac,
10505 + &chip->dma.req_rx);
10506 + dma_start_request(chip->dma.req_rx.req.dmac,
10507 + chip->dma.req_rx.req.channel);
10508 + camr |= AC97C_CMR_CENA;
10509 + break;
10510 + case SNDRV_PCM_TRIGGER_STOP:
10511 + err = dma_stop_request(chip->dma.req_rx.req.dmac,
10512 + chip->dma.req_rx.req.channel);
10513 + mutex_lock(&opened_mutex);
10514 + if (chip->opened <= 1)
10515 + camr &= ~AC97C_CMR_CENA;
10516 + mutex_unlock(&opened_mutex);
10517 + break;
10518 + default:
10519 + err = -EINVAL;
10520 + break;
10521 + }
10522 +
10523 + ac97c_writel(chip, CAMR, camr);
10524 +
10525 + spin_unlock_irqrestore(&chip->lock, flags);
10526 + return err;
10527 +}
10528 +
10529 + static snd_pcm_uframes_t
10530 +snd_atmel_ac97_playback_pointer(struct snd_pcm_substream *substream)
10531 +{
10532 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
10533 + struct snd_pcm_runtime *runtime = substream->runtime;
10534 + snd_pcm_uframes_t pos;
10535 + unsigned long bytes;
10536 +
10537 + bytes = (dma_get_current_pos
10538 + (chip->dma.req_tx.req.dmac,
10539 + chip->dma.req_tx.req.channel) - runtime->dma_addr);
10540 + pos = bytes_to_frames(runtime, bytes);
10541 + if (pos >= runtime->buffer_size)
10542 + pos -= runtime->buffer_size;
10543 +
10544 + return pos;
10545 +}
10546 +
10547 + static snd_pcm_uframes_t
10548 +snd_atmel_ac97_capture_pointer(struct snd_pcm_substream *substream)
10549 +{
10550 + struct atmel_ac97 *chip = snd_pcm_substream_chip(substream);
10551 + struct snd_pcm_runtime *runtime = substream->runtime;
10552 + snd_pcm_uframes_t pos;
10553 + unsigned long bytes;
10554 +
10555 + bytes = (dma_get_current_pos
10556 + (chip->dma.req_rx.req.dmac,
10557 + chip->dma.req_rx.req.channel)
10558 + - runtime->dma_addr);
10559 + pos = bytes_to_frames(runtime, bytes);
10560 + if (pos >= runtime->buffer_size)
10561 + pos -= runtime->buffer_size;
10562 +
10563 +
10564 + return pos;
10565 +}
10566 +
10567 +static struct snd_pcm_ops atmel_ac97_playback_ops = {
10568 + .open = snd_atmel_ac97_playback_open,
10569 + .close = snd_atmel_ac97_playback_close,
10570 + .ioctl = snd_pcm_lib_ioctl,
10571 + .hw_params = snd_atmel_ac97_playback_hw_params,
10572 + .hw_free = snd_atmel_ac97_playback_hw_free,
10573 + .prepare = snd_atmel_ac97_playback_prepare,
10574 + .trigger = snd_atmel_ac97_playback_trigger,
10575 + .pointer = snd_atmel_ac97_playback_pointer,
10576 +};
10577 +
10578 +static struct snd_pcm_ops atmel_ac97_capture_ops = {
10579 + .open = snd_atmel_ac97_capture_open,
10580 + .close = snd_atmel_ac97_capture_close,
10581 + .ioctl = snd_pcm_lib_ioctl,
10582 + .hw_params = snd_atmel_ac97_capture_hw_params,
10583 + .hw_free = snd_atmel_ac97_capture_hw_free,
10584 + .prepare = snd_atmel_ac97_capture_prepare,
10585 + .trigger = snd_atmel_ac97_capture_trigger,
10586 + .pointer = snd_atmel_ac97_capture_pointer,
10587 +};
10588 +
10589 +static struct ac97_pcm atmel_ac97_pcm_defs[] __devinitdata = {
10590 + /* Playback */
10591 + {
10592 + .exclusive = 1,
10593 + .r = { {
10594 + .slots = ((1 << AC97_SLOT_PCM_LEFT)
10595 + | (1 << AC97_SLOT_PCM_RIGHT)
10596 + | (1 << AC97_SLOT_PCM_CENTER)
10597 + | (1 << AC97_SLOT_PCM_SLEFT)
10598 + | (1 << AC97_SLOT_PCM_SRIGHT)
10599 + | (1 << AC97_SLOT_LFE)),
10600 + } }
10601 + },
10602 + /* PCM in */
10603 + {
10604 + .stream = 1,
10605 + .exclusive = 1,
10606 + .r = { {
10607 + .slots = ((1 << AC97_SLOT_PCM_LEFT)
10608 + | (1 << AC97_SLOT_PCM_RIGHT)),
10609 + } }
10610 + },
10611 + /* Mic in */
10612 + {
10613 + .stream = 1,
10614 + .exclusive = 1,
10615 + .r = { {
10616 + .slots = (1<<AC97_SLOT_MIC),
10617 + } }
10618 + },
10619 +};
10620 +
10621 +static int __devinit snd_atmel_ac97_pcm_new(struct atmel_ac97 *chip)
10622 +{
10623 + struct snd_pcm *pcm;
10624 + int err;
10625 +
10626 + err = snd_ac97_pcm_assign(chip->ac97_bus,
10627 + ARRAY_SIZE(atmel_ac97_pcm_defs),
10628 + atmel_ac97_pcm_defs);
10629 + if (err)
10630 + return err;
10631 +
10632 + err = snd_pcm_new(chip->card, "Atmel-AC97", 0, 1, 1, &pcm);
10633 + if (err)
10634 + return err;
10635 +
10636 + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
10637 + &atmel_ac97_playback_ops);
10638 +
10639 + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
10640 + &atmel_ac97_capture_ops);
10641 +
10642 + snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
10643 + &chip->pdev->dev,
10644 + 128 * 1024, 128 * 1024);
10645 +
10646 + pcm->private_data = chip;
10647 + pcm->info_flags = 0;
10648 + strcpy(pcm->name, "Atmel-AC97");
10649 + chip->pcm = pcm;
10650 +
10651 + return 0;
10652 +}
10653 +
10654 +/*
10655 + * Mixer part.
10656 + */
10657 +static int snd_atmel_ac97_mixer_new(struct atmel_ac97 *chip)
10658 +{
10659 + int err;
10660 + struct snd_ac97_template template;
10661 +
10662 + memset(&template, 0, sizeof(template));
10663 + template.private_data = chip;
10664 + err = snd_ac97_mixer(chip->ac97_bus, &template, &chip->ac97);
10665 +
10666 + return err;
10667 +}
10668 +
10669 +static void atmel_ac97_error(struct dma_request *_req)
10670 +{
10671 + struct dma_request_cyclic *req = to_dma_request_cyclic(_req);
10672 + struct atmel_ac97 *chip = req->dev_id;
10673 +
10674 + dev_dbg(&chip->pdev->dev, "DMA Controller error, channel %d\n",
10675 + req->req.channel);
10676 +}
10677 +
10678 +static void atmel_ac97_block_complete(struct dma_request *_req)
10679 +{
10680 + struct dma_request_cyclic *req = to_dma_request_cyclic(_req);
10681 + struct atmel_ac97 *chip = req->dev_id;
10682 + if (req->periph_id == chip->dma.tx_periph_id)
10683 + snd_pcm_period_elapsed(chip->playback_substream);
10684 + else
10685 + snd_pcm_period_elapsed(chip->capture_substream);
10686 +}
10687 +
10688 +/*
10689 + * Codec part.
10690 + */
10691 +static void snd_atmel_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
10692 + unsigned short val)
10693 +{
10694 + struct atmel_ac97 *chip = get_chip(ac97);
10695 + unsigned long word;
10696 + int timeout = 40;
10697 +
10698 + word = (reg & 0x7f) << 16 | val;
10699 +
10700 + do {
10701 + if (ac97c_readl(chip, COSR) & AC97C_CSR_TXRDY) {
10702 + ac97c_writel(chip, COTHR, word);
10703 + return;
10704 + }
10705 + udelay(1);
10706 + } while (--timeout);
10707 +
10708 + dev_dbg(&chip->pdev->dev, "codec write timeout\n");
10709 +}
10710 +
10711 +static unsigned short snd_atmel_ac97_read(struct snd_ac97 *ac97,
10712 + unsigned short reg)
10713 +{
10714 + struct atmel_ac97 *chip = get_chip(ac97);
10715 + unsigned long word;
10716 + int timeout = 40;
10717 + int write = 10;
10718 +
10719 + word = (0x80 | (reg & 0x7f)) << 16;
10720 +
10721 + if ((ac97c_readl(chip, COSR) & AC97C_CSR_RXRDY) != 0)
10722 + ac97c_readl(chip, CORHR);
10723 +
10724 +retry_write:
10725 + timeout = 40;
10726 +
10727 + do {
10728 + if ((ac97c_readl(chip, COSR) & AC97C_CSR_TXRDY) != 0) {
10729 + ac97c_writel(chip, COTHR, word);
10730 + goto read_reg;
10731 + }
10732 + mdelay(10);
10733 + } while (--timeout);
10734 +
10735 + if (!--write)
10736 + goto timed_out;
10737 + goto retry_write;
10738 +
10739 +read_reg:
10740 + do {
10741 + if ((ac97c_readl(chip, COSR) & AC97C_CSR_RXRDY) != 0) {
10742 + unsigned short val = ac97c_readl(chip, CORHR);
10743 + return val;
10744 + }
10745 + mdelay(10);
10746 + } while (--timeout);
10747 +
10748 + if (!--write)
10749 + goto timed_out;
10750 + goto retry_write;
10751 +
10752 +timed_out:
10753 + dev_dbg(&chip->pdev->dev, "codec read timeout\n");
10754 + return 0xffff;
10755 +}
10756 +
10757 +static void snd_atmel_ac97_reset(struct atmel_ac97 *chip)
10758 +{
10759 + ac97c_writel(chip, MR, AC97C_MR_WRST);
10760 + mdelay(1);
10761 + ac97c_writel(chip, MR, AC97C_MR_ENA);
10762 +}
10763 +
10764 +static void snd_atmel_ac97_destroy(struct snd_card *card)
10765 +{
10766 + struct atmel_ac97 *chip = get_chip(card);
10767 +
10768 + if (chip->regs)
10769 + iounmap(chip->regs);
10770 +
10771 + if (chip->mck) {
10772 + clk_disable(chip->mck);
10773 + clk_put(chip->mck);
10774 + }
10775 +
10776 + if (chip->dma.req_tx.req.dmac) {
10777 + dma_release_channel(chip->dma.req_tx.req.dmac,
10778 + chip->dma.req_tx.req.channel);
10779 + }
10780 + if (chip->dma.req_rx.req.dmac) {
10781 + dma_release_channel(chip->dma.req_rx.req.dmac,
10782 + chip->dma.req_rx.req.channel);
10783 + }
10784 +}
10785 +
10786 +static int __devinit snd_atmel_ac97_create(struct snd_card *card,
10787 + struct platform_device *pdev)
10788 +{
10789 + static struct snd_ac97_bus_ops ops = {
10790 + .write = snd_atmel_ac97_write,
10791 + .read = snd_atmel_ac97_read,
10792 + };
10793 + struct atmel_ac97 *chip = get_chip(card);
10794 + struct resource *regs;
10795 + struct clk *mck;
10796 + int err;
10797 +
10798 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
10799 + if (!regs)
10800 + return -ENXIO;
10801 +
10802 + mck = clk_get(&pdev->dev, "pclk");
10803 + if (IS_ERR(mck))
10804 + return PTR_ERR(mck);
10805 + clk_enable(mck);
10806 + chip->mck = mck;
10807 +
10808 + card->private_free = snd_atmel_ac97_destroy;
10809 +
10810 + spin_lock_init(&chip->lock);
10811 + chip->card = card;
10812 + chip->pdev = pdev;
10813 +
10814 + chip->regs = ioremap(regs->start, regs->end - regs->start + 1);
10815 + if (!chip->regs)
10816 + return -ENOMEM;
10817 +
10818 + snd_card_set_dev(card, &pdev->dev);
10819 +
10820 + err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus);
10821 +
10822 + return err;
10823 +}
10824 +
10825 +static int __devinit snd_atmel_ac97_probe(struct platform_device *pdev)
10826 +{
10827 + static int dev;
10828 + struct snd_card *card;
10829 + struct atmel_ac97 *chip;
10830 + int err;
10831 + int ch;
10832 +
10833 + mutex_init(&opened_mutex);
10834 +
10835 + err = -ENOMEM;
10836 + card = snd_card_new(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
10837 + THIS_MODULE, sizeof(struct atmel_ac97));
10838 + if (!card)
10839 + goto out;
10840 + chip = get_chip(card);
10841 +
10842 + err = snd_atmel_ac97_create(card, pdev);
10843 + if (err)
10844 + goto out_free_card;
10845 +
10846 + snd_atmel_ac97_reset(chip);
10847 +
10848 + err = snd_atmel_ac97_mixer_new(chip);
10849 + if (err)
10850 + goto out_free_card;
10851 +
10852 + err = snd_atmel_ac97_pcm_new(chip);
10853 + if (err)
10854 + goto out_free_card;
10855 +
10856 + /* TODO: Get this information from the platform device */
10857 + chip->dma.req_tx.req.dmac = find_dma_controller(0);
10858 + if (!chip->dma.req_tx.req.dmac) {
10859 + dev_dbg(&chip->pdev->dev, "DMA controller for TX missing\n");
10860 + err = -ENODEV;
10861 + goto out_free_card;
10862 + }
10863 + chip->dma.req_rx.req.dmac = find_dma_controller(0);
10864 + if (!chip->dma.req_rx.req.dmac) {
10865 + dev_dbg(&chip->pdev->dev, "DMA controller for RX missing\n");
10866 + err = -ENODEV;
10867 + goto out_free_card;
10868 + }
10869 +
10870 + chip->dma.rx_periph_id = 3;
10871 + chip->dma.tx_periph_id = 4;
10872 +
10873 + ch = dma_alloc_channel(chip->dma.req_tx.req.dmac);
10874 + if (ch < 0) {
10875 + dev_dbg(&chip->pdev->dev,
10876 + "could not allocate TX DMA channel\n");
10877 + err = ch;
10878 + goto out_free_card;
10879 + }
10880 + chip->dma.req_tx.req.channel = ch;
10881 + chip->dma.req_tx.width = DMA_WIDTH_16BIT;
10882 + chip->dma.req_tx.req.block_complete = atmel_ac97_block_complete;
10883 + chip->dma.req_tx.req.error = atmel_ac97_error;
10884 +
10885 + ch = dma_alloc_channel(chip->dma.req_rx.req.dmac);
10886 + if (ch < 0) {
10887 + dev_dbg(&chip->pdev->dev,
10888 + "could not allocate RX DMA channel\n");
10889 + err = ch;
10890 + goto out_free_card;
10891 + }
10892 + chip->dma.req_rx.req.channel = ch;
10893 + chip->dma.req_rx.width = DMA_WIDTH_16BIT;
10894 + chip->dma.req_rx.req.block_complete = atmel_ac97_block_complete;
10895 + chip->dma.req_rx.req.error = atmel_ac97_error;
10896 +
10897 + strcpy(card->driver, "atmel_ac97c");
10898 + strcpy(card->shortname, "atmel_ac97c");
10899 + sprintf(card->longname, "Atmel AVR32 AC97 controller");
10900 +
10901 + err = snd_card_register(card);
10902 + if (err)
10903 + goto out_free_card;
10904 +
10905 + platform_set_drvdata(pdev, card);
10906 + dev++;
10907 +
10908 + dev_info(&pdev->dev, "Atmel AVR32 AC97 controller at 0x%p\n",
10909 + chip->regs);
10910 +
10911 + return 0;
10912 +
10913 +out_free_card:
10914 + snd_card_free(card);
10915 +out:
10916 + return err;
10917 +}
10918 +
10919 +#ifdef CONFIG_PM
10920 + static int
10921 +snd_atmel_ac97_suspend(struct platform_device *pdev, pm_message_t msg)
10922 +{
10923 + struct snd_card *card = platform_get_drvdata(pdev);
10924 + struct atmel_ac97 *chip = card->private_data;
10925 +
10926 + clk_disable(chip->mck);
10927 +
10928 + return 0;
10929 +}
10930 +
10931 +static int snd_atmel_ac97_resume(struct platform_device *pdev)
10932 +{
10933 + struct snd_card *card = dev_get_drvdata(pdev);
10934 + struct atmel_ac97 *chip = card->private_data;
10935 +
10936 + clk_enable(chip->mck);
10937 +
10938 + return 0;
10939 +}
10940 +#else
10941 +#define snd_atmel_ac97_suspend NULL
10942 +#define snd_atmel_ac97_resume NULL
10943 +#endif
10944 +
10945 +static int __devexit snd_atmel_ac97_remove(struct platform_device *pdev)
10946 +{
10947 + struct snd_card *card = platform_get_drvdata(pdev);
10948 +
10949 + snd_card_free(card);
10950 + platform_set_drvdata(pdev, NULL);
10951 + return 0;
10952 +}
10953 +
10954 +static struct platform_driver atmel_ac97_driver = {
10955 + .remove = __devexit_p(snd_atmel_ac97_remove),
10956 + .driver = {
10957 + .name = "atmel_ac97c",
10958 + },
10959 + .suspend = snd_atmel_ac97_suspend,
10960 + .resume = snd_atmel_ac97_resume,
10961 +};
10962 +
10963 +static int __init atmel_ac97_init(void)
10964 +{
10965 + return platform_driver_probe(&atmel_ac97_driver,
10966 + snd_atmel_ac97_probe);
10967 +}
10968 +module_init(atmel_ac97_init);
10969 +
10970 +static void __exit atmel_ac97_exit(void)
10971 +{
10972 + platform_driver_unregister(&atmel_ac97_driver);
10973 +}
10974 +module_exit(atmel_ac97_exit);
10975 +
10976 +MODULE_LICENSE("GPL");
10977 +MODULE_DESCRIPTION("Driver for Atmel AC97 Controller");
10978 +MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
10979 diff --git a/sound/avr32/ac97c.h b/sound/avr32/ac97c.h
10980 new file mode 100644
10981 index 0000000..96246e7
10982 --- /dev/null
10983 +++ b/sound/avr32/ac97c.h
10984 @@ -0,0 +1,71 @@
10985 +/*
10986 + * Register definitions for the Atmel AC97 Controller.
10987 + *
10988 + * Copyright (C) 2005-2006 Atmel Corporation
10989 + *
10990 + * This program is free software; you can redistribute it and/or modify
10991 + * it under the terms of the GNU General Public License version 2 as
10992 + * published by the Free Software Foundation.
10993 + */
10994 +#ifndef __SOUND_AVR32_AC97C_H
10995 +#define __SOUND_AVR32_AC97C_H
10996 +
10997 +#define AC97C_MR 0x08
10998 +#define AC97C_ICA 0x10
10999 +#define AC97C_OCA 0x14
11000 +#define AC97C_CARHR 0x20
11001 +#define AC97C_CATHR 0x24
11002 +#define AC97C_CASR 0x28
11003 +#define AC97C_CAMR 0x2c
11004 +#define AC97C_CBRHR 0x30
11005 +#define AC97C_CBTHR 0x34
11006 +#define AC97C_CBSR 0x38
11007 +#define AC97C_CBMR 0x3c
11008 +#define AC97C_CORHR 0x40
11009 +#define AC97C_COTHR 0x44
11010 +#define AC97C_COSR 0x48
11011 +#define AC97C_COMR 0x4c
11012 +#define AC97C_SR 0x50
11013 +#define AC97C_IER 0x54
11014 +#define AC97C_IDR 0x58
11015 +#define AC97C_IMR 0x5c
11016 +#define AC97C_VERSION 0xfc
11017 +
11018 +#define AC97C_CATPR PDC_TPR
11019 +#define AC97C_CATCR PDC_TCR
11020 +#define AC97C_CATNPR PDC_TNPR
11021 +#define AC97C_CATNCR PDC_TNCR
11022 +#define AC97C_CARPR PDC_RPR
11023 +#define AC97C_CARCR PDC_RCR
11024 +#define AC97C_CARNPR PDC_RNPR
11025 +#define AC97C_CARNCR PDC_RNCR
11026 +#define AC97C_PTCR PDC_PTCR
11027 +
11028 +#define AC97C_MR_ENA (1 << 0)
11029 +#define AC97C_MR_WRST (1 << 1)
11030 +#define AC97C_MR_VRA (1 << 2)
11031 +
11032 +#define AC97C_CSR_TXRDY (1 << 0)
11033 +#define AC97C_CSR_UNRUN (1 << 2)
11034 +#define AC97C_CSR_RXRDY (1 << 4)
11035 +#define AC97C_CSR_ENDTX (1 << 10)
11036 +#define AC97C_CSR_ENDRX (1 << 14)
11037 +
11038 +#define AC97C_CMR_SIZE_20 (0 << 16)
11039 +#define AC97C_CMR_SIZE_18 (1 << 16)
11040 +#define AC97C_CMR_SIZE_16 (2 << 16)
11041 +#define AC97C_CMR_SIZE_10 (3 << 16)
11042 +#define AC97C_CMR_CEM_LITTLE (1 << 18)
11043 +#define AC97C_CMR_CEM_BIG (0 << 18)
11044 +#define AC97C_CMR_CENA (1 << 21)
11045 +#define AC97C_CMR_PDCEN (1 << 22)
11046 +
11047 +#define AC97C_SR_CAEVT (1 << 3)
11048 +
11049 +#define AC97C_CH_ASSIGN(slot, channel) \
11050 + (AC97C_CHANNEL_##channel << (3 * (AC97_SLOT_##slot - 3)))
11051 +#define AC97C_CHANNEL_NONE 0x0
11052 +#define AC97C_CHANNEL_A 0x1
11053 +#define AC97C_CHANNEL_B 0x2
11054 +
11055 +#endif /* __SOUND_AVR32_AC97C_H */
11056 diff --git a/sound/oss/Kconfig b/sound/oss/Kconfig
11057 index af37cd0..e3cc557 100644
11058 --- a/sound/oss/Kconfig
11059 +++ b/sound/oss/Kconfig
11060 @@ -654,3 +654,7 @@ config SOUND_SH_DAC_AUDIO_CHANNEL
11061 int "DAC channel"
11062 default "1"
11063 depends on SOUND_SH_DAC_AUDIO
11064 +
11065 +config SOUND_AT32_ABDAC
11066 + tristate "Atmel AT32 Audio Bitstream DAC (ABDAC) support"
11067 + depends on SOUND_PRIME && AVR32
11068 diff --git a/sound/oss/Makefile b/sound/oss/Makefile
11069 index 1200670..fafc246 100644
11070 --- a/sound/oss/Makefile
11071 +++ b/sound/oss/Makefile
11072 @@ -10,6 +10,7 @@ obj-$(CONFIG_SOUND_CS4232) += cs4232.o ad1848.o
11073
11074 # Please leave it as is, cause the link order is significant !
11075
11076 +obj-$(CONFIG_SOUND_AT32_ABDAC) += at32_abdac.o
11077 obj-$(CONFIG_SOUND_SH_DAC_AUDIO) += sh_dac_audio.o
11078 obj-$(CONFIG_SOUND_HAL2) += hal2.o
11079 obj-$(CONFIG_SOUND_AEDSP16) += aedsp16.o
11080 diff --git a/sound/oss/at32_abdac.c b/sound/oss/at32_abdac.c
11081 new file mode 100644
11082 index 0000000..cb997d7
11083 --- /dev/null
11084 +++ b/sound/oss/at32_abdac.c
11085 @@ -0,0 +1,722 @@
11086 +/*
11087 + * OSS Sound Driver for the Atmel AT32 on-chip DAC.
11088 + *
11089 + * Copyright (C) 2006 Atmel Corporation
11090 + *
11091 + * This program is free software; you can redistribute it and/or modify
11092 + * it under the terms of the GNU General Public License version 2 as
11093 + * published by the Free Software Foundation.
11094 + */
11095 +#include <linux/clk.h>
11096 +#include <linux/dma-mapping.h>
11097 +#include <linux/fs.h>
11098 +#include <linux/init.h>
11099 +#include <linux/interrupt.h>
11100 +#include <linux/kernel.h>
11101 +#include <linux/module.h>
11102 +#include <linux/platform_device.h>
11103 +#include <linux/sound.h>
11104 +#include <linux/soundcard.h>
11105 +
11106 +#include <asm/byteorder.h>
11107 +#include <asm/dma-controller.h>
11108 +#include <asm/io.h>
11109 +#include <asm/uaccess.h>
11110 +
11111 +/* We want to use the "bizarre" swap-bytes-in-each-halfword macro */
11112 +#include <linux/byteorder/swabb.h>
11113 +
11114 +#include "at32_abdac.h"
11115 +
11116 +#define DMA_BUFFER_SIZE 32768
11117 +#define DMA_PERIOD_SHIFT 10
11118 +#define DMA_PERIOD_SIZE (1 << DMA_PERIOD_SHIFT)
11119 +#define DMA_WRITE_THRESHOLD DMA_PERIOD_SIZE
11120 +
11121 +struct sound_settings {
11122 + unsigned int format;
11123 + unsigned int channels;
11124 + unsigned int sample_rate;
11125 + /* log2(bytes per sample) */
11126 + unsigned int input_order;
11127 +};
11128 +
11129 +struct at32_dac {
11130 + spinlock_t lock;
11131 + void __iomem *regs;
11132 +
11133 + /* head and tail refer to number of words */
11134 + struct {
11135 + u32 *buf;
11136 + int head;
11137 + int tail;
11138 + } dma;
11139 +
11140 + struct semaphore sem;
11141 + wait_queue_head_t write_wait;
11142 +
11143 + /*
11144 + * Read at most ucount bytes from ubuf, translate to 2-channel
11145 + * signed 16-bit big endian format and write to the DMA buffer
11146 + * as long as there is room left. Return the number of bytes
11147 + * successfully copied from ubuf, or -EFAULT if the first
11148 + * sample from ubuf couldn't be read. This function is not
11149 + * called unless there is room for at least one sample (4
11150 + * bytes) in the DMA buffer.
11151 + */
11152 + ssize_t (*trans)(struct at32_dac *dac, const char __user *ubuf,
11153 + size_t ucount);
11154 +
11155 + struct sound_settings dsp_settings;
11156 + struct dma_request_cyclic req;
11157 +
11158 + struct clk *mck;
11159 + struct clk *sample_clk;
11160 + struct platform_device *pdev;
11161 + int busy;
11162 + int playing;
11163 + int dev_dsp;
11164 +};
11165 +static struct at32_dac *the_dac;
11166 +
11167 +static inline unsigned int abdac_get_head(struct at32_dac *dac)
11168 +{
11169 + return dac->dma.head & ((DMA_BUFFER_SIZE / 4) - 1);
11170 +}
11171 +
11172 +static inline unsigned int abdac_get_tail(struct at32_dac *dac)
11173 +{
11174 + return dac->dma.tail & ((DMA_BUFFER_SIZE / 4) - 1);
11175 +}
11176 +
11177 +static inline unsigned int abdac_dma_space(struct at32_dac *dac)
11178 +{
11179 + unsigned int space;
11180 +
11181 + space = ((dac->dma.tail - dac->dma.head - 1)
11182 + & ((DMA_BUFFER_SIZE / 4) - 1));
11183 + return space;
11184 +}
11185 +
11186 +static void abdac_update_dma_tail(struct at32_dac *dac)
11187 +{
11188 + dma_addr_t dma_addr;
11189 + unsigned int new_tail;
11190 +
11191 + if (dac->playing) {
11192 + dma_addr = dma_get_current_pos(dac->req.req.dmac,
11193 + dac->req.req.channel);
11194 + new_tail = (dma_addr - dac->req.buffer_start) / 4;
11195 + if (new_tail >= dac->dma.head
11196 + && (dac->dma.tail < dac->dma.head
11197 + || dac->dma.tail > new_tail))
11198 + dev_notice(&dac->pdev->dev, "DMA underrun detected!\n");
11199 + dac->dma.tail = new_tail;
11200 + dev_dbg(&dac->pdev->dev, "update tail: 0x%x - 0x%x = %u\n",
11201 + dma_addr, dac->req.buffer_start, dac->dma.tail);
11202 + }
11203 +}
11204 +
11205 +static int abdac_start(struct at32_dac *dac)
11206 +{
11207 + int ret;
11208 +
11209 + if (dac->playing)
11210 + return 0;
11211 +
11212 + memset(dac->dma.buf, 0, DMA_BUFFER_SIZE);
11213 +
11214 + clk_enable(dac->sample_clk);
11215 +
11216 + ret = dma_prepare_request_cyclic(dac->req.req.dmac, &dac->req);
11217 + if (ret)
11218 + goto out_stop_clock;
11219 +
11220 + dev_dbg(&dac->pdev->dev, "starting DMA...\n");
11221 + ret = dma_start_request(dac->req.req.dmac, dac->req.req.channel);
11222 + if (ret)
11223 + goto out_stop_request;
11224 +
11225 + dac_writel(dac, CTRL, DAC_BIT(EN));
11226 + dac->playing = 1;
11227 +
11228 + return 0;
11229 +
11230 +out_stop_request:
11231 + dma_stop_request(dac->req.req.dmac,
11232 + dac->req.req.channel);
11233 +out_stop_clock:
11234 + clk_disable(dac->sample_clk);
11235 + return ret;
11236 +}
11237 +
11238 +static int abdac_stop(struct at32_dac *dac)
11239 +{
11240 + if (dac->playing) {
11241 + dma_stop_request(dac->req.req.dmac, dac->req.req.channel);
11242 + dac_writel(dac, DATA, 0);
11243 + dac_writel(dac, CTRL, 0);
11244 + dac->playing = 0;
11245 + clk_disable(dac->sample_clk);
11246 + }
11247 +
11248 + return 0;
11249 +}
11250 +
11251 +static int abdac_dma_prepare(struct at32_dac *dac)
11252 +{
11253 + dac->dma.buf = dma_alloc_coherent(&dac->pdev->dev, DMA_BUFFER_SIZE,
11254 + &dac->req.buffer_start, GFP_KERNEL);
11255 + if (!dac->dma.buf)
11256 + return -ENOMEM;
11257 +
11258 + dac->dma.head = dac->dma.tail = 0;
11259 + dac->req.periods = DMA_BUFFER_SIZE / DMA_PERIOD_SIZE;
11260 + dac->req.buffer_size = DMA_BUFFER_SIZE;
11261 +
11262 + return 0;
11263 +}
11264 +
11265 +static void abdac_dma_cleanup(struct at32_dac *dac)
11266 +{
11267 + if (dac->dma.buf)
11268 + dma_free_coherent(&dac->pdev->dev, DMA_BUFFER_SIZE,
11269 + dac->dma.buf, dac->req.buffer_start);
11270 + dac->dma.buf = NULL;
11271 +}
11272 +
11273 +static void abdac_dma_block_complete(struct dma_request *req)
11274 +{
11275 + struct dma_request_cyclic *creq = to_dma_request_cyclic(req);
11276 + struct at32_dac *dac = container_of(creq, struct at32_dac, req);
11277 +
11278 + wake_up(&dac->write_wait);
11279 +}
11280 +
11281 +static void abdac_dma_error(struct dma_request *req)
11282 +{
11283 + struct dma_request_cyclic *creq = to_dma_request_cyclic(req);
11284 + struct at32_dac *dac = container_of(creq, struct at32_dac, req);
11285 +
11286 + dev_err(&dac->pdev->dev, "DMA error\n");
11287 +}
11288 +
11289 +static irqreturn_t abdac_interrupt(int irq, void *dev_id)
11290 +{
11291 + struct at32_dac *dac = dev_id;
11292 + u32 status;
11293 +
11294 + status = dac_readl(dac, INT_STATUS);
11295 + if (status & DAC_BIT(UNDERRUN)) {
11296 + dev_err(&dac->pdev->dev, "Underrun detected!\n");
11297 + dac_writel(dac, INT_CLR, DAC_BIT(UNDERRUN));
11298 + } else {
11299 + dev_err(&dac->pdev->dev, "Spurious interrupt (status=0x%x)\n",
11300 + status);
11301 + dac_writel(dac, INT_CLR, status);
11302 + }
11303 +
11304 + return IRQ_HANDLED;
11305 +}
11306 +
11307 +static ssize_t trans_s16be(struct at32_dac *dac, const char __user *ubuf,
11308 + size_t ucount)
11309 +{
11310 + ssize_t ret;
11311 +
11312 + if (dac->dsp_settings.channels == 2) {
11313 + const u32 __user *up = (const u32 __user *)ubuf;
11314 + u32 sample;
11315 +
11316 + for (ret = 0; ret < (ssize_t)(ucount - 3); ret += 4) {
11317 + if (!abdac_dma_space(dac))
11318 + break;
11319 +
11320 + if (unlikely(__get_user(sample, up++))) {
11321 + if (ret == 0)
11322 + ret = -EFAULT;
11323 + break;
11324 + }
11325 + dac->dma.buf[abdac_get_head(dac)] = sample;
11326 + dac->dma.head++;
11327 + }
11328 + } else {
11329 + const u16 __user *up = (const u16 __user *)ubuf;
11330 + u16 sample;
11331 +
11332 + for (ret = 0; ret < (ssize_t)(ucount - 1); ret += 2) {
11333 + if (!abdac_dma_space(dac))
11334 + break;
11335 +
11336 + if (unlikely(__get_user(sample, up++))) {
11337 + if (ret == 0)
11338 + ret = -EFAULT;
11339 + break;
11340 + }
11341 + dac->dma.buf[abdac_get_head(dac)]
11342 + = (sample << 16) | sample;
11343 + dac->dma.head++;
11344 + }
11345 + }
11346 +
11347 + return ret;
11348 +}
11349 +
11350 +static ssize_t trans_s16le(struct at32_dac *dac, const char __user *ubuf,
11351 + size_t ucount)
11352 +{
11353 + ssize_t ret;
11354 +
11355 + if (dac->dsp_settings.channels == 2) {
11356 + const u32 __user *up = (const u32 __user *)ubuf;
11357 + u32 sample;
11358 +
11359 + for (ret = 0; ret < (ssize_t)(ucount - 3); ret += 4) {
11360 + if (!abdac_dma_space(dac))
11361 + break;
11362 +
11363 + if (unlikely(__get_user(sample, up++))) {
11364 + if (ret == 0)
11365 + ret = -EFAULT;
11366 + break;
11367 + }
11368 + /* Swap bytes in each halfword */
11369 + dac->dma.buf[abdac_get_head(dac)] = swahb32(sample);
11370 + dac->dma.head++;
11371 + }
11372 + } else {
11373 + const u16 __user *up = (const u16 __user *)ubuf;
11374 + u16 sample;
11375 +
11376 + for (ret = 0; ret < (ssize_t)(ucount - 1); ret += 2) {
11377 + if (!abdac_dma_space(dac))
11378 + break;
11379 +
11380 + if (unlikely(__get_user(sample, up++))) {
11381 + if (ret == 0)
11382 + ret = -EFAULT;
11383 + break;
11384 + }
11385 + sample = swab16(sample);
11386 + dac->dma.buf[abdac_get_head(dac)]
11387 + = (sample << 16) | sample;
11388 + dac->dma.head++;
11389 + }
11390 + }
11391 +
11392 + return ret;
11393 +}
11394 +
11395 +static ssize_t abdac_dma_translate_from_user(struct at32_dac *dac,
11396 + const char __user *buffer,
11397 + size_t count)
11398 +{
11399 + /* At least one buffer must be available at this point */
11400 + dev_dbg(&dac->pdev->dev, "copying %zu bytes from user...\n", count);
11401 +
11402 + return dac->trans(dac, buffer, count);
11403 +}
11404 +
11405 +static int abdac_set_format(struct at32_dac *dac, int format)
11406 +{
11407 + unsigned int order;
11408 +
11409 + switch (format) {
11410 + case AFMT_S16_BE:
11411 + order = 1;
11412 + dac->trans = trans_s16be;
11413 + break;
11414 + case AFMT_S16_LE:
11415 + order = 1;
11416 + dac->trans = trans_s16le;
11417 + break;
11418 + default:
11419 + dev_dbg(&dac->pdev->dev, "unsupported format: %d\n", format);
11420 + return -EINVAL;
11421 + }
11422 +
11423 + if (dac->dsp_settings.channels == 2)
11424 + order++;
11425 +
11426 + dac->dsp_settings.input_order = order;
11427 + dac->dsp_settings.format = format;
11428 + return 0;
11429 +}
11430 +
11431 +static int abdac_set_sample_rate(struct at32_dac *dac, unsigned long rate)
11432 +{
11433 + unsigned long new_rate;
11434 + int ret;
11435 +
11436 + ret = clk_set_rate(dac->sample_clk, 256 * rate);
11437 + if (ret < 0)
11438 + return ret;
11439 +
11440 + /* TODO: mplayer seems to have a problem with this */
11441 +#if 0
11442 + new_rate = clk_get_rate(dac->sample_clk);
11443 + dac->dsp_settings.sample_rate = new_rate / 256;
11444 +#else
11445 + dac->dsp_settings.sample_rate = rate;
11446 +#endif
11447 +
11448 + return 0;
11449 +}
11450 +
11451 +static ssize_t abdac_dsp_write(struct file *file,
11452 + const char __user *buffer,
11453 + size_t count, loff_t *ppos)
11454 +{
11455 + struct at32_dac *dac = file->private_data;
11456 + DECLARE_WAITQUEUE(wait, current);
11457 + unsigned int avail;
11458 + ssize_t copied;
11459 + ssize_t ret;
11460 +
11461 + /* Avoid address space checking in the translation functions */
11462 + if (!access_ok(buffer, count, VERIFY_READ))
11463 + return -EFAULT;
11464 +
11465 + down(&dac->sem);
11466 +
11467 + if (!dac->dma.buf) {
11468 + ret = abdac_dma_prepare(dac);
11469 + if (ret)
11470 + goto out;
11471 + }
11472 +
11473 + add_wait_queue(&dac->write_wait, &wait);
11474 + ret = 0;
11475 + while (count > 0) {
11476 + do {
11477 + abdac_update_dma_tail(dac);
11478 + avail = abdac_dma_space(dac);
11479 + set_current_state(TASK_INTERRUPTIBLE);
11480 + if (avail >= DMA_WRITE_THRESHOLD)
11481 + break;
11482 +
11483 + if (file->f_flags & O_NONBLOCK) {
11484 + if (!ret)
11485 + ret = -EAGAIN;
11486 + goto out;
11487 + }
11488 +
11489 + pr_debug("Going to wait (avail = %u, count = %zu)\n",
11490 + avail, count);
11491 +
11492 + up(&dac->sem);
11493 + schedule();
11494 + if (signal_pending(current)) {
11495 + if (!ret)
11496 + ret = -ERESTARTSYS;
11497 + goto out_nosem;
11498 + }
11499 + down(&dac->sem);
11500 + } while (1);
11501 +
11502 + copied = abdac_dma_translate_from_user(dac, buffer, count);
11503 + if (copied < 0) {
11504 + if (!ret)
11505 + ret = -EFAULT;
11506 + goto out;
11507 + }
11508 +
11509 + abdac_start(dac);
11510 +
11511 + count -= copied;
11512 + ret += copied;
11513 + }
11514 +
11515 +out:
11516 + up(&dac->sem);
11517 +out_nosem:
11518 + remove_wait_queue(&dac->write_wait, &wait);
11519 + set_current_state(TASK_RUNNING);
11520 + return ret;
11521 +}
11522 +
11523 +static int abdac_dsp_ioctl(struct inode *inode, struct file *file,
11524 + unsigned int cmd, unsigned long arg)
11525 +{
11526 + struct at32_dac *dac = file->private_data;
11527 + int __user *up = (int __user *)arg;
11528 + struct audio_buf_info abinfo;
11529 + int val, ret;
11530 +
11531 + switch (cmd) {
11532 + case OSS_GETVERSION:
11533 + return put_user(SOUND_VERSION, up);
11534 +
11535 + case SNDCTL_DSP_SPEED:
11536 + if (get_user(val, up))
11537 + return -EFAULT;
11538 + if (val >= 0) {
11539 + abdac_stop(dac);
11540 + ret = abdac_set_sample_rate(dac, val);
11541 + if (ret)
11542 + return ret;
11543 + }
11544 + return put_user(dac->dsp_settings.sample_rate, up);
11545 +
11546 + case SNDCTL_DSP_STEREO:
11547 + if (get_user(val, up))
11548 + return -EFAULT;
11549 + abdac_stop(dac);
11550 + if (val && dac->dsp_settings.channels == 1)
11551 + dac->dsp_settings.input_order++;
11552 + else if (!val && dac->dsp_settings.channels != 1)
11553 + dac->dsp_settings.input_order--;
11554 + dac->dsp_settings.channels = val ? 2 : 1;
11555 + return 0;
11556 +
11557 + case SNDCTL_DSP_CHANNELS:
11558 + if (get_user(val, up))
11559 + return -EFAULT;
11560 +
11561 + if (val) {
11562 + if (val < 0 || val > 2)
11563 + return -EINVAL;
11564 +
11565 + abdac_stop(dac);
11566 + dac->dsp_settings.input_order
11567 + += val - dac->dsp_settings.channels;
11568 + dac->dsp_settings.channels = val;
11569 + }
11570 + return put_user(val, (int *)arg);
11571 +
11572 + case SNDCTL_DSP_GETFMTS:
11573 + return put_user(AFMT_S16_BE | AFMT_S16_BE, up);
11574 +
11575 + case SNDCTL_DSP_SETFMT:
11576 + if (get_user(val, up))
11577 + return -EFAULT;
11578 +
11579 + if (val == AFMT_QUERY) {
11580 + val = dac->dsp_settings.format;
11581 + } else {
11582 + ret = abdac_set_format(dac, val);
11583 + if (ret)
11584 + return ret;
11585 + }
11586 + return put_user(val, up);
11587 +
11588 + case SNDCTL_DSP_GETOSPACE:
11589 + abdac_update_dma_tail(dac);
11590 + abinfo.fragsize = ((1 << dac->dsp_settings.input_order)
11591 + * (DMA_PERIOD_SIZE / 4));
11592 + abinfo.bytes = (abdac_dma_space(dac)
11593 + << dac->dsp_settings.input_order);
11594 + abinfo.fragstotal = ((DMA_BUFFER_SIZE * 4)
11595 + >> (DMA_PERIOD_SHIFT
11596 + + dac->dsp_settings.input_order));
11597 + abinfo.fragments = ((abinfo.bytes
11598 + >> dac->dsp_settings.input_order)
11599 + / (DMA_PERIOD_SIZE / 4));
11600 + pr_debug("fragments=%d fragstotal=%d fragsize=%d bytes=%d\n",
11601 + abinfo.fragments, abinfo.fragstotal, abinfo.fragsize,
11602 + abinfo.bytes);
11603 + return copy_to_user(up, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
11604 +
11605 + default:
11606 + dev_dbg(&dac->pdev->dev, "Unimplemented ioctl cmd: 0x%x\n", cmd);
11607 + return -EINVAL;
11608 + }
11609 +}
11610 +
11611 +static int abdac_dsp_open(struct inode *inode, struct file *file)
11612 +{
11613 + struct at32_dac *dac = the_dac;
11614 + int ret;
11615 +
11616 + if (file->f_mode & FMODE_READ)
11617 + return -ENXIO;
11618 +
11619 + down(&dac->sem);
11620 + ret = -EBUSY;
11621 + if (dac->busy)
11622 + goto out;
11623 +
11624 + dac->dma.head = dac->dma.tail = 0;
11625 +
11626 + /* FIXME: What are the correct defaults? */
11627 + dac->dsp_settings.channels = 2;
11628 + abdac_set_format(dac, AFMT_S16_BE);
11629 + ret = abdac_set_sample_rate(dac, 8000);
11630 + if (ret)
11631 + goto out;
11632 +
11633 + file->private_data = dac;
11634 + dac->busy = 1;
11635 +
11636 + ret = 0;
11637 +
11638 +out:
11639 + up(&dac->sem);
11640 + return ret;
11641 +}
11642 +
11643 +static int abdac_dsp_release(struct inode *inode, struct file *file)
11644 +{
11645 + struct at32_dac *dac = file->private_data;
11646 +
11647 + down(&dac->sem);
11648 +
11649 + abdac_stop(dac);
11650 + abdac_dma_cleanup(dac);
11651 + dac->busy = 0;
11652 +
11653 + up(&dac->sem);
11654 +
11655 + return 0;
11656 +}
11657 +
11658 +static struct file_operations abdac_dsp_fops = {
11659 + .owner = THIS_MODULE,
11660 + .llseek = no_llseek,
11661 + .write = abdac_dsp_write,
11662 + .ioctl = abdac_dsp_ioctl,
11663 + .open = abdac_dsp_open,
11664 + .release = abdac_dsp_release,
11665 +};
11666 +
11667 +static int __init abdac_probe(struct platform_device *pdev)
11668 +{
11669 + struct at32_dac *dac;
11670 + struct resource *regs;
11671 + struct clk *mck;
11672 + struct clk *sample_clk;
11673 + int irq;
11674 + int ret;
11675 +
11676 + if (the_dac)
11677 + return -EBUSY;
11678 +
11679 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
11680 + if (!regs)
11681 + return -ENXIO;
11682 + irq = platform_get_irq(pdev, 0);
11683 + if (irq < 0)
11684 + return irq;
11685 +
11686 + mck = clk_get(&pdev->dev, "pclk");
11687 + if (IS_ERR(mck))
11688 + return PTR_ERR(mck);
11689 + sample_clk = clk_get(&pdev->dev, "sample_clk");
11690 + if (IS_ERR(sample_clk)) {
11691 + ret = PTR_ERR(sample_clk);
11692 + goto out_put_mck;
11693 + }
11694 + clk_enable(mck);
11695 +
11696 + ret = -ENOMEM;
11697 + dac = kzalloc(sizeof(struct at32_dac), GFP_KERNEL);
11698 + if (!dac)
11699 + goto out_disable_clk;
11700 +
11701 + spin_lock_init(&dac->lock);
11702 + init_MUTEX(&dac->sem);
11703 + init_waitqueue_head(&dac->write_wait);
11704 + dac->pdev = pdev;
11705 + dac->mck = mck;
11706 + dac->sample_clk = sample_clk;
11707 +
11708 + dac->regs = ioremap(regs->start, regs->end - regs->start + 1);
11709 + if (!dac->regs)
11710 + goto out_free_dac;
11711 +
11712 + ret = request_irq(irq, abdac_interrupt, 0, "dac", dac);
11713 + if (ret)
11714 + goto out_unmap_regs;
11715 +
11716 + /* FIXME */
11717 + dac->req.req.dmac = find_dma_controller(0);
11718 + if (!dac->req.req.dmac)
11719 + goto out_free_irq;
11720 +
11721 + ret = dma_alloc_channel(dac->req.req.dmac);
11722 + if (ret < 0)
11723 + goto out_free_irq;
11724 +
11725 + dac->req.req.channel = ret;
11726 + dac->req.req.block_complete = abdac_dma_block_complete;
11727 + dac->req.req.error = abdac_dma_error;
11728 + dac->req.data_reg = regs->start + DAC_DATA;
11729 + dac->req.periph_id = 2; /* FIXME */
11730 + dac->req.direction = DMA_DIR_MEM_TO_PERIPH;
11731 + dac->req.width = DMA_WIDTH_32BIT;
11732 +
11733 + /* Make sure the DAC is silent and disabled */
11734 + dac_writel(dac, DATA, 0);
11735 + dac_writel(dac, CTRL, 0);
11736 +
11737 + ret = register_sound_dsp(&abdac_dsp_fops, -1);
11738 + if (ret < 0)
11739 + goto out_free_dma;
11740 + dac->dev_dsp = ret;
11741 +
11742 + /* TODO: Register mixer */
11743 +
11744 + the_dac = dac;
11745 + platform_set_drvdata(pdev, dac);
11746 +
11747 + return 0;
11748 +
11749 +out_free_dma:
11750 + dma_release_channel(dac->req.req.dmac, dac->req.req.channel);
11751 +out_free_irq:
11752 + free_irq(irq, dac);
11753 +out_unmap_regs:
11754 + iounmap(dac->regs);
11755 +out_free_dac:
11756 + kfree(dac);
11757 +out_disable_clk:
11758 + clk_disable(mck);
11759 + clk_put(sample_clk);
11760 +out_put_mck:
11761 + clk_put(mck);
11762 + return ret;
11763 +}
11764 +
11765 +static int __exit abdac_remove(struct platform_device *pdev)
11766 +{
11767 + struct at32_dac *dac;
11768 +
11769 + dac = platform_get_drvdata(pdev);
11770 + if (dac) {
11771 + unregister_sound_dsp(dac->dev_dsp);
11772 + dma_release_channel(dac->req.req.dmac, dac->req.req.channel);
11773 + free_irq(platform_get_irq(pdev, 0), dac);
11774 + iounmap(dac->regs);
11775 + clk_disable(dac->mck);
11776 + clk_put(dac->sample_clk);
11777 + clk_put(dac->mck);
11778 + kfree(dac);
11779 + platform_set_drvdata(pdev, NULL);
11780 + the_dac = NULL;
11781 + }
11782 +
11783 + return 0;
11784 +}
11785 +
11786 +static struct platform_driver abdac_driver = {
11787 + .remove = __exit_p(abdac_remove),
11788 + .driver = {
11789 + .name = "abdac",
11790 + },
11791 +};
11792 +
11793 +static int __init abdac_init(void)
11794 +{
11795 + return platform_driver_probe(&abdac_driver, abdac_probe);
11796 +}
11797 +module_init(abdac_init);
11798 +
11799 +static void __exit abdac_exit(void)
11800 +{
11801 + platform_driver_unregister(&abdac_driver);
11802 +}
11803 +module_exit(abdac_exit);
11804 +
11805 +MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
11806 +MODULE_DESCRIPTION("Sound Driver for the Atmel AT32 ABDAC");
11807 +MODULE_LICENSE("GPL");
11808 diff --git a/sound/oss/at32_abdac.h b/sound/oss/at32_abdac.h
11809 new file mode 100644
11810 index 0000000..3c88e25
11811 --- /dev/null
11812 +++ b/sound/oss/at32_abdac.h
11813 @@ -0,0 +1,59 @@
11814 +/*
11815 + * Register definitions for the Atmel AT32 on-chip DAC.
11816 + *
11817 + * Copyright (C) 2006 Atmel Corporation
11818 + *
11819 + * This program is free software; you can redistribute it and/or modify
11820 + * it under the terms of the GNU General Public License version 2 as
11821 + * published by the Free Software Foundation.
11822 + */
11823 +#ifndef __SOUND_OSS_AT32_ABDAC_H__
11824 +#define __SOUND_OSS_AT32_ABDAC_H__
11825 +
11826 +/* DAC register offsets */
11827 +#define DAC_DATA 0x0000
11828 +#define DAC_CTRL 0x0008
11829 +#define DAC_INT_MASK 0x000c
11830 +#define DAC_INT_EN 0x0010
11831 +#define DAC_INT_DIS 0x0014
11832 +#define DAC_INT_CLR 0x0018
11833 +#define DAC_INT_STATUS 0x001c
11834 +#define DAC_PDC_DATA 0x0020
11835 +
11836 +/* Bitfields in CTRL */
11837 +#define DAC_SWAP_OFFSET 30
11838 +#define DAC_SWAP_SIZE 1
11839 +#define DAC_EN_OFFSET 31
11840 +#define DAC_EN_SIZE 1
11841 +
11842 +/* Bitfields in INT_MASK/INT_EN/INT_DIS/INT_STATUS/INT_CLR */
11843 +#define DAC_UNDERRUN_OFFSET 28
11844 +#define DAC_UNDERRUN_SIZE 1
11845 +#define DAC_TX_READY_OFFSET 29
11846 +#define DAC_TX_READY_SIZE 1
11847 +#define DAC_TX_BUFFER_EMPTY_OFFSET 30
11848 +#define DAC_TX_BUFFER_EMPTY_SIZE 1
11849 +#define DAC_CHANNEL_TX_END_OFFSET 31
11850 +#define DAC_CHANNEL_TX_END_SIZE 1
11851 +
11852 +/* Bit manipulation macros */
11853 +#define DAC_BIT(name) \
11854 + (1 << DAC_##name##_OFFSET)
11855 +#define DAC_BF(name, value) \
11856 + (((value) & ((1 << DAC_##name##_SIZE) - 1)) \
11857 + << DAC_##name##_OFFSET)
11858 +#define DAC_BFEXT(name, value) \
11859 + (((value) >> DAC_##name##_OFFSET) \
11860 + & ((1 << DAC_##name##_SIZE) - 1))
11861 +#define DAC_BFINS(name, value, old) \
11862 + (((old) & ~(((1 << DAC_##name##_SIZE) - 1) \
11863 + << DAC_##name##_OFFSET)) \
11864 + | DAC_BF(name,value))
11865 +
11866 +/* Register access macros */
11867 +#define dac_readl(port, reg) \
11868 + __raw_readl((port)->regs + DAC_##reg)
11869 +#define dac_writel(port, reg, value) \
11870 + __raw_writel((value), (port)->regs + DAC_##reg)
11871 +
11872 +#endif /* __SOUND_OSS_AT32_ABDAC_H__ */
11873 diff --git a/sound/spi/Kconfig b/sound/spi/Kconfig
11874 new file mode 100644
11875 index 0000000..0d08c29
11876 --- /dev/null
11877 +++ b/sound/spi/Kconfig
11878 @@ -0,0 +1,31 @@
11879 +#SPI drivers
11880 +
11881 +menu "SPI devices"
11882 + depends on SND != n
11883 +
11884 +config SND_AT73C213
11885 + tristate "Atmel AT73C213 DAC driver"
11886 + depends on ATMEL_SSC
11887 + select SND_PCM
11888 + help
11889 + Say Y here if you want to use the Atmel AT73C213 external DAC. This
11890 + DAC can be found on Atmel development boards.
11891 +
11892 + This driver requires the Atmel SSC driver for sound sink, a
11893 + peripheral found on most AT91 and AVR32 microprocessors.
11894 +
11895 + To compile this driver as a module, choose M here: the module will be
11896 + called snd-at73c213.
11897 +
11898 +config SND_AT73C213_TARGET_BITRATE
11899 + int "Target bitrate for AT73C213"
11900 + depends on SND_AT73C213
11901 + default "48000"
11902 + range 8000 50000
11903 + help
11904 + Sets the target bitrate for the bitrate calculator in the driver.
11905 + Limited by hardware to be between 8000 Hz and 50000 Hz.
11906 +
11907 + Set to 48000 Hz by default.
11908 +
11909 +endmenu
11910 diff --git a/sound/spi/Makefile b/sound/spi/Makefile
11911 new file mode 100644
11912 index 0000000..026fb73
11913 --- /dev/null
11914 +++ b/sound/spi/Makefile
11915 @@ -0,0 +1,5 @@
11916 +# Makefile for SPI drivers
11917 +
11918 +snd-at73c213-objs := at73c213.o
11919 +
11920 +obj-$(CONFIG_SND_AT73C213) += snd-at73c213.o
11921 diff --git a/sound/spi/at73c213.c b/sound/spi/at73c213.c
11922 new file mode 100644
11923 index 0000000..f514f47
11924 --- /dev/null
11925 +++ b/sound/spi/at73c213.c
11926 @@ -0,0 +1,1121 @@
11927 +/*
11928 + * Driver for AT73C213 16-bit stereo DAC connected to Atmel SSC
11929 + *
11930 + * Copyright (C) 2006-2007 Atmel Norway
11931 + *
11932 + * This program is free software; you can redistribute it and/or modify it
11933 + * under the terms of the GNU General Public License version 2 as published by
11934 + * the Free Software Foundation.
11935 + */
11936 +
11937 +/*#define DEBUG*/
11938 +
11939 +#include <linux/clk.h>
11940 +#include <linux/err.h>
11941 +#include <linux/delay.h>
11942 +#include <linux/device.h>
11943 +#include <linux/dma-mapping.h>
11944 +#include <linux/init.h>
11945 +#include <linux/interrupt.h>
11946 +#include <linux/module.h>
11947 +#include <linux/platform_device.h>
11948 +#include <linux/io.h>
11949 +
11950 +#include <sound/driver.h>
11951 +#include <sound/initval.h>
11952 +#include <sound/control.h>
11953 +#include <sound/core.h>
11954 +#include <sound/pcm.h>
11955 +
11956 +#include <linux/atmel-ssc.h>
11957 +
11958 +#include <linux/spi/spi.h>
11959 +#include <linux/spi/at73c213.h>
11960 +
11961 +#include "at73c213.h"
11962 +
11963 +#define BITRATE_MIN 8000 /* Hardware limit? */
11964 +#define BITRATE_TARGET CONFIG_SND_AT73C213_TARGET_BITRATE
11965 +#define BITRATE_MAX 50000 /* Hardware limit. */
11966 +
11967 +/* Initial (hardware reset) AT73C213 register values. */
11968 +static u8 snd_at73c213_original_image[18] =
11969 +{
11970 + 0x00, /* 00 - CTRL */
11971 + 0x05, /* 01 - LLIG */
11972 + 0x05, /* 02 - RLIG */
11973 + 0x08, /* 03 - LPMG */
11974 + 0x08, /* 04 - RPMG */
11975 + 0x00, /* 05 - LLOG */
11976 + 0x00, /* 06 - RLOG */
11977 + 0x22, /* 07 - OLC */
11978 + 0x09, /* 08 - MC */
11979 + 0x00, /* 09 - CSFC */
11980 + 0x00, /* 0A - MISC */
11981 + 0x00, /* 0B - */
11982 + 0x00, /* 0C - PRECH */
11983 + 0x05, /* 0D - AUXG */
11984 + 0x00, /* 0E - */
11985 + 0x00, /* 0F - */
11986 + 0x00, /* 10 - RST */
11987 + 0x00, /* 11 - PA_CTRL */
11988 +};
11989 +
11990 +struct snd_at73c213 {
11991 + struct snd_card *card;
11992 + struct snd_pcm *pcm;
11993 + struct snd_pcm_substream *substream;
11994 + struct at73c213_board_info *board;
11995 + int irq;
11996 + int period;
11997 + unsigned long bitrate;
11998 + struct clk *bitclk;
11999 + struct ssc_device *ssc;
12000 + struct spi_device *spi;
12001 + u8 spi_wbuffer[2];
12002 + u8 spi_rbuffer[2];
12003 + /* Image of the SPI registers in AT73C213. */
12004 + u8 reg_image[18];
12005 + /* Protect registers against concurrent access. */
12006 + spinlock_t lock;
12007 +};
12008 +
12009 +#define get_chip(card) ((struct snd_at73c213 *)card->private_data)
12010 +
12011 +static int
12012 +snd_at73c213_write_reg(struct snd_at73c213 *chip, u8 reg, u8 val)
12013 +{
12014 + struct spi_message msg;
12015 + struct spi_transfer msg_xfer = {
12016 + .len = 2,
12017 + .cs_change = 0,
12018 + };
12019 + int retval;
12020 +
12021 + spi_message_init(&msg);
12022 +
12023 + chip->spi_wbuffer[0] = reg;
12024 + chip->spi_wbuffer[1] = val;
12025 +
12026 + msg_xfer.tx_buf = chip->spi_wbuffer;
12027 + msg_xfer.rx_buf = chip->spi_rbuffer;
12028 + spi_message_add_tail(&msg_xfer, &msg);
12029 +
12030 + retval = spi_sync(chip->spi, &msg);
12031 +
12032 + if (!retval)
12033 + chip->reg_image[reg] = val;
12034 +
12035 + return retval;
12036 +}
12037 +
12038 +static struct snd_pcm_hardware snd_at73c213_playback_hw = {
12039 + .info = SNDRV_PCM_INFO_INTERLEAVED |
12040 + SNDRV_PCM_INFO_BLOCK_TRANSFER,
12041 + .formats = SNDRV_PCM_FMTBIT_S16_BE,
12042 + .rates = SNDRV_PCM_RATE_CONTINUOUS,
12043 + .rate_min = 8000, /* Replaced by chip->bitrate later. */
12044 + .rate_max = 50000, /* Replaced by chip->bitrate later. */
12045 + .channels_min = 2,
12046 + .channels_max = 2,
12047 + .buffer_bytes_max = 64 * 1024 - 1,
12048 + .period_bytes_min = 512,
12049 + .period_bytes_max = 64 * 1024 - 1,
12050 + .periods_min = 4,
12051 + .periods_max = 1024,
12052 +};
12053 +
12054 +/*
12055 + * Calculate and set bitrate and divisions.
12056 + */
12057 +static int snd_at73c213_set_bitrate(struct snd_at73c213 *chip)
12058 +{
12059 + unsigned long ssc_rate = clk_get_rate(chip->ssc->clk);
12060 + unsigned long dac_rate_new, ssc_div, status;
12061 + unsigned long ssc_div_max, ssc_div_min;
12062 + int max_tries;
12063 +
12064 + /*
12065 + * We connect two clocks here, picking divisors so the I2S clocks
12066 + * out data at the same rate the DAC clocks it in ... and as close
12067 + * as practical to the desired target rate.
12068 + *
12069 + * The DAC master clock (MCLK) is programmable, and is either 256
12070 + * or (not here) 384 times the I2S output clock (BCLK).
12071 + */
12072 +
12073 + /* SSC clock / (bitrate * stereo * 16-bit). */
12074 + ssc_div = ssc_rate / (BITRATE_TARGET * 2 * 16);
12075 + ssc_div_min = ssc_rate / (BITRATE_MAX * 2 * 16);
12076 + ssc_div_max = ssc_rate / (BITRATE_MIN * 2 * 16);
12077 + max_tries = (ssc_div_max - ssc_div_min) / 2;
12078 +
12079 + if (max_tries < 1)
12080 + max_tries = 1;
12081 +
12082 + /* ssc_div must be a power of 2. */
12083 + ssc_div = (ssc_div + 1) & ~1UL;
12084 +
12085 + if ((ssc_rate / (ssc_div * 2 * 16)) < BITRATE_MIN) {
12086 + ssc_div -= 2;
12087 + if ((ssc_rate / (ssc_div * 2 * 16)) > BITRATE_MAX)
12088 + return -ENXIO;
12089 + }
12090 +
12091 + /* Search for a possible bitrate. */
12092 + do {
12093 + /* SSC clock / (ssc divider * 16-bit * stereo). */
12094 + if ((ssc_rate / (ssc_div * 2 * 16)) < BITRATE_MIN)
12095 + return -ENXIO;
12096 +
12097 + /* 256 / (2 * 16) = 8 */
12098 + dac_rate_new = 8 * (ssc_rate / ssc_div);
12099 +
12100 + status = clk_round_rate(chip->board->dac_clk, dac_rate_new);
12101 + if (status < 0)
12102 + return status;
12103 +
12104 + /* Ignore difference smaller than 256 Hz. */
12105 + if ((status/256) == (dac_rate_new/256))
12106 + goto set_rate;
12107 +
12108 + ssc_div += 2;
12109 + } while (--max_tries);
12110 +
12111 + /* Not able to find a valid bitrate. */
12112 + return -ENXIO;
12113 +
12114 +set_rate:
12115 + status = clk_set_rate(chip->board->dac_clk, status);
12116 + if (status < 0)
12117 + return status;
12118 +
12119 + /* Set divider in SSC device. */
12120 + ssc_writel(chip->ssc->regs, CMR, ssc_div/2);
12121 +
12122 + /* SSC clock / (ssc divider * 16-bit * stereo). */
12123 + chip->bitrate = ssc_rate / (ssc_div * 16 * 2);
12124 +
12125 + dev_info(&chip->spi->dev,
12126 + "at73c213: supported bitrate is %lu (%lu divider)\n",
12127 + chip->bitrate, ssc_div);
12128 +
12129 + return 0;
12130 +}
12131 +
12132 +static int snd_at73c213_pcm_open(struct snd_pcm_substream *substream)
12133 +{
12134 + struct snd_at73c213 *chip = snd_pcm_substream_chip(substream);
12135 + struct snd_pcm_runtime *runtime = substream->runtime;
12136 +
12137 + snd_at73c213_playback_hw.rate_min = chip->bitrate;
12138 + snd_at73c213_playback_hw.rate_max = chip->bitrate;
12139 + runtime->hw = snd_at73c213_playback_hw;
12140 + chip->substream = substream;
12141 +
12142 + return 0;
12143 +}
12144 +
12145 +static int snd_at73c213_pcm_close(struct snd_pcm_substream *substream)
12146 +{
12147 + struct snd_at73c213 *chip = snd_pcm_substream_chip(substream);
12148 + chip->substream = NULL;
12149 + return 0;
12150 +}
12151 +
12152 +static int snd_at73c213_pcm_hw_params(struct snd_pcm_substream *substream,
12153 + struct snd_pcm_hw_params *hw_params)
12154 +{
12155 + return snd_pcm_lib_malloc_pages(substream,
12156 + params_buffer_bytes(hw_params));
12157 +}
12158 +
12159 +static int snd_at73c213_pcm_hw_free(struct snd_pcm_substream *substream)
12160 +{
12161 + return snd_pcm_lib_free_pages(substream);
12162 +}
12163 +
12164 +static int snd_at73c213_pcm_prepare(struct snd_pcm_substream *substream)
12165 +{
12166 + struct snd_at73c213 *chip = snd_pcm_substream_chip(substream);
12167 + struct snd_pcm_runtime *runtime = substream->runtime;
12168 + int block_size;
12169 +
12170 + block_size = frames_to_bytes(runtime, runtime->period_size);
12171 +
12172 + chip->period = 0;
12173 +
12174 + ssc_writel(chip->ssc->regs, PDC_TPR,
12175 + (long)runtime->dma_addr);
12176 + ssc_writel(chip->ssc->regs, PDC_TCR, runtime->period_size * 2);
12177 + ssc_writel(chip->ssc->regs, PDC_TNPR,
12178 + (long)runtime->dma_addr + block_size);
12179 + ssc_writel(chip->ssc->regs, PDC_TNCR, runtime->period_size * 2);
12180 +
12181 + return 0;
12182 +}
12183 +
12184 +static int snd_at73c213_pcm_trigger(struct snd_pcm_substream *substream,
12185 + int cmd)
12186 +{
12187 + struct snd_at73c213 *chip = snd_pcm_substream_chip(substream);
12188 + int retval = 0;
12189 +
12190 + spin_lock(&chip->lock);
12191 +
12192 + switch (cmd) {
12193 + case SNDRV_PCM_TRIGGER_START:
12194 + ssc_writel(chip->ssc->regs, IER, SSC_BIT(IER_ENDTX));
12195 + ssc_writel(chip->ssc->regs, PDC_PTCR, SSC_BIT(PDC_PTCR_TXTEN));
12196 + break;
12197 + case SNDRV_PCM_TRIGGER_STOP:
12198 + ssc_writel(chip->ssc->regs, PDC_PTCR, SSC_BIT(PDC_PTCR_TXTDIS));
12199 + ssc_writel(chip->ssc->regs, IDR, SSC_BIT(IDR_ENDTX));
12200 + break;
12201 + default:
12202 + dev_dbg(&chip->spi->dev, "spurious command %x\n", cmd);
12203 + retval = -EINVAL;
12204 + break;
12205 + }
12206 +
12207 + spin_unlock(&chip->lock);
12208 +
12209 + return retval;
12210 +}
12211 +
12212 +static snd_pcm_uframes_t
12213 +snd_at73c213_pcm_pointer(struct snd_pcm_substream *substream)
12214 +{
12215 + struct snd_at73c213 *chip = snd_pcm_substream_chip(substream);
12216 + struct snd_pcm_runtime *runtime = substream->runtime;
12217 + snd_pcm_uframes_t pos;
12218 + unsigned long bytes;
12219 +
12220 + bytes = ssc_readl(chip->ssc->regs, PDC_TPR)
12221 + - (unsigned long)runtime->dma_addr;
12222 +
12223 + pos = bytes_to_frames(runtime, bytes);
12224 + if (pos >= runtime->buffer_size)
12225 + pos -= runtime->buffer_size;
12226 +
12227 + return pos;
12228 +}
12229 +
12230 +static struct snd_pcm_ops at73c213_playback_ops = {
12231 + .open = snd_at73c213_pcm_open,
12232 + .close = snd_at73c213_pcm_close,
12233 + .ioctl = snd_pcm_lib_ioctl,
12234 + .hw_params = snd_at73c213_pcm_hw_params,
12235 + .hw_free = snd_at73c213_pcm_hw_free,
12236 + .prepare = snd_at73c213_pcm_prepare,
12237 + .trigger = snd_at73c213_pcm_trigger,
12238 + .pointer = snd_at73c213_pcm_pointer,
12239 +};
12240 +
12241 +static void snd_at73c213_pcm_free(struct snd_pcm *pcm)
12242 +{
12243 + struct snd_at73c213 *chip = snd_pcm_chip(pcm);
12244 + if (chip->pcm) {
12245 + snd_pcm_lib_preallocate_free_for_all(chip->pcm);
12246 + chip->pcm = NULL;
12247 + }
12248 +}
12249 +
12250 +static int __devinit snd_at73c213_pcm_new(struct snd_at73c213 *chip, int device)
12251 +{
12252 + struct snd_pcm *pcm;
12253 + int retval;
12254 +
12255 + retval = snd_pcm_new(chip->card, chip->card->shortname,
12256 + device, 1, 0, &pcm);
12257 + if (retval < 0)
12258 + goto out;
12259 +
12260 + pcm->private_data = chip;
12261 + pcm->private_free = snd_at73c213_pcm_free;
12262 + pcm->info_flags = SNDRV_PCM_INFO_BLOCK_TRANSFER;
12263 + strcpy(pcm->name, "at73c213");
12264 + chip->pcm = pcm;
12265 +
12266 + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &at73c213_playback_ops);
12267 +
12268 + retval = snd_pcm_lib_preallocate_pages_for_all(chip->pcm,
12269 + SNDRV_DMA_TYPE_DEV, &chip->ssc->pdev->dev,
12270 + 64 * 1024, 64 * 1024);
12271 +out:
12272 + return retval;
12273 +}
12274 +
12275 +static irqreturn_t snd_at73c213_interrupt(int irq, void *dev_id)
12276 +{
12277 + struct snd_at73c213 *chip = dev_id;
12278 + struct snd_pcm_runtime *runtime = chip->substream->runtime;
12279 + u32 status;
12280 + int offset;
12281 + int block_size;
12282 + int next_period;
12283 + int retval = IRQ_NONE;
12284 +
12285 + spin_lock(&chip->lock);
12286 +
12287 + block_size = frames_to_bytes(runtime, runtime->period_size);
12288 + status = ssc_readl(chip->ssc->regs, IMR);
12289 +
12290 + if (status & SSC_BIT(IMR_ENDTX)) {
12291 + chip->period++;
12292 + if (chip->period == runtime->periods)
12293 + chip->period = 0;
12294 + next_period = chip->period + 1;
12295 + if (next_period == runtime->periods)
12296 + next_period = 0;
12297 +
12298 + offset = block_size * next_period;
12299 +
12300 + ssc_writel(chip->ssc->regs, PDC_TNPR,
12301 + (long)runtime->dma_addr + offset);
12302 + ssc_writel(chip->ssc->regs, PDC_TNCR, runtime->period_size * 2);
12303 + retval = IRQ_HANDLED;
12304 + }
12305 +
12306 + ssc_readl(chip->ssc->regs, IMR);
12307 + spin_unlock(&chip->lock);
12308 +
12309 + if (status & SSC_BIT(IMR_ENDTX))
12310 + snd_pcm_period_elapsed(chip->substream);
12311 +
12312 + return retval;
12313 +}
12314 +
12315 +/*
12316 + * Mixer functions.
12317 + */
12318 +static int snd_at73c213_mono_get(struct snd_kcontrol *kcontrol,
12319 + struct snd_ctl_elem_value *ucontrol)
12320 +{
12321 + struct snd_at73c213 *chip = snd_kcontrol_chip(kcontrol);
12322 + int reg = kcontrol->private_value & 0xff;
12323 + int shift = (kcontrol->private_value >> 8) & 0xff;
12324 + int mask = (kcontrol->private_value >> 16) & 0xff;
12325 + int invert = (kcontrol->private_value >> 24) & 0xff;
12326 +
12327 + spin_lock_irq(&chip->lock);
12328 +
12329 + ucontrol->value.integer.value[0] = (chip->reg_image[reg] >> shift) & mask;
12330 +
12331 + if (invert)
12332 + ucontrol->value.integer.value[0] =
12333 + (mask - ucontrol->value.integer.value[0]);
12334 +
12335 + spin_unlock_irq(&chip->lock);
12336 +
12337 + return 0;
12338 +}
12339 +
12340 +static int snd_at73c213_mono_put(struct snd_kcontrol *kcontrol,
12341 + struct snd_ctl_elem_value *ucontrol)
12342 +{
12343 + struct snd_at73c213 *chip = snd_kcontrol_chip(kcontrol);
12344 + int reg = kcontrol->private_value & 0xff;
12345 + int shift = (kcontrol->private_value >> 8) & 0xff;
12346 + int mask = (kcontrol->private_value >> 16) & 0xff;
12347 + int invert = (kcontrol->private_value >> 24) & 0xff;
12348 + int change, retval;
12349 + unsigned short val;
12350 +
12351 + val = (ucontrol->value.integer.value[0] & mask);
12352 + if (invert)
12353 + val = mask - val;
12354 + val <<= shift;
12355 +
12356 + spin_lock_irq(&chip->lock);
12357 +
12358 + val = (chip->reg_image[reg] & ~(mask << shift)) | val;
12359 + change = val != chip->reg_image[reg];
12360 + retval = snd_at73c213_write_reg(chip, reg, val);
12361 +
12362 + spin_unlock_irq(&chip->lock);
12363 +
12364 + if (retval)
12365 + return retval;
12366 +
12367 + return change;
12368 +}
12369 +
12370 +static int snd_at73c213_stereo_info(struct snd_kcontrol *kcontrol,
12371 + struct snd_ctl_elem_info *uinfo)
12372 +{
12373 + int mask = (kcontrol->private_value >> 24) & 0xff;
12374 +
12375 + if (mask == 1)
12376 + uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
12377 + else
12378 + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
12379 +
12380 + uinfo->count = 2;
12381 + uinfo->value.integer.min = 0;
12382 + uinfo->value.integer.max = mask;
12383 +
12384 + return 0;
12385 +}
12386 +
12387 +static int snd_at73c213_stereo_get(struct snd_kcontrol *kcontrol,
12388 + struct snd_ctl_elem_value *ucontrol)
12389 +{
12390 + struct snd_at73c213 *chip = snd_kcontrol_chip(kcontrol);
12391 + int left_reg = kcontrol->private_value & 0xff;
12392 + int right_reg = (kcontrol->private_value >> 8) & 0xff;
12393 + int shift_left = (kcontrol->private_value >> 16) & 0x07;
12394 + int shift_right = (kcontrol->private_value >> 19) & 0x07;
12395 + int mask = (kcontrol->private_value >> 24) & 0xff;
12396 + int invert = (kcontrol->private_value >> 22) & 1;
12397 +
12398 + spin_lock_irq(&chip->lock);
12399 +
12400 + ucontrol->value.integer.value[0] =
12401 + (chip->reg_image[left_reg] >> shift_left) & mask;
12402 + ucontrol->value.integer.value[1] =
12403 + (chip->reg_image[right_reg] >> shift_right) & mask;
12404 +
12405 + if (invert) {
12406 + ucontrol->value.integer.value[0] =
12407 + (mask - ucontrol->value.integer.value[0]);
12408 + ucontrol->value.integer.value[1] =
12409 + (mask - ucontrol->value.integer.value[1]);
12410 + }
12411 +
12412 + spin_unlock_irq(&chip->lock);
12413 +
12414 + return 0;
12415 +}
12416 +
12417 +static int snd_at73c213_stereo_put(struct snd_kcontrol *kcontrol,
12418 + struct snd_ctl_elem_value *ucontrol)
12419 +{
12420 + struct snd_at73c213 *chip = snd_kcontrol_chip(kcontrol);
12421 + int left_reg = kcontrol->private_value & 0xff;
12422 + int right_reg = (kcontrol->private_value >> 8) & 0xff;
12423 + int shift_left = (kcontrol->private_value >> 16) & 0x07;
12424 + int shift_right = (kcontrol->private_value >> 19) & 0x07;
12425 + int mask = (kcontrol->private_value >> 24) & 0xff;
12426 + int invert = (kcontrol->private_value >> 22) & 1;
12427 + int change, retval;
12428 + unsigned short val1, val2;
12429 +
12430 + val1 = ucontrol->value.integer.value[0] & mask;
12431 + val2 = ucontrol->value.integer.value[1] & mask;
12432 + if (invert) {
12433 + val1 = mask - val1;
12434 + val2 = mask - val2;
12435 + }
12436 + val1 <<= shift_left;
12437 + val2 <<= shift_right;
12438 +
12439 + spin_lock_irq(&chip->lock);
12440 +
12441 + val1 = (chip->reg_image[left_reg] & ~(mask << shift_left)) | val1;
12442 + val2 = (chip->reg_image[right_reg] & ~(mask << shift_right)) | val2;
12443 + change = val1 != chip->reg_image[left_reg]
12444 + || val2 != chip->reg_image[right_reg];
12445 + retval = snd_at73c213_write_reg(chip, left_reg, val1);
12446 + if (retval) {
12447 + spin_unlock_irq(&chip->lock);
12448 + goto out;
12449 + }
12450 + retval = snd_at73c213_write_reg(chip, right_reg, val2);
12451 + if (retval) {
12452 + spin_unlock_irq(&chip->lock);
12453 + goto out;
12454 + }
12455 +
12456 + spin_unlock_irq(&chip->lock);
12457 +
12458 + return change;
12459 +
12460 +out:
12461 + return retval;
12462 +}
12463 +
12464 +static int snd_at73c213_mono_switch_info(struct snd_kcontrol *kcontrol,
12465 + struct snd_ctl_elem_info *uinfo)
12466 +{
12467 + uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
12468 + uinfo->count = 1;
12469 + uinfo->value.integer.min = 0;
12470 + uinfo->value.integer.max = 1;
12471 +
12472 + return 0;
12473 +}
12474 +
12475 +static int snd_at73c213_mono_switch_get(struct snd_kcontrol *kcontrol,
12476 + struct snd_ctl_elem_value *ucontrol)
12477 +{
12478 + struct snd_at73c213 *chip = snd_kcontrol_chip(kcontrol);
12479 + int reg = kcontrol->private_value & 0xff;
12480 + int shift = (kcontrol->private_value >> 8) & 0xff;
12481 + int invert = (kcontrol->private_value >> 24) & 0xff;
12482 +
12483 + spin_lock_irq(&chip->lock);
12484 +
12485 + ucontrol->value.integer.value[0] = (chip->reg_image[reg] >> shift) & 0x01;
12486 +
12487 + if (invert)
12488 + ucontrol->value.integer.value[0] =
12489 + (0x01 - ucontrol->value.integer.value[0]);
12490 +
12491 + spin_unlock_irq(&chip->lock);
12492 +
12493 + return 0;
12494 +}
12495 +
12496 +static int snd_at73c213_mono_switch_put(struct snd_kcontrol *kcontrol,
12497 + struct snd_ctl_elem_value *ucontrol)
12498 +{
12499 + struct snd_at73c213 *chip = snd_kcontrol_chip(kcontrol);
12500 + int reg = kcontrol->private_value & 0xff;
12501 + int shift = (kcontrol->private_value >> 8) & 0xff;
12502 + int mask = (kcontrol->private_value >> 16) & 0xff;
12503 + int invert = (kcontrol->private_value >> 24) & 0xff;
12504 + int change, retval;
12505 + unsigned short val;
12506 +
12507 + if (ucontrol->value.integer.value[0])
12508 + val = mask;
12509 + else
12510 + val = 0;
12511 +
12512 + if (invert)
12513 + val = mask - val;
12514 + val <<= shift;
12515 +
12516 + spin_lock_irq(&chip->lock);
12517 +
12518 + val |= (chip->reg_image[reg] & ~(mask << shift));
12519 + change = val != chip->reg_image[reg];
12520 +
12521 + retval = snd_at73c213_write_reg(chip, reg, val);
12522 +
12523 + spin_unlock_irq(&chip->lock);
12524 +
12525 + if (retval)
12526 + return retval;
12527 +
12528 + return change;
12529 +}
12530 +
12531 +static int snd_at73c213_pa_volume_info(struct snd_kcontrol *kcontrol,
12532 + struct snd_ctl_elem_info *uinfo)
12533 +{
12534 + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
12535 + uinfo->count = 1;
12536 + uinfo->value.integer.min = 0;
12537 + uinfo->value.integer.max = ((kcontrol->private_value >> 16) & 0xff) - 1;
12538 +
12539 + return 0;
12540 +}
12541 +
12542 +static int snd_at73c213_line_capture_volume_info(
12543 + struct snd_kcontrol *kcontrol,
12544 + struct snd_ctl_elem_info *uinfo)
12545 +{
12546 + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
12547 + uinfo->count = 2;
12548 + /* When inverted will give values 0x10001 => 0. */
12549 + uinfo->value.integer.min = 14;
12550 + uinfo->value.integer.max = 31;
12551 +
12552 + return 0;
12553 +}
12554 +
12555 +static int snd_at73c213_aux_capture_volume_info(
12556 + struct snd_kcontrol *kcontrol,
12557 + struct snd_ctl_elem_info *uinfo)
12558 +{
12559 + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
12560 + uinfo->count = 1;
12561 + /* When inverted will give values 0x10001 => 0. */
12562 + uinfo->value.integer.min = 14;
12563 + uinfo->value.integer.max = 31;
12564 +
12565 + return 0;
12566 +}
12567 +
12568 +#define AT73C213_MONO_SWITCH(xname, xindex, reg, shift, mask, invert) \
12569 +{ \
12570 + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
12571 + .name = xname, \
12572 + .index = xindex, \
12573 + .info = snd_at73c213_mono_switch_info, \
12574 + .get = snd_at73c213_mono_switch_get, \
12575 + .put = snd_at73c213_mono_switch_put, \
12576 + .private_value = (reg | (shift << 8) | (mask << 16) | (invert << 24)) \
12577 +}
12578 +
12579 +#define AT73C213_STEREO(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \
12580 +{ \
12581 + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
12582 + .name = xname, \
12583 + .index = xindex, \
12584 + .info = snd_at73c213_stereo_info, \
12585 + .get = snd_at73c213_stereo_get, \
12586 + .put = snd_at73c213_stereo_put, \
12587 + .private_value = (left_reg | (right_reg << 8) \
12588 + | (shift_left << 16) | (shift_right << 19) \
12589 + | (mask << 24) | (invert << 22)) \
12590 +}
12591 +
12592 +static struct snd_kcontrol_new snd_at73c213_controls[] __devinitdata = {
12593 +AT73C213_STEREO("Master Playback Volume", 0, DAC_LMPG, DAC_RMPG, 0, 0, 0x1f, 1),
12594 +AT73C213_STEREO("Master Playback Switch", 0, DAC_LMPG, DAC_RMPG, 5, 5, 1, 1),
12595 +AT73C213_STEREO("PCM Playback Volume", 0, DAC_LLOG, DAC_RLOG, 0, 0, 0x1f, 1),
12596 +AT73C213_STEREO("PCM Playback Switch", 0, DAC_LLOG, DAC_RLOG, 5, 5, 1, 1),
12597 +AT73C213_MONO_SWITCH("Mono PA Playback Switch", 0, DAC_CTRL, DAC_CTRL_ONPADRV, 0x01, 0),
12598 +{
12599 + .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
12600 + .name = "PA Playback Volume",
12601 + .index = 0,
12602 + .info = snd_at73c213_pa_volume_info,
12603 + .get = snd_at73c213_mono_get,
12604 + .put = snd_at73c213_mono_put,
12605 + .private_value = PA_CTRL | (PA_CTRL_APAGAIN << 8) | (0x0f << 16) | (1 << 24),
12606 +},
12607 +AT73C213_MONO_SWITCH("PA High Gain Playback Switch", 0, PA_CTRL, PA_CTRL_APALP, 0x01, 1),
12608 +AT73C213_MONO_SWITCH("PA Playback Switch", 0, PA_CTRL, PA_CTRL_APAON, 0x01, 0),
12609 +{
12610 + .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
12611 + .name = "Aux Capture Volume",
12612 + .index = 0,
12613 + .info = snd_at73c213_aux_capture_volume_info,
12614 + .get = snd_at73c213_mono_get,
12615 + .put = snd_at73c213_mono_put,
12616 + .private_value = DAC_AUXG | (0 << 8) | (0x1f << 16) | (1 << 24),
12617 +},
12618 +AT73C213_MONO_SWITCH("Aux Capture Switch", 0, DAC_CTRL, DAC_CTRL_ONAUXIN, 0x01, 0),
12619 +{
12620 + .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
12621 + .name = "Line Capture Volume",
12622 + .index = 0,
12623 + .info = snd_at73c213_line_capture_volume_info,
12624 + .get = snd_at73c213_stereo_get,
12625 + .put = snd_at73c213_stereo_put,
12626 + .private_value = DAC_LLIG | (DAC_RLIG << 8) | (0 << 16) | (0 << 19)
12627 + | (0x1f << 24) | (1 << 22),
12628 +},
12629 +AT73C213_MONO_SWITCH("Line Capture Switch", 0, DAC_CTRL, 0, 0x03, 0),
12630 +};
12631 +
12632 +static int __devinit snd_at73c213_mixer(struct snd_at73c213 *chip)
12633 +{
12634 + struct snd_card *card;
12635 + int errval, idx;
12636 +
12637 + if (chip == NULL || chip->pcm == NULL)
12638 + return -EINVAL;
12639 +
12640 + card = chip->card;
12641 +
12642 + strcpy(card->mixername, chip->pcm->name);
12643 +
12644 + for (idx = 0; idx < ARRAY_SIZE(snd_at73c213_controls); idx++) {
12645 + errval = snd_ctl_add(card,
12646 + snd_ctl_new1(&snd_at73c213_controls[idx],
12647 + chip));
12648 + if (errval < 0)
12649 + goto cleanup;
12650 + }
12651 +
12652 + return 0;
12653 +
12654 +cleanup:
12655 + for (idx = 1; idx < ARRAY_SIZE(snd_at73c213_controls) + 1; idx++) {
12656 + struct snd_kcontrol *kctl;
12657 + kctl = snd_ctl_find_numid(card, idx);
12658 + if (kctl)
12659 + snd_ctl_remove(card, kctl);
12660 + }
12661 + return errval;
12662 +}
12663 +
12664 +/*
12665 + * Device functions
12666 + */
12667 +static int snd_at73c213_ssc_init(struct snd_at73c213 *chip)
12668 +{
12669 + /*
12670 + * Continuous clock output.
12671 + * Starts on falling TF.
12672 + * Delay 1 cycle (1 bit).
12673 + * Periode is 16 bit (16 - 1).
12674 + */
12675 + ssc_writel(chip->ssc->regs, TCMR,
12676 + SSC_BF(TCMR_CKO, 1)
12677 + | SSC_BF(TCMR_START, 4)
12678 + | SSC_BF(TCMR_STTDLY, 1)
12679 + | SSC_BF(TCMR_PERIOD, 16 - 1));
12680 + /*
12681 + * Data length is 16 bit (16 - 1).
12682 + * Transmit MSB first.
12683 + * Transmit 2 words each transfer.
12684 + * Frame sync length is 16 bit (16 - 1).
12685 + * Frame starts on negative pulse.
12686 + */
12687 + ssc_writel(chip->ssc->regs, TFMR,
12688 + SSC_BF(TFMR_DATLEN, 16 - 1)
12689 + | SSC_BIT(TFMR_MSBF)
12690 + | SSC_BF(TFMR_DATNB, 1)
12691 + | SSC_BF(TFMR_FSLEN, 16 - 1)
12692 + | SSC_BF(TFMR_FSOS, 1));
12693 +
12694 + return 0;
12695 +}
12696 +
12697 +static int snd_at73c213_chip_init(struct snd_at73c213 *chip)
12698 +{
12699 + int retval;
12700 + unsigned char dac_ctrl = 0;
12701 +
12702 + retval = snd_at73c213_set_bitrate(chip);
12703 + if (retval)
12704 + goto out;
12705 +
12706 + /* Enable DAC master clock. */
12707 + clk_enable(chip->board->dac_clk);
12708 +
12709 + /* Initialize at73c213 on SPI bus. */
12710 + retval = snd_at73c213_write_reg(chip, DAC_RST, 0x04);
12711 + if (retval)
12712 + goto out_clk;
12713 + msleep(1);
12714 + retval = snd_at73c213_write_reg(chip, DAC_RST, 0x03);
12715 + if (retval)
12716 + goto out_clk;
12717 +
12718 + /* Precharge everything. */
12719 + retval = snd_at73c213_write_reg(chip, DAC_PRECH, 0xff);
12720 + if (retval)
12721 + goto out_clk;
12722 + retval = snd_at73c213_write_reg(chip, PA_CTRL, (1<<PA_CTRL_APAPRECH));
12723 + if (retval)
12724 + goto out_clk;
12725 + retval = snd_at73c213_write_reg(chip, DAC_CTRL,
12726 + (1<<DAC_CTRL_ONLNOL) | (1<<DAC_CTRL_ONLNOR));
12727 + if (retval)
12728 + goto out_clk;
12729 +
12730 + msleep(50);
12731 +
12732 + /* Stop precharging PA. */
12733 + retval = snd_at73c213_write_reg(chip, PA_CTRL,
12734 + (1<<PA_CTRL_APALP) | 0x0f);
12735 + if (retval)
12736 + goto out_clk;
12737 +
12738 + msleep(450);
12739 +
12740 + /* Stop precharging DAC, turn on master power. */
12741 + retval = snd_at73c213_write_reg(chip, DAC_PRECH, (1<<DAC_PRECH_ONMSTR));
12742 + if (retval)
12743 + goto out_clk;
12744 +
12745 + msleep(1);
12746 +
12747 + /* Turn on DAC. */
12748 + dac_ctrl = (1<<DAC_CTRL_ONDACL) | (1<<DAC_CTRL_ONDACR)
12749 + | (1<<DAC_CTRL_ONLNOL) | (1<<DAC_CTRL_ONLNOR);
12750 +
12751 + retval = snd_at73c213_write_reg(chip, DAC_CTRL, dac_ctrl);
12752 + if (retval)
12753 + goto out_clk;
12754 +
12755 + /* Mute sound. */
12756 + retval = snd_at73c213_write_reg(chip, DAC_LMPG, 0x3f);
12757 + if (retval)
12758 + goto out_clk;
12759 + retval = snd_at73c213_write_reg(chip, DAC_RMPG, 0x3f);
12760 + if (retval)
12761 + goto out_clk;
12762 + retval = snd_at73c213_write_reg(chip, DAC_LLOG, 0x3f);
12763 + if (retval)
12764 + goto out_clk;
12765 + retval = snd_at73c213_write_reg(chip, DAC_RLOG, 0x3f);
12766 + if (retval)
12767 + goto out_clk;
12768 + retval = snd_at73c213_write_reg(chip, DAC_LLIG, 0x11);
12769 + if (retval)
12770 + goto out_clk;
12771 + retval = snd_at73c213_write_reg(chip, DAC_RLIG, 0x11);
12772 + if (retval)
12773 + goto out_clk;
12774 + retval = snd_at73c213_write_reg(chip, DAC_AUXG, 0x11);
12775 + if (retval)
12776 + goto out_clk;
12777 +
12778 + /* Enable I2S device, i.e. clock output. */
12779 + ssc_writel(chip->ssc->regs, CR, SSC_BIT(CR_TXEN));
12780 +
12781 + goto out;
12782 +
12783 +out_clk:
12784 + clk_disable(chip->board->dac_clk);
12785 +out:
12786 + return retval;
12787 +}
12788 +
12789 +static int snd_at73c213_dev_free(struct snd_device *device)
12790 +{
12791 + struct snd_at73c213 *chip = device->device_data;
12792 +
12793 + ssc_writel(chip->ssc->regs, CR, SSC_BIT(CR_TXDIS));
12794 + if (chip->irq >= 0) {
12795 + free_irq(chip->irq, chip);
12796 + chip->irq = -1;
12797 + }
12798 +
12799 + return 0;
12800 +}
12801 +
12802 +static int __devinit snd_at73c213_dev_init(struct snd_card *card,
12803 + struct spi_device *spi)
12804 +{
12805 + static struct snd_device_ops ops = {
12806 + .dev_free = snd_at73c213_dev_free,
12807 + };
12808 + struct snd_at73c213 *chip = get_chip(card);
12809 + int irq, retval;
12810 +
12811 + irq = chip->ssc->irq;
12812 + if (irq < 0)
12813 + return irq;
12814 +
12815 + spin_lock_init(&chip->lock);
12816 + chip->card = card;
12817 + chip->irq = -1;
12818 +
12819 + retval = request_irq(irq, snd_at73c213_interrupt, 0, "at73c213", chip);
12820 + if (retval) {
12821 + dev_dbg(&chip->spi->dev, "unable to request irq %d\n", irq);
12822 + goto out;
12823 + }
12824 + chip->irq = irq;
12825 +
12826 + memcpy(&chip->reg_image, &snd_at73c213_original_image,
12827 + sizeof(snd_at73c213_original_image));
12828 +
12829 + retval = snd_at73c213_ssc_init(chip);
12830 + if (retval)
12831 + goto out_irq;
12832 +
12833 + retval = snd_at73c213_chip_init(chip);
12834 + if (retval)
12835 + goto out_irq;
12836 +
12837 + retval = snd_at73c213_pcm_new(chip, 0);
12838 + if (retval)
12839 + goto out_irq;
12840 +
12841 + retval = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
12842 + if (retval)
12843 + goto out_irq;
12844 +
12845 + retval = snd_at73c213_mixer(chip);
12846 + if (retval)
12847 + goto out_snd_dev;
12848 +
12849 + snd_card_set_dev(card, &spi->dev);
12850 +
12851 + goto out;
12852 +
12853 +out_snd_dev:
12854 + snd_device_free(card, chip);
12855 +out_irq:
12856 + free_irq(chip->irq, chip);
12857 + chip->irq = -1;
12858 +out:
12859 + return retval;
12860 +}
12861 +
12862 +static int snd_at73c213_probe(struct spi_device *spi)
12863 +{
12864 + struct snd_card *card;
12865 + struct snd_at73c213 *chip;
12866 + struct at73c213_board_info *board;
12867 + int retval;
12868 + char id[16];
12869 +
12870 + board = spi->dev.platform_data;
12871 + if (!board) {
12872 + dev_dbg(&spi->dev, "no platform_data\n");
12873 + return -ENXIO;
12874 + }
12875 +
12876 + if (!board->dac_clk) {
12877 + dev_dbg(&spi->dev, "no DAC clk\n");
12878 + return -ENXIO;
12879 + }
12880 +
12881 + if (IS_ERR(board->dac_clk)) {
12882 + dev_dbg(&spi->dev, "no DAC clk\n");
12883 + return PTR_ERR(board->dac_clk);
12884 + }
12885 +
12886 + retval = -ENOMEM;
12887 +
12888 + /* Allocate "card" using some unused identifiers. */
12889 + snprintf(id, sizeof id, "at73c213_%d", board->ssc_id);
12890 + card = snd_card_new(-1, id, THIS_MODULE, sizeof(struct snd_at73c213));
12891 + if (!card)
12892 + goto out;
12893 +
12894 + chip = card->private_data;
12895 + chip->spi = spi;
12896 + chip->board = board;
12897 +
12898 + chip->ssc = ssc_request(board->ssc_id);
12899 + if (IS_ERR(chip->ssc)) {
12900 + dev_dbg(&spi->dev, "could not get ssc%d device\n",
12901 + board->ssc_id);
12902 + retval = PTR_ERR(chip->ssc);
12903 + goto out_card;
12904 + }
12905 +
12906 + retval = snd_at73c213_dev_init(card, spi);
12907 + if (retval)
12908 + goto out_ssc;
12909 +
12910 + strcpy(card->driver, "at73c213");
12911 + strcpy(card->shortname, board->shortname);
12912 + sprintf(card->longname, "%s on irq %d", card->shortname, chip->irq);
12913 +
12914 + retval = snd_card_register(card);
12915 + if (retval)
12916 + goto out_ssc;
12917 +
12918 + dev_set_drvdata(&spi->dev, card);
12919 +
12920 + goto out;
12921 +
12922 +out_ssc:
12923 + ssc_free(chip->ssc);
12924 +out_card:
12925 + snd_card_free(card);
12926 +out:
12927 + return retval;
12928 +}
12929 +
12930 +static int __devexit snd_at73c213_remove(struct spi_device *spi)
12931 +{
12932 + struct snd_card *card = dev_get_drvdata(&spi->dev);
12933 + struct snd_at73c213 *chip = card->private_data;
12934 + int retval;
12935 +
12936 + /* Stop playback. */
12937 + ssc_writel(chip->ssc->regs, CR, SSC_BIT(CR_TXDIS));
12938 +
12939 + /* Mute sound. */
12940 + retval = snd_at73c213_write_reg(chip, DAC_LMPG, 0x3f);
12941 + if (retval)
12942 + goto out;
12943 + retval = snd_at73c213_write_reg(chip, DAC_RMPG, 0x3f);
12944 + if (retval)
12945 + goto out;
12946 + retval = snd_at73c213_write_reg(chip, DAC_LLOG, 0x3f);
12947 + if (retval)
12948 + goto out;
12949 + retval = snd_at73c213_write_reg(chip, DAC_RLOG, 0x3f);
12950 + if (retval)
12951 + goto out;
12952 + retval = snd_at73c213_write_reg(chip, DAC_LLIG, 0x11);
12953 + if (retval)
12954 + goto out;
12955 + retval = snd_at73c213_write_reg(chip, DAC_RLIG, 0x11);
12956 + if (retval)
12957 + goto out;
12958 + retval = snd_at73c213_write_reg(chip, DAC_AUXG, 0x11);
12959 + if (retval)
12960 + goto out;
12961 +
12962 + /* Turn off PA. */
12963 + retval = snd_at73c213_write_reg(chip, PA_CTRL, (chip->reg_image[PA_CTRL]|0x0f));
12964 + if (retval)
12965 + goto out;
12966 + msleep(10);
12967 + retval = snd_at73c213_write_reg(chip, PA_CTRL, (1<<PA_CTRL_APALP)|0x0f);
12968 + if (retval)
12969 + goto out;
12970 +
12971 + /* Turn off external DAC. */
12972 + retval = snd_at73c213_write_reg(chip, DAC_CTRL, 0x0c);
12973 + if (retval)
12974 + goto out;
12975 + msleep(2);
12976 + retval = snd_at73c213_write_reg(chip, DAC_CTRL, 0x00);
12977 + if (retval)
12978 + goto out;
12979 +
12980 + /* Turn off master power. */
12981 + retval = snd_at73c213_write_reg(chip, DAC_PRECH, 0x00);
12982 + if (retval)
12983 + goto out;
12984 +
12985 +out:
12986 + /* Stop DAC master clock. */
12987 + clk_disable(chip->board->dac_clk);
12988 +
12989 + ssc_free(chip->ssc);
12990 + snd_card_free(card);
12991 + dev_set_drvdata(&spi->dev, NULL);
12992 +
12993 + return 0;
12994 +}
12995 +
12996 +#ifdef CONFIG_PM
12997 +static int snd_at73c213_suspend(struct spi_device *spi, pm_message_t msg)
12998 +{
12999 + struct snd_card *card = dev_get_drvdata(&spi->dev);
13000 + struct snd_at73c213 *chip = card->private_data;
13001 +
13002 + ssc_writel(chip->ssc->regs, CR, SSC_BIT(CR_TXDIS));
13003 + clk_disable(chip->board->dac_clk);
13004 +
13005 + return 0;
13006 +}
13007 +
13008 +static int snd_at73c213_resume(struct spi_device *spi)
13009 +{
13010 + struct snd_card *card = dev_get_drvdata(&spi->dev);
13011 + struct snd_at73c213 *chip = card->private_data;
13012 +
13013 + clk_enable(chip->board->dac_clk);
13014 + ssc_writel(chip->ssc->regs, CR, SSC_BIT(CR_TXEN));
13015 +
13016 + return 0;
13017 +}
13018 +#else
13019 +#define snd_at73c213_suspend NULL
13020 +#define snd_at73c213_resume NULL
13021 +#endif
13022 +
13023 +static struct spi_driver at73c213_driver = {
13024 + .driver = {
13025 + .name = "at73c213",
13026 + },
13027 + .probe = snd_at73c213_probe,
13028 + .suspend = snd_at73c213_suspend,
13029 + .resume = snd_at73c213_resume,
13030 + .remove = __devexit_p(snd_at73c213_remove),
13031 +};
13032 +
13033 +static int __init at73c213_init(void)
13034 +{
13035 + return spi_register_driver(&at73c213_driver);
13036 +}
13037 +module_init(at73c213_init);
13038 +
13039 +static void __exit at73c213_exit(void)
13040 +{
13041 + spi_unregister_driver(&at73c213_driver);
13042 +}
13043 +module_exit(at73c213_exit);
13044 +
13045 +MODULE_AUTHOR("Hans-Christian Egtvedt <hcegtvedt@atmel.com>");
13046 +MODULE_DESCRIPTION("Sound driver for AT73C213 with Atmel SSC");
13047 +MODULE_LICENSE("GPL");
13048 diff --git a/sound/spi/at73c213.h b/sound/spi/at73c213.h
13049 new file mode 100644
13050 index 0000000..fd8b372
13051 --- /dev/null
13052 +++ b/sound/spi/at73c213.h
13053 @@ -0,0 +1,119 @@
13054 +/*
13055 + * Driver for the AT73C213 16-bit stereo DAC on Atmel ATSTK1000
13056 + *
13057 + * Copyright (C) 2006 - 2007 Atmel Corporation
13058 + *
13059 + * This program is free software; you can redistribute it and/or
13060 + * modify it under the terms of the GNU General Public License as
13061 + * published by the Free Software Foundation; either version 2 of the
13062 + * License, or (at your option) any later version.
13063 + *
13064 + * This program is distributed in the hope that it will be useful, but
13065 + * WITHOUT ANY WARRANTY; without even the implied warranty of
13066 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13067 + * General Public License for more details.
13068 + *
13069 + * You should have received a copy of the GNU General Public License
13070 + * along with this program; if not, write to the Free Software
13071 + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
13072 + * 02111-1307, USA.
13073 + *
13074 + * The full GNU General Public License is included in this
13075 + * distribution in the file called COPYING.
13076 + */
13077 +
13078 +#ifndef _SND_AT73C213_H
13079 +#define _SND_AT73C213_H
13080 +
13081 +/* DAC control register */
13082 +#define DAC_CTRL 0x00
13083 +#define DAC_CTRL_ONPADRV 7
13084 +#define DAC_CTRL_ONAUXIN 6
13085 +#define DAC_CTRL_ONDACR 5
13086 +#define DAC_CTRL_ONDACL 4
13087 +#define DAC_CTRL_ONLNOR 3
13088 +#define DAC_CTRL_ONLNOL 2
13089 +#define DAC_CTRL_ONLNIR 1
13090 +#define DAC_CTRL_ONLNIL 0
13091 +
13092 +/* DAC left line in gain register */
13093 +#define DAC_LLIG 0x01
13094 +#define DAC_LLIG_LLIG 0
13095 +
13096 +/* DAC right line in gain register */
13097 +#define DAC_RLIG 0x02
13098 +#define DAC_RLIG_RLIG 0
13099 +
13100 +/* DAC Left Master Playback Gain Register */
13101 +#define DAC_LMPG 0x03
13102 +#define DAC_LMPG_LMPG 0
13103 +
13104 +/* DAC Right Master Playback Gain Register */
13105 +#define DAC_RMPG 0x04
13106 +#define DAC_RMPG_RMPG 0
13107 +
13108 +/* DAC Left Line Out Gain Register */
13109 +#define DAC_LLOG 0x05
13110 +#define DAC_LLOG_LLOG 0
13111 +
13112 +/* DAC Right Line Out Gain Register */
13113 +#define DAC_RLOG 0x06
13114 +#define DAC_RLOG_RLOG 0
13115 +
13116 +/* DAC Output Level Control Register */
13117 +#define DAC_OLC 0x07
13118 +#define DAC_OLC_RSHORT 7
13119 +#define DAC_OLC_ROLC 4
13120 +#define DAC_OLC_LSHORT 3
13121 +#define DAC_OLC_LOLC 0
13122 +
13123 +/* DAC Mixer Control Register */
13124 +#define DAC_MC 0x08
13125 +#define DAC_MC_INVR 5
13126 +#define DAC_MC_INVL 4
13127 +#define DAC_MC_RMSMIN2 3
13128 +#define DAC_MC_RMSMIN1 2
13129 +#define DAC_MC_LMSMIN2 1
13130 +#define DAC_MC_LMSMIN1 0
13131 +
13132 +/* DAC Clock and Sampling Frequency Control Register */
13133 +#define DAC_CSFC 0x09
13134 +#define DAC_CSFC_OVRSEL 4
13135 +
13136 +/* DAC Miscellaneous Register */
13137 +#define DAC_MISC 0x0A
13138 +#define DAC_MISC_VCMCAPSEL 7
13139 +#define DAC_MISC_DINTSEL 4
13140 +#define DAC_MISC_DITHEN 3
13141 +#define DAC_MISC_DEEMPEN 2
13142 +#define DAC_MISC_NBITS 0
13143 +
13144 +/* DAC Precharge Control Register */
13145 +#define DAC_PRECH 0x0C
13146 +#define DAC_PRECH_PRCHGPDRV 7
13147 +#define DAC_PRECH_PRCHGAUX1 6
13148 +#define DAC_PRECH_PRCHGLNOR 5
13149 +#define DAC_PRECH_PRCHGLNOL 4
13150 +#define DAC_PRECH_PRCHGLNIR 3
13151 +#define DAC_PRECH_PRCHGLNIL 2
13152 +#define DAC_PRECH_PRCHG 1
13153 +#define DAC_PRECH_ONMSTR 0
13154 +
13155 +/* DAC Auxiliary Input Gain Control Register */
13156 +#define DAC_AUXG 0x0D
13157 +#define DAC_AUXG_AUXG 0
13158 +
13159 +/* DAC Reset Register */
13160 +#define DAC_RST 0x10
13161 +#define DAC_RST_RESMASK 2
13162 +#define DAC_RST_RESFILZ 1
13163 +#define DAC_RST_RSTZ 0
13164 +
13165 +/* Power Amplifier Control Register */
13166 +#define PA_CTRL 0x11
13167 +#define PA_CTRL_APAON 6
13168 +#define PA_CTRL_APAPRECH 5
13169 +#define PA_CTRL_APALP 4
13170 +#define PA_CTRL_APAGAIN 0
13171 +
13172 +#endif /* _SND_AT73C213_H */
OpenWrt Source Repository