target/linux/bcm53xx/patches-4.1/077-ARM-l2c-Add-support-for-the-arm-shared-override-prop.patch

   1 From 1bc7c02e7f37ddfa09cb0db330ee8cd4034d6410 Mon Sep 17 00:00:00 2001
   2 From: Geert Uytterhoeven <geert+renesas@glider.be>
   3 Date: Thu, 7 May 2015 11:27:11 +0200
   4 Subject: [PATCH 1/4] ARM: l2c: Add support for the "arm, shared-override"
   5  property
   6
   7 "CoreLink Level 2 Cache Controller L2C-310", p. 2-15, section 2.3.2
   8 Shareable attribute" states:
   9
  10     "The default behavior of the cache controller with respect to the
  11      shareable attribute is to transform Normal Memory Non-cacheable
  12      transactions into:
  13         - cacheable no allocate for reads
  14         - write through no write allocate for writes."
  15
  16 Depending on the system architecture, this may cause memory corruption
  17 in the presence of bus mastering devices (e.g. OHCI). To avoid such
  18 corruption, the default behavior can be disabled by setting the Shared
  19 Override bit in the Auxiliary Control register.
  20
  21 Currently the Shared Override bit can be set only using C code:
  22   - by calling l2x0_init() directly, which is deprecated,
  23   - by setting/clearing the bit in the machine_desc.l2c_aux_val/mask
  24     fields, but using values differing from 0/~0 is also deprecated.
  25
  26 Hence add support for an "arm,shared-override" device tree property for
  27 the l2c device node. By specifying this property, affected systems can
  28 indicate that non-cacheable transactions must not be transformed.
  29 Then, it's up to the OS to decide. The current behavior is to set the
  30 "shared attribute override enable" bit, as there may exist kernel linear
  31 mappings and cacheable aliases for the DMA buffers, even if CMA is
  32 enabled.
  33
  34 See also commit 1a8e41cd672f894b ("ARM: 6395/1: VExpress: Set bit 22 in
  35 the PL310 (cache controller) AuxCtlr register"):
  36
  37     "Clearing bit 22 in the PL310 Auxiliary Control register (shared
  38      attribute override enable) has the side effect of transforming
  39      Normal Shared Non-cacheable reads into Cacheable no-allocate reads.
  40
  41      Coherent DMA buffers in Linux always have a Cacheable alias via the
  42      kernel linear mapping and the processor can speculatively load
  43      cache lines into the PL310 controller. With bit 22 cleared,
  44      Non-cacheable reads would unexpectedly hit such cache lines leading
  45      to buffer corruption."
  46
  47 Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
  48 ---
  49  Documentation/devicetree/bindings/arm/l2cc.txt | 6 ++++++
  50  arch/arm/mm/cache-l2x0.c                       | 5 +++++
  51  2 files changed, 11 insertions(+)
  52
  53 --- a/Documentation/devicetree/bindings/arm/l2cc.txt
  54 +++ b/Documentation/devicetree/bindings/arm/l2cc.txt
  55 @@ -72,6 +72,12 @@ Optional properties:
  56  - prefetch-instr : Instruction prefetch. Value: <0> (forcibly disable),
  57    <1> (forcibly enable), property absent (retain settings set by
  58    firmware)
  59 +- arm,shared-override : The default behavior of the pl310 cache controller with
  60 +  respect to the shareable attribute is to transform "normal memory
  61 +  non-cacheable transactions" into "cacheable no allocate" (for reads) or
  62 +  "write through no write allocate" (for writes).
  63 +  On systems where this may cause DMA buffer corruption, this property must be
  64 +  specified to indicate that such transforms are precluded.
  65
  66  Example:
  67
  68 --- a/arch/arm/mm/cache-l2x0.c
  69 +++ b/arch/arm/mm/cache-l2x0.c
  70 @@ -1171,6 +1171,11 @@ static void __init l2c310_of_parse(const
  71                 }
  72         }
  73
  74 +       if (of_property_read_bool(np, "arm,shared-override")) {
  75 +               *aux_val |= L2C_AUX_CTRL_SHARED_OVERRIDE;
  76 +               *aux_mask &= ~L2C_AUX_CTRL_SHARED_OVERRIDE;
  77 +       }
  78 +
  79         prefetch = l2x0_saved_regs.prefetch_ctrl;
  80
  81         ret = of_property_read_u32(np, "arm,double-linefill", &val);