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bcm53xx: add upstream nand driver
[openwrt/openwrt.git] / target / linux / bcm53xx / patches-4.1 / 092-Add-Broadcom-STB-NAND.patch
1 This contains the following commits:
2
3 commit bcb83a19d3ac95fe3c0e79e942fb628120738853
4 Author: Hauke Mehrtens <hauke@hauke-m.de>
5 Date: Sun May 17 17:41:01 2015 +0200
6
7 mtd: brcmnand: do not make local variable static
8
9 Remove static in front of ctrl. This variable should not be shared
10 between different instances of brcmnand_probe(), it should be local to
11 this function and stored on the stack.
12
13 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
14 Signed-off-by: Brian Norris <computersforpeace@gmail.com>
15
16 commit 802041247a0abbeaf1dddb8a8d56f491762ae357
17 Author: Hauke Mehrtens <hauke@hauke-m.de>
18 Date: Sun May 17 17:41:00 2015 +0200
19
20 mtd: brcmnand: remove double new line from print
21
22 The caller already adds a new line and in the other cases there is no
23 new line added.
24
25 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
26 Signed-off-by: Brian Norris <computersforpeace@gmail.com>
27
28 commit f628ece6636c2f0354a52566cafdea6d2f963b3d
29 Author: Brian Norris <computersforpeace@gmail.com>
30 Date: Tue May 12 12:13:14 2015 -0700
31
32 mtd: brcmnand: add BCM63138 support
33
34 Signed-off-by: Brian Norris <computersforpeace@gmail.com>
35 Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
36 Tested-by: Florian Fainelli <f.fainelli@gmail.com>
37
38 commit ca22f040dd145fc4d8069ce174f6eb0bc3ebd19f
39 Author: Brian Norris <computersforpeace@gmail.com>
40 Date: Tue May 12 12:12:02 2015 -0700
41
42 mtd: brcmnand: add support for Broadcom's IPROC family
43
44 Signed-off-by: Brian Norris <computersforpeace@gmail.com>
45
46
47 commit c26211d37f11d5913d9803fdede6d053f918ba7b
48 Author: Brian Norris <computersforpeace@gmail.com>
49 Date: Tue May 12 12:09:28 2015 -0700
50
51 mtd: brcmnand: add extra SoC support to library
52
53 There are a few small hooks required for chips like BCM63138 and the
54 iProc family. Let's introduce those now.
55
56 Signed-off-by: Brian Norris <computersforpeace@gmail.com>
57 Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
58 Tested-by: Florian Fainelli <f.fainelli@gmail.com>
59
60 commit 303b4420ff1896b444017b5b0eb8252ce197797d
61 Author: Brian Norris <computersforpeace@gmail.com>
62 Date: Tue May 12 17:00:57 2015 -0700
63
64 mtd: brcmnand: add support for STB chips
65
66 BCM7xxx chips are supported entirely by the library code, since they use
67 generic irqchip interfaces and don't need any extra SoC-specific
68 configuration.
69
70 Signed-off-by: Brian Norris <computersforpeace@gmail.com>
71
72 commit 27c5b17cd1b10564fa36f8f51e4b4b41436ecc32
73 Author: Brian Norris <computersforpeace@gmail.com>
74 Date: Fri Mar 6 11:38:08 2015 -0800
75
76 mtd: nand: add NAND driver "library" for Broadcom STB NAND controller
77
78 This core originated in Set-Top Box chips (BCM7xxx) but is used in a
79 variety of other Broadcom chips, including some BCM63xxx, BCM33xx, and
80 iProc/Cygnus. It's been used only on ARM and MIPS SoCs, so restrict it
81 to those architectures.
82
83 There are multiple revisions of this core throughout the years, and
84 almost every version broke register compatibility in some small way, but
85 with some effort, this driver is able to support v4.0, v5.0, v6.x, v7.0,
86 and v7.1. It's been tested on v5.0, v6.0, v6.1, v7.0, and v7.1 recently,
87 so there hopefully are no more lurking inconsistencies.
88
89 This patch adds just some library support, on which platform drivers can
90 be built.
91
92 Signed-off-by: Brian Norris <computersforpeace@gmail.com>
93 Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
94 Tested-by: Florian Fainelli <f.fainelli@gmail.com>
95
96 --- a/drivers/mtd/nand/Kconfig
97 +++ b/drivers/mtd/nand/Kconfig
98 @@ -394,6 +394,14 @@ config MTD_NAND_GPMI_NAND
99 block, such as SD card. So pay attention to it when you enable
100 the GPMI.
101
102 +config MTD_NAND_BRCMNAND
103 + tristate "Broadcom STB NAND controller"
104 + depends on ARM || MIPS
105 + help
106 + Enables the Broadcom NAND controller driver. The controller was
107 + originally designed for Set-Top Box but is used on various BCM7xxx,
108 + BCM3xxx, BCM63xxx, iProc/Cygnus and more.
109 +
110 config MTD_NAND_BCM47XXNFLASH
111 tristate "Support for NAND flash on BCM4706 BCMA bus"
112 depends on BCMA_NFLASH
113 --- a/drivers/mtd/nand/Makefile
114 +++ b/drivers/mtd/nand/Makefile
115 @@ -52,5 +52,6 @@ obj-$(CONFIG_MTD_NAND_XWAY) += xway_nan
116 obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/
117 obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_nand.o
118 obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o
119 +obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
120
121 nand-objs := nand_base.o nand_bbt.o nand_timings.o
122 --- /dev/null
123 +++ b/drivers/mtd/nand/brcmnand/Makefile
124 @@ -0,0 +1,6 @@
125 +# link order matters; don't link the more generic brcmstb_nand.o before the
126 +# more specific iproc_nand.o, for instance
127 +obj-$(CONFIG_MTD_NAND_BRCMNAND) += iproc_nand.o
128 +obj-$(CONFIG_MTD_NAND_BRCMNAND) += bcm63138_nand.o
129 +obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmstb_nand.o
130 +obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand.o
131 --- /dev/null
132 +++ b/drivers/mtd/nand/brcmnand/bcm63138_nand.c
133 @@ -0,0 +1,109 @@
134 +/*
135 + * Copyright © 2015 Broadcom Corporation
136 + *
137 + * This program is free software; you can redistribute it and/or modify
138 + * it under the terms of the GNU General Public License version 2 as
139 + * published by the Free Software Foundation.
140 + *
141 + * This program is distributed in the hope that it will be useful,
142 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
143 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
144 + * GNU General Public License for more details.
145 + */
146 +
147 +#include <linux/device.h>
148 +#include <linux/io.h>
149 +#include <linux/ioport.h>
150 +#include <linux/module.h>
151 +#include <linux/of.h>
152 +#include <linux/of_address.h>
153 +#include <linux/platform_device.h>
154 +#include <linux/slab.h>
155 +
156 +#include "brcmnand.h"
157 +
158 +struct bcm63138_nand_soc {
159 + struct brcmnand_soc soc;
160 + void __iomem *base;
161 +};
162 +
163 +#define BCM63138_NAND_INT_STATUS 0x00
164 +#define BCM63138_NAND_INT_EN 0x04
165 +
166 +enum {
167 + BCM63138_CTLRDY = BIT(4),
168 +};
169 +
170 +static bool bcm63138_nand_intc_ack(struct brcmnand_soc *soc)
171 +{
172 + struct bcm63138_nand_soc *priv =
173 + container_of(soc, struct bcm63138_nand_soc, soc);
174 + void __iomem *mmio = priv->base + BCM63138_NAND_INT_STATUS;
175 + u32 val = brcmnand_readl(mmio);
176 +
177 + if (val & BCM63138_CTLRDY) {
178 + brcmnand_writel(val & ~BCM63138_CTLRDY, mmio);
179 + return true;
180 + }
181 +
182 + return false;
183 +}
184 +
185 +static void bcm63138_nand_intc_set(struct brcmnand_soc *soc, bool en)
186 +{
187 + struct bcm63138_nand_soc *priv =
188 + container_of(soc, struct bcm63138_nand_soc, soc);
189 + void __iomem *mmio = priv->base + BCM63138_NAND_INT_EN;
190 + u32 val = brcmnand_readl(mmio);
191 +
192 + if (en)
193 + val |= BCM63138_CTLRDY;
194 + else
195 + val &= ~BCM63138_CTLRDY;
196 +
197 + brcmnand_writel(val, mmio);
198 +}
199 +
200 +static int bcm63138_nand_probe(struct platform_device *pdev)
201 +{
202 + struct device *dev = &pdev->dev;
203 + struct bcm63138_nand_soc *priv;
204 + struct brcmnand_soc *soc;
205 + struct resource *res;
206 +
207 + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
208 + if (!priv)
209 + return -ENOMEM;
210 + soc = &priv->soc;
211 +
212 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-int-base");
213 + priv->base = devm_ioremap_resource(dev, res);
214 + if (IS_ERR(priv->base))
215 + return PTR_ERR(priv->base);
216 +
217 + soc->ctlrdy_ack = bcm63138_nand_intc_ack;
218 + soc->ctlrdy_set_enabled = bcm63138_nand_intc_set;
219 +
220 + return brcmnand_probe(pdev, soc);
221 +}
222 +
223 +static const struct of_device_id bcm63138_nand_of_match[] = {
224 + { .compatible = "brcm,nand-bcm63138" },
225 + {},
226 +};
227 +MODULE_DEVICE_TABLE(of, bcm63138_nand_of_match);
228 +
229 +static struct platform_driver bcm63138_nand_driver = {
230 + .probe = bcm63138_nand_probe,
231 + .remove = brcmnand_remove,
232 + .driver = {
233 + .name = "bcm63138_nand",
234 + .pm = &brcmnand_pm_ops,
235 + .of_match_table = bcm63138_nand_of_match,
236 + }
237 +};
238 +module_platform_driver(bcm63138_nand_driver);
239 +
240 +MODULE_LICENSE("GPL v2");
241 +MODULE_AUTHOR("Brian Norris");
242 +MODULE_DESCRIPTION("NAND driver for BCM63138");
243 --- /dev/null
244 +++ b/drivers/mtd/nand/brcmnand/brcmnand.c
245 @@ -0,0 +1,2246 @@
246 +/*
247 + * Copyright © 2010-2015 Broadcom Corporation
248 + *
249 + * This program is free software; you can redistribute it and/or modify
250 + * it under the terms of the GNU General Public License version 2 as
251 + * published by the Free Software Foundation.
252 + *
253 + * This program is distributed in the hope that it will be useful,
254 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
255 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
256 + * GNU General Public License for more details.
257 + */
258 +
259 +#include <linux/version.h>
260 +#include <linux/module.h>
261 +#include <linux/init.h>
262 +#include <linux/delay.h>
263 +#include <linux/device.h>
264 +#include <linux/platform_device.h>
265 +#include <linux/err.h>
266 +#include <linux/completion.h>
267 +#include <linux/interrupt.h>
268 +#include <linux/spinlock.h>
269 +#include <linux/dma-mapping.h>
270 +#include <linux/ioport.h>
271 +#include <linux/bug.h>
272 +#include <linux/kernel.h>
273 +#include <linux/bitops.h>
274 +#include <linux/mm.h>
275 +#include <linux/mtd/mtd.h>
276 +#include <linux/mtd/nand.h>
277 +#include <linux/mtd/partitions.h>
278 +#include <linux/of.h>
279 +#include <linux/of_mtd.h>
280 +#include <linux/of_platform.h>
281 +#include <linux/slab.h>
282 +#include <linux/list.h>
283 +#include <linux/log2.h>
284 +
285 +#include "brcmnand.h"
286 +
287 +/*
288 + * This flag controls if WP stays on between erase/write commands to mitigate
289 + * flash corruption due to power glitches. Values:
290 + * 0: NAND_WP is not used or not available
291 + * 1: NAND_WP is set by default, cleared for erase/write operations
292 + * 2: NAND_WP is always cleared
293 + */
294 +static int wp_on = 1;
295 +module_param(wp_on, int, 0444);
296 +
297 +/***********************************************************************
298 + * Definitions
299 + ***********************************************************************/
300 +
301 +#define DRV_NAME "brcmnand"
302 +
303 +#define CMD_NULL 0x00
304 +#define CMD_PAGE_READ 0x01
305 +#define CMD_SPARE_AREA_READ 0x02
306 +#define CMD_STATUS_READ 0x03
307 +#define CMD_PROGRAM_PAGE 0x04
308 +#define CMD_PROGRAM_SPARE_AREA 0x05
309 +#define CMD_COPY_BACK 0x06
310 +#define CMD_DEVICE_ID_READ 0x07
311 +#define CMD_BLOCK_ERASE 0x08
312 +#define CMD_FLASH_RESET 0x09
313 +#define CMD_BLOCKS_LOCK 0x0a
314 +#define CMD_BLOCKS_LOCK_DOWN 0x0b
315 +#define CMD_BLOCKS_UNLOCK 0x0c
316 +#define CMD_READ_BLOCKS_LOCK_STATUS 0x0d
317 +#define CMD_PARAMETER_READ 0x0e
318 +#define CMD_PARAMETER_CHANGE_COL 0x0f
319 +#define CMD_LOW_LEVEL_OP 0x10
320 +
321 +struct brcm_nand_dma_desc {
322 + u32 next_desc;
323 + u32 next_desc_ext;
324 + u32 cmd_irq;
325 + u32 dram_addr;
326 + u32 dram_addr_ext;
327 + u32 tfr_len;
328 + u32 total_len;
329 + u32 flash_addr;
330 + u32 flash_addr_ext;
331 + u32 cs;
332 + u32 pad2[5];
333 + u32 status_valid;
334 +} __packed;
335 +
336 +/* Bitfields for brcm_nand_dma_desc::status_valid */
337 +#define FLASH_DMA_ECC_ERROR (1 << 8)
338 +#define FLASH_DMA_CORR_ERROR (1 << 9)
339 +
340 +/* 512B flash cache in the NAND controller HW */
341 +#define FC_SHIFT 9U
342 +#define FC_BYTES 512U
343 +#define FC_WORDS (FC_BYTES >> 2)
344 +
345 +#define BRCMNAND_MIN_PAGESIZE 512
346 +#define BRCMNAND_MIN_BLOCKSIZE (8 * 1024)
347 +#define BRCMNAND_MIN_DEVSIZE (4ULL * 1024 * 1024)
348 +
349 +/* Controller feature flags */
350 +enum {
351 + BRCMNAND_HAS_1K_SECTORS = BIT(0),
352 + BRCMNAND_HAS_PREFETCH = BIT(1),
353 + BRCMNAND_HAS_CACHE_MODE = BIT(2),
354 + BRCMNAND_HAS_WP = BIT(3),
355 +};
356 +
357 +struct brcmnand_controller {
358 + struct device *dev;
359 + struct nand_hw_control controller;
360 + void __iomem *nand_base;
361 + void __iomem *nand_fc; /* flash cache */
362 + void __iomem *flash_dma_base;
363 + unsigned int irq;
364 + unsigned int dma_irq;
365 + int nand_version;
366 +
367 + /* Some SoCs provide custom interrupt status register(s) */
368 + struct brcmnand_soc *soc;
369 +
370 + int cmd_pending;
371 + bool dma_pending;
372 + struct completion done;
373 + struct completion dma_done;
374 +
375 + /* List of NAND hosts (one for each chip-select) */
376 + struct list_head host_list;
377 +
378 + struct brcm_nand_dma_desc *dma_desc;
379 + dma_addr_t dma_pa;
380 +
381 + /* in-memory cache of the FLASH_CACHE, used only for some commands */
382 + u32 flash_cache[FC_WORDS];
383 +
384 + /* Controller revision details */
385 + const u16 *reg_offsets;
386 + unsigned int reg_spacing; /* between CS1, CS2, ... regs */
387 + const u8 *cs_offsets; /* within each chip-select */
388 + const u8 *cs0_offsets; /* within CS0, if different */
389 + unsigned int max_block_size;
390 + const unsigned int *block_sizes;
391 + unsigned int max_page_size;
392 + const unsigned int *page_sizes;
393 + unsigned int max_oob;
394 + u32 features;
395 +
396 + /* for low-power standby/resume only */
397 + u32 nand_cs_nand_select;
398 + u32 nand_cs_nand_xor;
399 + u32 corr_stat_threshold;
400 + u32 flash_dma_mode;
401 +};
402 +
403 +struct brcmnand_cfg {
404 + u64 device_size;
405 + unsigned int block_size;
406 + unsigned int page_size;
407 + unsigned int spare_area_size;
408 + unsigned int device_width;
409 + unsigned int col_adr_bytes;
410 + unsigned int blk_adr_bytes;
411 + unsigned int ful_adr_bytes;
412 + unsigned int sector_size_1k;
413 + unsigned int ecc_level;
414 + /* use for low-power standby/resume only */
415 + u32 acc_control;
416 + u32 config;
417 + u32 config_ext;
418 + u32 timing_1;
419 + u32 timing_2;
420 +};
421 +
422 +struct brcmnand_host {
423 + struct list_head node;
424 + struct device_node *of_node;
425 +
426 + struct nand_chip chip;
427 + struct mtd_info mtd;
428 + struct platform_device *pdev;
429 + int cs;
430 +
431 + unsigned int last_cmd;
432 + unsigned int last_byte;
433 + u64 last_addr;
434 + struct brcmnand_cfg hwcfg;
435 + struct brcmnand_controller *ctrl;
436 +};
437 +
438 +enum brcmnand_reg {
439 + BRCMNAND_CMD_START = 0,
440 + BRCMNAND_CMD_EXT_ADDRESS,
441 + BRCMNAND_CMD_ADDRESS,
442 + BRCMNAND_INTFC_STATUS,
443 + BRCMNAND_CS_SELECT,
444 + BRCMNAND_CS_XOR,
445 + BRCMNAND_LL_OP,
446 + BRCMNAND_CS0_BASE,
447 + BRCMNAND_CS1_BASE, /* CS1 regs, if non-contiguous */
448 + BRCMNAND_CORR_THRESHOLD,
449 + BRCMNAND_CORR_THRESHOLD_EXT,
450 + BRCMNAND_UNCORR_COUNT,
451 + BRCMNAND_CORR_COUNT,
452 + BRCMNAND_CORR_EXT_ADDR,
453 + BRCMNAND_CORR_ADDR,
454 + BRCMNAND_UNCORR_EXT_ADDR,
455 + BRCMNAND_UNCORR_ADDR,
456 + BRCMNAND_SEMAPHORE,
457 + BRCMNAND_ID,
458 + BRCMNAND_ID_EXT,
459 + BRCMNAND_LL_RDATA,
460 + BRCMNAND_OOB_READ_BASE,
461 + BRCMNAND_OOB_READ_10_BASE, /* offset 0x10, if non-contiguous */
462 + BRCMNAND_OOB_WRITE_BASE,
463 + BRCMNAND_OOB_WRITE_10_BASE, /* offset 0x10, if non-contiguous */
464 + BRCMNAND_FC_BASE,
465 +};
466 +
467 +/* BRCMNAND v4.0 */
468 +static const u16 brcmnand_regs_v40[] = {
469 + [BRCMNAND_CMD_START] = 0x04,
470 + [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
471 + [BRCMNAND_CMD_ADDRESS] = 0x0c,
472 + [BRCMNAND_INTFC_STATUS] = 0x6c,
473 + [BRCMNAND_CS_SELECT] = 0x14,
474 + [BRCMNAND_CS_XOR] = 0x18,
475 + [BRCMNAND_LL_OP] = 0x178,
476 + [BRCMNAND_CS0_BASE] = 0x40,
477 + [BRCMNAND_CS1_BASE] = 0xd0,
478 + [BRCMNAND_CORR_THRESHOLD] = 0x84,
479 + [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
480 + [BRCMNAND_UNCORR_COUNT] = 0,
481 + [BRCMNAND_CORR_COUNT] = 0,
482 + [BRCMNAND_CORR_EXT_ADDR] = 0x70,
483 + [BRCMNAND_CORR_ADDR] = 0x74,
484 + [BRCMNAND_UNCORR_EXT_ADDR] = 0x78,
485 + [BRCMNAND_UNCORR_ADDR] = 0x7c,
486 + [BRCMNAND_SEMAPHORE] = 0x58,
487 + [BRCMNAND_ID] = 0x60,
488 + [BRCMNAND_ID_EXT] = 0x64,
489 + [BRCMNAND_LL_RDATA] = 0x17c,
490 + [BRCMNAND_OOB_READ_BASE] = 0x20,
491 + [BRCMNAND_OOB_READ_10_BASE] = 0x130,
492 + [BRCMNAND_OOB_WRITE_BASE] = 0x30,
493 + [BRCMNAND_OOB_WRITE_10_BASE] = 0,
494 + [BRCMNAND_FC_BASE] = 0x200,
495 +};
496 +
497 +/* BRCMNAND v5.0 */
498 +static const u16 brcmnand_regs_v50[] = {
499 + [BRCMNAND_CMD_START] = 0x04,
500 + [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
501 + [BRCMNAND_CMD_ADDRESS] = 0x0c,
502 + [BRCMNAND_INTFC_STATUS] = 0x6c,
503 + [BRCMNAND_CS_SELECT] = 0x14,
504 + [BRCMNAND_CS_XOR] = 0x18,
505 + [BRCMNAND_LL_OP] = 0x178,
506 + [BRCMNAND_CS0_BASE] = 0x40,
507 + [BRCMNAND_CS1_BASE] = 0xd0,
508 + [BRCMNAND_CORR_THRESHOLD] = 0x84,
509 + [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
510 + [BRCMNAND_UNCORR_COUNT] = 0,
511 + [BRCMNAND_CORR_COUNT] = 0,
512 + [BRCMNAND_CORR_EXT_ADDR] = 0x70,
513 + [BRCMNAND_CORR_ADDR] = 0x74,
514 + [BRCMNAND_UNCORR_EXT_ADDR] = 0x78,
515 + [BRCMNAND_UNCORR_ADDR] = 0x7c,
516 + [BRCMNAND_SEMAPHORE] = 0x58,
517 + [BRCMNAND_ID] = 0x60,
518 + [BRCMNAND_ID_EXT] = 0x64,
519 + [BRCMNAND_LL_RDATA] = 0x17c,
520 + [BRCMNAND_OOB_READ_BASE] = 0x20,
521 + [BRCMNAND_OOB_READ_10_BASE] = 0x130,
522 + [BRCMNAND_OOB_WRITE_BASE] = 0x30,
523 + [BRCMNAND_OOB_WRITE_10_BASE] = 0x140,
524 + [BRCMNAND_FC_BASE] = 0x200,
525 +};
526 +
527 +/* BRCMNAND v6.0 - v7.1 */
528 +static const u16 brcmnand_regs_v60[] = {
529 + [BRCMNAND_CMD_START] = 0x04,
530 + [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
531 + [BRCMNAND_CMD_ADDRESS] = 0x0c,
532 + [BRCMNAND_INTFC_STATUS] = 0x14,
533 + [BRCMNAND_CS_SELECT] = 0x18,
534 + [BRCMNAND_CS_XOR] = 0x1c,
535 + [BRCMNAND_LL_OP] = 0x20,
536 + [BRCMNAND_CS0_BASE] = 0x50,
537 + [BRCMNAND_CS1_BASE] = 0,
538 + [BRCMNAND_CORR_THRESHOLD] = 0xc0,
539 + [BRCMNAND_CORR_THRESHOLD_EXT] = 0xc4,
540 + [BRCMNAND_UNCORR_COUNT] = 0xfc,
541 + [BRCMNAND_CORR_COUNT] = 0x100,
542 + [BRCMNAND_CORR_EXT_ADDR] = 0x10c,
543 + [BRCMNAND_CORR_ADDR] = 0x110,
544 + [BRCMNAND_UNCORR_EXT_ADDR] = 0x114,
545 + [BRCMNAND_UNCORR_ADDR] = 0x118,
546 + [BRCMNAND_SEMAPHORE] = 0x150,
547 + [BRCMNAND_ID] = 0x194,
548 + [BRCMNAND_ID_EXT] = 0x198,
549 + [BRCMNAND_LL_RDATA] = 0x19c,
550 + [BRCMNAND_OOB_READ_BASE] = 0x200,
551 + [BRCMNAND_OOB_READ_10_BASE] = 0,
552 + [BRCMNAND_OOB_WRITE_BASE] = 0x280,
553 + [BRCMNAND_OOB_WRITE_10_BASE] = 0,
554 + [BRCMNAND_FC_BASE] = 0x400,
555 +};
556 +
557 +enum brcmnand_cs_reg {
558 + BRCMNAND_CS_CFG_EXT = 0,
559 + BRCMNAND_CS_CFG,
560 + BRCMNAND_CS_ACC_CONTROL,
561 + BRCMNAND_CS_TIMING1,
562 + BRCMNAND_CS_TIMING2,
563 +};
564 +
565 +/* Per chip-select offsets for v7.1 */
566 +static const u8 brcmnand_cs_offsets_v71[] = {
567 + [BRCMNAND_CS_ACC_CONTROL] = 0x00,
568 + [BRCMNAND_CS_CFG_EXT] = 0x04,
569 + [BRCMNAND_CS_CFG] = 0x08,
570 + [BRCMNAND_CS_TIMING1] = 0x0c,
571 + [BRCMNAND_CS_TIMING2] = 0x10,
572 +};
573 +
574 +/* Per chip-select offsets for pre v7.1, except CS0 on <= v5.0 */
575 +static const u8 brcmnand_cs_offsets[] = {
576 + [BRCMNAND_CS_ACC_CONTROL] = 0x00,
577 + [BRCMNAND_CS_CFG_EXT] = 0x04,
578 + [BRCMNAND_CS_CFG] = 0x04,
579 + [BRCMNAND_CS_TIMING1] = 0x08,
580 + [BRCMNAND_CS_TIMING2] = 0x0c,
581 +};
582 +
583 +/* Per chip-select offset for <= v5.0 on CS0 only */
584 +static const u8 brcmnand_cs_offsets_cs0[] = {
585 + [BRCMNAND_CS_ACC_CONTROL] = 0x00,
586 + [BRCMNAND_CS_CFG_EXT] = 0x08,
587 + [BRCMNAND_CS_CFG] = 0x08,
588 + [BRCMNAND_CS_TIMING1] = 0x10,
589 + [BRCMNAND_CS_TIMING2] = 0x14,
590 +};
591 +
592 +/* BRCMNAND_INTFC_STATUS */
593 +enum {
594 + INTFC_FLASH_STATUS = GENMASK(7, 0),
595 +
596 + INTFC_ERASED = BIT(27),
597 + INTFC_OOB_VALID = BIT(28),
598 + INTFC_CACHE_VALID = BIT(29),
599 + INTFC_FLASH_READY = BIT(30),
600 + INTFC_CTLR_READY = BIT(31),
601 +};
602 +
603 +static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs)
604 +{
605 + return brcmnand_readl(ctrl->nand_base + offs);
606 +}
607 +
608 +static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs,
609 + u32 val)
610 +{
611 + brcmnand_writel(val, ctrl->nand_base + offs);
612 +}
613 +
614 +static int brcmnand_revision_init(struct brcmnand_controller *ctrl)
615 +{
616 + static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };
617 + static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };
618 + static const unsigned int page_sizes[] = { 512, 2048, 4096, 8192, 0 };
619 +
620 + ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;
621 +
622 + /* Only support v4.0+? */
623 + if (ctrl->nand_version < 0x0400) {
624 + dev_err(ctrl->dev, "version %#x not supported\n",
625 + ctrl->nand_version);
626 + return -ENODEV;
627 + }
628 +
629 + /* Register offsets */
630 + if (ctrl->nand_version >= 0x0600)
631 + ctrl->reg_offsets = brcmnand_regs_v60;
632 + else if (ctrl->nand_version >= 0x0500)
633 + ctrl->reg_offsets = brcmnand_regs_v50;
634 + else if (ctrl->nand_version >= 0x0400)
635 + ctrl->reg_offsets = brcmnand_regs_v40;
636 +
637 + /* Chip-select stride */
638 + if (ctrl->nand_version >= 0x0701)
639 + ctrl->reg_spacing = 0x14;
640 + else
641 + ctrl->reg_spacing = 0x10;
642 +
643 + /* Per chip-select registers */
644 + if (ctrl->nand_version >= 0x0701) {
645 + ctrl->cs_offsets = brcmnand_cs_offsets_v71;
646 + } else {
647 + ctrl->cs_offsets = brcmnand_cs_offsets;
648 +
649 + /* v5.0 and earlier has a different CS0 offset layout */
650 + if (ctrl->nand_version <= 0x0500)
651 + ctrl->cs0_offsets = brcmnand_cs_offsets_cs0;
652 + }
653 +
654 + /* Page / block sizes */
655 + if (ctrl->nand_version >= 0x0701) {
656 + /* >= v7.1 use nice power-of-2 values! */
657 + ctrl->max_page_size = 16 * 1024;
658 + ctrl->max_block_size = 2 * 1024 * 1024;
659 + } else {
660 + ctrl->page_sizes = page_sizes;
661 + if (ctrl->nand_version >= 0x0600)
662 + ctrl->block_sizes = block_sizes_v6;
663 + else
664 + ctrl->block_sizes = block_sizes_v4;
665 +
666 + if (ctrl->nand_version < 0x0400) {
667 + ctrl->max_page_size = 4096;
668 + ctrl->max_block_size = 512 * 1024;
669 + }
670 + }
671 +
672 + /* Maximum spare area sector size (per 512B) */
673 + if (ctrl->nand_version >= 0x0600)
674 + ctrl->max_oob = 64;
675 + else if (ctrl->nand_version >= 0x0500)
676 + ctrl->max_oob = 32;
677 + else
678 + ctrl->max_oob = 16;
679 +
680 + /* v6.0 and newer (except v6.1) have prefetch support */
681 + if (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601)
682 + ctrl->features |= BRCMNAND_HAS_PREFETCH;
683 +
684 + /*
685 + * v6.x has cache mode, but it's implemented differently. Ignore it for
686 + * now.
687 + */
688 + if (ctrl->nand_version >= 0x0700)
689 + ctrl->features |= BRCMNAND_HAS_CACHE_MODE;
690 +
691 + if (ctrl->nand_version >= 0x0500)
692 + ctrl->features |= BRCMNAND_HAS_1K_SECTORS;
693 +
694 + if (ctrl->nand_version >= 0x0700)
695 + ctrl->features |= BRCMNAND_HAS_WP;
696 + else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp"))
697 + ctrl->features |= BRCMNAND_HAS_WP;
698 +
699 + return 0;
700 +}
701 +
702 +static inline u32 brcmnand_read_reg(struct brcmnand_controller *ctrl,
703 + enum brcmnand_reg reg)
704 +{
705 + u16 offs = ctrl->reg_offsets[reg];
706 +
707 + if (offs)
708 + return nand_readreg(ctrl, offs);
709 + else
710 + return 0;
711 +}
712 +
713 +static inline void brcmnand_write_reg(struct brcmnand_controller *ctrl,
714 + enum brcmnand_reg reg, u32 val)
715 +{
716 + u16 offs = ctrl->reg_offsets[reg];
717 +
718 + if (offs)
719 + nand_writereg(ctrl, offs, val);
720 +}
721 +
722 +static inline void brcmnand_rmw_reg(struct brcmnand_controller *ctrl,
723 + enum brcmnand_reg reg, u32 mask, unsigned
724 + int shift, u32 val)
725 +{
726 + u32 tmp = brcmnand_read_reg(ctrl, reg);
727 +
728 + tmp &= ~mask;
729 + tmp |= val << shift;
730 + brcmnand_write_reg(ctrl, reg, tmp);
731 +}
732 +
733 +static inline u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word)
734 +{
735 + return __raw_readl(ctrl->nand_fc + word * 4);
736 +}
737 +
738 +static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl,
739 + int word, u32 val)
740 +{
741 + __raw_writel(val, ctrl->nand_fc + word * 4);
742 +}
743 +
744 +static inline u16 brcmnand_cs_offset(struct brcmnand_controller *ctrl, int cs,
745 + enum brcmnand_cs_reg reg)
746 +{
747 + u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE];
748 + u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE];
749 + u8 cs_offs;
750 +
751 + if (cs == 0 && ctrl->cs0_offsets)
752 + cs_offs = ctrl->cs0_offsets[reg];
753 + else
754 + cs_offs = ctrl->cs_offsets[reg];
755 +
756 + if (cs && offs_cs1)
757 + return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs;
758 +
759 + return offs_cs0 + cs * ctrl->reg_spacing + cs_offs;
760 +}
761 +
762 +static inline u32 brcmnand_count_corrected(struct brcmnand_controller *ctrl)
763 +{
764 + if (ctrl->nand_version < 0x0600)
765 + return 1;
766 + return brcmnand_read_reg(ctrl, BRCMNAND_CORR_COUNT);
767 +}
768 +
769 +static void brcmnand_wr_corr_thresh(struct brcmnand_host *host, u8 val)
770 +{
771 + struct brcmnand_controller *ctrl = host->ctrl;
772 + unsigned int shift = 0, bits;
773 + enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD;
774 + int cs = host->cs;
775 +
776 + if (ctrl->nand_version >= 0x0600)
777 + bits = 6;
778 + else if (ctrl->nand_version >= 0x0500)
779 + bits = 5;
780 + else
781 + bits = 4;
782 +
783 + if (ctrl->nand_version >= 0x0600) {
784 + if (cs >= 5)
785 + reg = BRCMNAND_CORR_THRESHOLD_EXT;
786 + shift = (cs % 5) * bits;
787 + }
788 + brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val);
789 +}
790 +
791 +static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl)
792 +{
793 + if (ctrl->nand_version < 0x0700)
794 + return 24;
795 + return 0;
796 +}
797 +
798 +/***********************************************************************
799 + * NAND ACC CONTROL bitfield
800 + *
801 + * Some bits have remained constant throughout hardware revision, while
802 + * others have shifted around.
803 + ***********************************************************************/
804 +
805 +/* Constant for all versions (where supported) */
806 +enum {
807 + /* See BRCMNAND_HAS_CACHE_MODE */
808 + ACC_CONTROL_CACHE_MODE = BIT(22),
809 +
810 + /* See BRCMNAND_HAS_PREFETCH */
811 + ACC_CONTROL_PREFETCH = BIT(23),
812 +
813 + ACC_CONTROL_PAGE_HIT = BIT(24),
814 + ACC_CONTROL_WR_PREEMPT = BIT(25),
815 + ACC_CONTROL_PARTIAL_PAGE = BIT(26),
816 + ACC_CONTROL_RD_ERASED = BIT(27),
817 + ACC_CONTROL_FAST_PGM_RDIN = BIT(28),
818 + ACC_CONTROL_WR_ECC = BIT(30),
819 + ACC_CONTROL_RD_ECC = BIT(31),
820 +};
821 +
822 +static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl)
823 +{
824 + if (ctrl->nand_version >= 0x0600)
825 + return GENMASK(6, 0);
826 + else
827 + return GENMASK(5, 0);
828 +}
829 +
830 +#define NAND_ACC_CONTROL_ECC_SHIFT 16
831 +
832 +static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl)
833 +{
834 + u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f;
835 +
836 + return mask << NAND_ACC_CONTROL_ECC_SHIFT;
837 +}
838 +
839 +static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en)
840 +{
841 + struct brcmnand_controller *ctrl = host->ctrl;
842 + u16 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
843 + u32 acc_control = nand_readreg(ctrl, offs);
844 + u32 ecc_flags = ACC_CONTROL_WR_ECC | ACC_CONTROL_RD_ECC;
845 +
846 + if (en) {
847 + acc_control |= ecc_flags; /* enable RD/WR ECC */
848 + acc_control |= host->hwcfg.ecc_level
849 + << NAND_ACC_CONTROL_ECC_SHIFT;
850 + } else {
851 + acc_control &= ~ecc_flags; /* disable RD/WR ECC */
852 + acc_control &= ~brcmnand_ecc_level_mask(ctrl);
853 + }
854 +
855 + nand_writereg(ctrl, offs, acc_control);
856 +}
857 +
858 +static inline int brcmnand_sector_1k_shift(struct brcmnand_controller *ctrl)
859 +{
860 + if (ctrl->nand_version >= 0x0600)
861 + return 7;
862 + else if (ctrl->nand_version >= 0x0500)
863 + return 6;
864 + else
865 + return -1;
866 +}
867 +
868 +static int brcmnand_get_sector_size_1k(struct brcmnand_host *host)
869 +{
870 + struct brcmnand_controller *ctrl = host->ctrl;
871 + int shift = brcmnand_sector_1k_shift(ctrl);
872 + u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
873 + BRCMNAND_CS_ACC_CONTROL);
874 +
875 + if (shift < 0)
876 + return 0;
877 +
878 + return (nand_readreg(ctrl, acc_control_offs) >> shift) & 0x1;
879 +}
880 +
881 +static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int val)
882 +{
883 + struct brcmnand_controller *ctrl = host->ctrl;
884 + int shift = brcmnand_sector_1k_shift(ctrl);
885 + u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
886 + BRCMNAND_CS_ACC_CONTROL);
887 + u32 tmp;
888 +
889 + if (shift < 0)
890 + return;
891 +
892 + tmp = nand_readreg(ctrl, acc_control_offs);
893 + tmp &= ~(1 << shift);
894 + tmp |= (!!val) << shift;
895 + nand_writereg(ctrl, acc_control_offs, tmp);
896 +}
897 +
898 +/***********************************************************************
899 + * CS_NAND_SELECT
900 + ***********************************************************************/
901 +
902 +enum {
903 + CS_SELECT_NAND_WP = BIT(29),
904 + CS_SELECT_AUTO_DEVICE_ID_CFG = BIT(30),
905 +};
906 +
907 +static inline void brcmnand_set_wp(struct brcmnand_controller *ctrl, bool en)
908 +{
909 + u32 val = en ? CS_SELECT_NAND_WP : 0;
910 +
911 + brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, CS_SELECT_NAND_WP, 0, val);
912 +}
913 +
914 +/***********************************************************************
915 + * Flash DMA
916 + ***********************************************************************/
917 +
918 +enum flash_dma_reg {
919 + FLASH_DMA_REVISION = 0x00,
920 + FLASH_DMA_FIRST_DESC = 0x04,
921 + FLASH_DMA_FIRST_DESC_EXT = 0x08,
922 + FLASH_DMA_CTRL = 0x0c,
923 + FLASH_DMA_MODE = 0x10,
924 + FLASH_DMA_STATUS = 0x14,
925 + FLASH_DMA_INTERRUPT_DESC = 0x18,
926 + FLASH_DMA_INTERRUPT_DESC_EXT = 0x1c,
927 + FLASH_DMA_ERROR_STATUS = 0x20,
928 + FLASH_DMA_CURRENT_DESC = 0x24,
929 + FLASH_DMA_CURRENT_DESC_EXT = 0x28,
930 +};
931 +
932 +static inline bool has_flash_dma(struct brcmnand_controller *ctrl)
933 +{
934 + return ctrl->flash_dma_base;
935 +}
936 +
937 +static inline bool flash_dma_buf_ok(const void *buf)
938 +{
939 + return buf && !is_vmalloc_addr(buf) &&
940 + likely(IS_ALIGNED((uintptr_t)buf, 4));
941 +}
942 +
943 +static inline void flash_dma_writel(struct brcmnand_controller *ctrl, u8 offs,
944 + u32 val)
945 +{
946 + brcmnand_writel(val, ctrl->flash_dma_base + offs);
947 +}
948 +
949 +static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl, u8 offs)
950 +{
951 + return brcmnand_readl(ctrl->flash_dma_base + offs);
952 +}
953 +
954 +/* Low-level operation types: command, address, write, or read */
955 +enum brcmnand_llop_type {
956 + LL_OP_CMD,
957 + LL_OP_ADDR,
958 + LL_OP_WR,
959 + LL_OP_RD,
960 +};
961 +
962 +/***********************************************************************
963 + * Internal support functions
964 + ***********************************************************************/
965 +
966 +static inline bool is_hamming_ecc(struct brcmnand_cfg *cfg)
967 +{
968 + return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 &&
969 + cfg->ecc_level == 15;
970 +}
971 +
972 +/*
973 + * Returns a nand_ecclayout strucutre for the given layout/configuration.
974 + * Returns NULL on failure.
975 + */
976 +static struct nand_ecclayout *brcmnand_create_layout(int ecc_level,
977 + struct brcmnand_host *host)
978 +{
979 + struct brcmnand_cfg *cfg = &host->hwcfg;
980 + int i, j;
981 + struct nand_ecclayout *layout;
982 + int req;
983 + int sectors;
984 + int sas;
985 + int idx1, idx2;
986 +
987 + layout = devm_kzalloc(&host->pdev->dev, sizeof(*layout), GFP_KERNEL);
988 + if (!layout)
989 + return NULL;
990 +
991 + sectors = cfg->page_size / (512 << cfg->sector_size_1k);
992 + sas = cfg->spare_area_size << cfg->sector_size_1k;
993 +
994 + /* Hamming */
995 + if (is_hamming_ecc(cfg)) {
996 + for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) {
997 + /* First sector of each page may have BBI */
998 + if (i == 0) {
999 + layout->oobfree[idx2].offset = i * sas + 1;
1000 + /* Small-page NAND use byte 6 for BBI */
1001 + if (cfg->page_size == 512)
1002 + layout->oobfree[idx2].offset--;
1003 + layout->oobfree[idx2].length = 5;
1004 + } else {
1005 + layout->oobfree[idx2].offset = i * sas;
1006 + layout->oobfree[idx2].length = 6;
1007 + }
1008 + idx2++;
1009 + layout->eccpos[idx1++] = i * sas + 6;
1010 + layout->eccpos[idx1++] = i * sas + 7;
1011 + layout->eccpos[idx1++] = i * sas + 8;
1012 + layout->oobfree[idx2].offset = i * sas + 9;
1013 + layout->oobfree[idx2].length = 7;
1014 + idx2++;
1015 + /* Leave zero-terminated entry for OOBFREE */
1016 + if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE ||
1017 + idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1)
1018 + break;
1019 + }
1020 + goto out;
1021 + }
1022 +
1023 + /*
1024 + * CONTROLLER_VERSION:
1025 + * < v5.0: ECC_REQ = ceil(BCH_T * 13/8)
1026 + * >= v5.0: ECC_REQ = ceil(BCH_T * 14/8)
1027 + * But we will just be conservative.
1028 + */
1029 + req = DIV_ROUND_UP(ecc_level * 14, 8);
1030 + if (req >= sas) {
1031 + dev_err(&host->pdev->dev,
1032 + "error: ECC too large for OOB (ECC bytes %d, spare sector %d)\n",
1033 + req, sas);
1034 + return NULL;
1035 + }
1036 +
1037 + layout->eccbytes = req * sectors;
1038 + for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) {
1039 + for (j = sas - req; j < sas && idx1 <
1040 + MTD_MAX_ECCPOS_ENTRIES_LARGE; j++, idx1++)
1041 + layout->eccpos[idx1] = i * sas + j;
1042 +
1043 + /* First sector of each page may have BBI */
1044 + if (i == 0) {
1045 + if (cfg->page_size == 512 && (sas - req >= 6)) {
1046 + /* Small-page NAND use byte 6 for BBI */
1047 + layout->oobfree[idx2].offset = 0;
1048 + layout->oobfree[idx2].length = 5;
1049 + idx2++;
1050 + if (sas - req > 6) {
1051 + layout->oobfree[idx2].offset = 6;
1052 + layout->oobfree[idx2].length =
1053 + sas - req - 6;
1054 + idx2++;
1055 + }
1056 + } else if (sas > req + 1) {
1057 + layout->oobfree[idx2].offset = i * sas + 1;
1058 + layout->oobfree[idx2].length = sas - req - 1;
1059 + idx2++;
1060 + }
1061 + } else if (sas > req) {
1062 + layout->oobfree[idx2].offset = i * sas;
1063 + layout->oobfree[idx2].length = sas - req;
1064 + idx2++;
1065 + }
1066 + /* Leave zero-terminated entry for OOBFREE */
1067 + if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE ||
1068 + idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1)
1069 + break;
1070 + }
1071 +out:
1072 + /* Sum available OOB */
1073 + for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE; i++)
1074 + layout->oobavail += layout->oobfree[i].length;
1075 + return layout;
1076 +}
1077 +
1078 +static struct nand_ecclayout *brcmstb_choose_ecc_layout(
1079 + struct brcmnand_host *host)
1080 +{
1081 + struct nand_ecclayout *layout;
1082 + struct brcmnand_cfg *p = &host->hwcfg;
1083 + unsigned int ecc_level = p->ecc_level;
1084 +
1085 + if (p->sector_size_1k)
1086 + ecc_level <<= 1;
1087 +
1088 + layout = brcmnand_create_layout(ecc_level, host);
1089 + if (!layout) {
1090 + dev_err(&host->pdev->dev,
1091 + "no proper ecc_layout for this NAND cfg\n");
1092 + return NULL;
1093 + }
1094 +
1095 + return layout;
1096 +}
1097 +
1098 +static void brcmnand_wp(struct mtd_info *mtd, int wp)
1099 +{
1100 + struct nand_chip *chip = mtd->priv;
1101 + struct brcmnand_host *host = chip->priv;
1102 + struct brcmnand_controller *ctrl = host->ctrl;
1103 +
1104 + if ((ctrl->features & BRCMNAND_HAS_WP) && wp_on == 1) {
1105 + static int old_wp = -1;
1106 +
1107 + if (old_wp != wp) {
1108 + dev_dbg(ctrl->dev, "WP %s\n", wp ? "on" : "off");
1109 + old_wp = wp;
1110 + }
1111 + brcmnand_set_wp(ctrl, wp);
1112 + }
1113 +}
1114 +
1115 +/* Helper functions for reading and writing OOB registers */
1116 +static inline u8 oob_reg_read(struct brcmnand_controller *ctrl, u32 offs)
1117 +{
1118 + u16 offset0, offset10, reg_offs;
1119 +
1120 + offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE];
1121 + offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE];
1122 +
1123 + if (offs >= ctrl->max_oob)
1124 + return 0x77;
1125 +
1126 + if (offs >= 16 && offset10)
1127 + reg_offs = offset10 + ((offs - 0x10) & ~0x03);
1128 + else
1129 + reg_offs = offset0 + (offs & ~0x03);
1130 +
1131 + return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3));
1132 +}
1133 +
1134 +static inline void oob_reg_write(struct brcmnand_controller *ctrl, u32 offs,
1135 + u32 data)
1136 +{
1137 + u16 offset0, offset10, reg_offs;
1138 +
1139 + offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE];
1140 + offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE];
1141 +
1142 + if (offs >= ctrl->max_oob)
1143 + return;
1144 +
1145 + if (offs >= 16 && offset10)
1146 + reg_offs = offset10 + ((offs - 0x10) & ~0x03);
1147 + else
1148 + reg_offs = offset0 + (offs & ~0x03);
1149 +
1150 + nand_writereg(ctrl, reg_offs, data);
1151 +}
1152 +
1153 +/*
1154 + * read_oob_from_regs - read data from OOB registers
1155 + * @ctrl: NAND controller
1156 + * @i: sub-page sector index
1157 + * @oob: buffer to read to
1158 + * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
1159 + * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
1160 + */
1161 +static int read_oob_from_regs(struct brcmnand_controller *ctrl, int i, u8 *oob,
1162 + int sas, int sector_1k)
1163 +{
1164 + int tbytes = sas << sector_1k;
1165 + int j;
1166 +
1167 + /* Adjust OOB values for 1K sector size */
1168 + if (sector_1k && (i & 0x01))
1169 + tbytes = max(0, tbytes - (int)ctrl->max_oob);
1170 + tbytes = min_t(int, tbytes, ctrl->max_oob);
1171 +
1172 + for (j = 0; j < tbytes; j++)
1173 + oob[j] = oob_reg_read(ctrl, j);
1174 + return tbytes;
1175 +}
1176 +
1177 +/*
1178 + * write_oob_to_regs - write data to OOB registers
1179 + * @i: sub-page sector index
1180 + * @oob: buffer to write from
1181 + * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
1182 + * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
1183 + */
1184 +static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i,
1185 + const u8 *oob, int sas, int sector_1k)
1186 +{
1187 + int tbytes = sas << sector_1k;
1188 + int j;
1189 +
1190 + /* Adjust OOB values for 1K sector size */
1191 + if (sector_1k && (i & 0x01))
1192 + tbytes = max(0, tbytes - (int)ctrl->max_oob);
1193 + tbytes = min_t(int, tbytes, ctrl->max_oob);
1194 +
1195 + for (j = 0; j < tbytes; j += 4)
1196 + oob_reg_write(ctrl, j,
1197 + (oob[j + 0] << 24) |
1198 + (oob[j + 1] << 16) |
1199 + (oob[j + 2] << 8) |
1200 + (oob[j + 3] << 0));
1201 + return tbytes;
1202 +}
1203 +
1204 +static irqreturn_t brcmnand_ctlrdy_irq(int irq, void *data)
1205 +{
1206 + struct brcmnand_controller *ctrl = data;
1207 +
1208 + /* Discard all NAND_CTLRDY interrupts during DMA */
1209 + if (ctrl->dma_pending)
1210 + return IRQ_HANDLED;
1211 +
1212 + complete(&ctrl->done);
1213 + return IRQ_HANDLED;
1214 +}
1215 +
1216 +/* Handle SoC-specific interrupt hardware */
1217 +static irqreturn_t brcmnand_irq(int irq, void *data)
1218 +{
1219 + struct brcmnand_controller *ctrl = data;
1220 +
1221 + if (ctrl->soc->ctlrdy_ack(ctrl->soc))
1222 + return brcmnand_ctlrdy_irq(irq, data);
1223 +
1224 + return IRQ_NONE;
1225 +}
1226 +
1227 +static irqreturn_t brcmnand_dma_irq(int irq, void *data)
1228 +{
1229 + struct brcmnand_controller *ctrl = data;
1230 +
1231 + complete(&ctrl->dma_done);
1232 +
1233 + return IRQ_HANDLED;
1234 +}
1235 +
1236 +static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd)
1237 +{
1238 + struct brcmnand_controller *ctrl = host->ctrl;
1239 + u32 intfc;
1240 +
1241 + dev_dbg(ctrl->dev, "send native cmd %d addr_lo 0x%x\n", cmd,
1242 + brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS));
1243 + BUG_ON(ctrl->cmd_pending != 0);
1244 + ctrl->cmd_pending = cmd;
1245 +
1246 + intfc = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS);
1247 + BUG_ON(!(intfc & INTFC_CTLR_READY));
1248 +
1249 + mb(); /* flush previous writes */
1250 + brcmnand_write_reg(ctrl, BRCMNAND_CMD_START,
1251 + cmd << brcmnand_cmd_shift(ctrl));
1252 +}
1253 +
1254 +/***********************************************************************
1255 + * NAND MTD API: read/program/erase
1256 + ***********************************************************************/
1257 +
1258 +static void brcmnand_cmd_ctrl(struct mtd_info *mtd, int dat,
1259 + unsigned int ctrl)
1260 +{
1261 + /* intentionally left blank */
1262 +}
1263 +
1264 +static int brcmnand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
1265 +{
1266 + struct nand_chip *chip = mtd->priv;
1267 + struct brcmnand_host *host = chip->priv;
1268 + struct brcmnand_controller *ctrl = host->ctrl;
1269 + unsigned long timeo = msecs_to_jiffies(100);
1270 +
1271 + dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending);
1272 + if (ctrl->cmd_pending &&
1273 + wait_for_completion_timeout(&ctrl->done, timeo) <= 0) {
1274 + u32 cmd = brcmnand_read_reg(ctrl, BRCMNAND_CMD_START)
1275 + >> brcmnand_cmd_shift(ctrl);
1276 +
1277 + dev_err_ratelimited(ctrl->dev,
1278 + "timeout waiting for command %#02x\n", cmd);
1279 + dev_err_ratelimited(ctrl->dev, "intfc status %08x\n",
1280 + brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS));
1281 + }
1282 + ctrl->cmd_pending = 0;
1283 + return brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1284 + INTFC_FLASH_STATUS;
1285 +}
1286 +
1287 +enum {
1288 + LLOP_RE = BIT(16),
1289 + LLOP_WE = BIT(17),
1290 + LLOP_ALE = BIT(18),
1291 + LLOP_CLE = BIT(19),
1292 + LLOP_RETURN_IDLE = BIT(31),
1293 +
1294 + LLOP_DATA_MASK = GENMASK(15, 0),
1295 +};
1296 +
1297 +static int brcmnand_low_level_op(struct brcmnand_host *host,
1298 + enum brcmnand_llop_type type, u32 data,
1299 + bool last_op)
1300 +{
1301 + struct mtd_info *mtd = &host->mtd;
1302 + struct nand_chip *chip = &host->chip;
1303 + struct brcmnand_controller *ctrl = host->ctrl;
1304 + u32 tmp;
1305 +
1306 + tmp = data & LLOP_DATA_MASK;
1307 + switch (type) {
1308 + case LL_OP_CMD:
1309 + tmp |= LLOP_WE | LLOP_CLE;
1310 + break;
1311 + case LL_OP_ADDR:
1312 + /* WE | ALE */
1313 + tmp |= LLOP_WE | LLOP_ALE;
1314 + break;
1315 + case LL_OP_WR:
1316 + /* WE */
1317 + tmp |= LLOP_WE;
1318 + break;
1319 + case LL_OP_RD:
1320 + /* RE */
1321 + tmp |= LLOP_RE;
1322 + break;
1323 + }
1324 + if (last_op)
1325 + /* RETURN_IDLE */
1326 + tmp |= LLOP_RETURN_IDLE;
1327 +
1328 + dev_dbg(ctrl->dev, "ll_op cmd %#x\n", tmp);
1329 +
1330 + brcmnand_write_reg(ctrl, BRCMNAND_LL_OP, tmp);
1331 + (void)brcmnand_read_reg(ctrl, BRCMNAND_LL_OP);
1332 +
1333 + brcmnand_send_cmd(host, CMD_LOW_LEVEL_OP);
1334 + return brcmnand_waitfunc(mtd, chip);
1335 +}
1336 +
1337 +static void brcmnand_cmdfunc(struct mtd_info *mtd, unsigned command,
1338 + int column, int page_addr)
1339 +{
1340 + struct nand_chip *chip = mtd->priv;
1341 + struct brcmnand_host *host = chip->priv;
1342 + struct brcmnand_controller *ctrl = host->ctrl;
1343 + u64 addr = (u64)page_addr << chip->page_shift;
1344 + int native_cmd = 0;
1345 +
1346 + if (command == NAND_CMD_READID || command == NAND_CMD_PARAM ||
1347 + command == NAND_CMD_RNDOUT)
1348 + addr = (u64)column;
1349 + /* Avoid propagating a negative, don't-care address */
1350 + else if (page_addr < 0)
1351 + addr = 0;
1352 +
1353 + dev_dbg(ctrl->dev, "cmd 0x%x addr 0x%llx\n", command,
1354 + (unsigned long long)addr);
1355 +
1356 + host->last_cmd = command;
1357 + host->last_byte = 0;
1358 + host->last_addr = addr;
1359 +
1360 + switch (command) {
1361 + case NAND_CMD_RESET:
1362 + native_cmd = CMD_FLASH_RESET;
1363 + break;
1364 + case NAND_CMD_STATUS:
1365 + native_cmd = CMD_STATUS_READ;
1366 + break;
1367 + case NAND_CMD_READID:
1368 + native_cmd = CMD_DEVICE_ID_READ;
1369 + break;
1370 + case NAND_CMD_READOOB:
1371 + native_cmd = CMD_SPARE_AREA_READ;
1372 + break;
1373 + case NAND_CMD_ERASE1:
1374 + native_cmd = CMD_BLOCK_ERASE;
1375 + brcmnand_wp(mtd, 0);
1376 + break;
1377 + case NAND_CMD_PARAM:
1378 + native_cmd = CMD_PARAMETER_READ;
1379 + break;
1380 + case NAND_CMD_SET_FEATURES:
1381 + case NAND_CMD_GET_FEATURES:
1382 + brcmnand_low_level_op(host, LL_OP_CMD, command, false);
1383 + brcmnand_low_level_op(host, LL_OP_ADDR, column, false);
1384 + break;
1385 + case NAND_CMD_RNDOUT:
1386 + native_cmd = CMD_PARAMETER_CHANGE_COL;
1387 + addr &= ~((u64)(FC_BYTES - 1));
1388 + /*
1389 + * HW quirk: PARAMETER_CHANGE_COL requires SECTOR_SIZE_1K=0
1390 + * NB: hwcfg.sector_size_1k may not be initialized yet
1391 + */
1392 + if (brcmnand_get_sector_size_1k(host)) {
1393 + host->hwcfg.sector_size_1k =
1394 + brcmnand_get_sector_size_1k(host);
1395 + brcmnand_set_sector_size_1k(host, 0);
1396 + }
1397 + break;
1398 + }
1399 +
1400 + if (!native_cmd)
1401 + return;
1402 +
1403 + brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1404 + (host->cs << 16) | ((addr >> 32) & 0xffff));
1405 + (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1406 + brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, lower_32_bits(addr));
1407 + (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1408 +
1409 + brcmnand_send_cmd(host, native_cmd);
1410 + brcmnand_waitfunc(mtd, chip);
1411 +
1412 + if (native_cmd == CMD_PARAMETER_READ ||
1413 + native_cmd == CMD_PARAMETER_CHANGE_COL) {
1414 + int i;
1415 +
1416 + brcmnand_soc_data_bus_prepare(ctrl->soc);
1417 +
1418 + /*
1419 + * Must cache the FLASH_CACHE now, since changes in
1420 + * SECTOR_SIZE_1K may invalidate it
1421 + */
1422 + for (i = 0; i < FC_WORDS; i++)
1423 + ctrl->flash_cache[i] = brcmnand_read_fc(ctrl, i);
1424 +
1425 + brcmnand_soc_data_bus_unprepare(ctrl->soc);
1426 +
1427 + /* Cleanup from HW quirk: restore SECTOR_SIZE_1K */
1428 + if (host->hwcfg.sector_size_1k)
1429 + brcmnand_set_sector_size_1k(host,
1430 + host->hwcfg.sector_size_1k);
1431 + }
1432 +
1433 + /* Re-enable protection is necessary only after erase */
1434 + if (command == NAND_CMD_ERASE1)
1435 + brcmnand_wp(mtd, 1);
1436 +}
1437 +
1438 +static uint8_t brcmnand_read_byte(struct mtd_info *mtd)
1439 +{
1440 + struct nand_chip *chip = mtd->priv;
1441 + struct brcmnand_host *host = chip->priv;
1442 + struct brcmnand_controller *ctrl = host->ctrl;
1443 + uint8_t ret = 0;
1444 + int addr, offs;
1445 +
1446 + switch (host->last_cmd) {
1447 + case NAND_CMD_READID:
1448 + if (host->last_byte < 4)
1449 + ret = brcmnand_read_reg(ctrl, BRCMNAND_ID) >>
1450 + (24 - (host->last_byte << 3));
1451 + else if (host->last_byte < 8)
1452 + ret = brcmnand_read_reg(ctrl, BRCMNAND_ID_EXT) >>
1453 + (56 - (host->last_byte << 3));
1454 + break;
1455 +
1456 + case NAND_CMD_READOOB:
1457 + ret = oob_reg_read(ctrl, host->last_byte);
1458 + break;
1459 +
1460 + case NAND_CMD_STATUS:
1461 + ret = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1462 + INTFC_FLASH_STATUS;
1463 + if (wp_on) /* hide WP status */
1464 + ret |= NAND_STATUS_WP;
1465 + break;
1466 +
1467 + case NAND_CMD_PARAM:
1468 + case NAND_CMD_RNDOUT:
1469 + addr = host->last_addr + host->last_byte;
1470 + offs = addr & (FC_BYTES - 1);
1471 +
1472 + /* At FC_BYTES boundary, switch to next column */
1473 + if (host->last_byte > 0 && offs == 0)
1474 + chip->cmdfunc(mtd, NAND_CMD_RNDOUT, addr, -1);
1475 +
1476 + ret = ctrl->flash_cache[offs >> 2] >>
1477 + (24 - ((offs & 0x03) << 3));
1478 + break;
1479 + case NAND_CMD_GET_FEATURES:
1480 + if (host->last_byte >= ONFI_SUBFEATURE_PARAM_LEN) {
1481 + ret = 0;
1482 + } else {
1483 + bool last = host->last_byte ==
1484 + ONFI_SUBFEATURE_PARAM_LEN - 1;
1485 + brcmnand_low_level_op(host, LL_OP_RD, 0, last);
1486 + ret = brcmnand_read_reg(ctrl, BRCMNAND_LL_RDATA) & 0xff;
1487 + }
1488 + }
1489 +
1490 + dev_dbg(ctrl->dev, "read byte = 0x%02x\n", ret);
1491 + host->last_byte++;
1492 +
1493 + return ret;
1494 +}
1495 +
1496 +static void brcmnand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1497 +{
1498 + int i;
1499 +
1500 + for (i = 0; i < len; i++, buf++)
1501 + *buf = brcmnand_read_byte(mtd);
1502 +}
1503 +
1504 +static void brcmnand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
1505 + int len)
1506 +{
1507 + int i;
1508 + struct nand_chip *chip = mtd->priv;
1509 + struct brcmnand_host *host = chip->priv;
1510 +
1511 + switch (host->last_cmd) {
1512 + case NAND_CMD_SET_FEATURES:
1513 + for (i = 0; i < len; i++)
1514 + brcmnand_low_level_op(host, LL_OP_WR, buf[i],
1515 + (i + 1) == len);
1516 + break;
1517 + default:
1518 + BUG();
1519 + break;
1520 + }
1521 +}
1522 +
1523 +/**
1524 + * Construct a FLASH_DMA descriptor as part of a linked list. You must know the
1525 + * following ahead of time:
1526 + * - Is this descriptor the beginning or end of a linked list?
1527 + * - What is the (DMA) address of the next descriptor in the linked list?
1528 + */
1529 +static int brcmnand_fill_dma_desc(struct brcmnand_host *host,
1530 + struct brcm_nand_dma_desc *desc, u64 addr,
1531 + dma_addr_t buf, u32 len, u8 dma_cmd,
1532 + bool begin, bool end,
1533 + dma_addr_t next_desc)
1534 +{
1535 + memset(desc, 0, sizeof(*desc));
1536 + /* Descriptors are written in native byte order (wordwise) */
1537 + desc->next_desc = lower_32_bits(next_desc);
1538 + desc->next_desc_ext = upper_32_bits(next_desc);
1539 + desc->cmd_irq = (dma_cmd << 24) |
1540 + (end ? (0x03 << 8) : 0) | /* IRQ | STOP */
1541 + (!!begin) | ((!!end) << 1); /* head, tail */
1542 +#ifdef CONFIG_CPU_BIG_ENDIAN
1543 + desc->cmd_irq |= 0x01 << 12;
1544 +#endif
1545 + desc->dram_addr = lower_32_bits(buf);
1546 + desc->dram_addr_ext = upper_32_bits(buf);
1547 + desc->tfr_len = len;
1548 + desc->total_len = len;
1549 + desc->flash_addr = lower_32_bits(addr);
1550 + desc->flash_addr_ext = upper_32_bits(addr);
1551 + desc->cs = host->cs;
1552 + desc->status_valid = 0x01;
1553 + return 0;
1554 +}
1555 +
1556 +/**
1557 + * Kick the FLASH_DMA engine, with a given DMA descriptor
1558 + */
1559 +static void brcmnand_dma_run(struct brcmnand_host *host, dma_addr_t desc)
1560 +{
1561 + struct brcmnand_controller *ctrl = host->ctrl;
1562 + unsigned long timeo = msecs_to_jiffies(100);
1563 +
1564 + flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, lower_32_bits(desc));
1565 + (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC);
1566 + flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT, upper_32_bits(desc));
1567 + (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT);
1568 +
1569 + /* Start FLASH_DMA engine */
1570 + ctrl->dma_pending = true;
1571 + mb(); /* flush previous writes */
1572 + flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0x03); /* wake | run */
1573 +
1574 + if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) {
1575 + dev_err(ctrl->dev,
1576 + "timeout waiting for DMA; status %#x, error status %#x\n",
1577 + flash_dma_readl(ctrl, FLASH_DMA_STATUS),
1578 + flash_dma_readl(ctrl, FLASH_DMA_ERROR_STATUS));
1579 + }
1580 + ctrl->dma_pending = false;
1581 + flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0); /* force stop */
1582 +}
1583 +
1584 +static int brcmnand_dma_trans(struct brcmnand_host *host, u64 addr, u32 *buf,
1585 + u32 len, u8 dma_cmd)
1586 +{
1587 + struct brcmnand_controller *ctrl = host->ctrl;
1588 + dma_addr_t buf_pa;
1589 + int dir = dma_cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1590 +
1591 + buf_pa = dma_map_single(ctrl->dev, buf, len, dir);
1592 + if (dma_mapping_error(ctrl->dev, buf_pa)) {
1593 + dev_err(ctrl->dev, "unable to map buffer for DMA\n");
1594 + return -ENOMEM;
1595 + }
1596 +
1597 + brcmnand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len,
1598 + dma_cmd, true, true, 0);
1599 +
1600 + brcmnand_dma_run(host, ctrl->dma_pa);
1601 +
1602 + dma_unmap_single(ctrl->dev, buf_pa, len, dir);
1603 +
1604 + if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR)
1605 + return -EBADMSG;
1606 + else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR)
1607 + return -EUCLEAN;
1608 +
1609 + return 0;
1610 +}
1611 +
1612 +/*
1613 + * Assumes proper CS is already set
1614 + */
1615 +static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip,
1616 + u64 addr, unsigned int trans, u32 *buf,
1617 + u8 *oob, u64 *err_addr)
1618 +{
1619 + struct brcmnand_host *host = chip->priv;
1620 + struct brcmnand_controller *ctrl = host->ctrl;
1621 + int i, j, ret = 0;
1622 +
1623 + /* Clear error addresses */
1624 + brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_ADDR, 0);
1625 + brcmnand_write_reg(ctrl, BRCMNAND_CORR_ADDR, 0);
1626 +
1627 + brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1628 + (host->cs << 16) | ((addr >> 32) & 0xffff));
1629 + (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1630 +
1631 + for (i = 0; i < trans; i++, addr += FC_BYTES) {
1632 + brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
1633 + lower_32_bits(addr));
1634 + (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1635 + /* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */
1636 + brcmnand_send_cmd(host, CMD_PAGE_READ);
1637 + brcmnand_waitfunc(mtd, chip);
1638 +
1639 + if (likely(buf)) {
1640 + brcmnand_soc_data_bus_prepare(ctrl->soc);
1641 +
1642 + for (j = 0; j < FC_WORDS; j++, buf++)
1643 + *buf = brcmnand_read_fc(ctrl, j);
1644 +
1645 + brcmnand_soc_data_bus_unprepare(ctrl->soc);
1646 + }
1647 +
1648 + if (oob)
1649 + oob += read_oob_from_regs(ctrl, i, oob,
1650 + mtd->oobsize / trans,
1651 + host->hwcfg.sector_size_1k);
1652 +
1653 + if (!ret) {
1654 + *err_addr = brcmnand_read_reg(ctrl,
1655 + BRCMNAND_UNCORR_ADDR) |
1656 + ((u64)(brcmnand_read_reg(ctrl,
1657 + BRCMNAND_UNCORR_EXT_ADDR)
1658 + & 0xffff) << 32);
1659 + if (*err_addr)
1660 + ret = -EBADMSG;
1661 + }
1662 +
1663 + if (!ret) {
1664 + *err_addr = brcmnand_read_reg(ctrl,
1665 + BRCMNAND_CORR_ADDR) |
1666 + ((u64)(brcmnand_read_reg(ctrl,
1667 + BRCMNAND_CORR_EXT_ADDR)
1668 + & 0xffff) << 32);
1669 + if (*err_addr)
1670 + ret = -EUCLEAN;
1671 + }
1672 + }
1673 +
1674 + return ret;
1675 +}
1676 +
1677 +static int brcmnand_read(struct mtd_info *mtd, struct nand_chip *chip,
1678 + u64 addr, unsigned int trans, u32 *buf, u8 *oob)
1679 +{
1680 + struct brcmnand_host *host = chip->priv;
1681 + struct brcmnand_controller *ctrl = host->ctrl;
1682 + u64 err_addr = 0;
1683 + int err;
1684 +
1685 + dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf);
1686 +
1687 + brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_COUNT, 0);
1688 +
1689 + if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
1690 + err = brcmnand_dma_trans(host, addr, buf, trans * FC_BYTES,
1691 + CMD_PAGE_READ);
1692 + if (err) {
1693 + if (mtd_is_bitflip_or_eccerr(err))
1694 + err_addr = addr;
1695 + else
1696 + return -EIO;
1697 + }
1698 + } else {
1699 + if (oob)
1700 + memset(oob, 0x99, mtd->oobsize);
1701 +
1702 + err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf,
1703 + oob, &err_addr);
1704 + }
1705 +
1706 + if (mtd_is_eccerr(err)) {
1707 + dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n",
1708 + (unsigned long long)err_addr);
1709 + mtd->ecc_stats.failed++;
1710 + /* NAND layer expects zero on ECC errors */
1711 + return 0;
1712 + }
1713 +
1714 + if (mtd_is_bitflip(err)) {
1715 + unsigned int corrected = brcmnand_count_corrected(ctrl);
1716 +
1717 + dev_dbg(ctrl->dev, "corrected error at 0x%llx\n",
1718 + (unsigned long long)err_addr);
1719 + mtd->ecc_stats.corrected += corrected;
1720 + /* Always exceed the software-imposed threshold */
1721 + return max(mtd->bitflip_threshold, corrected);
1722 + }
1723 +
1724 + return 0;
1725 +}
1726 +
1727 +static int brcmnand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1728 + uint8_t *buf, int oob_required, int page)
1729 +{
1730 + struct brcmnand_host *host = chip->priv;
1731 + u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
1732 +
1733 + return brcmnand_read(mtd, chip, host->last_addr,
1734 + mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
1735 +}
1736 +
1737 +static int brcmnand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1738 + uint8_t *buf, int oob_required, int page)
1739 +{
1740 + struct brcmnand_host *host = chip->priv;
1741 + u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
1742 + int ret;
1743 +
1744 + brcmnand_set_ecc_enabled(host, 0);
1745 + ret = brcmnand_read(mtd, chip, host->last_addr,
1746 + mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
1747 + brcmnand_set_ecc_enabled(host, 1);
1748 + return ret;
1749 +}
1750 +
1751 +static int brcmnand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
1752 + int page)
1753 +{
1754 + return brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
1755 + mtd->writesize >> FC_SHIFT,
1756 + NULL, (u8 *)chip->oob_poi);
1757 +}
1758 +
1759 +static int brcmnand_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
1760 + int page)
1761 +{
1762 + struct brcmnand_host *host = chip->priv;
1763 +
1764 + brcmnand_set_ecc_enabled(host, 0);
1765 + brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
1766 + mtd->writesize >> FC_SHIFT,
1767 + NULL, (u8 *)chip->oob_poi);
1768 + brcmnand_set_ecc_enabled(host, 1);
1769 + return 0;
1770 +}
1771 +
1772 +static int brcmnand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1773 + uint32_t data_offs, uint32_t readlen,
1774 + uint8_t *bufpoi, int page)
1775 +{
1776 + struct brcmnand_host *host = chip->priv;
1777 +
1778 + return brcmnand_read(mtd, chip, host->last_addr + data_offs,
1779 + readlen >> FC_SHIFT, (u32 *)bufpoi, NULL);
1780 +}
1781 +
1782 +static int brcmnand_write(struct mtd_info *mtd, struct nand_chip *chip,
1783 + u64 addr, const u32 *buf, u8 *oob)
1784 +{
1785 + struct brcmnand_host *host = chip->priv;
1786 + struct brcmnand_controller *ctrl = host->ctrl;
1787 + unsigned int i, j, trans = mtd->writesize >> FC_SHIFT;
1788 + int status, ret = 0;
1789 +
1790 + dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf);
1791 +
1792 + if (unlikely((u32)buf & 0x03)) {
1793 + dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf);
1794 + buf = (u32 *)((u32)buf & ~0x03);
1795 + }
1796 +
1797 + brcmnand_wp(mtd, 0);
1798 +
1799 + for (i = 0; i < ctrl->max_oob; i += 4)
1800 + oob_reg_write(ctrl, i, 0xffffffff);
1801 +
1802 + if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
1803 + if (brcmnand_dma_trans(host, addr, (u32 *)buf,
1804 + mtd->writesize, CMD_PROGRAM_PAGE))
1805 + ret = -EIO;
1806 + goto out;
1807 + }
1808 +
1809 + brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1810 + (host->cs << 16) | ((addr >> 32) & 0xffff));
1811 + (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1812 +
1813 + for (i = 0; i < trans; i++, addr += FC_BYTES) {
1814 + /* full address MUST be set before populating FC */
1815 + brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
1816 + lower_32_bits(addr));
1817 + (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1818 +
1819 + if (buf) {
1820 + brcmnand_soc_data_bus_prepare(ctrl->soc);
1821 +
1822 + for (j = 0; j < FC_WORDS; j++, buf++)
1823 + brcmnand_write_fc(ctrl, j, *buf);
1824 +
1825 + brcmnand_soc_data_bus_unprepare(ctrl->soc);
1826 + } else if (oob) {
1827 + for (j = 0; j < FC_WORDS; j++)
1828 + brcmnand_write_fc(ctrl, j, 0xffffffff);
1829 + }
1830 +
1831 + if (oob) {
1832 + oob += write_oob_to_regs(ctrl, i, oob,
1833 + mtd->oobsize / trans,
1834 + host->hwcfg.sector_size_1k);
1835 + }
1836 +
1837 + /* we cannot use SPARE_AREA_PROGRAM when PARTIAL_PAGE_EN=0 */
1838 + brcmnand_send_cmd(host, CMD_PROGRAM_PAGE);
1839 + status = brcmnand_waitfunc(mtd, chip);
1840 +
1841 + if (status & NAND_STATUS_FAIL) {
1842 + dev_info(ctrl->dev, "program failed at %llx\n",
1843 + (unsigned long long)addr);
1844 + ret = -EIO;
1845 + goto out;
1846 + }
1847 + }
1848 +out:
1849 + brcmnand_wp(mtd, 1);
1850 + return ret;
1851 +}
1852 +
1853 +static int brcmnand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1854 + const uint8_t *buf, int oob_required)
1855 +{
1856 + struct brcmnand_host *host = chip->priv;
1857 + void *oob = oob_required ? chip->oob_poi : NULL;
1858 +
1859 + brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
1860 + return 0;
1861 +}
1862 +
1863 +static int brcmnand_write_page_raw(struct mtd_info *mtd,
1864 + struct nand_chip *chip, const uint8_t *buf,
1865 + int oob_required)
1866 +{
1867 + struct brcmnand_host *host = chip->priv;
1868 + void *oob = oob_required ? chip->oob_poi : NULL;
1869 +
1870 + brcmnand_set_ecc_enabled(host, 0);
1871 + brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
1872 + brcmnand_set_ecc_enabled(host, 1);
1873 + return 0;
1874 +}
1875 +
1876 +static int brcmnand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
1877 + int page)
1878 +{
1879 + return brcmnand_write(mtd, chip, (u64)page << chip->page_shift,
1880 + NULL, chip->oob_poi);
1881 +}
1882 +
1883 +static int brcmnand_write_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
1884 + int page)
1885 +{
1886 + struct brcmnand_host *host = chip->priv;
1887 + int ret;
1888 +
1889 + brcmnand_set_ecc_enabled(host, 0);
1890 + ret = brcmnand_write(mtd, chip, (u64)page << chip->page_shift, NULL,
1891 + (u8 *)chip->oob_poi);
1892 + brcmnand_set_ecc_enabled(host, 1);
1893 +
1894 + return ret;
1895 +}
1896 +
1897 +/***********************************************************************
1898 + * Per-CS setup (1 NAND device)
1899 + ***********************************************************************/
1900 +
1901 +static int brcmnand_set_cfg(struct brcmnand_host *host,
1902 + struct brcmnand_cfg *cfg)
1903 +{
1904 + struct brcmnand_controller *ctrl = host->ctrl;
1905 + struct nand_chip *chip = &host->chip;
1906 + u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
1907 + u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
1908 + BRCMNAND_CS_CFG_EXT);
1909 + u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
1910 + BRCMNAND_CS_ACC_CONTROL);
1911 + u8 block_size = 0, page_size = 0, device_size = 0;
1912 + u32 tmp;
1913 +
1914 + if (ctrl->block_sizes) {
1915 + int i, found;
1916 +
1917 + for (i = 0, found = 0; ctrl->block_sizes[i]; i++)
1918 + if (ctrl->block_sizes[i] * 1024 == cfg->block_size) {
1919 + block_size = i;
1920 + found = 1;
1921 + }
1922 + if (!found) {
1923 + dev_warn(ctrl->dev, "invalid block size %u\n",
1924 + cfg->block_size);
1925 + return -EINVAL;
1926 + }
1927 + } else {
1928 + block_size = ffs(cfg->block_size) - ffs(BRCMNAND_MIN_BLOCKSIZE);
1929 + }
1930 +
1931 + if (cfg->block_size < BRCMNAND_MIN_BLOCKSIZE || (ctrl->max_block_size &&
1932 + cfg->block_size > ctrl->max_block_size)) {
1933 + dev_warn(ctrl->dev, "invalid block size %u\n",
1934 + cfg->block_size);
1935 + block_size = 0;
1936 + }
1937 +
1938 + if (ctrl->page_sizes) {
1939 + int i, found;
1940 +
1941 + for (i = 0, found = 0; ctrl->page_sizes[i]; i++)
1942 + if (ctrl->page_sizes[i] == cfg->page_size) {
1943 + page_size = i;
1944 + found = 1;
1945 + }
1946 + if (!found) {
1947 + dev_warn(ctrl->dev, "invalid page size %u\n",
1948 + cfg->page_size);
1949 + return -EINVAL;
1950 + }
1951 + } else {
1952 + page_size = ffs(cfg->page_size) - ffs(BRCMNAND_MIN_PAGESIZE);
1953 + }
1954 +
1955 + if (cfg->page_size < BRCMNAND_MIN_PAGESIZE || (ctrl->max_page_size &&
1956 + cfg->page_size > ctrl->max_page_size)) {
1957 + dev_warn(ctrl->dev, "invalid page size %u\n", cfg->page_size);
1958 + return -EINVAL;
1959 + }
1960 +
1961 + if (fls64(cfg->device_size) < fls64(BRCMNAND_MIN_DEVSIZE)) {
1962 + dev_warn(ctrl->dev, "invalid device size 0x%llx\n",
1963 + (unsigned long long)cfg->device_size);
1964 + return -EINVAL;
1965 + }
1966 + device_size = fls64(cfg->device_size) - fls64(BRCMNAND_MIN_DEVSIZE);
1967 +
1968 + tmp = (cfg->blk_adr_bytes << 8) |
1969 + (cfg->col_adr_bytes << 12) |
1970 + (cfg->ful_adr_bytes << 16) |
1971 + (!!(cfg->device_width == 16) << 23) |
1972 + (device_size << 24);
1973 + if (cfg_offs == cfg_ext_offs) {
1974 + tmp |= (page_size << 20) | (block_size << 28);
1975 + nand_writereg(ctrl, cfg_offs, tmp);
1976 + } else {
1977 + nand_writereg(ctrl, cfg_offs, tmp);
1978 + tmp = page_size | (block_size << 4);
1979 + nand_writereg(ctrl, cfg_ext_offs, tmp);
1980 + }
1981 +
1982 + tmp = nand_readreg(ctrl, acc_control_offs);
1983 + tmp &= ~brcmnand_ecc_level_mask(ctrl);
1984 + tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
1985 + tmp &= ~brcmnand_spare_area_mask(ctrl);
1986 + tmp |= cfg->spare_area_size;
1987 + nand_writereg(ctrl, acc_control_offs, tmp);
1988 +
1989 + brcmnand_set_sector_size_1k(host, cfg->sector_size_1k);
1990 +
1991 + /* threshold = ceil(BCH-level * 0.75) */
1992 + brcmnand_wr_corr_thresh(host, DIV_ROUND_UP(chip->ecc.strength * 3, 4));
1993 +
1994 + return 0;
1995 +}
1996 +
1997 +static void brcmnand_print_cfg(char *buf, struct brcmnand_cfg *cfg)
1998 +{
1999 + buf += sprintf(buf,
2000 + "%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit",
2001 + (unsigned long long)cfg->device_size >> 20,
2002 + cfg->block_size >> 10,
2003 + cfg->page_size >= 1024 ? cfg->page_size >> 10 : cfg->page_size,
2004 + cfg->page_size >= 1024 ? "KiB" : "B",
2005 + cfg->spare_area_size, cfg->device_width);
2006 +
2007 + /* Account for Hamming ECC and for BCH 512B vs 1KiB sectors */
2008 + if (is_hamming_ecc(cfg))
2009 + sprintf(buf, ", Hamming ECC");
2010 + else if (cfg->sector_size_1k)
2011 + sprintf(buf, ", BCH-%u (1KiB sector)", cfg->ecc_level << 1);
2012 + else
2013 + sprintf(buf, ", BCH-%u", cfg->ecc_level);
2014 +}
2015 +
2016 +/*
2017 + * Minimum number of bytes to address a page. Calculated as:
2018 + * roundup(log2(size / page-size) / 8)
2019 + *
2020 + * NB: the following does not "round up" for non-power-of-2 'size'; but this is
2021 + * OK because many other things will break if 'size' is irregular...
2022 + */
2023 +static inline int get_blk_adr_bytes(u64 size, u32 writesize)
2024 +{
2025 + return ALIGN(ilog2(size) - ilog2(writesize), 8) >> 3;
2026 +}
2027 +
2028 +static int brcmnand_setup_dev(struct brcmnand_host *host)
2029 +{
2030 + struct mtd_info *mtd = &host->mtd;
2031 + struct nand_chip *chip = &host->chip;
2032 + struct brcmnand_controller *ctrl = host->ctrl;
2033 + struct brcmnand_cfg *cfg = &host->hwcfg;
2034 + char msg[128];
2035 + u32 offs, tmp, oob_sector;
2036 + int ret;
2037 +
2038 + memset(cfg, 0, sizeof(*cfg));
2039 +
2040 + ret = of_property_read_u32(chip->dn, "brcm,nand-oob-sector-size",
2041 + &oob_sector);
2042 + if (ret) {
2043 + /* Use detected size */
2044 + cfg->spare_area_size = mtd->oobsize /
2045 + (mtd->writesize >> FC_SHIFT);
2046 + } else {
2047 + cfg->spare_area_size = oob_sector;
2048 + }
2049 + if (cfg->spare_area_size > ctrl->max_oob)
2050 + cfg->spare_area_size = ctrl->max_oob;
2051 + /*
2052 + * Set oobsize to be consistent with controller's spare_area_size, as
2053 + * the rest is inaccessible.
2054 + */
2055 + mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT);
2056 +
2057 + cfg->device_size = mtd->size;
2058 + cfg->block_size = mtd->erasesize;
2059 + cfg->page_size = mtd->writesize;
2060 + cfg->device_width = (chip->options & NAND_BUSWIDTH_16) ? 16 : 8;
2061 + cfg->col_adr_bytes = 2;
2062 + cfg->blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize);
2063 +
2064 + switch (chip->ecc.size) {
2065 + case 512:
2066 + if (chip->ecc.strength == 1) /* Hamming */
2067 + cfg->ecc_level = 15;
2068 + else
2069 + cfg->ecc_level = chip->ecc.strength;
2070 + cfg->sector_size_1k = 0;
2071 + break;
2072 + case 1024:
2073 + if (!(ctrl->features & BRCMNAND_HAS_1K_SECTORS)) {
2074 + dev_err(ctrl->dev, "1KB sectors not supported\n");
2075 + return -EINVAL;
2076 + }
2077 + if (chip->ecc.strength & 0x1) {
2078 + dev_err(ctrl->dev,
2079 + "odd ECC not supported with 1KB sectors\n");
2080 + return -EINVAL;
2081 + }
2082 +
2083 + cfg->ecc_level = chip->ecc.strength >> 1;
2084 + cfg->sector_size_1k = 1;
2085 + break;
2086 + default:
2087 + dev_err(ctrl->dev, "unsupported ECC size: %d\n",
2088 + chip->ecc.size);
2089 + return -EINVAL;
2090 + }
2091 +
2092 + cfg->ful_adr_bytes = cfg->blk_adr_bytes;
2093 + if (mtd->writesize > 512)
2094 + cfg->ful_adr_bytes += cfg->col_adr_bytes;
2095 + else
2096 + cfg->ful_adr_bytes += 1;
2097 +
2098 + ret = brcmnand_set_cfg(host, cfg);
2099 + if (ret)
2100 + return ret;
2101 +
2102 + brcmnand_set_ecc_enabled(host, 1);
2103 +
2104 + brcmnand_print_cfg(msg, cfg);
2105 + dev_info(ctrl->dev, "detected %s\n", msg);
2106 +
2107 + /* Configure ACC_CONTROL */
2108 + offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
2109 + tmp = nand_readreg(ctrl, offs);
2110 + tmp &= ~ACC_CONTROL_PARTIAL_PAGE;
2111 + tmp &= ~ACC_CONTROL_RD_ERASED;
2112 + tmp &= ~ACC_CONTROL_FAST_PGM_RDIN;
2113 + if (ctrl->features & BRCMNAND_HAS_PREFETCH) {
2114 + /*
2115 + * FIXME: Flash DMA + prefetch may see spurious erased-page ECC
2116 + * errors
2117 + */
2118 + if (has_flash_dma(ctrl))
2119 + tmp &= ~ACC_CONTROL_PREFETCH;
2120 + else
2121 + tmp |= ACC_CONTROL_PREFETCH;
2122 + }
2123 + nand_writereg(ctrl, offs, tmp);
2124 +
2125 + return 0;
2126 +}
2127 +
2128 +static int brcmnand_init_cs(struct brcmnand_host *host)
2129 +{
2130 + struct brcmnand_controller *ctrl = host->ctrl;
2131 + struct device_node *dn = host->of_node;
2132 + struct platform_device *pdev = host->pdev;
2133 + struct mtd_info *mtd;
2134 + struct nand_chip *chip;
2135 + int ret = 0;
2136 + struct mtd_part_parser_data ppdata = { .of_node = dn };
2137 +
2138 + ret = of_property_read_u32(dn, "reg", &host->cs);
2139 + if (ret) {
2140 + dev_err(&pdev->dev, "can't get chip-select\n");
2141 + return -ENXIO;
2142 + }
2143 +
2144 + mtd = &host->mtd;
2145 + chip = &host->chip;
2146 +
2147 + chip->dn = dn;
2148 + chip->priv = host;
2149 + mtd->priv = chip;
2150 + mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "brcmnand.%d",
2151 + host->cs);
2152 + mtd->owner = THIS_MODULE;
2153 + mtd->dev.parent = &pdev->dev;
2154 +
2155 + chip->IO_ADDR_R = (void __iomem *)0xdeadbeef;
2156 + chip->IO_ADDR_W = (void __iomem *)0xdeadbeef;
2157 +
2158 + chip->cmd_ctrl = brcmnand_cmd_ctrl;
2159 + chip->cmdfunc = brcmnand_cmdfunc;
2160 + chip->waitfunc = brcmnand_waitfunc;
2161 + chip->read_byte = brcmnand_read_byte;
2162 + chip->read_buf = brcmnand_read_buf;
2163 + chip->write_buf = brcmnand_write_buf;
2164 +
2165 + chip->ecc.mode = NAND_ECC_HW;
2166 + chip->ecc.read_page = brcmnand_read_page;
2167 + chip->ecc.read_subpage = brcmnand_read_subpage;
2168 + chip->ecc.write_page = brcmnand_write_page;
2169 + chip->ecc.read_page_raw = brcmnand_read_page_raw;
2170 + chip->ecc.write_page_raw = brcmnand_write_page_raw;
2171 + chip->ecc.write_oob_raw = brcmnand_write_oob_raw;
2172 + chip->ecc.read_oob_raw = brcmnand_read_oob_raw;
2173 + chip->ecc.read_oob = brcmnand_read_oob;
2174 + chip->ecc.write_oob = brcmnand_write_oob;
2175 +
2176 + chip->controller = &ctrl->controller;
2177 +
2178 + if (nand_scan_ident(mtd, 1, NULL))
2179 + return -ENXIO;
2180 +
2181 + chip->options |= NAND_NO_SUBPAGE_WRITE;
2182 + /*
2183 + * Avoid (for instance) kmap()'d buffers from JFFS2, which we can't DMA
2184 + * to/from, and have nand_base pass us a bounce buffer instead, as
2185 + * needed.
2186 + */
2187 + chip->options |= NAND_USE_BOUNCE_BUFFER;
2188 +
2189 + if (of_get_nand_on_flash_bbt(dn))
2190 + chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
2191 +
2192 + if (brcmnand_setup_dev(host))
2193 + return -ENXIO;
2194 +
2195 + chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512;
2196 + /* only use our internal HW threshold */
2197 + mtd->bitflip_threshold = 1;
2198 +
2199 + chip->ecc.layout = brcmstb_choose_ecc_layout(host);
2200 + if (!chip->ecc.layout)
2201 + return -ENXIO;
2202 +
2203 + if (nand_scan_tail(mtd))
2204 + return -ENXIO;
2205 +
2206 + return mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
2207 +}
2208 +
2209 +static void brcmnand_save_restore_cs_config(struct brcmnand_host *host,
2210 + int restore)
2211 +{
2212 + struct brcmnand_controller *ctrl = host->ctrl;
2213 + u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
2214 + u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
2215 + BRCMNAND_CS_CFG_EXT);
2216 + u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
2217 + BRCMNAND_CS_ACC_CONTROL);
2218 + u16 t1_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING1);
2219 + u16 t2_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING2);
2220 +
2221 + if (restore) {
2222 + nand_writereg(ctrl, cfg_offs, host->hwcfg.config);
2223 + if (cfg_offs != cfg_ext_offs)
2224 + nand_writereg(ctrl, cfg_ext_offs,
2225 + host->hwcfg.config_ext);
2226 + nand_writereg(ctrl, acc_control_offs, host->hwcfg.acc_control);
2227 + nand_writereg(ctrl, t1_offs, host->hwcfg.timing_1);
2228 + nand_writereg(ctrl, t2_offs, host->hwcfg.timing_2);
2229 + } else {
2230 + host->hwcfg.config = nand_readreg(ctrl, cfg_offs);
2231 + if (cfg_offs != cfg_ext_offs)
2232 + host->hwcfg.config_ext =
2233 + nand_readreg(ctrl, cfg_ext_offs);
2234 + host->hwcfg.acc_control = nand_readreg(ctrl, acc_control_offs);
2235 + host->hwcfg.timing_1 = nand_readreg(ctrl, t1_offs);
2236 + host->hwcfg.timing_2 = nand_readreg(ctrl, t2_offs);
2237 + }
2238 +}
2239 +
2240 +static int brcmnand_suspend(struct device *dev)
2241 +{
2242 + struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
2243 + struct brcmnand_host *host;
2244 +
2245 + list_for_each_entry(host, &ctrl->host_list, node)
2246 + brcmnand_save_restore_cs_config(host, 0);
2247 +
2248 + ctrl->nand_cs_nand_select = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT);
2249 + ctrl->nand_cs_nand_xor = brcmnand_read_reg(ctrl, BRCMNAND_CS_XOR);
2250 + ctrl->corr_stat_threshold =
2251 + brcmnand_read_reg(ctrl, BRCMNAND_CORR_THRESHOLD);
2252 +
2253 + if (has_flash_dma(ctrl))
2254 + ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE);
2255 +
2256 + return 0;
2257 +}
2258 +
2259 +static int brcmnand_resume(struct device *dev)
2260 +{
2261 + struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
2262 + struct brcmnand_host *host;
2263 +
2264 + if (has_flash_dma(ctrl)) {
2265 + flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode);
2266 + flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
2267 + }
2268 +
2269 + brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select);
2270 + brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor);
2271 + brcmnand_write_reg(ctrl, BRCMNAND_CORR_THRESHOLD,
2272 + ctrl->corr_stat_threshold);
2273 + if (ctrl->soc) {
2274 + /* Clear/re-enable interrupt */
2275 + ctrl->soc->ctlrdy_ack(ctrl->soc);
2276 + ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
2277 + }
2278 +
2279 + list_for_each_entry(host, &ctrl->host_list, node) {
2280 + struct mtd_info *mtd = &host->mtd;
2281 + struct nand_chip *chip = mtd->priv;
2282 +
2283 + brcmnand_save_restore_cs_config(host, 1);
2284 +
2285 + /* Reset the chip, required by some chips after power-up */
2286 + chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2287 + }
2288 +
2289 + return 0;
2290 +}
2291 +
2292 +const struct dev_pm_ops brcmnand_pm_ops = {
2293 + .suspend = brcmnand_suspend,
2294 + .resume = brcmnand_resume,
2295 +};
2296 +EXPORT_SYMBOL_GPL(brcmnand_pm_ops);
2297 +
2298 +static const struct of_device_id brcmnand_of_match[] = {
2299 + { .compatible = "brcm,brcmnand-v4.0" },
2300 + { .compatible = "brcm,brcmnand-v5.0" },
2301 + { .compatible = "brcm,brcmnand-v6.0" },
2302 + { .compatible = "brcm,brcmnand-v6.1" },
2303 + { .compatible = "brcm,brcmnand-v7.0" },
2304 + { .compatible = "brcm,brcmnand-v7.1" },
2305 + {},
2306 +};
2307 +MODULE_DEVICE_TABLE(of, brcmnand_of_match);
2308 +
2309 +/***********************************************************************
2310 + * Platform driver setup (per controller)
2311 + ***********************************************************************/
2312 +
2313 +int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
2314 +{
2315 + struct device *dev = &pdev->dev;
2316 + struct device_node *dn = dev->of_node, *child;
2317 + struct brcmnand_controller *ctrl;
2318 + struct resource *res;
2319 + int ret;
2320 +
2321 + /* We only support device-tree instantiation */
2322 + if (!dn)
2323 + return -ENODEV;
2324 +
2325 + if (!of_match_node(brcmnand_of_match, dn))
2326 + return -ENODEV;
2327 +
2328 + ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
2329 + if (!ctrl)
2330 + return -ENOMEM;
2331 +
2332 + dev_set_drvdata(dev, ctrl);
2333 + ctrl->dev = dev;
2334 +
2335 + init_completion(&ctrl->done);
2336 + init_completion(&ctrl->dma_done);
2337 + spin_lock_init(&ctrl->controller.lock);
2338 + init_waitqueue_head(&ctrl->controller.wq);
2339 + INIT_LIST_HEAD(&ctrl->host_list);
2340 +
2341 + /* NAND register range */
2342 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2343 + ctrl->nand_base = devm_ioremap_resource(dev, res);
2344 + if (IS_ERR(ctrl->nand_base))
2345 + return PTR_ERR(ctrl->nand_base);
2346 +
2347 + /* Initialize NAND revision */
2348 + ret = brcmnand_revision_init(ctrl);
2349 + if (ret)
2350 + return ret;
2351 +
2352 + /*
2353 + * Most chips have this cache at a fixed offset within 'nand' block.
2354 + * Some must specify this region separately.
2355 + */
2356 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache");
2357 + if (res) {
2358 + ctrl->nand_fc = devm_ioremap_resource(dev, res);
2359 + if (IS_ERR(ctrl->nand_fc))
2360 + return PTR_ERR(ctrl->nand_fc);
2361 + } else {
2362 + ctrl->nand_fc = ctrl->nand_base +
2363 + ctrl->reg_offsets[BRCMNAND_FC_BASE];
2364 + }
2365 +
2366 + /* FLASH_DMA */
2367 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma");
2368 + if (res) {
2369 + ctrl->flash_dma_base = devm_ioremap_resource(dev, res);
2370 + if (IS_ERR(ctrl->flash_dma_base))
2371 + return PTR_ERR(ctrl->flash_dma_base);
2372 +
2373 + flash_dma_writel(ctrl, FLASH_DMA_MODE, 1); /* linked-list */
2374 + flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
2375 +
2376 + /* Allocate descriptor(s) */
2377 + ctrl->dma_desc = dmam_alloc_coherent(dev,
2378 + sizeof(*ctrl->dma_desc),
2379 + &ctrl->dma_pa, GFP_KERNEL);
2380 + if (!ctrl->dma_desc)
2381 + return -ENOMEM;
2382 +
2383 + ctrl->dma_irq = platform_get_irq(pdev, 1);
2384 + if ((int)ctrl->dma_irq < 0) {
2385 + dev_err(dev, "missing FLASH_DMA IRQ\n");
2386 + return -ENODEV;
2387 + }
2388 +
2389 + ret = devm_request_irq(dev, ctrl->dma_irq,
2390 + brcmnand_dma_irq, 0, DRV_NAME,
2391 + ctrl);
2392 + if (ret < 0) {
2393 + dev_err(dev, "can't allocate IRQ %d: error %d\n",
2394 + ctrl->dma_irq, ret);
2395 + return ret;
2396 + }
2397 +
2398 + dev_info(dev, "enabling FLASH_DMA\n");
2399 + }
2400 +
2401 + /* Disable automatic device ID config, direct addressing */
2402 + brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT,
2403 + CS_SELECT_AUTO_DEVICE_ID_CFG | 0xff, 0, 0);
2404 + /* Disable XOR addressing */
2405 + brcmnand_rmw_reg(ctrl, BRCMNAND_CS_XOR, 0xff, 0, 0);
2406 +
2407 + if (ctrl->features & BRCMNAND_HAS_WP) {
2408 + /* Permanently disable write protection */
2409 + if (wp_on == 2)
2410 + brcmnand_set_wp(ctrl, false);
2411 + } else {
2412 + wp_on = 0;
2413 + }
2414 +
2415 + /* IRQ */
2416 + ctrl->irq = platform_get_irq(pdev, 0);
2417 + if ((int)ctrl->irq < 0) {
2418 + dev_err(dev, "no IRQ defined\n");
2419 + return -ENODEV;
2420 + }
2421 +
2422 + /*
2423 + * Some SoCs integrate this controller (e.g., its interrupt bits) in
2424 + * interesting ways
2425 + */
2426 + if (soc) {
2427 + ctrl->soc = soc;
2428 +
2429 + ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0,
2430 + DRV_NAME, ctrl);
2431 +
2432 + /* Enable interrupt */
2433 + ctrl->soc->ctlrdy_ack(ctrl->soc);
2434 + ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
2435 + } else {
2436 + /* Use standard interrupt infrastructure */
2437 + ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0,
2438 + DRV_NAME, ctrl);
2439 + }
2440 + if (ret < 0) {
2441 + dev_err(dev, "can't allocate IRQ %d: error %d\n",
2442 + ctrl->irq, ret);
2443 + return ret;
2444 + }
2445 +
2446 + for_each_available_child_of_node(dn, child) {
2447 + if (of_device_is_compatible(child, "brcm,nandcs")) {
2448 + struct brcmnand_host *host;
2449 +
2450 + host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
2451 + if (!host)
2452 + return -ENOMEM;
2453 + host->pdev = pdev;
2454 + host->ctrl = ctrl;
2455 + host->of_node = child;
2456 +
2457 + ret = brcmnand_init_cs(host);
2458 + if (ret)
2459 + continue; /* Try all chip-selects */
2460 +
2461 + list_add_tail(&host->node, &ctrl->host_list);
2462 + }
2463 + }
2464 +
2465 + /* No chip-selects could initialize properly */
2466 + if (list_empty(&ctrl->host_list))
2467 + return -ENODEV;
2468 +
2469 + return 0;
2470 +}
2471 +EXPORT_SYMBOL_GPL(brcmnand_probe);
2472 +
2473 +int brcmnand_remove(struct platform_device *pdev)
2474 +{
2475 + struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev);
2476 + struct brcmnand_host *host;
2477 +
2478 + list_for_each_entry(host, &ctrl->host_list, node)
2479 + nand_release(&host->mtd);
2480 +
2481 + dev_set_drvdata(&pdev->dev, NULL);
2482 +
2483 + return 0;
2484 +}
2485 +EXPORT_SYMBOL_GPL(brcmnand_remove);
2486 +
2487 +MODULE_LICENSE("GPL v2");
2488 +MODULE_AUTHOR("Kevin Cernekee");
2489 +MODULE_AUTHOR("Brian Norris");
2490 +MODULE_DESCRIPTION("NAND driver for Broadcom chips");
2491 +MODULE_ALIAS("platform:brcmnand");
2492 --- /dev/null
2493 +++ b/drivers/mtd/nand/brcmnand/brcmnand.h
2494 @@ -0,0 +1,71 @@
2495 +/*
2496 + * Copyright © 2015 Broadcom Corporation
2497 + *
2498 + * This program is free software; you can redistribute it and/or modify
2499 + * it under the terms of the GNU General Public License version 2 as
2500 + * published by the Free Software Foundation.
2501 + *
2502 + * This program is distributed in the hope that it will be useful,
2503 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2504 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2505 + * GNU General Public License for more details.
2506 + */
2507 +
2508 +#ifndef __BRCMNAND_H__
2509 +#define __BRCMNAND_H__
2510 +
2511 +#include <linux/types.h>
2512 +#include <linux/io.h>
2513 +
2514 +struct platform_device;
2515 +struct dev_pm_ops;
2516 +
2517 +struct brcmnand_soc {
2518 + bool (*ctlrdy_ack)(struct brcmnand_soc *soc);
2519 + void (*ctlrdy_set_enabled)(struct brcmnand_soc *soc, bool en);
2520 + void (*prepare_data_bus)(struct brcmnand_soc *soc, bool prepare);
2521 +};
2522 +
2523 +static inline void brcmnand_soc_data_bus_prepare(struct brcmnand_soc *soc)
2524 +{
2525 + if (soc && soc->prepare_data_bus)
2526 + soc->prepare_data_bus(soc, true);
2527 +}
2528 +
2529 +static inline void brcmnand_soc_data_bus_unprepare(struct brcmnand_soc *soc)
2530 +{
2531 + if (soc && soc->prepare_data_bus)
2532 + soc->prepare_data_bus(soc, false);
2533 +}
2534 +
2535 +static inline u32 brcmnand_readl(void __iomem *addr)
2536 +{
2537 + /*
2538 + * MIPS endianness is configured by boot strap, which also reverses all
2539 + * bus endianness (i.e., big-endian CPU + big endian bus ==> native
2540 + * endian I/O).
2541 + *
2542 + * Other architectures (e.g., ARM) either do not support big endian, or
2543 + * else leave I/O in little endian mode.
2544 + */
2545 + if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(__BIG_ENDIAN))
2546 + return __raw_readl(addr);
2547 + else
2548 + return readl_relaxed(addr);
2549 +}
2550 +
2551 +static inline void brcmnand_writel(u32 val, void __iomem *addr)
2552 +{
2553 + /* See brcmnand_readl() comments */
2554 + if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(__BIG_ENDIAN))
2555 + __raw_writel(val, addr);
2556 + else
2557 + writel_relaxed(val, addr);
2558 +}
2559 +
2560 +int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc);
2561 +int brcmnand_remove(struct platform_device *pdev);
2562 +
2563 +extern const struct dev_pm_ops brcmnand_pm_ops;
2564 +
2565 +#endif /* __BRCMNAND_H__ */
2566 --- /dev/null
2567 +++ b/drivers/mtd/nand/brcmnand/brcmstb_nand.c
2568 @@ -0,0 +1,44 @@
2569 +/*
2570 + * Copyright © 2015 Broadcom Corporation
2571 + *
2572 + * This program is free software; you can redistribute it and/or modify
2573 + * it under the terms of the GNU General Public License version 2 as
2574 + * published by the Free Software Foundation.
2575 + *
2576 + * This program is distributed in the hope that it will be useful,
2577 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2578 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2579 + * GNU General Public License for more details.
2580 + */
2581 +
2582 +#include <linux/device.h>
2583 +#include <linux/module.h>
2584 +#include <linux/platform_device.h>
2585 +
2586 +#include "brcmnand.h"
2587 +
2588 +static const struct of_device_id brcmstb_nand_of_match[] = {
2589 + { .compatible = "brcm,brcmnand" },
2590 + {},
2591 +};
2592 +MODULE_DEVICE_TABLE(of, brcmstb_nand_of_match);
2593 +
2594 +static int brcmstb_nand_probe(struct platform_device *pdev)
2595 +{
2596 + return brcmnand_probe(pdev, NULL);
2597 +}
2598 +
2599 +static struct platform_driver brcmstb_nand_driver = {
2600 + .probe = brcmstb_nand_probe,
2601 + .remove = brcmnand_remove,
2602 + .driver = {
2603 + .name = "brcmstb_nand",
2604 + .pm = &brcmnand_pm_ops,
2605 + .of_match_table = brcmstb_nand_of_match,
2606 + }
2607 +};
2608 +module_platform_driver(brcmstb_nand_driver);
2609 +
2610 +MODULE_LICENSE("GPL v2");
2611 +MODULE_AUTHOR("Brian Norris");
2612 +MODULE_DESCRIPTION("NAND driver for Broadcom STB chips");
2613 --- /dev/null
2614 +++ b/drivers/mtd/nand/brcmnand/iproc_nand.c
2615 @@ -0,0 +1,150 @@
2616 +/*
2617 + * Copyright © 2015 Broadcom Corporation
2618 + *
2619 + * This program is free software; you can redistribute it and/or modify
2620 + * it under the terms of the GNU General Public License version 2 as
2621 + * published by the Free Software Foundation.
2622 + *
2623 + * This program is distributed in the hope that it will be useful,
2624 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2625 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2626 + * GNU General Public License for more details.
2627 + */
2628 +
2629 +#include <linux/device.h>
2630 +#include <linux/io.h>
2631 +#include <linux/ioport.h>
2632 +#include <linux/module.h>
2633 +#include <linux/of.h>
2634 +#include <linux/of_address.h>
2635 +#include <linux/platform_device.h>
2636 +#include <linux/slab.h>
2637 +
2638 +#include "brcmnand.h"
2639 +
2640 +struct iproc_nand_soc {
2641 + struct brcmnand_soc soc;
2642 +
2643 + void __iomem *idm_base;
2644 + void __iomem *ext_base;
2645 + spinlock_t idm_lock;
2646 +};
2647 +
2648 +#define IPROC_NAND_CTLR_READY_OFFSET 0x10
2649 +#define IPROC_NAND_CTLR_READY BIT(0)
2650 +
2651 +#define IPROC_NAND_IO_CTRL_OFFSET 0x00
2652 +#define IPROC_NAND_APB_LE_MODE BIT(24)
2653 +#define IPROC_NAND_INT_CTRL_READ_ENABLE BIT(6)
2654 +
2655 +static bool iproc_nand_intc_ack(struct brcmnand_soc *soc)
2656 +{
2657 + struct iproc_nand_soc *priv =
2658 + container_of(soc, struct iproc_nand_soc, soc);
2659 + void __iomem *mmio = priv->ext_base + IPROC_NAND_CTLR_READY_OFFSET;
2660 + u32 val = brcmnand_readl(mmio);
2661 +
2662 + if (val & IPROC_NAND_CTLR_READY) {
2663 + brcmnand_writel(IPROC_NAND_CTLR_READY, mmio);
2664 + return true;
2665 + }
2666 +
2667 + return false;
2668 +}
2669 +
2670 +static void iproc_nand_intc_set(struct brcmnand_soc *soc, bool en)
2671 +{
2672 + struct iproc_nand_soc *priv =
2673 + container_of(soc, struct iproc_nand_soc, soc);
2674 + void __iomem *mmio = priv->idm_base + IPROC_NAND_IO_CTRL_OFFSET;
2675 + u32 val;
2676 + unsigned long flags;
2677 +
2678 + spin_lock_irqsave(&priv->idm_lock, flags);
2679 +
2680 + val = brcmnand_readl(mmio);
2681 +
2682 + if (en)
2683 + val |= IPROC_NAND_INT_CTRL_READ_ENABLE;
2684 + else
2685 + val &= ~IPROC_NAND_INT_CTRL_READ_ENABLE;
2686 +
2687 + brcmnand_writel(val, mmio);
2688 +
2689 + spin_unlock_irqrestore(&priv->idm_lock, flags);
2690 +}
2691 +
2692 +static void iproc_nand_apb_access(struct brcmnand_soc *soc, bool prepare)
2693 +{
2694 + struct iproc_nand_soc *priv =
2695 + container_of(soc, struct iproc_nand_soc, soc);
2696 + void __iomem *mmio = priv->idm_base + IPROC_NAND_IO_CTRL_OFFSET;
2697 + u32 val;
2698 + unsigned long flags;
2699 +
2700 + spin_lock_irqsave(&priv->idm_lock, flags);
2701 +
2702 + val = brcmnand_readl(mmio);
2703 +
2704 + if (prepare)
2705 + val |= IPROC_NAND_APB_LE_MODE;
2706 + else
2707 + val &= ~IPROC_NAND_APB_LE_MODE;
2708 +
2709 + brcmnand_writel(val, mmio);
2710 +
2711 + spin_unlock_irqrestore(&priv->idm_lock, flags);
2712 +}
2713 +
2714 +static int iproc_nand_probe(struct platform_device *pdev)
2715 +{
2716 + struct device *dev = &pdev->dev;
2717 + struct iproc_nand_soc *priv;
2718 + struct brcmnand_soc *soc;
2719 + struct resource *res;
2720 +
2721 + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
2722 + if (!priv)
2723 + return -ENOMEM;
2724 + soc = &priv->soc;
2725 +
2726 + spin_lock_init(&priv->idm_lock);
2727 +
2728 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "iproc-idm");
2729 + priv->idm_base = devm_ioremap_resource(dev, res);
2730 + if (IS_ERR(priv->idm_base))
2731 + return PTR_ERR(priv->idm_base);
2732 +
2733 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "iproc-ext");
2734 + priv->ext_base = devm_ioremap_resource(dev, res);
2735 + if (IS_ERR(priv->ext_base))
2736 + return PTR_ERR(priv->ext_base);
2737 +
2738 + soc->ctlrdy_ack = iproc_nand_intc_ack;
2739 + soc->ctlrdy_set_enabled = iproc_nand_intc_set;
2740 + soc->prepare_data_bus = iproc_nand_apb_access;
2741 +
2742 + return brcmnand_probe(pdev, soc);
2743 +}
2744 +
2745 +static const struct of_device_id iproc_nand_of_match[] = {
2746 + { .compatible = "brcm,nand-iproc" },
2747 + {},
2748 +};
2749 +MODULE_DEVICE_TABLE(of, iproc_nand_of_match);
2750 +
2751 +static struct platform_driver iproc_nand_driver = {
2752 + .probe = iproc_nand_probe,
2753 + .remove = brcmnand_remove,
2754 + .driver = {
2755 + .name = "iproc_nand",
2756 + .pm = &brcmnand_pm_ops,
2757 + .of_match_table = iproc_nand_of_match,
2758 + }
2759 +};
2760 +module_platform_driver(iproc_nand_driver);
2761 +
2762 +MODULE_LICENSE("GPL v2");
2763 +MODULE_AUTHOR("Brian Norris");
2764 +MODULE_AUTHOR("Ray Jui");
2765 +MODULE_DESCRIPTION("NAND driver for Broadcom IPROC-based SoCs");
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