target/linux/bcm53xx/patches-4.3/046-clk-nsp-add-clock-support-for-Broadcom-Northstar-Plu.patch

   1 From d358480591b34d081806ecb5a9474930a4d59f8a Mon Sep 17 00:00:00 2001
   2 From: Jon Mason <jonmason@broadcom.com>
   3 Date: Thu, 15 Oct 2015 15:48:27 -0400
   4 Subject: [PATCH 46/50] clk: nsp: add clock support for Broadcom Northstar Plus
   5  SoC
   6
   7 The Broadcom Northstar Plus SoC is architected under the iProc
   8 architecture. It has the following PLLs: ARMPLL, GENPLL, LCPLL0, all
   9 derived from an onboard crystal.
  10
  11 Signed-off-by: Jon Mason <jonmason@broadcom.com>
  12 ---
  13  drivers/clk/bcm/Makefile            |   2 +
  14  drivers/clk/bcm/clk-nsp.c           | 135 ++++++++++++++++++++++++++++++++++++
  15  include/dt-bindings/clock/bcm-nsp.h |  51 ++++++++++++++
  16  3 files changed, 188 insertions(+)
  17  create mode 100644 drivers/clk/bcm/clk-nsp.c
  18  create mode 100644 include/dt-bindings/clock/bcm-nsp.h
  19
  20 --- a/drivers/clk/bcm/Makefile
  21 +++ b/drivers/clk/bcm/Makefile
  22 @@ -4,3 +4,5 @@ obj-$(CONFIG_CLK_BCM_KONA)      += clk-bcm281
  23  obj-$(CONFIG_CLK_BCM_KONA)     += clk-bcm21664.o
  24  obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o clk-iproc-asiu.o
  25  obj-$(CONFIG_ARCH_BCM_CYGNUS)  += clk-cygnus.o
  26 +obj-$(CONFIG_ARCH_BCM_NSP)     += clk-nsp.o
  27 +obj-$(CONFIG_ARCH_BCM_5301X)   += clk-nsp.o
  28 --- /dev/null
  29 +++ b/drivers/clk/bcm/clk-nsp.c
  30 @@ -0,0 +1,135 @@
  31 +/*
  32 + * Copyright (C) 2015 Broadcom Corporation
  33 + *
  34 + * This program is free software; you can redistribute it and/or
  35 + * modify it under the terms of the GNU General Public License as
  36 + * published by the Free Software Foundation version 2.
  37 + *
  38 + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  39 + * kind, whether express or implied; without even the implied warranty
  40 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  41 + * GNU General Public License for more details.
  42 + */
  43 +
  44 +#include <linux/kernel.h>
  45 +#include <linux/err.h>
  46 +#include <linux/clk-provider.h>
  47 +#include <linux/io.h>
  48 +#include <linux/of.h>
  49 +#include <linux/of_address.h>
  50 +
  51 +#include <dt-bindings/clock/bcm-nsp.h>
  52 +#include "clk-iproc.h"
  53 +
  54 +#define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, }
  55 +
  56 +#define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
  57 +       .pwr_shift = ps, .iso_shift = is }
  58 +
  59 +#define RESET_VAL(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \
  60 +       .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \
  61 +       .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \
  62 +       .ka_width = kaw }
  63 +
  64 +#define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \
  65 +       .hold_shift = hs, .bypass_shift = bs }
  66 +
  67 +static void __init nsp_armpll_init(struct device_node *node)
  68 +{
  69 +       iproc_armpll_setup(node);
  70 +}
  71 +CLK_OF_DECLARE(nsp_armpll, "brcm,nsp-armpll", nsp_armpll_init);
  72 +
  73 +static const struct iproc_pll_ctrl genpll = {
  74 +       .flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL,
  75 +       .aon = AON_VAL(0x0, 1, 12, 0),
  76 +       .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 3),
  77 +       .ndiv_int = REG_VAL(0x14, 20, 10),
  78 +       .ndiv_frac = REG_VAL(0x14, 0, 20),
  79 +       .pdiv = REG_VAL(0x18, 24, 3),
  80 +       .status = REG_VAL(0x20, 12, 1),
  81 +};
  82 +
  83 +static const struct iproc_clk_ctrl genpll_clk[] = {
  84 +       [BCM_NSP_GENPLL_PHY_CLK] = {
  85 +               .channel = BCM_NSP_GENPLL_PHY_CLK,
  86 +               .flags = IPROC_CLK_AON,
  87 +               .enable = ENABLE_VAL(0x4, 12, 6, 18),
  88 +               .mdiv = REG_VAL(0x18, 16, 8),
  89 +       },
  90 +       [BCM_NSP_GENPLL_ENET_SW_CLK] = {
  91 +               .channel = BCM_NSP_GENPLL_ENET_SW_CLK,
  92 +               .flags = IPROC_CLK_AON,
  93 +               .enable = ENABLE_VAL(0x4, 13, 7, 19),
  94 +               .mdiv = REG_VAL(0x18, 8, 8),
  95 +       },
  96 +       [BCM_NSP_GENPLL_USB_PHY_REF_CLK] = {
  97 +               .channel = BCM_NSP_GENPLL_USB_PHY_REF_CLK,
  98 +               .flags = IPROC_CLK_AON,
  99 +               .enable = ENABLE_VAL(0x4, 14, 8, 20),
 100 +               .mdiv = REG_VAL(0x18, 0, 8),
 101 +       },
 102 +       [BCM_NSP_GENPLL_IPROCFAST_CLK] = {
 103 +               .channel = BCM_NSP_GENPLL_IPROCFAST_CLK,
 104 +               .flags = IPROC_CLK_AON,
 105 +               .enable = ENABLE_VAL(0x4, 15, 9, 21),
 106 +               .mdiv = REG_VAL(0x1c, 16, 8),
 107 +       },
 108 +       [BCM_NSP_GENPLL_SATA1_CLK] = {
 109 +               .channel = BCM_NSP_GENPLL_SATA1_CLK,
 110 +               .flags = IPROC_CLK_AON,
 111 +               .enable = ENABLE_VAL(0x4, 16, 10, 22),
 112 +               .mdiv = REG_VAL(0x1c, 8, 8),
 113 +       },
 114 +       [BCM_NSP_GENPLL_SATA2_CLK] = {
 115 +               .channel = BCM_NSP_GENPLL_SATA2_CLK,
 116 +               .flags = IPROC_CLK_AON,
 117 +               .enable = ENABLE_VAL(0x4, 17, 11, 23),
 118 +               .mdiv = REG_VAL(0x1c, 0, 8),
 119 +       },
 120 +};
 121 +
 122 +static void __init nsp_genpll_clk_init(struct device_node *node)
 123 +{
 124 +       iproc_pll_clk_setup(node, &genpll, NULL, 0, genpll_clk,
 125 +                           ARRAY_SIZE(genpll_clk));
 126 +}
 127 +CLK_OF_DECLARE(nsp_genpll_clk, "brcm,nsp-genpll", nsp_genpll_clk_init);
 128 +
 129 +static const struct iproc_pll_ctrl lcpll0 = {
 130 +       .flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL,
 131 +       .aon = AON_VAL(0x0, 1, 24, 0),
 132 +       .reset = RESET_VAL(0x0, 23, 22, 16, 3, 12, 4, 19, 4),
 133 +       .ndiv_int = REG_VAL(0x4, 20, 8),
 134 +       .ndiv_frac = REG_VAL(0x4, 0, 20),
 135 +       .pdiv = REG_VAL(0x4, 28, 3),
 136 +       .status = REG_VAL(0x10, 12, 1),
 137 +};
 138 +
 139 +static const struct iproc_clk_ctrl lcpll0_clk[] = {
 140 +       [BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK] = {
 141 +               .channel = BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK,
 142 +               .flags = IPROC_CLK_AON,
 143 +               .enable = ENABLE_VAL(0x0, 6, 3, 9),
 144 +               .mdiv = REG_VAL(0x8, 24, 8),
 145 +       },
 146 +       [BCM_NSP_LCPLL0_SDIO_CLK] = {
 147 +               .channel = BCM_NSP_LCPLL0_SDIO_CLK,
 148 +               .flags = IPROC_CLK_AON,
 149 +               .enable = ENABLE_VAL(0x0, 7, 4, 10),
 150 +               .mdiv = REG_VAL(0x8, 16, 8),
 151 +       },
 152 +       [BCM_NSP_LCPLL0_DDR_PHY_CLK] = {
 153 +               .channel = BCM_NSP_LCPLL0_DDR_PHY_CLK,
 154 +               .flags = IPROC_CLK_AON,
 155 +               .enable = ENABLE_VAL(0x0, 8, 5, 11),
 156 +               .mdiv = REG_VAL(0x8, 8, 8),
 157 +       },
 158 +};
 159 +
 160 +static void __init nsp_lcpll0_clk_init(struct device_node *node)
 161 +{
 162 +       iproc_pll_clk_setup(node, &lcpll0, NULL, 0, lcpll0_clk,
 163 +                           ARRAY_SIZE(lcpll0_clk));
 164 +}
 165 +CLK_OF_DECLARE(nsp_lcpll0_clk, "brcm,nsp-lcpll0", nsp_lcpll0_clk_init);
 166 --- /dev/null
 167 +++ b/include/dt-bindings/clock/bcm-nsp.h
 168 @@ -0,0 +1,51 @@
 169 +/*
 170 + *  BSD LICENSE
 171 + *
 172 + *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.
 173 + *
 174 + *  Redistribution and use in source and binary forms, with or without
 175 + *  modification, are permitted provided that the following conditions
 176 + *  are met:
 177 + *
 178 + *     * Redistributions of source code must retain the above copyright
 179 + *       notice, this list of conditions and the following disclaimer.
 180 + *     * Redistributions in binary form must reproduce the above copyright
 181 + *       notice, this list of conditions and the following disclaimer in
 182 + *       the documentation and/or other materials provided with the
 183 + *       distribution.
 184 + *     * Neither the name of Broadcom Corporation nor the names of its
 185 + *       contributors may be used to endorse or promote products derived
 186 + *       from this software without specific prior written permission.
 187 + *
 188 + *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 189 + *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 190 + *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 191 + *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 192 + *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 193 + *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 194 + *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 195 + *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 196 + *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 197 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 198 + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 199 + */
 200 +
 201 +#ifndef _CLOCK_BCM_NSP_H
 202 +#define _CLOCK_BCM_NSP_H
 203 +
 204 +/* GENPLL clock channel ID */
 205 +#define BCM_NSP_GENPLL                 0
 206 +#define BCM_NSP_GENPLL_PHY_CLK         1
 207 +#define BCM_NSP_GENPLL_ENET_SW_CLK     2
 208 +#define BCM_NSP_GENPLL_USB_PHY_REF_CLK 3
 209 +#define BCM_NSP_GENPLL_IPROCFAST_CLK   4
 210 +#define BCM_NSP_GENPLL_SATA1_CLK       5
 211 +#define BCM_NSP_GENPLL_SATA2_CLK       6
 212 +
 213 +/* LCPLL0 clock channel ID */
 214 +#define BCM_NSP_LCPLL0                 0
 215 +#define BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK        1
 216 +#define BCM_NSP_LCPLL0_SDIO_CLK                2
 217 +#define BCM_NSP_LCPLL0_DDR_PHY_CLK     3
 218 +
 219 +#endif /* _CLOCK_BCM_NSP_H */