target/linux/bcm53xx/patches-4.4/038-0002-ARM-dts-BCM5301X-Add-SRAB-interrupts.patch

   1 From 2cd0c0202f138fa95b3fbb027e87b191ad0b1884 Mon Sep 17 00:00:00 2001
   2 From: Florian Fainelli <f.fainelli@gmail.com>
   3 Date: Tue, 24 May 2016 11:41:58 -0700
   4 Subject: [PATCH 2/3] ARM: dts: BCM5301X: Add SRAB interrupts
   5
   6 Add interrupt mapping for the Switch Register Access Block. Only 12
   7 interrupts are usable at the moment even though up to 32 are dedicated
   8 to the SRAB.
   9
  10 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
  11 ---
  12  arch/arm/boot/dts/bcm5301x.dtsi | 15 +++++++++++++++
  13  1 file changed, 15 insertions(+)
  14
  15 --- a/arch/arm/boot/dts/bcm5301x.dtsi
  16 +++ b/arch/arm/boot/dts/bcm5301x.dtsi
  17 @@ -153,6 +153,21 @@
  18                         /* ChipCommon */
  19                         <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
  20
  21 +                       /* Switch Register Access Block */
  22 +                       <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
  23 +                       <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
  24 +                       <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
  25 +                       <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
  26 +                       <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
  27 +                       <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
  28 +                       <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
  29 +                       <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
  30 +                       <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
  31 +                       <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
  32 +                       <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
  33 +                       <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
  34 +                       <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
  35 +
  36                         /* PCIe Controller 0 */
  37                         <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
  38                         <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,