target/linux/bcm53xx/patches-4.4/071-0002-phy-bcm-ns-usb3-split-all-writes-into-reg-val-pairs.patch

   1 From fff3364a637796611c06f59a6f2be61685d99bfe Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
   3 Date: Sun, 2 Apr 2017 18:55:22 +0200
   4 Subject: [PATCH] phy: bcm-ns-usb3: split all writes into reg & val pairs
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 So far all the PHY initialization was implemented using some totally
  10 magic values. There was some pattern there but it wasn't clear what is
  11 it about.
  12
  13 Thanks to the patch submitted by Broadcom:
  14 [PATCH 5/6] phy: Add USB3 PHY support for Broadcom NSP SoC
  15 and the upstream "iproc-mdio" driver we now know there is a MDIO bus
  16 underneath with PHY(s) and their registers.
  17
  18 It allows us to clean the driver a bit by making all these values less
  19 magical. The next step is switching to using a proper MDIO layer.
  20
  21 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
  22 Acked-by: Jon Mason <jon.mason@broadcom.com>
  23 Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
  24 ---
  25  drivers/phy/phy-bcm-ns-usb3.c | 69 ++++++++++++++++++++++++++++++-------------
  26  1 file changed, 49 insertions(+), 20 deletions(-)
  27
  28 --- a/drivers/phy/phy-bcm-ns-usb3.c
  29 +++ b/drivers/phy/phy-bcm-ns-usb3.c
  30 @@ -2,6 +2,7 @@
  31   * Broadcom Northstar USB 3.0 PHY Driver
  32   *
  33   * Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
  34 + * Copyright (C) 2016 Broadcom
  35   *
  36   * All magic values used for initialization (and related comments) were obtained
  37   * from Broadcom's SDK:
  38 @@ -23,6 +24,23 @@
  39
  40  #define BCM_NS_USB3_MII_MNG_TIMEOUT_US 1000    /* usecs */
  41
  42 +#define BCM_NS_USB3_PHY_BASE_ADDR_REG  0x1f
  43 +#define BCM_NS_USB3_PHY_PLL30_BLOCK    0x8000
  44 +#define BCM_NS_USB3_PHY_TX_PMD_BLOCK   0x8040
  45 +#define BCM_NS_USB3_PHY_PIPE_BLOCK     0x8060
  46 +
  47 +/* Registers of PLL30 block */
  48 +#define BCM_NS_USB3_PLL_CONTROL                0x01
  49 +#define BCM_NS_USB3_PLLA_CONTROL0      0x0a
  50 +#define BCM_NS_USB3_PLLA_CONTROL1      0x0b
  51 +
  52 +/* Registers of TX PMD block */
  53 +#define BCM_NS_USB3_TX_PMD_CONTROL1    0x01
  54 +
  55 +/* Registers of PIPE block */
  56 +#define BCM_NS_USB3_LFPS_CMP           0x02
  57 +#define BCM_NS_USB3_LFPS_DEGLITCH      0x03
  58 +
  59  enum bcm_ns_family {
  60         BCM_NS_UNKNOWN,
  61         BCM_NS_AX,
  62 @@ -76,8 +94,10 @@ static inline int bcm_ns_usb3_mii_mng_wa
  63                                     usecs_to_jiffies(BCM_NS_USB3_MII_MNG_TIMEOUT_US));
  64  }
  65
  66 -static int bcm_ns_usb3_mii_mng_write32(struct bcm_ns_usb3 *usb3, u32 value)
  67 +static int bcm_ns_usb3_mdio_phy_write(struct bcm_ns_usb3 *usb3, u16 reg,
  68 +                                     u16 value)
  69  {
  70 +       u32 tmp = 0;
  71         int err;
  72
  73         err = bcm_ns_usb3_mii_mng_wait_idle(usb3);
  74 @@ -86,7 +106,11 @@ static int bcm_ns_usb3_mii_mng_write32(s
  75                 return err;
  76         }
  77
  78 -       writel(value, usb3->ccb_mii + BCMA_CCB_MII_MNG_CMD_DATA);
  79 +       /* TODO: Use a proper MDIO bus layer */
  80 +       tmp |= 0x58020000; /* Magic value for MDIO PHY write */
  81 +       tmp |= reg << 18;
  82 +       tmp |= value;
  83 +       writel(tmp, usb3->ccb_mii + BCMA_CCB_MII_MNG_CMD_DATA);
  84
  85         return 0;
  86  }
  87 @@ -102,21 +126,22 @@ static int bcm_ns_usb3_phy_init_ns_bx(st
  88         udelay(2);
  89
  90         /* USB3 PLL Block */
  91 -       err = bcm_ns_usb3_mii_mng_write32(usb3, 0x587e8000);
  92 +       err = bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG,
  93 +                                        BCM_NS_USB3_PHY_PLL30_BLOCK);
  94         if (err < 0)
  95                 return err;
  96
  97         /* Assert Ana_Pllseq start */
  98 -       bcm_ns_usb3_mii_mng_write32(usb3, 0x58061000);
  99 +       bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLL_CONTROL, 0x1000);
 100
 101         /* Assert CML Divider ratio to 26 */
 102 -       bcm_ns_usb3_mii_mng_write32(usb3, 0x582a6400);
 103 +       bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLLA_CONTROL0, 0x6400);
 104
 105         /* Asserting PLL Reset */
 106 -       bcm_ns_usb3_mii_mng_write32(usb3, 0x582ec000);
 107 +       bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLLA_CONTROL1, 0xc000);
 108
 109         /* Deaaserting PLL Reset */
 110 -       bcm_ns_usb3_mii_mng_write32(usb3, 0x582e8000);
 111 +       bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLLA_CONTROL1, 0x8000);
 112
 113         /* Waiting MII Mgt interface idle */
 114         bcm_ns_usb3_mii_mng_wait_idle(usb3);
 115 @@ -125,22 +150,24 @@ static int bcm_ns_usb3_phy_init_ns_bx(st
 116         writel(0, usb3->dmp + BCMA_RESET_CTL);
 117
 118         /* PLL frequency monitor enable */
 119 -       bcm_ns_usb3_mii_mng_write32(usb3, 0x58069000);
 120 +       bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLL_CONTROL, 0x9000);
 121
 122         /* PIPE Block */
 123 -       bcm_ns_usb3_mii_mng_write32(usb3, 0x587e8060);
 124 +       bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG,
 125 +                                  BCM_NS_USB3_PHY_PIPE_BLOCK);
 126
 127         /* CMPMAX & CMPMINTH setting */
 128 -       bcm_ns_usb3_mii_mng_write32(usb3, 0x580af30d);
 129 +       bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_LFPS_CMP, 0xf30d);
 130
 131         /* DEGLITCH MIN & MAX setting */
 132 -       bcm_ns_usb3_mii_mng_write32(usb3, 0x580e6302);
 133 +       bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_LFPS_DEGLITCH, 0x6302);
 134
 135         /* TXPMD block */
 136 -       bcm_ns_usb3_mii_mng_write32(usb3, 0x587e8040);
 137 +       bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG,
 138 +                                  BCM_NS_USB3_PHY_TX_PMD_BLOCK);
 139
 140         /* Enabling SSC */
 141 -       bcm_ns_usb3_mii_mng_write32(usb3, 0x58061003);
 142 +       bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_TX_PMD_CONTROL1, 0x1003);
 143
 144         /* Waiting MII Mgt interface idle */
 145         bcm_ns_usb3_mii_mng_wait_idle(usb3);
 146 @@ -159,22 +186,24 @@ static int bcm_ns_usb3_phy_init_ns_ax(st
 147         udelay(2);
 148
 149         /* PLL30 block */
 150 -       err = bcm_ns_usb3_mii_mng_write32(usb3, 0x587e8000);
 151 +       err = bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG,
 152 +                                        BCM_NS_USB3_PHY_PLL30_BLOCK);
 153         if (err < 0)
 154                 return err;
 155
 156 -       bcm_ns_usb3_mii_mng_write32(usb3, 0x582a6400);
 157 +       bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLLA_CONTROL0, 0x6400);
 158
 159 -       bcm_ns_usb3_mii_mng_write32(usb3, 0x587e80e0);
 160 +       bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG, 0x80e0);
 161
 162 -       bcm_ns_usb3_mii_mng_write32(usb3, 0x580a009c);
 163 +       bcm_ns_usb3_mdio_phy_write(usb3, 0x02, 0x009c);
 164
 165         /* Enable SSC */
 166 -       bcm_ns_usb3_mii_mng_write32(usb3, 0x587e8040);
 167 +       bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG,
 168 +                                  BCM_NS_USB3_PHY_TX_PMD_BLOCK);
 169
 170 -       bcm_ns_usb3_mii_mng_write32(usb3, 0x580a21d3);
 171 +       bcm_ns_usb3_mdio_phy_write(usb3, 0x02, 0x21d3);
 172
 173 -       bcm_ns_usb3_mii_mng_write32(usb3, 0x58061003);
 174 +       bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_TX_PMD_CONTROL1, 0x1003);
 175
 176         /* Waiting MII Mgt interface idle */
 177         bcm_ns_usb3_mii_mng_wait_idle(usb3);