target/linux/bcm53xx/patches-4.4/087-0004-PCI-iproc-Add-iProc-PCIe-MSI-support.patch

   1 From 3bc2b2348835f6edd33c383a2fbcf15fe3dac3b2 Mon Sep 17 00:00:00 2001
   2 From: Ray Jui <rjui@broadcom.com>
   3 Date: Wed, 6 Jan 2016 18:04:35 -0600
   4 Subject: [PATCH 4/5] PCI: iproc: Add iProc PCIe MSI support
   5
   6 Add PCIe MSI support for both PAXB and PAXC interfaces on all iProc-based
   7 platforms.
   8
   9 The iProc PCIe MSI support deploys an event queue-based implementation.
  10 Each event queue is serviced by a GIC interrupt and can support up to 64
  11 MSI vectors.  Host memory is allocated for the event queues, and each event
  12 queue consists of 64 word-sized entries.  MSI data is written to the lower
  13 16-bit of each entry, whereas the upper 16-bit of the entry is reserved for
  14 the controller for internal processing.
  15
  16 Each event queue is tracked by a head pointer and tail pointer.  Head
  17 pointer indicates the next entry in the event queue to be processed by
  18 the driver and is updated by the driver after processing is done.
  19 The controller uses the tail pointer as the next MSI data insertion
  20 point.  The controller ensures MSI data is flushed to host memory before
  21 updating the tail pointer and then triggering the interrupt.
  22
  23 MSI IRQ affinity is supported by evenly distributing the interrupts to each
  24 CPU core.  MSI vector is moved from one GIC interrupt to another in order
  25 to steer to the target CPU.
  26
  27 Therefore, the actual number of supported MSI vectors is:
  28
  29   M * 64 / N
  30
  31 where M denotes the number of GIC interrupts (event queues), and N denotes
  32 the number of CPU cores.
  33
  34 This iProc event queue-based MSI support should not be used with newer
  35 platforms with integrated MSI support in the GIC (e.g., giv2m or
  36 gicv3-its).
  37
  38 [bhelgaas: fold in Kconfig fixes from Arnd Bergmann <arnd@arndb.de>]
  39 Signed-off-by: Ray Jui <rjui@broadcom.com>
  40 Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  41 Reviewed-by: Anup Patel <anup.patel@broadcom.com>
  42 Reviewed-by: Vikram Prakash <vikramp@broadcom.com>
  43 Reviewed-by: Scott Branden <sbranden@broadcom.com>
  44 Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
  45 ---
  46  drivers/pci/host/Kconfig               |  10 +
  47  drivers/pci/host/Makefile              |   1 +
  48  drivers/pci/host/pcie-iproc-bcma.c     |   1 +
  49  drivers/pci/host/pcie-iproc-msi.c      | 675 +++++++++++++++++++++++++++++++++
  50  drivers/pci/host/pcie-iproc-platform.c |   1 +
  51  drivers/pci/host/pcie-iproc.c          |  26 ++
  52  drivers/pci/host/pcie-iproc.h          |  23 +-
  53  7 files changed, 735 insertions(+), 2 deletions(-)
  54  create mode 100644 drivers/pci/host/pcie-iproc-msi.c
  55
  56 --- a/drivers/pci/host/Kconfig
  57 +++ b/drivers/pci/host/Kconfig
  58 @@ -146,6 +146,16 @@ config PCIE_IPROC_BCMA
  59           Say Y here if you want to use the Broadcom iProc PCIe controller
  60           through the BCMA bus interface
  61
  62 +config PCIE_IPROC_MSI
  63 +       bool "Broadcom iProc PCIe MSI support"
  64 +       depends on PCIE_IPROC_PLATFORM || PCIE_IPROC_BCMA
  65 +       depends on PCI_MSI
  66 +       select PCI_MSI_IRQ_DOMAIN
  67 +       default ARCH_BCM_IPROC
  68 +       help
  69 +         Say Y here if you want to enable MSI support for Broadcom's iProc
  70 +         PCIe controller
  71 +
  72  config PCIE_ALTERA
  73         bool "Altera PCIe controller"
  74         depends on ARM || NIOS2
  75 --- a/drivers/pci/host/Makefile
  76 +++ b/drivers/pci/host/Makefile
  77 @@ -15,6 +15,7 @@ obj-$(CONFIG_PCI_XGENE_MSI) += pci-xgene
  78  obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
  79  obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
  80  obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
  81 +obj-$(CONFIG_PCIE_IPROC_MSI) += pcie-iproc-msi.o
  82  obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
  83  obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
  84  obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
  85 --- a/drivers/pci/host/pcie-iproc-bcma.c
  86 +++ b/drivers/pci/host/pcie-iproc-bcma.c
  87 @@ -55,6 +55,7 @@ static int iproc_pcie_bcma_probe(struct
  88         bcma_set_drvdata(bdev, pcie);
  89
  90         pcie->base = bdev->io_addr;
  91 +       pcie->base_addr = bdev->addr;
  92
  93         res_mem.start = bdev->addr_s[0];
  94         res_mem.end = bdev->addr_s[0] + SZ_128M - 1;
  95 --- /dev/null
  96 +++ b/drivers/pci/host/pcie-iproc-msi.c
  97 @@ -0,0 +1,675 @@
  98 +/*
  99 + * Copyright (C) 2015 Broadcom Corporation
 100 + *
 101 + * This program is free software; you can redistribute it and/or
 102 + * modify it under the terms of the GNU General Public License as
 103 + * published by the Free Software Foundation version 2.
 104 + *
 105 + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 106 + * kind, whether express or implied; without even the implied warranty
 107 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 108 + * GNU General Public License for more details.
 109 + */
 110 +
 111 +#include <linux/interrupt.h>
 112 +#include <linux/irqchip/chained_irq.h>
 113 +#include <linux/irqdomain.h>
 114 +#include <linux/msi.h>
 115 +#include <linux/of_irq.h>
 116 +#include <linux/of_pci.h>
 117 +#include <linux/pci.h>
 118 +
 119 +#include "pcie-iproc.h"
 120 +
 121 +#define IPROC_MSI_INTR_EN_SHIFT        11
 122 +#define IPROC_MSI_INTR_EN              BIT(IPROC_MSI_INTR_EN_SHIFT)
 123 +#define IPROC_MSI_INT_N_EVENT_SHIFT    1
 124 +#define IPROC_MSI_INT_N_EVENT          BIT(IPROC_MSI_INT_N_EVENT_SHIFT)
 125 +#define IPROC_MSI_EQ_EN_SHIFT          0
 126 +#define IPROC_MSI_EQ_EN                BIT(IPROC_MSI_EQ_EN_SHIFT)
 127 +
 128 +#define IPROC_MSI_EQ_MASK              0x3f
 129 +
 130 +/* Max number of GIC interrupts */
 131 +#define NR_HW_IRQS                     6
 132 +
 133 +/* Number of entries in each event queue */
 134 +#define EQ_LEN                         64
 135 +
 136 +/* Size of each event queue memory region */
 137 +#define EQ_MEM_REGION_SIZE             SZ_4K
 138 +
 139 +/* Size of each MSI address region */
 140 +#define MSI_MEM_REGION_SIZE            SZ_4K
 141 +
 142 +enum iproc_msi_reg {
 143 +       IPROC_MSI_EQ_PAGE = 0,
 144 +       IPROC_MSI_EQ_PAGE_UPPER,
 145 +       IPROC_MSI_PAGE,
 146 +       IPROC_MSI_PAGE_UPPER,
 147 +       IPROC_MSI_CTRL,
 148 +       IPROC_MSI_EQ_HEAD,
 149 +       IPROC_MSI_EQ_TAIL,
 150 +       IPROC_MSI_INTS_EN,
 151 +       IPROC_MSI_REG_SIZE,
 152 +};
 153 +
 154 +struct iproc_msi;
 155 +
 156 +/**
 157 + * iProc MSI group
 158 + *
 159 + * One MSI group is allocated per GIC interrupt, serviced by one iProc MSI
 160 + * event queue.
 161 + *
 162 + * @msi: pointer to iProc MSI data
 163 + * @gic_irq: GIC interrupt
 164 + * @eq: Event queue number
 165 + */
 166 +struct iproc_msi_grp {
 167 +       struct iproc_msi *msi;
 168 +       int gic_irq;
 169 +       unsigned int eq;
 170 +};
 171 +
 172 +/**
 173 + * iProc event queue based MSI
 174 + *
 175 + * Only meant to be used on platforms without MSI support integrated into the
 176 + * GIC.
 177 + *
 178 + * @pcie: pointer to iProc PCIe data
 179 + * @reg_offsets: MSI register offsets
 180 + * @grps: MSI groups
 181 + * @nr_irqs: number of total interrupts connected to GIC
 182 + * @nr_cpus: number of toal CPUs
 183 + * @has_inten_reg: indicates the MSI interrupt enable register needs to be
 184 + * set explicitly (required for some legacy platforms)
 185 + * @bitmap: MSI vector bitmap
 186 + * @bitmap_lock: lock to protect access to the MSI bitmap
 187 + * @nr_msi_vecs: total number of MSI vectors
 188 + * @inner_domain: inner IRQ domain
 189 + * @msi_domain: MSI IRQ domain
 190 + * @nr_eq_region: required number of 4K aligned memory region for MSI event
 191 + * queues
 192 + * @nr_msi_region: required number of 4K aligned address region for MSI posted
 193 + * writes
 194 + * @eq_cpu: pointer to allocated memory region for MSI event queues
 195 + * @eq_dma: DMA address of MSI event queues
 196 + * @msi_addr: MSI address
 197 + */
 198 +struct iproc_msi {
 199 +       struct iproc_pcie *pcie;
 200 +       const u16 (*reg_offsets)[IPROC_MSI_REG_SIZE];
 201 +       struct iproc_msi_grp *grps;
 202 +       int nr_irqs;
 203 +       int nr_cpus;
 204 +       bool has_inten_reg;
 205 +       unsigned long *bitmap;
 206 +       struct mutex bitmap_lock;
 207 +       unsigned int nr_msi_vecs;
 208 +       struct irq_domain *inner_domain;
 209 +       struct irq_domain *msi_domain;
 210 +       unsigned int nr_eq_region;
 211 +       unsigned int nr_msi_region;
 212 +       void *eq_cpu;
 213 +       dma_addr_t eq_dma;
 214 +       phys_addr_t msi_addr;
 215 +};
 216 +
 217 +static const u16 iproc_msi_reg_paxb[NR_HW_IRQS][IPROC_MSI_REG_SIZE] = {
 218 +       { 0x200, 0x2c0, 0x204, 0x2c4, 0x210, 0x250, 0x254, 0x208 },
 219 +       { 0x200, 0x2c0, 0x204, 0x2c4, 0x214, 0x258, 0x25c, 0x208 },
 220 +       { 0x200, 0x2c0, 0x204, 0x2c4, 0x218, 0x260, 0x264, 0x208 },
 221 +       { 0x200, 0x2c0, 0x204, 0x2c4, 0x21c, 0x268, 0x26c, 0x208 },
 222 +       { 0x200, 0x2c0, 0x204, 0x2c4, 0x220, 0x270, 0x274, 0x208 },
 223 +       { 0x200, 0x2c0, 0x204, 0x2c4, 0x224, 0x278, 0x27c, 0x208 },
 224 +};
 225 +
 226 +static const u16 iproc_msi_reg_paxc[NR_HW_IRQS][IPROC_MSI_REG_SIZE] = {
 227 +       { 0xc00, 0xc04, 0xc08, 0xc0c, 0xc40, 0xc50, 0xc60 },
 228 +       { 0xc10, 0xc14, 0xc18, 0xc1c, 0xc44, 0xc54, 0xc64 },
 229 +       { 0xc20, 0xc24, 0xc28, 0xc2c, 0xc48, 0xc58, 0xc68 },
 230 +       { 0xc30, 0xc34, 0xc38, 0xc3c, 0xc4c, 0xc5c, 0xc6c },
 231 +};
 232 +
 233 +static inline u32 iproc_msi_read_reg(struct iproc_msi *msi,
 234 +                                    enum iproc_msi_reg reg,
 235 +                                    unsigned int eq)
 236 +{
 237 +       struct iproc_pcie *pcie = msi->pcie;
 238 +
 239 +       return readl_relaxed(pcie->base + msi->reg_offsets[eq][reg]);
 240 +}
 241 +
 242 +static inline void iproc_msi_write_reg(struct iproc_msi *msi,
 243 +                                      enum iproc_msi_reg reg,
 244 +                                      int eq, u32 val)
 245 +{
 246 +       struct iproc_pcie *pcie = msi->pcie;
 247 +
 248 +       writel_relaxed(val, pcie->base + msi->reg_offsets[eq][reg]);
 249 +}
 250 +
 251 +static inline u32 hwirq_to_group(struct iproc_msi *msi, unsigned long hwirq)
 252 +{
 253 +       return (hwirq % msi->nr_irqs);
 254 +}
 255 +
 256 +static inline unsigned int iproc_msi_addr_offset(struct iproc_msi *msi,
 257 +                                                unsigned long hwirq)
 258 +{
 259 +       if (msi->nr_msi_region > 1)
 260 +               return hwirq_to_group(msi, hwirq) * MSI_MEM_REGION_SIZE;
 261 +       else
 262 +               return hwirq_to_group(msi, hwirq) * sizeof(u32);
 263 +}
 264 +
 265 +static inline unsigned int iproc_msi_eq_offset(struct iproc_msi *msi, u32 eq)
 266 +{
 267 +       if (msi->nr_eq_region > 1)
 268 +               return eq * EQ_MEM_REGION_SIZE;
 269 +       else
 270 +               return eq * EQ_LEN * sizeof(u32);
 271 +}
 272 +
 273 +static struct irq_chip iproc_msi_irq_chip = {
 274 +       .name = "iProc-MSI",
 275 +};
 276 +
 277 +static struct msi_domain_info iproc_msi_domain_info = {
 278 +       .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
 279 +               MSI_FLAG_PCI_MSIX,
 280 +       .chip = &iproc_msi_irq_chip,
 281 +};
 282 +
 283 +/*
 284 + * In iProc PCIe core, each MSI group is serviced by a GIC interrupt and a
 285 + * dedicated event queue.  Each MSI group can support up to 64 MSI vectors.
 286 + *
 287 + * The number of MSI groups varies between different iProc SoCs.  The total
 288 + * number of CPU cores also varies.  To support MSI IRQ affinity, we
 289 + * distribute GIC interrupts across all available CPUs.  MSI vector is moved
 290 + * from one GIC interrupt to another to steer to the target CPU.
 291 + *
 292 + * Assuming:
 293 + * - the number of MSI groups is M
 294 + * - the number of CPU cores is N
 295 + * - M is always a multiple of N
 296 + *
 297 + * Total number of raw MSI vectors = M * 64
 298 + * Total number of supported MSI vectors = (M * 64) / N
 299 + */
 300 +static inline int hwirq_to_cpu(struct iproc_msi *msi, unsigned long hwirq)
 301 +{
 302 +       return (hwirq % msi->nr_cpus);
 303 +}
 304 +
 305 +static inline unsigned long hwirq_to_canonical_hwirq(struct iproc_msi *msi,
 306 +                                                    unsigned long hwirq)
 307 +{
 308 +       return (hwirq - hwirq_to_cpu(msi, hwirq));
 309 +}
 310 +
 311 +static int iproc_msi_irq_set_affinity(struct irq_data *data,
 312 +                                     const struct cpumask *mask, bool force)
 313 +{
 314 +       struct iproc_msi *msi = irq_data_get_irq_chip_data(data);
 315 +       int target_cpu = cpumask_first(mask);
 316 +       int curr_cpu;
 317 +
 318 +       curr_cpu = hwirq_to_cpu(msi, data->hwirq);
 319 +       if (curr_cpu == target_cpu)
 320 +               return IRQ_SET_MASK_OK_DONE;
 321 +
 322 +       /* steer MSI to the target CPU */
 323 +       data->hwirq = hwirq_to_canonical_hwirq(msi, data->hwirq) + target_cpu;
 324 +
 325 +       return IRQ_SET_MASK_OK;
 326 +}
 327 +
 328 +static void iproc_msi_irq_compose_msi_msg(struct irq_data *data,
 329 +                                         struct msi_msg *msg)
 330 +{
 331 +       struct iproc_msi *msi = irq_data_get_irq_chip_data(data);
 332 +       dma_addr_t addr;
 333 +
 334 +       addr = msi->msi_addr + iproc_msi_addr_offset(msi, data->hwirq);
 335 +       msg->address_lo = lower_32_bits(addr);
 336 +       msg->address_hi = upper_32_bits(addr);
 337 +       msg->data = data->hwirq;
 338 +}
 339 +
 340 +static struct irq_chip iproc_msi_bottom_irq_chip = {
 341 +       .name = "MSI",
 342 +       .irq_set_affinity = iproc_msi_irq_set_affinity,
 343 +       .irq_compose_msi_msg = iproc_msi_irq_compose_msi_msg,
 344 +};
 345 +
 346 +static int iproc_msi_irq_domain_alloc(struct irq_domain *domain,
 347 +                                     unsigned int virq, unsigned int nr_irqs,
 348 +                                     void *args)
 349 +{
 350 +       struct iproc_msi *msi = domain->host_data;
 351 +       int hwirq;
 352 +
 353 +       mutex_lock(&msi->bitmap_lock);
 354 +
 355 +       /* Allocate 'nr_cpus' number of MSI vectors each time */
 356 +       hwirq = bitmap_find_next_zero_area(msi->bitmap, msi->nr_msi_vecs, 0,
 357 +                                          msi->nr_cpus, 0);
 358 +       if (hwirq < msi->nr_msi_vecs) {
 359 +               bitmap_set(msi->bitmap, hwirq, msi->nr_cpus);
 360 +       } else {
 361 +               mutex_unlock(&msi->bitmap_lock);
 362 +               return -ENOSPC;
 363 +       }
 364 +
 365 +       mutex_unlock(&msi->bitmap_lock);
 366 +
 367 +       irq_domain_set_info(domain, virq, hwirq, &iproc_msi_bottom_irq_chip,
 368 +                           domain->host_data, handle_simple_irq, NULL, NULL);
 369 +
 370 +       return 0;
 371 +}
 372 +
 373 +static void iproc_msi_irq_domain_free(struct irq_domain *domain,
 374 +                                     unsigned int virq, unsigned int nr_irqs)
 375 +{
 376 +       struct irq_data *data = irq_domain_get_irq_data(domain, virq);
 377 +       struct iproc_msi *msi = irq_data_get_irq_chip_data(data);
 378 +       unsigned int hwirq;
 379 +
 380 +       mutex_lock(&msi->bitmap_lock);
 381 +
 382 +       hwirq = hwirq_to_canonical_hwirq(msi, data->hwirq);
 383 +       bitmap_clear(msi->bitmap, hwirq, msi->nr_cpus);
 384 +
 385 +       mutex_unlock(&msi->bitmap_lock);
 386 +
 387 +       irq_domain_free_irqs_parent(domain, virq, nr_irqs);
 388 +}
 389 +
 390 +static const struct irq_domain_ops msi_domain_ops = {
 391 +       .alloc = iproc_msi_irq_domain_alloc,
 392 +       .free = iproc_msi_irq_domain_free,
 393 +};
 394 +
 395 +static inline u32 decode_msi_hwirq(struct iproc_msi *msi, u32 eq, u32 head)
 396 +{
 397 +       u32 *msg, hwirq;
 398 +       unsigned int offs;
 399 +
 400 +       offs = iproc_msi_eq_offset(msi, eq) + head * sizeof(u32);
 401 +       msg = (u32 *)(msi->eq_cpu + offs);
 402 +       hwirq = *msg & IPROC_MSI_EQ_MASK;
 403 +
 404 +       /*
 405 +        * Since we have multiple hwirq mapped to a single MSI vector,
 406 +        * now we need to derive the hwirq at CPU0.  It can then be used to
 407 +        * mapped back to virq.
 408 +        */
 409 +       return hwirq_to_canonical_hwirq(msi, hwirq);
 410 +}
 411 +
 412 +static void iproc_msi_handler(struct irq_desc *desc)
 413 +{
 414 +       struct irq_chip *chip = irq_desc_get_chip(desc);
 415 +       struct iproc_msi_grp *grp;
 416 +       struct iproc_msi *msi;
 417 +       struct iproc_pcie *pcie;
 418 +       u32 eq, head, tail, nr_events;
 419 +       unsigned long hwirq;
 420 +       int virq;
 421 +
 422 +       chained_irq_enter(chip, desc);
 423 +
 424 +       grp = irq_desc_get_handler_data(desc);
 425 +       msi = grp->msi;
 426 +       pcie = msi->pcie;
 427 +       eq = grp->eq;
 428 +
 429 +       /*
 430 +        * iProc MSI event queue is tracked by head and tail pointers.  Head
 431 +        * pointer indicates the next entry (MSI data) to be consumed by SW in
 432 +        * the queue and needs to be updated by SW.  iProc MSI core uses the
 433 +        * tail pointer as the next data insertion point.
 434 +        *
 435 +        * Entries between head and tail pointers contain valid MSI data.  MSI
 436 +        * data is guaranteed to be in the event queue memory before the tail
 437 +        * pointer is updated by the iProc MSI core.
 438 +        */
 439 +       head = iproc_msi_read_reg(msi, IPROC_MSI_EQ_HEAD,
 440 +                                 eq) & IPROC_MSI_EQ_MASK;
 441 +       do {
 442 +               tail = iproc_msi_read_reg(msi, IPROC_MSI_EQ_TAIL,
 443 +                                         eq) & IPROC_MSI_EQ_MASK;
 444 +
 445 +               /*
 446 +                * Figure out total number of events (MSI data) to be
 447 +                * processed.
 448 +                */
 449 +               nr_events = (tail < head) ?
 450 +                       (EQ_LEN - (head - tail)) : (tail - head);
 451 +               if (!nr_events)
 452 +                       break;
 453 +
 454 +               /* process all outstanding events */
 455 +               while (nr_events--) {
 456 +                       hwirq = decode_msi_hwirq(msi, eq, head);
 457 +                       virq = irq_find_mapping(msi->inner_domain, hwirq);
 458 +                       generic_handle_irq(virq);
 459 +
 460 +                       head++;
 461 +                       head %= EQ_LEN;
 462 +               }
 463 +
 464 +               /*
 465 +                * Now all outstanding events have been processed.  Update the
 466 +                * head pointer.
 467 +                */
 468 +               iproc_msi_write_reg(msi, IPROC_MSI_EQ_HEAD, eq, head);
 469 +
 470 +               /*
 471 +                * Now go read the tail pointer again to see if there are new
 472 +                * oustanding events that came in during the above window.
 473 +                */
 474 +       } while (true);
 475 +
 476 +       chained_irq_exit(chip, desc);
 477 +}
 478 +
 479 +static void iproc_msi_enable(struct iproc_msi *msi)
 480 +{
 481 +       int i, eq;
 482 +       u32 val;
 483 +
 484 +       /* Program memory region for each event queue */
 485 +       for (i = 0; i < msi->nr_eq_region; i++) {
 486 +               dma_addr_t addr = msi->eq_dma + (i * EQ_MEM_REGION_SIZE);
 487 +
 488 +               iproc_msi_write_reg(msi, IPROC_MSI_EQ_PAGE, i,
 489 +                                   lower_32_bits(addr));
 490 +               iproc_msi_write_reg(msi, IPROC_MSI_EQ_PAGE_UPPER, i,
 491 +                                   upper_32_bits(addr));
 492 +       }
 493 +
 494 +       /* Program address region for MSI posted writes */
 495 +       for (i = 0; i < msi->nr_msi_region; i++) {
 496 +               phys_addr_t addr = msi->msi_addr + (i * MSI_MEM_REGION_SIZE);
 497 +
 498 +               iproc_msi_write_reg(msi, IPROC_MSI_PAGE, i,
 499 +                                   lower_32_bits(addr));
 500 +               iproc_msi_write_reg(msi, IPROC_MSI_PAGE_UPPER, i,
 501 +                                   upper_32_bits(addr));
 502 +       }
 503 +
 504 +       for (eq = 0; eq < msi->nr_irqs; eq++) {
 505 +               /* Enable MSI event queue */
 506 +               val = IPROC_MSI_INTR_EN | IPROC_MSI_INT_N_EVENT |
 507 +                       IPROC_MSI_EQ_EN;
 508 +               iproc_msi_write_reg(msi, IPROC_MSI_CTRL, eq, val);
 509 +
 510 +               /*
 511 +                * Some legacy platforms require the MSI interrupt enable
 512 +                * register to be set explicitly.
 513 +                */
 514 +               if (msi->has_inten_reg) {
 515 +                       val = iproc_msi_read_reg(msi, IPROC_MSI_INTS_EN, eq);
 516 +                       val |= BIT(eq);
 517 +                       iproc_msi_write_reg(msi, IPROC_MSI_INTS_EN, eq, val);
 518 +               }
 519 +       }
 520 +}
 521 +
 522 +static void iproc_msi_disable(struct iproc_msi *msi)
 523 +{
 524 +       u32 eq, val;
 525 +
 526 +       for (eq = 0; eq < msi->nr_irqs; eq++) {
 527 +               if (msi->has_inten_reg) {
 528 +                       val = iproc_msi_read_reg(msi, IPROC_MSI_INTS_EN, eq);
 529 +                       val &= ~BIT(eq);
 530 +                       iproc_msi_write_reg(msi, IPROC_MSI_INTS_EN, eq, val);
 531 +               }
 532 +
 533 +               val = iproc_msi_read_reg(msi, IPROC_MSI_CTRL, eq);
 534 +               val &= ~(IPROC_MSI_INTR_EN | IPROC_MSI_INT_N_EVENT |
 535 +                        IPROC_MSI_EQ_EN);
 536 +               iproc_msi_write_reg(msi, IPROC_MSI_CTRL, eq, val);
 537 +       }
 538 +}
 539 +
 540 +static int iproc_msi_alloc_domains(struct device_node *node,
 541 +                                  struct iproc_msi *msi)
 542 +{
 543 +       msi->inner_domain = irq_domain_add_linear(NULL, msi->nr_msi_vecs,
 544 +                                                 &msi_domain_ops, msi);
 545 +       if (!msi->inner_domain)
 546 +               return -ENOMEM;
 547 +
 548 +       msi->msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(node),
 549 +                                                   &iproc_msi_domain_info,
 550 +                                                   msi->inner_domain);
 551 +       if (!msi->msi_domain) {
 552 +               irq_domain_remove(msi->inner_domain);
 553 +               return -ENOMEM;
 554 +       }
 555 +
 556 +       return 0;
 557 +}
 558 +
 559 +static void iproc_msi_free_domains(struct iproc_msi *msi)
 560 +{
 561 +       if (msi->msi_domain)
 562 +               irq_domain_remove(msi->msi_domain);
 563 +
 564 +       if (msi->inner_domain)
 565 +               irq_domain_remove(msi->inner_domain);
 566 +}
 567 +
 568 +static void iproc_msi_irq_free(struct iproc_msi *msi, unsigned int cpu)
 569 +{
 570 +       int i;
 571 +
 572 +       for (i = cpu; i < msi->nr_irqs; i += msi->nr_cpus) {
 573 +               irq_set_chained_handler_and_data(msi->grps[i].gic_irq,
 574 +                                                NULL, NULL);
 575 +       }
 576 +}
 577 +
 578 +static int iproc_msi_irq_setup(struct iproc_msi *msi, unsigned int cpu)
 579 +{
 580 +       int i, ret;
 581 +       cpumask_var_t mask;
 582 +       struct iproc_pcie *pcie = msi->pcie;
 583 +
 584 +       for (i = cpu; i < msi->nr_irqs; i += msi->nr_cpus) {
 585 +               irq_set_chained_handler_and_data(msi->grps[i].gic_irq,
 586 +                                                iproc_msi_handler,
 587 +                                                &msi->grps[i]);
 588 +               /* Dedicate GIC interrupt to each CPU core */
 589 +               if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
 590 +                       cpumask_clear(mask);
 591 +                       cpumask_set_cpu(cpu, mask);
 592 +                       ret = irq_set_affinity(msi->grps[i].gic_irq, mask);
 593 +                       if (ret)
 594 +                               dev_err(pcie->dev,
 595 +                                       "failed to set affinity for IRQ%d\n",
 596 +                                       msi->grps[i].gic_irq);
 597 +                       free_cpumask_var(mask);
 598 +               } else {
 599 +                       dev_err(pcie->dev, "failed to alloc CPU mask\n");
 600 +                       ret = -EINVAL;
 601 +               }
 602 +
 603 +               if (ret) {
 604 +                       /* Free all configured/unconfigured IRQs */
 605 +                       iproc_msi_irq_free(msi, cpu);
 606 +                       return ret;
 607 +               }
 608 +       }
 609 +
 610 +       return 0;
 611 +}
 612 +
 613 +int iproc_msi_init(struct iproc_pcie *pcie, struct device_node *node)
 614 +{
 615 +       struct iproc_msi *msi;
 616 +       int i, ret;
 617 +       unsigned int cpu;
 618 +
 619 +       if (!of_device_is_compatible(node, "brcm,iproc-msi"))
 620 +               return -ENODEV;
 621 +
 622 +       if (!of_find_property(node, "msi-controller", NULL))
 623 +               return -ENODEV;
 624 +
 625 +       if (pcie->msi)
 626 +               return -EBUSY;
 627 +
 628 +       msi = devm_kzalloc(pcie->dev, sizeof(*msi), GFP_KERNEL);
 629 +       if (!msi)
 630 +               return -ENOMEM;
 631 +
 632 +       msi->pcie = pcie;
 633 +       pcie->msi = msi;
 634 +       msi->msi_addr = pcie->base_addr;
 635 +       mutex_init(&msi->bitmap_lock);
 636 +       msi->nr_cpus = num_possible_cpus();
 637 +
 638 +       msi->nr_irqs = of_irq_count(node);
 639 +       if (!msi->nr_irqs) {
 640 +               dev_err(pcie->dev, "found no MSI GIC interrupt\n");
 641 +               return -ENODEV;
 642 +       }
 643 +
 644 +       if (msi->nr_irqs > NR_HW_IRQS) {
 645 +               dev_warn(pcie->dev, "too many MSI GIC interrupts defined %d\n",
 646 +                        msi->nr_irqs);
 647 +               msi->nr_irqs = NR_HW_IRQS;
 648 +       }
 649 +
 650 +       if (msi->nr_irqs < msi->nr_cpus) {
 651 +               dev_err(pcie->dev,
 652 +                       "not enough GIC interrupts for MSI affinity\n");
 653 +               return -EINVAL;
 654 +       }
 655 +
 656 +       if (msi->nr_irqs % msi->nr_cpus != 0) {
 657 +               msi->nr_irqs -= msi->nr_irqs % msi->nr_cpus;
 658 +               dev_warn(pcie->dev, "Reducing number of interrupts to %d\n",
 659 +                        msi->nr_irqs);
 660 +       }
 661 +
 662 +       switch (pcie->type) {
 663 +       case IPROC_PCIE_PAXB:
 664 +               msi->reg_offsets = iproc_msi_reg_paxb;
 665 +               msi->nr_eq_region = 1;
 666 +               msi->nr_msi_region = 1;
 667 +               break;
 668 +       case IPROC_PCIE_PAXC:
 669 +               msi->reg_offsets = iproc_msi_reg_paxc;
 670 +               msi->nr_eq_region = msi->nr_irqs;
 671 +               msi->nr_msi_region = msi->nr_irqs;
 672 +               break;
 673 +       default:
 674 +               dev_err(pcie->dev, "incompatible iProc PCIe interface\n");
 675 +               return -EINVAL;
 676 +       }
 677 +
 678 +       if (of_find_property(node, "brcm,pcie-msi-inten", NULL))
 679 +               msi->has_inten_reg = true;
 680 +
 681 +       msi->nr_msi_vecs = msi->nr_irqs * EQ_LEN;
 682 +       msi->bitmap = devm_kcalloc(pcie->dev, BITS_TO_LONGS(msi->nr_msi_vecs),
 683 +                                  sizeof(*msi->bitmap), GFP_KERNEL);
 684 +       if (!msi->bitmap)
 685 +               return -ENOMEM;
 686 +
 687 +       msi->grps = devm_kcalloc(pcie->dev, msi->nr_irqs, sizeof(*msi->grps),
 688 +                                GFP_KERNEL);
 689 +       if (!msi->grps)
 690 +               return -ENOMEM;
 691 +
 692 +       for (i = 0; i < msi->nr_irqs; i++) {
 693 +               unsigned int irq = irq_of_parse_and_map(node, i);
 694 +
 695 +               if (!irq) {
 696 +                       dev_err(pcie->dev, "unable to parse/map interrupt\n");
 697 +                       ret = -ENODEV;
 698 +                       goto free_irqs;
 699 +               }
 700 +               msi->grps[i].gic_irq = irq;
 701 +               msi->grps[i].msi = msi;
 702 +               msi->grps[i].eq = i;
 703 +       }
 704 +
 705 +       /* Reserve memory for event queue and make sure memories are zeroed */
 706 +       msi->eq_cpu = dma_zalloc_coherent(pcie->dev,
 707 +                                         msi->nr_eq_region * EQ_MEM_REGION_SIZE,
 708 +                                         &msi->eq_dma, GFP_KERNEL);
 709 +       if (!msi->eq_cpu) {
 710 +               ret = -ENOMEM;
 711 +               goto free_irqs;
 712 +       }
 713 +
 714 +       ret = iproc_msi_alloc_domains(node, msi);
 715 +       if (ret) {
 716 +               dev_err(pcie->dev, "failed to create MSI domains\n");
 717 +               goto free_eq_dma;
 718 +       }
 719 +
 720 +       for_each_online_cpu(cpu) {
 721 +               ret = iproc_msi_irq_setup(msi, cpu);
 722 +               if (ret)
 723 +                       goto free_msi_irq;
 724 +       }
 725 +
 726 +       iproc_msi_enable(msi);
 727 +
 728 +       return 0;
 729 +
 730 +free_msi_irq:
 731 +       for_each_online_cpu(cpu)
 732 +               iproc_msi_irq_free(msi, cpu);
 733 +       iproc_msi_free_domains(msi);
 734 +
 735 +free_eq_dma:
 736 +       dma_free_coherent(pcie->dev, msi->nr_eq_region * EQ_MEM_REGION_SIZE,
 737 +                         msi->eq_cpu, msi->eq_dma);
 738 +
 739 +free_irqs:
 740 +       for (i = 0; i < msi->nr_irqs; i++) {
 741 +               if (msi->grps[i].gic_irq)
 742 +                       irq_dispose_mapping(msi->grps[i].gic_irq);
 743 +       }
 744 +       pcie->msi = NULL;
 745 +       return ret;
 746 +}
 747 +EXPORT_SYMBOL(iproc_msi_init);
 748 +
 749 +void iproc_msi_exit(struct iproc_pcie *pcie)
 750 +{
 751 +       struct iproc_msi *msi = pcie->msi;
 752 +       unsigned int i, cpu;
 753 +
 754 +       if (!msi)
 755 +               return;
 756 +
 757 +       iproc_msi_disable(msi);
 758 +
 759 +       for_each_online_cpu(cpu)
 760 +               iproc_msi_irq_free(msi, cpu);
 761 +
 762 +       iproc_msi_free_domains(msi);
 763 +
 764 +       dma_free_coherent(pcie->dev, msi->nr_eq_region * EQ_MEM_REGION_SIZE,
 765 +                         msi->eq_cpu, msi->eq_dma);
 766 +
 767 +       for (i = 0; i < msi->nr_irqs; i++) {
 768 +               if (msi->grps[i].gic_irq)
 769 +                       irq_dispose_mapping(msi->grps[i].gic_irq);
 770 +       }
 771 +}
 772 +EXPORT_SYMBOL(iproc_msi_exit);
 773 --- a/drivers/pci/host/pcie-iproc-platform.c
 774 +++ b/drivers/pci/host/pcie-iproc-platform.c
 775 @@ -71,6 +71,7 @@ static int iproc_pcie_pltfm_probe(struct
 776                 dev_err(pcie->dev, "unable to map controller registers\n");
 777                 return -ENOMEM;
 778         }
 779 +       pcie->base_addr = reg.start;
 780
 781         if (of_property_read_bool(np, "brcm,pcie-ob")) {
 782                 u32 val;
 783 --- a/drivers/pci/host/pcie-iproc.c
 784 +++ b/drivers/pci/host/pcie-iproc.c
 785 @@ -440,6 +440,26 @@ static int iproc_pcie_map_ranges(struct
 786         return 0;
 787  }
 788
 789 +static int iproc_pcie_msi_enable(struct iproc_pcie *pcie)
 790 +{
 791 +       struct device_node *msi_node;
 792 +
 793 +       msi_node = of_parse_phandle(pcie->dev->of_node, "msi-parent", 0);
 794 +       if (!msi_node)
 795 +               return -ENODEV;
 796 +
 797 +       /*
 798 +        * If another MSI controller is being used, the call below should fail
 799 +        * but that is okay
 800 +        */
 801 +       return iproc_msi_init(pcie, msi_node);
 802 +}
 803 +
 804 +static void iproc_pcie_msi_disable(struct iproc_pcie *pcie)
 805 +{
 806 +       iproc_msi_exit(pcie);
 807 +}
 808 +
 809  int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res)
 810  {
 811         int ret;
 812 @@ -507,6 +527,10 @@ int iproc_pcie_setup(struct iproc_pcie *
 813
 814         iproc_pcie_enable(pcie);
 815
 816 +       if (IS_ENABLED(CONFIG_PCI_MSI))
 817 +               if (iproc_pcie_msi_enable(pcie))
 818 +                       dev_info(pcie->dev, "not using iProc MSI\n");
 819 +
 820         pci_scan_child_bus(bus);
 821         pci_assign_unassigned_bus_resources(bus);
 822         pci_fixup_irqs(pci_common_swizzle, pcie->map_irq);
 823 @@ -531,6 +555,8 @@ int iproc_pcie_remove(struct iproc_pcie
 824         pci_stop_root_bus(pcie->root_bus);
 825         pci_remove_root_bus(pcie->root_bus);
 826
 827 +       iproc_pcie_msi_disable(pcie);
 828 +
 829         phy_power_off(pcie->phy);
 830         phy_exit(pcie->phy);
 831
 832 --- a/drivers/pci/host/pcie-iproc.h
 833 +++ b/drivers/pci/host/pcie-iproc.h
 834 @@ -41,6 +41,8 @@ struct iproc_pcie_ob {
 835         resource_size_t window_size;
 836  };
 837
 838 +struct iproc_msi;
 839 +
 840  /**
 841   * iProc PCIe device
 842   *
 843 @@ -48,19 +50,21 @@ struct iproc_pcie_ob {
 844   * @type: iProc PCIe interface type
 845   * @reg_offsets: register offsets
 846   * @base: PCIe host controller I/O register base
 847 + * @base_addr: PCIe host controller register base physical address
 848   * @sysdata: Per PCI controller data (ARM-specific)
 849   * @root_bus: pointer to root bus
 850   * @phy: optional PHY device that controls the Serdes
 851 - * @irqs: interrupt IDs
 852   * @map_irq: function callback to map interrupts
 853 - * @need_ob_cfg: indidates SW needs to configure the outbound mapping window
 854 + * @need_ob_cfg: indicates SW needs to configure the outbound mapping window
 855   * @ob: outbound mapping parameters
 856 + * @msi: MSI data
 857   */
 858  struct iproc_pcie {
 859         struct device *dev;
 860         enum iproc_pcie_type type;
 861         const u16 *reg_offsets;
 862         void __iomem *base;
 863 +       phys_addr_t base_addr;
 864  #ifdef CONFIG_ARM
 865         struct pci_sys_data sysdata;
 866  #endif
 867 @@ -69,9 +73,24 @@ struct iproc_pcie {
 868         int (*map_irq)(const struct pci_dev *, u8, u8);
 869         bool need_ob_cfg;
 870         struct iproc_pcie_ob ob;
 871 +       struct iproc_msi *msi;
 872  };
 873
 874  int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res);
 875  int iproc_pcie_remove(struct iproc_pcie *pcie);
 876
 877 +#ifdef CONFIG_PCIE_IPROC_MSI
 878 +int iproc_msi_init(struct iproc_pcie *pcie, struct device_node *node);
 879 +void iproc_msi_exit(struct iproc_pcie *pcie);
 880 +#else
 881 +static inline int iproc_msi_init(struct iproc_pcie *pcie,
 882 +                                struct device_node *node)
 883 +{
 884 +       return -ENODEV;
 885 +}
 886 +static inline void iproc_msi_exit(struct iproc_pcie *pcie)
 887 +{
 888 +}
 889 +#endif
 890 +
 891  #endif /* _PCIE_IPROC_H */