target/linux/bmips/patches-5.15/200-mips-bmips-automatically-detect-CPU-frequency.patch

   1 From 0377ad93031d3e51c2afe44231241185f684b6af Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
   3 Date: Fri, 5 Mar 2021 15:14:32 +0100
   4 Subject: [PATCH 1/2] mips: bmips: automatically detect CPU frequency
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 Some BCM63xx SoCs support multiple CPU frequencies depending on HW config.
  10
  11 Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
  12 ---
  13  arch/mips/bmips/setup.c | 198 ++++++++++++++++++++++++++++++++++++++--
  14  1 file changed, 191 insertions(+), 7 deletions(-)
  15
  16 --- a/arch/mips/bmips/setup.c
  17 +++ b/arch/mips/bmips/setup.c
  18 @@ -31,13 +31,52 @@
  19
  20  #define RELO_NORMAL_VEC                BIT(18)
  21
  22 +#define REG_BCM6318_SOB                ((void __iomem *)CKSEG1ADDR(0x10000900))
  23 +#define BCM6318_FREQ_SHIFT     23
  24 +#define BCM6318_FREQ_MASK      (0x3 << BCM6318_FREQ_SHIFT)
  25 +
  26  #define REG_BCM6328_OTP                ((void __iomem *)CKSEG1ADDR(0x1000062c))
  27  #define BCM6328_TP1_DISABLED   BIT(9)
  28 +#define REG_BCM6328_MISC_SB    ((void __iomem *)CKSEG1ADDR(0x10001a40))
  29 +#define BCM6328_FCVO_SHIFT     7
  30 +#define BCM6328_FCVO_MASK      (0x1f << BCM6328_FCVO_SHIFT)
  31 +
  32 +#define REG_BCM6358_DDR_PLLC   ((void __iomem *)0xfffe12b8)
  33 +#define BCM6358_PLLC_M1_SHIFT  0
  34 +#define BCM6358_PLLC_M1_MASK   (0xff << BCM6358_PLLC_M1_SHIFT)
  35 +#define BCM6358_PLLC_N1_SHIFT  23
  36 +#define BCM6358_PLLC_N1_MASK   (0x3f << BCM6358_PLLC_N1_SHIFT)
  37 +#define BCM6358_PLLC_N2_SHIFT  29
  38 +#define BCM6358_PLLC_N2_MASK   (0x7 << BCM6358_PLLC_N2_SHIFT)
  39 +
  40 +#define REG_BCM6362_MISC_SB    ((void __iomem *)CKSEG1ADDR(0x10001814))
  41 +#define BCM6362_FCVO_SHIFT     1
  42 +#define BCM6362_FCVO_MASK      (0x1f << BCM6362_FCVO_SHIFT)
  43 +
  44 +#define REG_BCM6368_DDR_PLLC   ((void __iomem *)CKSEG1ADDR(0x100012a0))
  45 +#define BCM6368_PLLC_P1_SHIFT  0
  46 +#define BCM6368_PLLC_P1_MASK   (0xf << BCM6368_PLLC_P1_SHIFT)
  47 +#define BCM6368_PLLC_P2_SHIFT  4
  48 +#define BCM6368_PLLC_P2_MASK   (0xf << BCM6368_PLLC_P2_SHIFT)
  49 +#define BCM6368_PLLC_NDIV_SHIFT        16
  50 +#define BCM6368_PLLC_NDIV_MASK (0x1ff << BCM6368_PLLC_NDIV_SHIFT)
  51 +#define REG_BCM6368_DDR_PLLD   ((void __iomem *)CKSEG1ADDR(0x100012a4))
  52 +#define BCM6368_PLLD_MDIV_SHIFT        0
  53 +#define BCM6368_PLLD_MDIV_MASK (0xff << BCM6368_PLLD_MDIV_SHIFT)
  54 +
  55 +#define REG_BCM63268_MISC_SB   ((void __iomem *)CKSEG1ADDR(0x10001814))
  56 +#define BCM63268_FCVO_SHIFT    21
  57 +#define BCM63268_FCVO_MASK     (0xf << BCM63268_FCVO_SHIFT)
  58
  59  extern bool bmips_rac_flush_disable;
  60
  61  static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000;
  62
  63 +struct bmips_cpufreq {
  64 +       const char              *compatible;
  65 +       u32                     (*cpu_freq)(void);
  66 +};
  67 +
  68  struct bmips_quirk {
  69         const char              *compatible;
  70         void                    (*quirk_fn)(void);
  71 @@ -142,17 +181,161 @@ const char *get_system_type(void)
  72         return "Generic BMIPS kernel";
  73  }
  74
  75 +static u32 bcm6318_cpufreq(void)
  76 +{
  77 +       u32 val = __raw_readl(REG_BCM6318_SOB);
  78 +
  79 +       switch ((val & BCM6318_FREQ_MASK) >> BCM6318_FREQ_SHIFT) {
  80 +       case 0:
  81 +               return 166000000;
  82 +       case 2:
  83 +               return 250000000;
  84 +       case 3:
  85 +               return 333000000;
  86 +       case 1:
  87 +               return 400000000;
  88 +       default:
  89 +               return 0;
  90 +       }
  91 +}
  92 +
  93 +static u32 bcm6328_cpufreq(void)
  94 +{
  95 +       u32 val = __raw_readl(REG_BCM6328_MISC_SB);
  96 +
  97 +       switch ((val & BCM6328_FCVO_MASK) >> BCM6328_FCVO_SHIFT) {
  98 +       case 0x12:
  99 +       case 0x14:
 100 +       case 0x19:
 101 +               return 160000000;
 102 +       case 0x1c:
 103 +               return 192000000;
 104 +       case 0x13:
 105 +       case 0x15:
 106 +               return 200000000;
 107 +       case 0x1a:
 108 +               return 384000000;
 109 +       case 0x16:
 110 +               return 400000000;
 111 +       default:
 112 +               return 320000000;
 113 +       }
 114 +}
 115 +
 116 +static u32 bcm6358_cpufreq(void)
 117 +{
 118 +       u32 val, n1, n2, m1;
 119 +
 120 +       val = __raw_readl(REG_BCM6358_DDR_PLLC);
 121 +       n1 = (val & BCM6358_PLLC_N1_MASK) >> BCM6358_PLLC_N1_SHIFT;
 122 +       n2 = (val & BCM6358_PLLC_N2_MASK) >> BCM6358_PLLC_N2_SHIFT;
 123 +       m1 = (val & BCM6358_PLLC_M1_MASK) >> BCM6358_PLLC_M1_SHIFT;
 124 +
 125 +       return (16 * 1000000 * n1 * n2) / m1;
 126 +}
 127 +
 128 +static u32 bcm6362_cpufreq(void)
 129 +{
 130 +       u32 val = __raw_readl(REG_BCM6362_MISC_SB);
 131 +
 132 +       switch ((val & BCM6362_FCVO_MASK) >> BCM6362_FCVO_SHIFT) {
 133 +       case 0x04:
 134 +       case 0x0c:
 135 +       case 0x14:
 136 +       case 0x1c:
 137 +               return 160000000;
 138 +       case 0x15:
 139 +       case 0x1d:
 140 +               return 200000000;
 141 +       case 0x03:
 142 +       case 0x0b:
 143 +       case 0x13:
 144 +       case 0x1b:
 145 +               return 240000000;
 146 +       case 0x07:
 147 +       case 0x17:
 148 +               return 384000000;
 149 +       case 0x05:
 150 +       case 0x0e:
 151 +       case 0x16:
 152 +       case 0x1e:
 153 +       case 0x1f:
 154 +               return 400000000;
 155 +       case 0x06:
 156 +               return 440000000;
 157 +       default:
 158 +               return 320000000;
 159 +       }
 160 +}
 161 +
 162 +static u32 bcm6368_cpufreq(void)
 163 +{
 164 +       u32 val, p1, p2, ndiv, m1;
 165 +
 166 +       val = __raw_readl(REG_BCM6368_DDR_PLLC);
 167 +       p1 = (val & BCM6368_PLLC_P1_MASK) >> BCM6368_PLLC_P1_SHIFT;
 168 +       p2 = (val & BCM6368_PLLC_P2_MASK) >> BCM6368_PLLC_P2_SHIFT;
 169 +       ndiv = (val & BCM6368_PLLC_NDIV_MASK) >>
 170 +              BCM6368_PLLC_NDIV_SHIFT;
 171 +
 172 +       val = __raw_readl(REG_BCM6368_DDR_PLLD);
 173 +       m1 = (val & BCM6368_PLLD_MDIV_MASK) >> BCM6368_PLLD_MDIV_SHIFT;
 174 +
 175 +       return (((64 * 1000000) / p1) * p2 * ndiv) / m1;
 176 +}
 177 +
 178 +static u32 bcm63268_cpufreq(void)
 179 +{
 180 +       u32 val = __raw_readl(REG_BCM63268_MISC_SB);
 181 +
 182 +       switch ((val & BCM63268_FCVO_MASK) >> BCM63268_FCVO_SHIFT) {
 183 +       case 0x3:
 184 +       case 0xe:
 185 +               return 320000000;
 186 +       case 0xa:
 187 +               return 333000000;
 188 +       case 0x2:
 189 +       case 0xb:
 190 +       case 0xf:
 191 +               return 400000000;
 192 +       default:
 193 +               return 0;
 194 +       }
 195 +}
 196 +
 197 +static const struct bmips_cpufreq bmips_cpufreq_list[] = {
 198 +       { "brcm,bcm6318", &bcm6318_cpufreq },
 199 +       { "brcm,bcm6328", &bcm6328_cpufreq },
 200 +       { "brcm,bcm6358", &bcm6358_cpufreq },
 201 +       { "brcm,bcm6362", &bcm6362_cpufreq },
 202 +       { "brcm,bcm6368", &bcm6368_cpufreq },
 203 +       { "brcm,bcm63268", &bcm63268_cpufreq },
 204 +       { /* sentinel */ }
 205 +};
 206 +
 207  void __init plat_time_init(void)
 208  {
 209 +       const struct bmips_cpufreq *cf;
 210         struct device_node *np;
 211 -       u32 freq;
 212 +       u32 freq = 0;
 213
 214 -       np = of_find_node_by_name(NULL, "cpus");
 215 -       if (!np)
 216 -               panic("missing 'cpus' DT node");
 217 -       if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0)
 218 -               panic("missing 'mips-hpt-frequency' property");
 219 -       of_node_put(np);
 220 +       for (cf = bmips_cpufreq_list; cf->cpu_freq; cf++) {
 221 +               if (of_flat_dt_is_compatible(of_get_flat_dt_root(),
 222 +                                            cf->compatible)) {
 223 +                       freq = cf->cpu_freq() / 2;
 224 +                       printk("%s detected @ %u MHz\n", cf->compatible, freq / 500000);
 225 +                       break;
 226 +               }
 227 +       }
 228 +
 229 +       if (!freq) {
 230 +               np = of_find_node_by_name(NULL, "cpus");
 231 +               if (!np)
 232 +                       panic("missing 'cpus' DT node");
 233 +               if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0)
 234 +                       panic("missing 'mips-hpt-frequency' property");
 235 +               of_node_put(np);
 236 +       }
 237
 238         mips_hpt_frequency = freq;
 239  }