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[openwrt/openwrt.git] / target / linux / brcm2708 / patches-3.14 / 0001-Main-bcm2708-linux-port.patch
1 From fa45905bb2c22c8a349d30f00d9daa301fb1f2ab Mon Sep 17 00:00:00 2001
2 From: popcornmix <popcornmix@gmail.com>
3 Date: Sun, 12 May 2013 12:24:19 +0100
4 Subject: [PATCH 01/54] Main bcm2708 linux port
5
6 Signed-off-by: popcornmix <popcornmix@gmail.com>
7 ---
8 arch/arm/Kconfig | 17 +
9 arch/arm/Kconfig.debug | 8 +
10 arch/arm/Makefile | 1 +
11 arch/arm/configs/bcmrpi_cutdown_defconfig | 474 +++++++
12 arch/arm/configs/bcmrpi_defconfig | 510 ++++++++
13 arch/arm/configs/bcmrpi_emergency_defconfig | 532 ++++++++
14 arch/arm/kernel/process.c | 10 +
15 arch/arm/mach-bcm2708/Kconfig | 34 +
16 arch/arm/mach-bcm2708/Makefile | 7 +
17 arch/arm/mach-bcm2708/Makefile.boot | 3 +
18 arch/arm/mach-bcm2708/armctrl.c | 208 ++++
19 arch/arm/mach-bcm2708/armctrl.h | 27 +
20 arch/arm/mach-bcm2708/bcm2708.c | 720 +++++++++++
21 arch/arm/mach-bcm2708/bcm2708.h | 49 +
22 arch/arm/mach-bcm2708/bcm2708_gpio.c | 361 ++++++
23 arch/arm/mach-bcm2708/clock.c | 61 +
24 arch/arm/mach-bcm2708/clock.h | 24 +
25 arch/arm/mach-bcm2708/dma.c | 399 ++++++
26 arch/arm/mach-bcm2708/include/mach/arm_control.h | 419 +++++++
27 arch/arm/mach-bcm2708/include/mach/arm_power.h | 60 +
28 arch/arm/mach-bcm2708/include/mach/clkdev.h | 7 +
29 arch/arm/mach-bcm2708/include/mach/debug-macro.S | 22 +
30 arch/arm/mach-bcm2708/include/mach/dma.h | 86 ++
31 arch/arm/mach-bcm2708/include/mach/entry-macro.S | 69 ++
32 arch/arm/mach-bcm2708/include/mach/frc.h | 38 +
33 arch/arm/mach-bcm2708/include/mach/gpio.h | 17 +
34 arch/arm/mach-bcm2708/include/mach/hardware.h | 28 +
35 arch/arm/mach-bcm2708/include/mach/io.h | 27 +
36 arch/arm/mach-bcm2708/include/mach/irqs.h | 194 +++
37 arch/arm/mach-bcm2708/include/mach/memory.h | 57 +
38 arch/arm/mach-bcm2708/include/mach/platform.h | 220 ++++
39 arch/arm/mach-bcm2708/include/mach/power.h | 26 +
40 arch/arm/mach-bcm2708/include/mach/system.h | 38 +
41 arch/arm/mach-bcm2708/include/mach/timex.h | 23 +
42 arch/arm/mach-bcm2708/include/mach/uncompress.h | 84 ++
43 arch/arm/mach-bcm2708/include/mach/vc_mem.h | 35 +
44 arch/arm/mach-bcm2708/include/mach/vcio.h | 141 +++
45 arch/arm/mach-bcm2708/include/mach/vmalloc.h | 20 +
46 arch/arm/mach-bcm2708/power.c | 194 +++
47 arch/arm/mach-bcm2708/vc_mem.c | 432 +++++++
48 arch/arm/mach-bcm2708/vcio.c | 474 +++++++
49 arch/arm/mm/Kconfig | 2 +-
50 arch/arm/mm/proc-v6.S | 15 +-
51 arch/arm/tools/mach-types | 1 +
52 drivers/mmc/host/Kconfig | 21 +
53 drivers/mmc/host/Makefile | 1 +
54 drivers/mmc/host/sdhci-bcm2708.c | 1424 ++++++++++++++++++++++
55 drivers/mmc/host/sdhci.c | 203 ++-
56 drivers/mmc/host/sdhci.h | 37 +
57 drivers/tty/serial/amba-pl011.c | 2 +-
58 include/linux/mmc/sdhci.h | 2 +
59 51 files changed, 7792 insertions(+), 72 deletions(-)
60 create mode 100644 arch/arm/configs/bcmrpi_cutdown_defconfig
61 create mode 100644 arch/arm/configs/bcmrpi_defconfig
62 create mode 100644 arch/arm/configs/bcmrpi_emergency_defconfig
63 create mode 100644 arch/arm/mach-bcm2708/Kconfig
64 create mode 100644 arch/arm/mach-bcm2708/Makefile
65 create mode 100644 arch/arm/mach-bcm2708/Makefile.boot
66 create mode 100644 arch/arm/mach-bcm2708/armctrl.c
67 create mode 100644 arch/arm/mach-bcm2708/armctrl.h
68 create mode 100644 arch/arm/mach-bcm2708/bcm2708.c
69 create mode 100644 arch/arm/mach-bcm2708/bcm2708.h
70 create mode 100644 arch/arm/mach-bcm2708/bcm2708_gpio.c
71 create mode 100644 arch/arm/mach-bcm2708/clock.c
72 create mode 100644 arch/arm/mach-bcm2708/clock.h
73 create mode 100644 arch/arm/mach-bcm2708/dma.c
74 create mode 100644 arch/arm/mach-bcm2708/include/mach/arm_control.h
75 create mode 100644 arch/arm/mach-bcm2708/include/mach/arm_power.h
76 create mode 100644 arch/arm/mach-bcm2708/include/mach/clkdev.h
77 create mode 100644 arch/arm/mach-bcm2708/include/mach/debug-macro.S
78 create mode 100644 arch/arm/mach-bcm2708/include/mach/dma.h
79 create mode 100644 arch/arm/mach-bcm2708/include/mach/entry-macro.S
80 create mode 100644 arch/arm/mach-bcm2708/include/mach/frc.h
81 create mode 100644 arch/arm/mach-bcm2708/include/mach/gpio.h
82 create mode 100644 arch/arm/mach-bcm2708/include/mach/hardware.h
83 create mode 100644 arch/arm/mach-bcm2708/include/mach/io.h
84 create mode 100644 arch/arm/mach-bcm2708/include/mach/irqs.h
85 create mode 100644 arch/arm/mach-bcm2708/include/mach/memory.h
86 create mode 100644 arch/arm/mach-bcm2708/include/mach/platform.h
87 create mode 100644 arch/arm/mach-bcm2708/include/mach/power.h
88 create mode 100644 arch/arm/mach-bcm2708/include/mach/system.h
89 create mode 100644 arch/arm/mach-bcm2708/include/mach/timex.h
90 create mode 100644 arch/arm/mach-bcm2708/include/mach/uncompress.h
91 create mode 100644 arch/arm/mach-bcm2708/include/mach/vc_mem.h
92 create mode 100644 arch/arm/mach-bcm2708/include/mach/vcio.h
93 create mode 100644 arch/arm/mach-bcm2708/include/mach/vmalloc.h
94 create mode 100644 arch/arm/mach-bcm2708/power.c
95 create mode 100644 arch/arm/mach-bcm2708/vc_mem.c
96 create mode 100644 arch/arm/mach-bcm2708/vcio.c
97 create mode 100644 drivers/mmc/host/sdhci-bcm2708.c
98
99 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
100 index 4733d32..9e23417 100644
101 --- a/arch/arm/Kconfig
102 +++ b/arch/arm/Kconfig
103 @@ -380,6 +380,22 @@ config ARCH_AT91
104 This enables support for systems based on Atmel
105 AT91RM9200 and AT91SAM9* processors.
106
107 +config ARCH_BCM2708
108 + bool "Broadcom BCM2708 family"
109 + select CPU_V6
110 + select ARM_AMBA
111 + select HAVE_CLK
112 + select HAVE_SCHED_CLOCK
113 + select NEED_MACH_GPIO_H
114 + select NEED_MACH_MEMORY_H
115 + select CLKDEV_LOOKUP
116 + select GENERIC_CLOCKEVENTS
117 + select ARM_ERRATA_411920
118 + select MACH_BCM2708
119 + select VC4
120 + help
121 + This enables support for Broadcom BCM2708 boards.
122 +
123 config ARCH_CLPS711X
124 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
125 select ARCH_REQUIRE_GPIOLIB
126 @@ -1054,6 +1070,7 @@ source "arch/arm/mach-virt/Kconfig"
127 source "arch/arm/mach-vt8500/Kconfig"
128
129 source "arch/arm/mach-w90x900/Kconfig"
130 +source "arch/arm/mach-bcm2708/Kconfig"
131
132 source "arch/arm/mach-zynq/Kconfig"
133
134 diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
135 index 0531da8..117fb79 100644
136 --- a/arch/arm/Kconfig.debug
137 +++ b/arch/arm/Kconfig.debug
138 @@ -920,6 +920,14 @@ choice
139 options; the platform specific options are deprecated
140 and will be soon removed.
141
142 + config DEBUG_BCM2708_UART0
143 + bool "Broadcom BCM2708 UART0 (PL011)"
144 + depends on MACH_BCM2708
145 + help
146 + Say Y here if you want the debug print routines to direct
147 + their output to UART 0. The port must have been initialised
148 + by the boot-loader before use.
149 +
150 endchoice
151
152 config DEBUG_EXYNOS_UART
153 diff --git a/arch/arm/Makefile b/arch/arm/Makefile
154 index 08a9ef5..755e9c2 100644
155 --- a/arch/arm/Makefile
156 +++ b/arch/arm/Makefile
157 @@ -143,6 +143,7 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
158 # by CONFIG_* macro name.
159 machine-$(CONFIG_ARCH_AT91) += at91
160 machine-$(CONFIG_ARCH_BCM) += bcm
161 +machine-$(CONFIG_ARCH_BCM2708) += bcm2708
162 machine-$(CONFIG_ARCH_BCM2835) += bcm2835
163 machine-$(CONFIG_ARCH_BERLIN) += berlin
164 machine-$(CONFIG_ARCH_CLPS711X) += clps711x
165 diff --git a/arch/arm/configs/bcmrpi_cutdown_defconfig b/arch/arm/configs/bcmrpi_cutdown_defconfig
166 new file mode 100644
167 index 0000000..74f2dc9
168 --- /dev/null
169 +++ b/arch/arm/configs/bcmrpi_cutdown_defconfig
170 @@ -0,0 +1,474 @@
171 +CONFIG_EXPERIMENTAL=y
172 +# CONFIG_LOCALVERSION_AUTO is not set
173 +CONFIG_SYSVIPC=y
174 +CONFIG_POSIX_MQUEUE=y
175 +CONFIG_IKCONFIG=y
176 +CONFIG_IKCONFIG_PROC=y
177 +# CONFIG_UID16 is not set
178 +# CONFIG_KALLSYMS is not set
179 +CONFIG_EMBEDDED=y
180 +# CONFIG_VM_EVENT_COUNTERS is not set
181 +# CONFIG_COMPAT_BRK is not set
182 +CONFIG_SLAB=y
183 +CONFIG_MODULES=y
184 +CONFIG_MODULE_UNLOAD=y
185 +CONFIG_MODVERSIONS=y
186 +CONFIG_MODULE_SRCVERSION_ALL=y
187 +# CONFIG_BLK_DEV_BSG is not set
188 +CONFIG_ARCH_BCM2708=y
189 +CONFIG_NO_HZ=y
190 +CONFIG_HIGH_RES_TIMERS=y
191 +CONFIG_AEABI=y
192 +CONFIG_ZBOOT_ROM_TEXT=0x0
193 +CONFIG_ZBOOT_ROM_BSS=0x0
194 +CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait"
195 +CONFIG_CPU_IDLE=y
196 +CONFIG_VFP=y
197 +CONFIG_BINFMT_MISC=m
198 +CONFIG_NET=y
199 +CONFIG_PACKET=y
200 +CONFIG_UNIX=y
201 +CONFIG_XFRM_USER=y
202 +CONFIG_NET_KEY=m
203 +CONFIG_INET=y
204 +CONFIG_IP_MULTICAST=y
205 +CONFIG_IP_PNP=y
206 +CONFIG_IP_PNP_DHCP=y
207 +CONFIG_IP_PNP_RARP=y
208 +CONFIG_SYN_COOKIES=y
209 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
210 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
211 +# CONFIG_INET_XFRM_MODE_BEET is not set
212 +# CONFIG_INET_LRO is not set
213 +# CONFIG_INET_DIAG is not set
214 +# CONFIG_IPV6 is not set
215 +CONFIG_NET_PKTGEN=m
216 +CONFIG_IRDA=m
217 +CONFIG_IRLAN=m
218 +CONFIG_IRCOMM=m
219 +CONFIG_IRDA_ULTRA=y
220 +CONFIG_IRDA_CACHE_LAST_LSAP=y
221 +CONFIG_IRDA_FAST_RR=y
222 +CONFIG_IRTTY_SIR=m
223 +CONFIG_KINGSUN_DONGLE=m
224 +CONFIG_KSDAZZLE_DONGLE=m
225 +CONFIG_KS959_DONGLE=m
226 +CONFIG_USB_IRDA=m
227 +CONFIG_SIGMATEL_FIR=m
228 +CONFIG_MCS_FIR=m
229 +CONFIG_BT=m
230 +CONFIG_BT_L2CAP=y
231 +CONFIG_BT_SCO=y
232 +CONFIG_BT_RFCOMM=m
233 +CONFIG_BT_RFCOMM_TTY=y
234 +CONFIG_BT_BNEP=m
235 +CONFIG_BT_BNEP_MC_FILTER=y
236 +CONFIG_BT_BNEP_PROTO_FILTER=y
237 +CONFIG_BT_HIDP=m
238 +CONFIG_BT_HCIBTUSB=m
239 +CONFIG_BT_HCIBCM203X=m
240 +CONFIG_BT_HCIBPA10X=m
241 +CONFIG_BT_HCIBFUSB=m
242 +CONFIG_BT_HCIVHCI=m
243 +CONFIG_BT_MRVL=m
244 +CONFIG_BT_MRVL_SDIO=m
245 +CONFIG_BT_ATH3K=m
246 +CONFIG_CFG80211=m
247 +CONFIG_MAC80211=m
248 +CONFIG_MAC80211_RC_PID=y
249 +CONFIG_MAC80211_MESH=y
250 +CONFIG_WIMAX=m
251 +CONFIG_NET_9P=m
252 +CONFIG_NFC=m
253 +CONFIG_NFC_PN533=m
254 +CONFIG_DEVTMPFS=y
255 +CONFIG_BLK_DEV_LOOP=y
256 +CONFIG_BLK_DEV_CRYPTOLOOP=m
257 +CONFIG_BLK_DEV_NBD=m
258 +CONFIG_BLK_DEV_RAM=y
259 +CONFIG_CDROM_PKTCDVD=m
260 +CONFIG_MISC_DEVICES=y
261 +CONFIG_SCSI=y
262 +# CONFIG_SCSI_PROC_FS is not set
263 +CONFIG_BLK_DEV_SD=m
264 +CONFIG_BLK_DEV_SR=m
265 +CONFIG_SCSI_MULTI_LUN=y
266 +# CONFIG_SCSI_LOWLEVEL is not set
267 +CONFIG_NETDEVICES=y
268 +CONFIG_TUN=m
269 +CONFIG_PHYLIB=m
270 +CONFIG_MDIO_BITBANG=m
271 +CONFIG_NET_ETHERNET=y
272 +# CONFIG_NETDEV_1000 is not set
273 +# CONFIG_NETDEV_10000 is not set
274 +CONFIG_LIBERTAS_THINFIRM=m
275 +CONFIG_LIBERTAS_THINFIRM_USB=m
276 +CONFIG_AT76C50X_USB=m
277 +CONFIG_USB_ZD1201=m
278 +CONFIG_USB_NET_RNDIS_WLAN=m
279 +CONFIG_RTL8187=m
280 +CONFIG_MAC80211_HWSIM=m
281 +CONFIG_ATH_COMMON=m
282 +CONFIG_ATH9K=m
283 +CONFIG_ATH9K_HTC=m
284 +CONFIG_CARL9170=m
285 +CONFIG_B43=m
286 +CONFIG_B43LEGACY=m
287 +CONFIG_HOSTAP=m
288 +CONFIG_IWM=m
289 +CONFIG_LIBERTAS=m
290 +CONFIG_LIBERTAS_USB=m
291 +CONFIG_LIBERTAS_SDIO=m
292 +CONFIG_P54_COMMON=m
293 +CONFIG_P54_USB=m
294 +CONFIG_RT2X00=m
295 +CONFIG_RT2500USB=m
296 +CONFIG_RT73USB=m
297 +CONFIG_RT2800USB=m
298 +CONFIG_RT2800USB_RT53XX=y
299 +CONFIG_RTL8192CU=m
300 +CONFIG_WL1251=m
301 +CONFIG_WL12XX_MENU=m
302 +CONFIG_ZD1211RW=m
303 +CONFIG_MWIFIEX=m
304 +CONFIG_MWIFIEX_SDIO=m
305 +CONFIG_WIMAX_I2400M_USB=m
306 +CONFIG_USB_CATC=m
307 +CONFIG_USB_KAWETH=m
308 +CONFIG_USB_PEGASUS=m
309 +CONFIG_USB_RTL8150=m
310 +CONFIG_USB_USBNET=y
311 +CONFIG_USB_NET_AX8817X=m
312 +CONFIG_USB_NET_CDCETHER=m
313 +CONFIG_USB_NET_CDC_EEM=m
314 +CONFIG_USB_NET_DM9601=m
315 +CONFIG_USB_NET_SMSC75XX=m
316 +CONFIG_USB_NET_SMSC95XX=y
317 +CONFIG_USB_NET_GL620A=m
318 +CONFIG_USB_NET_NET1080=m
319 +CONFIG_USB_NET_PLUSB=m
320 +CONFIG_USB_NET_MCS7830=m
321 +CONFIG_USB_NET_CDC_SUBSET=m
322 +CONFIG_USB_ALI_M5632=y
323 +CONFIG_USB_AN2720=y
324 +CONFIG_USB_KC2190=y
325 +# CONFIG_USB_NET_ZAURUS is not set
326 +CONFIG_USB_NET_CX82310_ETH=m
327 +CONFIG_USB_NET_KALMIA=m
328 +CONFIG_USB_NET_INT51X1=m
329 +CONFIG_USB_IPHETH=m
330 +CONFIG_USB_SIERRA_NET=m
331 +CONFIG_USB_VL600=m
332 +CONFIG_PPP=m
333 +CONFIG_PPP_ASYNC=m
334 +CONFIG_PPP_SYNC_TTY=m
335 +CONFIG_PPP_DEFLATE=m
336 +CONFIG_PPP_BSDCOMP=m
337 +CONFIG_SLIP=m
338 +CONFIG_SLIP_COMPRESSED=y
339 +CONFIG_NETCONSOLE=m
340 +CONFIG_INPUT_POLLDEV=m
341 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
342 +CONFIG_INPUT_JOYDEV=m
343 +CONFIG_INPUT_EVDEV=m
344 +# CONFIG_INPUT_KEYBOARD is not set
345 +# CONFIG_INPUT_MOUSE is not set
346 +CONFIG_INPUT_MISC=y
347 +CONFIG_INPUT_AD714X=m
348 +CONFIG_INPUT_ATI_REMOTE=m
349 +CONFIG_INPUT_ATI_REMOTE2=m
350 +CONFIG_INPUT_KEYSPAN_REMOTE=m
351 +CONFIG_INPUT_POWERMATE=m
352 +CONFIG_INPUT_YEALINK=m
353 +CONFIG_INPUT_CM109=m
354 +CONFIG_INPUT_UINPUT=m
355 +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
356 +CONFIG_INPUT_ADXL34X=m
357 +CONFIG_INPUT_CMA3000=m
358 +CONFIG_SERIO=m
359 +CONFIG_SERIO_RAW=m
360 +CONFIG_GAMEPORT=m
361 +CONFIG_GAMEPORT_NS558=m
362 +CONFIG_GAMEPORT_L4=m
363 +CONFIG_VT_HW_CONSOLE_BINDING=y
364 +# CONFIG_LEGACY_PTYS is not set
365 +# CONFIG_DEVKMEM is not set
366 +CONFIG_SERIAL_AMBA_PL011=y
367 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
368 +# CONFIG_HW_RANDOM is not set
369 +CONFIG_RAW_DRIVER=y
370 +CONFIG_GPIO_SYSFS=y
371 +# CONFIG_HWMON is not set
372 +CONFIG_WATCHDOG=y
373 +CONFIG_BCM2708_WDT=m
374 +# CONFIG_MFD_SUPPORT is not set
375 +CONFIG_FB=y
376 +CONFIG_FB_BCM2708=y
377 +CONFIG_FRAMEBUFFER_CONSOLE=y
378 +CONFIG_LOGO=y
379 +# CONFIG_LOGO_LINUX_MONO is not set
380 +# CONFIG_LOGO_LINUX_VGA16 is not set
381 +CONFIG_HID_PID=y
382 +CONFIG_USB_HIDDEV=y
383 +CONFIG_HID_A4TECH=m
384 +CONFIG_HID_ACRUX=m
385 +CONFIG_HID_APPLE=m
386 +CONFIG_HID_BELKIN=m
387 +CONFIG_HID_CHERRY=m
388 +CONFIG_HID_CHICONY=m
389 +CONFIG_HID_CYPRESS=m
390 +CONFIG_HID_DRAGONRISE=m
391 +CONFIG_HID_EMS_FF=m
392 +CONFIG_HID_ELECOM=m
393 +CONFIG_HID_EZKEY=m
394 +CONFIG_HID_HOLTEK=m
395 +CONFIG_HID_KEYTOUCH=m
396 +CONFIG_HID_KYE=m
397 +CONFIG_HID_UCLOGIC=m
398 +CONFIG_HID_WALTOP=m
399 +CONFIG_HID_GYRATION=m
400 +CONFIG_HID_TWINHAN=m
401 +CONFIG_HID_KENSINGTON=m
402 +CONFIG_HID_LCPOWER=m
403 +CONFIG_HID_LOGITECH=m
404 +CONFIG_HID_MAGICMOUSE=m
405 +CONFIG_HID_MICROSOFT=m
406 +CONFIG_HID_MONTEREY=m
407 +CONFIG_HID_MULTITOUCH=m
408 +CONFIG_HID_NTRIG=m
409 +CONFIG_HID_ORTEK=m
410 +CONFIG_HID_PANTHERLORD=m
411 +CONFIG_HID_PETALYNX=m
412 +CONFIG_HID_PICOLCD=m
413 +CONFIG_HID_QUANTA=m
414 +CONFIG_HID_ROCCAT=m
415 +CONFIG_HID_SAMSUNG=m
416 +CONFIG_HID_SONY=m
417 +CONFIG_HID_SPEEDLINK=m
418 +CONFIG_HID_SUNPLUS=m
419 +CONFIG_HID_GREENASIA=m
420 +CONFIG_HID_SMARTJOYPLUS=m
421 +CONFIG_HID_TOPSEED=m
422 +CONFIG_HID_THRUSTMASTER=m
423 +CONFIG_HID_WACOM=m
424 +CONFIG_HID_WIIMOTE=m
425 +CONFIG_HID_ZEROPLUS=m
426 +CONFIG_HID_ZYDACRON=m
427 +CONFIG_USB=y
428 +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
429 +CONFIG_USB_MON=m
430 +CONFIG_USB_DWCOTG=y
431 +CONFIG_USB_STORAGE=y
432 +CONFIG_USB_STORAGE_REALTEK=m
433 +CONFIG_USB_STORAGE_DATAFAB=m
434 +CONFIG_USB_STORAGE_FREECOM=m
435 +CONFIG_USB_STORAGE_ISD200=m
436 +CONFIG_USB_STORAGE_USBAT=m
437 +CONFIG_USB_STORAGE_SDDR09=m
438 +CONFIG_USB_STORAGE_SDDR55=m
439 +CONFIG_USB_STORAGE_JUMPSHOT=m
440 +CONFIG_USB_STORAGE_ALAUDA=m
441 +CONFIG_USB_STORAGE_ONETOUCH=m
442 +CONFIG_USB_STORAGE_KARMA=m
443 +CONFIG_USB_STORAGE_CYPRESS_ATACB=m
444 +CONFIG_USB_STORAGE_ENE_UB6250=m
445 +CONFIG_USB_UAS=m
446 +CONFIG_USB_LIBUSUAL=y
447 +CONFIG_USB_MDC800=m
448 +CONFIG_USB_MICROTEK=m
449 +CONFIG_USB_SERIAL=m
450 +CONFIG_USB_SERIAL_GENERIC=y
451 +CONFIG_USB_SERIAL_AIRCABLE=m
452 +CONFIG_USB_SERIAL_ARK3116=m
453 +CONFIG_USB_SERIAL_BELKIN=m
454 +CONFIG_USB_SERIAL_CH341=m
455 +CONFIG_USB_SERIAL_WHITEHEAT=m
456 +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
457 +CONFIG_USB_SERIAL_CP210X=m
458 +CONFIG_USB_SERIAL_CYPRESS_M8=m
459 +CONFIG_USB_SERIAL_EMPEG=m
460 +CONFIG_USB_SERIAL_FTDI_SIO=m
461 +CONFIG_USB_SERIAL_FUNSOFT=m
462 +CONFIG_USB_SERIAL_VISOR=m
463 +CONFIG_USB_SERIAL_IPAQ=m
464 +CONFIG_USB_SERIAL_IR=m
465 +CONFIG_USB_SERIAL_EDGEPORT=m
466 +CONFIG_USB_SERIAL_EDGEPORT_TI=m
467 +CONFIG_USB_SERIAL_GARMIN=m
468 +CONFIG_USB_SERIAL_IPW=m
469 +CONFIG_USB_SERIAL_IUU=m
470 +CONFIG_USB_SERIAL_KEYSPAN_PDA=m
471 +CONFIG_USB_SERIAL_KEYSPAN=m
472 +CONFIG_USB_SERIAL_KLSI=m
473 +CONFIG_USB_SERIAL_KOBIL_SCT=m
474 +CONFIG_USB_SERIAL_MCT_U232=m
475 +CONFIG_USB_SERIAL_MOS7720=m
476 +CONFIG_USB_SERIAL_MOS7840=m
477 +CONFIG_USB_SERIAL_MOTOROLA=m
478 +CONFIG_USB_SERIAL_NAVMAN=m
479 +CONFIG_USB_SERIAL_PL2303=m
480 +CONFIG_USB_SERIAL_OTI6858=m
481 +CONFIG_USB_SERIAL_QCAUX=m
482 +CONFIG_USB_SERIAL_QUALCOMM=m
483 +CONFIG_USB_SERIAL_SPCP8X5=m
484 +CONFIG_USB_SERIAL_HP4X=m
485 +CONFIG_USB_SERIAL_SAFE=m
486 +CONFIG_USB_SERIAL_SIEMENS_MPI=m
487 +CONFIG_USB_SERIAL_SIERRAWIRELESS=m
488 +CONFIG_USB_SERIAL_SYMBOL=m
489 +CONFIG_USB_SERIAL_TI=m
490 +CONFIG_USB_SERIAL_CYBERJACK=m
491 +CONFIG_USB_SERIAL_XIRCOM=m
492 +CONFIG_USB_SERIAL_OPTION=m
493 +CONFIG_USB_SERIAL_OMNINET=m
494 +CONFIG_USB_SERIAL_OPTICON=m
495 +CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m
496 +CONFIG_USB_SERIAL_ZIO=m
497 +CONFIG_USB_SERIAL_SSU100=m
498 +CONFIG_USB_SERIAL_DEBUG=m
499 +CONFIG_USB_EMI62=m
500 +CONFIG_USB_EMI26=m
501 +CONFIG_USB_ADUTUX=m
502 +CONFIG_USB_SEVSEG=m
503 +CONFIG_USB_RIO500=m
504 +CONFIG_USB_LEGOTOWER=m
505 +CONFIG_USB_LCD=m
506 +CONFIG_USB_LED=m
507 +CONFIG_USB_CYPRESS_CY7C63=m
508 +CONFIG_USB_CYTHERM=m
509 +CONFIG_USB_IDMOUSE=m
510 +CONFIG_USB_FTDI_ELAN=m
511 +CONFIG_USB_APPLEDISPLAY=m
512 +CONFIG_USB_LD=m
513 +CONFIG_USB_TRANCEVIBRATOR=m
514 +CONFIG_USB_IOWARRIOR=m
515 +CONFIG_USB_TEST=m
516 +CONFIG_USB_ISIGHTFW=m
517 +CONFIG_USB_YUREX=m
518 +CONFIG_MMC=y
519 +CONFIG_MMC_SDHCI=y
520 +CONFIG_MMC_SDHCI_PLTFM=y
521 +CONFIG_MMC_SDHCI_BCM2708=y
522 +CONFIG_MMC_SDHCI_BCM2708_DMA=y
523 +CONFIG_LEDS_GPIO=y
524 +CONFIG_LEDS_TRIGGER_TIMER=m
525 +CONFIG_LEDS_TRIGGER_HEARTBEAT=m
526 +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
527 +CONFIG_UIO=m
528 +CONFIG_UIO_PDRV=m
529 +CONFIG_UIO_PDRV_GENIRQ=m
530 +# CONFIG_IOMMU_SUPPORT is not set
531 +CONFIG_EXT4_FS=y
532 +CONFIG_EXT4_FS_POSIX_ACL=y
533 +CONFIG_EXT4_FS_SECURITY=y
534 +CONFIG_REISERFS_FS=m
535 +CONFIG_REISERFS_FS_XATTR=y
536 +CONFIG_REISERFS_FS_POSIX_ACL=y
537 +CONFIG_REISERFS_FS_SECURITY=y
538 +CONFIG_JFS_FS=m
539 +CONFIG_JFS_POSIX_ACL=y
540 +CONFIG_JFS_SECURITY=y
541 +CONFIG_XFS_FS=m
542 +CONFIG_XFS_QUOTA=y
543 +CONFIG_XFS_POSIX_ACL=y
544 +CONFIG_XFS_RT=y
545 +CONFIG_GFS2_FS=m
546 +CONFIG_OCFS2_FS=m
547 +CONFIG_BTRFS_FS=m
548 +CONFIG_BTRFS_FS_POSIX_ACL=y
549 +CONFIG_NILFS2_FS=m
550 +CONFIG_AUTOFS4_FS=y
551 +CONFIG_FUSE_FS=m
552 +CONFIG_CUSE=m
553 +CONFIG_FSCACHE=y
554 +CONFIG_CACHEFILES=y
555 +CONFIG_ISO9660_FS=m
556 +CONFIG_JOLIET=y
557 +CONFIG_ZISOFS=y
558 +CONFIG_UDF_FS=m
559 +CONFIG_MSDOS_FS=y
560 +CONFIG_VFAT_FS=y
561 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
562 +CONFIG_NTFS_FS=m
563 +CONFIG_TMPFS=y
564 +CONFIG_TMPFS_POSIX_ACL=y
565 +CONFIG_CONFIGFS_FS=y
566 +CONFIG_SQUASHFS=m
567 +CONFIG_SQUASHFS_XATTR=y
568 +CONFIG_SQUASHFS_LZO=y
569 +CONFIG_SQUASHFS_XZ=y
570 +CONFIG_NFS_FS=y
571 +CONFIG_NFS_V3=y
572 +CONFIG_NFS_V3_ACL=y
573 +CONFIG_NFS_V4=y
574 +CONFIG_ROOT_NFS=y
575 +CONFIG_NFS_FSCACHE=y
576 +CONFIG_CIFS=m
577 +CONFIG_CIFS_WEAK_PW_HASH=y
578 +CONFIG_CIFS_XATTR=y
579 +CONFIG_CIFS_POSIX=y
580 +CONFIG_9P_FS=m
581 +CONFIG_PARTITION_ADVANCED=y
582 +CONFIG_MAC_PARTITION=y
583 +CONFIG_EFI_PARTITION=y
584 +CONFIG_NLS_DEFAULT="utf8"
585 +CONFIG_NLS_CODEPAGE_437=y
586 +CONFIG_NLS_CODEPAGE_737=m
587 +CONFIG_NLS_CODEPAGE_775=m
588 +CONFIG_NLS_CODEPAGE_850=m
589 +CONFIG_NLS_CODEPAGE_852=m
590 +CONFIG_NLS_CODEPAGE_855=m
591 +CONFIG_NLS_CODEPAGE_857=m
592 +CONFIG_NLS_CODEPAGE_860=m
593 +CONFIG_NLS_CODEPAGE_861=m
594 +CONFIG_NLS_CODEPAGE_862=m
595 +CONFIG_NLS_CODEPAGE_863=m
596 +CONFIG_NLS_CODEPAGE_864=m
597 +CONFIG_NLS_CODEPAGE_865=m
598 +CONFIG_NLS_CODEPAGE_866=m
599 +CONFIG_NLS_CODEPAGE_869=m
600 +CONFIG_NLS_CODEPAGE_936=m
601 +CONFIG_NLS_CODEPAGE_950=m
602 +CONFIG_NLS_CODEPAGE_932=m
603 +CONFIG_NLS_CODEPAGE_949=m
604 +CONFIG_NLS_CODEPAGE_874=m
605 +CONFIG_NLS_ISO8859_8=m
606 +CONFIG_NLS_CODEPAGE_1250=m
607 +CONFIG_NLS_CODEPAGE_1251=m
608 +CONFIG_NLS_ASCII=y
609 +CONFIG_NLS_ISO8859_1=m
610 +CONFIG_NLS_ISO8859_2=m
611 +CONFIG_NLS_ISO8859_3=m
612 +CONFIG_NLS_ISO8859_4=m
613 +CONFIG_NLS_ISO8859_5=m
614 +CONFIG_NLS_ISO8859_6=m
615 +CONFIG_NLS_ISO8859_7=m
616 +CONFIG_NLS_ISO8859_9=m
617 +CONFIG_NLS_ISO8859_13=m
618 +CONFIG_NLS_ISO8859_14=m
619 +CONFIG_NLS_ISO8859_15=m
620 +CONFIG_NLS_KOI8_R=m
621 +CONFIG_NLS_KOI8_U=m
622 +CONFIG_NLS_UTF8=m
623 +# CONFIG_SCHED_DEBUG is not set
624 +# CONFIG_DEBUG_BUGVERBOSE is not set
625 +# CONFIG_FTRACE is not set
626 +# CONFIG_ARM_UNWIND is not set
627 +CONFIG_CRYPTO_AUTHENC=m
628 +CONFIG_CRYPTO_SEQIV=m
629 +CONFIG_CRYPTO_CBC=y
630 +CONFIG_CRYPTO_HMAC=y
631 +CONFIG_CRYPTO_XCBC=m
632 +CONFIG_CRYPTO_MD5=y
633 +CONFIG_CRYPTO_SHA1=y
634 +CONFIG_CRYPTO_SHA256=m
635 +CONFIG_CRYPTO_SHA512=m
636 +CONFIG_CRYPTO_TGR192=m
637 +CONFIG_CRYPTO_WP512=m
638 +CONFIG_CRYPTO_CAST5=m
639 +CONFIG_CRYPTO_DES=y
640 +CONFIG_CRYPTO_DEFLATE=m
641 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
642 +# CONFIG_CRYPTO_HW is not set
643 +CONFIG_CRC_ITU_T=y
644 +CONFIG_LIBCRC32C=y
645 diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig
646 new file mode 100644
647 index 0000000..339aabf
648 --- /dev/null
649 +++ b/arch/arm/configs/bcmrpi_defconfig
650 @@ -0,0 +1,510 @@
651 +CONFIG_EXPERIMENTAL=y
652 +# CONFIG_LOCALVERSION_AUTO is not set
653 +CONFIG_SYSVIPC=y
654 +CONFIG_POSIX_MQUEUE=y
655 +CONFIG_BSD_PROCESS_ACCT=y
656 +CONFIG_BSD_PROCESS_ACCT_V3=y
657 +CONFIG_FHANDLE=y
658 +CONFIG_AUDIT=y
659 +CONFIG_IKCONFIG=y
660 +CONFIG_IKCONFIG_PROC=y
661 +CONFIG_CGROUP_FREEZER=y
662 +CONFIG_CGROUP_DEVICE=y
663 +CONFIG_CGROUP_CPUACCT=y
664 +CONFIG_RESOURCE_COUNTERS=y
665 +CONFIG_BLK_CGROUP=y
666 +CONFIG_NAMESPACES=y
667 +CONFIG_SCHED_AUTOGROUP=y
668 +CONFIG_EMBEDDED=y
669 +# CONFIG_COMPAT_BRK is not set
670 +CONFIG_SLAB=y
671 +CONFIG_PROFILING=y
672 +CONFIG_OPROFILE=m
673 +CONFIG_KPROBES=y
674 +CONFIG_MODULES=y
675 +CONFIG_MODULE_UNLOAD=y
676 +CONFIG_MODVERSIONS=y
677 +CONFIG_MODULE_SRCVERSION_ALL=y
678 +# CONFIG_BLK_DEV_BSG is not set
679 +CONFIG_BLK_DEV_THROTTLING=y
680 +CONFIG_CFQ_GROUP_IOSCHED=y
681 +CONFIG_ARCH_BCM2708=y
682 +CONFIG_NO_HZ=y
683 +CONFIG_HIGH_RES_TIMERS=y
684 +CONFIG_AEABI=y
685 +CONFIG_SECCOMP=y
686 +CONFIG_CC_STACKPROTECTOR=y
687 +CONFIG_ZBOOT_ROM_TEXT=0x0
688 +CONFIG_ZBOOT_ROM_BSS=0x0
689 +CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait"
690 +CONFIG_KEXEC=y
691 +CONFIG_CPU_IDLE=y
692 +CONFIG_VFP=y
693 +CONFIG_BINFMT_MISC=m
694 +CONFIG_NET=y
695 +CONFIG_PACKET=y
696 +CONFIG_UNIX=y
697 +CONFIG_XFRM_USER=y
698 +CONFIG_NET_KEY=m
699 +CONFIG_INET=y
700 +CONFIG_IP_MULTICAST=y
701 +CONFIG_IP_PNP=y
702 +CONFIG_IP_PNP_DHCP=y
703 +CONFIG_IP_PNP_RARP=y
704 +CONFIG_SYN_COOKIES=y
705 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
706 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
707 +# CONFIG_INET_XFRM_MODE_BEET is not set
708 +# CONFIG_INET_LRO is not set
709 +# CONFIG_INET_DIAG is not set
710 +# CONFIG_IPV6 is not set
711 +CONFIG_NET_PKTGEN=m
712 +CONFIG_IRDA=m
713 +CONFIG_IRLAN=m
714 +CONFIG_IRCOMM=m
715 +CONFIG_IRDA_ULTRA=y
716 +CONFIG_IRDA_CACHE_LAST_LSAP=y
717 +CONFIG_IRDA_FAST_RR=y
718 +CONFIG_IRTTY_SIR=m
719 +CONFIG_KINGSUN_DONGLE=m
720 +CONFIG_KSDAZZLE_DONGLE=m
721 +CONFIG_KS959_DONGLE=m
722 +CONFIG_USB_IRDA=m
723 +CONFIG_SIGMATEL_FIR=m
724 +CONFIG_MCS_FIR=m
725 +CONFIG_BT=m
726 +CONFIG_BT_L2CAP=y
727 +CONFIG_BT_SCO=y
728 +CONFIG_BT_RFCOMM=m
729 +CONFIG_BT_RFCOMM_TTY=y
730 +CONFIG_BT_BNEP=m
731 +CONFIG_BT_BNEP_MC_FILTER=y
732 +CONFIG_BT_BNEP_PROTO_FILTER=y
733 +CONFIG_BT_HIDP=m
734 +CONFIG_BT_HCIBTUSB=m
735 +CONFIG_BT_HCIBCM203X=m
736 +CONFIG_BT_HCIBPA10X=m
737 +CONFIG_BT_HCIBFUSB=m
738 +CONFIG_BT_HCIVHCI=m
739 +CONFIG_BT_MRVL=m
740 +CONFIG_BT_MRVL_SDIO=m
741 +CONFIG_BT_ATH3K=m
742 +CONFIG_CFG80211=m
743 +CONFIG_MAC80211=m
744 +CONFIG_MAC80211_RC_PID=y
745 +CONFIG_MAC80211_MESH=y
746 +CONFIG_WIMAX=m
747 +CONFIG_NET_9P=m
748 +CONFIG_NFC=m
749 +CONFIG_NFC_PN533=m
750 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
751 +CONFIG_BLK_DEV_LOOP=y
752 +CONFIG_BLK_DEV_CRYPTOLOOP=m
753 +CONFIG_BLK_DEV_NBD=m
754 +CONFIG_BLK_DEV_RAM=y
755 +CONFIG_CDROM_PKTCDVD=m
756 +CONFIG_MISC_DEVICES=y
757 +CONFIG_SCSI=y
758 +# CONFIG_SCSI_PROC_FS is not set
759 +CONFIG_BLK_DEV_SD=m
760 +CONFIG_BLK_DEV_SR=m
761 +CONFIG_SCSI_MULTI_LUN=y
762 +# CONFIG_SCSI_LOWLEVEL is not set
763 +CONFIG_MD=y
764 +CONFIG_NETDEVICES=y
765 +CONFIG_TUN=m
766 +CONFIG_PHYLIB=m
767 +CONFIG_MDIO_BITBANG=m
768 +CONFIG_NET_ETHERNET=y
769 +# CONFIG_NETDEV_1000 is not set
770 +# CONFIG_NETDEV_10000 is not set
771 +CONFIG_LIBERTAS_THINFIRM=m
772 +CONFIG_LIBERTAS_THINFIRM_USB=m
773 +CONFIG_AT76C50X_USB=m
774 +CONFIG_USB_ZD1201=m
775 +CONFIG_USB_NET_RNDIS_WLAN=m
776 +CONFIG_RTL8187=m
777 +CONFIG_MAC80211_HWSIM=m
778 +CONFIG_ATH_COMMON=m
779 +CONFIG_ATH9K=m
780 +CONFIG_ATH9K_HTC=m
781 +CONFIG_CARL9170=m
782 +CONFIG_B43=m
783 +CONFIG_B43LEGACY=m
784 +CONFIG_HOSTAP=m
785 +CONFIG_IWM=m
786 +CONFIG_LIBERTAS=m
787 +CONFIG_LIBERTAS_USB=m
788 +CONFIG_LIBERTAS_SDIO=m
789 +CONFIG_P54_COMMON=m
790 +CONFIG_P54_USB=m
791 +CONFIG_RT2X00=m
792 +CONFIG_RT2500USB=m
793 +CONFIG_RT73USB=m
794 +CONFIG_RT2800USB=m
795 +CONFIG_RT2800USB_RT53XX=y
796 +CONFIG_RTL8192CU=m
797 +CONFIG_WL1251=m
798 +CONFIG_WL12XX_MENU=m
799 +CONFIG_ZD1211RW=m
800 +CONFIG_MWIFIEX=m
801 +CONFIG_MWIFIEX_SDIO=m
802 +CONFIG_WIMAX_I2400M_USB=m
803 +CONFIG_USB_CATC=m
804 +CONFIG_USB_KAWETH=m
805 +CONFIG_USB_PEGASUS=m
806 +CONFIG_USB_RTL8150=m
807 +CONFIG_USB_USBNET=y
808 +CONFIG_USB_NET_AX8817X=m
809 +CONFIG_USB_NET_CDCETHER=m
810 +CONFIG_USB_NET_CDC_EEM=m
811 +CONFIG_USB_NET_DM9601=m
812 +CONFIG_USB_NET_SMSC75XX=m
813 +CONFIG_USB_NET_SMSC95XX=y
814 +CONFIG_USB_NET_GL620A=m
815 +CONFIG_USB_NET_NET1080=m
816 +CONFIG_USB_NET_PLUSB=m
817 +CONFIG_USB_NET_MCS7830=m
818 +CONFIG_USB_NET_CDC_SUBSET=m
819 +CONFIG_USB_ALI_M5632=y
820 +CONFIG_USB_AN2720=y
821 +CONFIG_USB_KC2190=y
822 +# CONFIG_USB_NET_ZAURUS is not set
823 +CONFIG_USB_NET_CX82310_ETH=m
824 +CONFIG_USB_NET_KALMIA=m
825 +CONFIG_USB_NET_INT51X1=m
826 +CONFIG_USB_IPHETH=m
827 +CONFIG_USB_SIERRA_NET=m
828 +CONFIG_USB_VL600=m
829 +CONFIG_PPP=m
830 +CONFIG_PPP_ASYNC=m
831 +CONFIG_PPP_SYNC_TTY=m
832 +CONFIG_PPP_DEFLATE=m
833 +CONFIG_PPP_BSDCOMP=m
834 +CONFIG_SLIP=m
835 +CONFIG_SLIP_COMPRESSED=y
836 +CONFIG_NETCONSOLE=m
837 +CONFIG_INPUT_POLLDEV=m
838 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
839 +CONFIG_INPUT_JOYDEV=m
840 +CONFIG_INPUT_EVDEV=m
841 +# CONFIG_INPUT_KEYBOARD is not set
842 +# CONFIG_INPUT_MOUSE is not set
843 +CONFIG_INPUT_MISC=y
844 +CONFIG_INPUT_AD714X=m
845 +CONFIG_INPUT_ATI_REMOTE=m
846 +CONFIG_INPUT_ATI_REMOTE2=m
847 +CONFIG_INPUT_KEYSPAN_REMOTE=m
848 +CONFIG_INPUT_POWERMATE=m
849 +CONFIG_INPUT_YEALINK=m
850 +CONFIG_INPUT_CM109=m
851 +CONFIG_INPUT_UINPUT=m
852 +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
853 +CONFIG_INPUT_ADXL34X=m
854 +CONFIG_INPUT_CMA3000=m
855 +CONFIG_SERIO=m
856 +CONFIG_SERIO_RAW=m
857 +CONFIG_GAMEPORT=m
858 +CONFIG_GAMEPORT_NS558=m
859 +CONFIG_GAMEPORT_L4=m
860 +CONFIG_VT_HW_CONSOLE_BINDING=y
861 +# CONFIG_LEGACY_PTYS is not set
862 +# CONFIG_DEVKMEM is not set
863 +CONFIG_SERIAL_AMBA_PL011=y
864 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
865 +# CONFIG_HW_RANDOM is not set
866 +CONFIG_RAW_DRIVER=y
867 +CONFIG_GPIO_SYSFS=y
868 +# CONFIG_HWMON is not set
869 +CONFIG_WATCHDOG=y
870 +CONFIG_BCM2708_WDT=m
871 +# CONFIG_MFD_SUPPORT is not set
872 +CONFIG_FB=y
873 +CONFIG_FB_BCM2708=y
874 +CONFIG_FRAMEBUFFER_CONSOLE=y
875 +CONFIG_LOGO=y
876 +# CONFIG_LOGO_LINUX_MONO is not set
877 +# CONFIG_LOGO_LINUX_VGA16 is not set
878 +CONFIG_HID_PID=y
879 +CONFIG_USB_HIDDEV=y
880 +CONFIG_HID_A4TECH=m
881 +CONFIG_HID_ACRUX=m
882 +CONFIG_HID_APPLE=m
883 +CONFIG_HID_BELKIN=m
884 +CONFIG_HID_CHERRY=m
885 +CONFIG_HID_CHICONY=m
886 +CONFIG_HID_CYPRESS=m
887 +CONFIG_HID_DRAGONRISE=m
888 +CONFIG_HID_EMS_FF=m
889 +CONFIG_HID_ELECOM=m
890 +CONFIG_HID_EZKEY=m
891 +CONFIG_HID_HOLTEK=m
892 +CONFIG_HID_KEYTOUCH=m
893 +CONFIG_HID_KYE=m
894 +CONFIG_HID_UCLOGIC=m
895 +CONFIG_HID_WALTOP=m
896 +CONFIG_HID_GYRATION=m
897 +CONFIG_HID_TWINHAN=m
898 +CONFIG_HID_KENSINGTON=m
899 +CONFIG_HID_LCPOWER=m
900 +CONFIG_HID_LOGITECH=m
901 +CONFIG_HID_MAGICMOUSE=m
902 +CONFIG_HID_MICROSOFT=m
903 +CONFIG_HID_MONTEREY=m
904 +CONFIG_HID_MULTITOUCH=m
905 +CONFIG_HID_NTRIG=m
906 +CONFIG_HID_ORTEK=m
907 +CONFIG_HID_PANTHERLORD=m
908 +CONFIG_HID_PETALYNX=m
909 +CONFIG_HID_PICOLCD=m
910 +CONFIG_HID_QUANTA=m
911 +CONFIG_HID_ROCCAT=m
912 +CONFIG_HID_SAMSUNG=m
913 +CONFIG_HID_SONY=m
914 +CONFIG_HID_SPEEDLINK=m
915 +CONFIG_HID_SUNPLUS=m
916 +CONFIG_HID_GREENASIA=m
917 +CONFIG_HID_SMARTJOYPLUS=m
918 +CONFIG_HID_TOPSEED=m
919 +CONFIG_HID_THRUSTMASTER=m
920 +CONFIG_HID_WACOM=m
921 +CONFIG_HID_WIIMOTE=m
922 +CONFIG_HID_ZEROPLUS=m
923 +CONFIG_HID_ZYDACRON=m
924 +CONFIG_USB=y
925 +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
926 +CONFIG_USB_MON=m
927 +CONFIG_USB_DWCOTG=y
928 +CONFIG_USB_STORAGE=y
929 +CONFIG_USB_STORAGE_REALTEK=m
930 +CONFIG_USB_STORAGE_DATAFAB=m
931 +CONFIG_USB_STORAGE_FREECOM=m
932 +CONFIG_USB_STORAGE_ISD200=m
933 +CONFIG_USB_STORAGE_USBAT=m
934 +CONFIG_USB_STORAGE_SDDR09=m
935 +CONFIG_USB_STORAGE_SDDR55=m
936 +CONFIG_USB_STORAGE_JUMPSHOT=m
937 +CONFIG_USB_STORAGE_ALAUDA=m
938 +CONFIG_USB_STORAGE_ONETOUCH=m
939 +CONFIG_USB_STORAGE_KARMA=m
940 +CONFIG_USB_STORAGE_CYPRESS_ATACB=m
941 +CONFIG_USB_STORAGE_ENE_UB6250=m
942 +CONFIG_USB_UAS=m
943 +CONFIG_USB_LIBUSUAL=y
944 +CONFIG_USB_MDC800=m
945 +CONFIG_USB_MICROTEK=m
946 +CONFIG_USB_SERIAL=m
947 +CONFIG_USB_SERIAL_GENERIC=y
948 +CONFIG_USB_SERIAL_AIRCABLE=m
949 +CONFIG_USB_SERIAL_ARK3116=m
950 +CONFIG_USB_SERIAL_BELKIN=m
951 +CONFIG_USB_SERIAL_CH341=m
952 +CONFIG_USB_SERIAL_WHITEHEAT=m
953 +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
954 +CONFIG_USB_SERIAL_CP210X=m
955 +CONFIG_USB_SERIAL_CYPRESS_M8=m
956 +CONFIG_USB_SERIAL_EMPEG=m
957 +CONFIG_USB_SERIAL_FTDI_SIO=m
958 +CONFIG_USB_SERIAL_FUNSOFT=m
959 +CONFIG_USB_SERIAL_VISOR=m
960 +CONFIG_USB_SERIAL_IPAQ=m
961 +CONFIG_USB_SERIAL_IR=m
962 +CONFIG_USB_SERIAL_EDGEPORT=m
963 +CONFIG_USB_SERIAL_EDGEPORT_TI=m
964 +CONFIG_USB_SERIAL_GARMIN=m
965 +CONFIG_USB_SERIAL_IPW=m
966 +CONFIG_USB_SERIAL_IUU=m
967 +CONFIG_USB_SERIAL_KEYSPAN_PDA=m
968 +CONFIG_USB_SERIAL_KEYSPAN=m
969 +CONFIG_USB_SERIAL_KLSI=m
970 +CONFIG_USB_SERIAL_KOBIL_SCT=m
971 +CONFIG_USB_SERIAL_MCT_U232=m
972 +CONFIG_USB_SERIAL_MOS7720=m
973 +CONFIG_USB_SERIAL_MOS7840=m
974 +CONFIG_USB_SERIAL_MOTOROLA=m
975 +CONFIG_USB_SERIAL_NAVMAN=m
976 +CONFIG_USB_SERIAL_PL2303=m
977 +CONFIG_USB_SERIAL_OTI6858=m
978 +CONFIG_USB_SERIAL_QCAUX=m
979 +CONFIG_USB_SERIAL_QUALCOMM=m
980 +CONFIG_USB_SERIAL_SPCP8X5=m
981 +CONFIG_USB_SERIAL_HP4X=m
982 +CONFIG_USB_SERIAL_SAFE=m
983 +CONFIG_USB_SERIAL_SIEMENS_MPI=m
984 +CONFIG_USB_SERIAL_SIERRAWIRELESS=m
985 +CONFIG_USB_SERIAL_SYMBOL=m
986 +CONFIG_USB_SERIAL_TI=m
987 +CONFIG_USB_SERIAL_CYBERJACK=m
988 +CONFIG_USB_SERIAL_XIRCOM=m
989 +CONFIG_USB_SERIAL_OPTION=m
990 +CONFIG_USB_SERIAL_OMNINET=m
991 +CONFIG_USB_SERIAL_OPTICON=m
992 +CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m
993 +CONFIG_USB_SERIAL_ZIO=m
994 +CONFIG_USB_SERIAL_SSU100=m
995 +CONFIG_USB_SERIAL_DEBUG=m
996 +CONFIG_USB_EMI62=m
997 +CONFIG_USB_EMI26=m
998 +CONFIG_USB_ADUTUX=m
999 +CONFIG_USB_SEVSEG=m
1000 +CONFIG_USB_RIO500=m
1001 +CONFIG_USB_LEGOTOWER=m
1002 +CONFIG_USB_LCD=m
1003 +CONFIG_USB_LED=m
1004 +CONFIG_USB_CYPRESS_CY7C63=m
1005 +CONFIG_USB_CYTHERM=m
1006 +CONFIG_USB_IDMOUSE=m
1007 +CONFIG_USB_FTDI_ELAN=m
1008 +CONFIG_USB_APPLEDISPLAY=m
1009 +CONFIG_USB_LD=m
1010 +CONFIG_USB_TRANCEVIBRATOR=m
1011 +CONFIG_USB_IOWARRIOR=m
1012 +CONFIG_USB_TEST=m
1013 +CONFIG_USB_ISIGHTFW=m
1014 +CONFIG_USB_YUREX=m
1015 +CONFIG_MMC=y
1016 +CONFIG_MMC_SDHCI=y
1017 +CONFIG_MMC_SDHCI_PLTFM=y
1018 +CONFIG_MMC_SDHCI_BCM2708=y
1019 +CONFIG_MMC_SDHCI_BCM2708_DMA=y
1020 +CONFIG_LEDS_GPIO=y
1021 +CONFIG_LEDS_TRIGGER_TIMER=m
1022 +CONFIG_LEDS_TRIGGER_HEARTBEAT=m
1023 +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
1024 +CONFIG_UIO=m
1025 +CONFIG_UIO_PDRV=m
1026 +CONFIG_UIO_PDRV_GENIRQ=m
1027 +# CONFIG_IOMMU_SUPPORT is not set
1028 +CONFIG_EXT4_FS=y
1029 +CONFIG_EXT4_FS_POSIX_ACL=y
1030 +CONFIG_EXT4_FS_SECURITY=y
1031 +CONFIG_REISERFS_FS=m
1032 +CONFIG_REISERFS_FS_XATTR=y
1033 +CONFIG_REISERFS_FS_POSIX_ACL=y
1034 +CONFIG_REISERFS_FS_SECURITY=y
1035 +CONFIG_JFS_FS=m
1036 +CONFIG_JFS_POSIX_ACL=y
1037 +CONFIG_JFS_SECURITY=y
1038 +CONFIG_JFS_STATISTICS=y
1039 +CONFIG_XFS_FS=m
1040 +CONFIG_XFS_QUOTA=y
1041 +CONFIG_XFS_POSIX_ACL=y
1042 +CONFIG_XFS_RT=y
1043 +CONFIG_GFS2_FS=m
1044 +CONFIG_OCFS2_FS=m
1045 +CONFIG_BTRFS_FS=m
1046 +CONFIG_BTRFS_FS_POSIX_ACL=y
1047 +CONFIG_NILFS2_FS=m
1048 +CONFIG_FANOTIFY=y
1049 +CONFIG_AUTOFS4_FS=y
1050 +CONFIG_FUSE_FS=m
1051 +CONFIG_CUSE=m
1052 +CONFIG_FSCACHE=y
1053 +CONFIG_FSCACHE_STATS=y
1054 +CONFIG_FSCACHE_HISTOGRAM=y
1055 +CONFIG_CACHEFILES=y
1056 +CONFIG_ISO9660_FS=m
1057 +CONFIG_JOLIET=y
1058 +CONFIG_ZISOFS=y
1059 +CONFIG_UDF_FS=m
1060 +CONFIG_MSDOS_FS=y
1061 +CONFIG_VFAT_FS=y
1062 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
1063 +CONFIG_NTFS_FS=m
1064 +CONFIG_TMPFS=y
1065 +CONFIG_TMPFS_POSIX_ACL=y
1066 +CONFIG_CONFIGFS_FS=y
1067 +CONFIG_SQUASHFS=m
1068 +CONFIG_SQUASHFS_XATTR=y
1069 +CONFIG_SQUASHFS_LZO=y
1070 +CONFIG_SQUASHFS_XZ=y
1071 +CONFIG_NFS_FS=y
1072 +CONFIG_NFS_V3=y
1073 +CONFIG_NFS_V3_ACL=y
1074 +CONFIG_NFS_V4=y
1075 +CONFIG_ROOT_NFS=y
1076 +CONFIG_NFS_FSCACHE=y
1077 +CONFIG_CIFS=m
1078 +CONFIG_CIFS_WEAK_PW_HASH=y
1079 +CONFIG_CIFS_XATTR=y
1080 +CONFIG_CIFS_POSIX=y
1081 +CONFIG_9P_FS=m
1082 +CONFIG_9P_FS_POSIX_ACL=y
1083 +CONFIG_PARTITION_ADVANCED=y
1084 +CONFIG_MAC_PARTITION=y
1085 +CONFIG_EFI_PARTITION=y
1086 +CONFIG_NLS_DEFAULT="utf8"
1087 +CONFIG_NLS_CODEPAGE_437=y
1088 +CONFIG_NLS_CODEPAGE_737=m
1089 +CONFIG_NLS_CODEPAGE_775=m
1090 +CONFIG_NLS_CODEPAGE_850=m
1091 +CONFIG_NLS_CODEPAGE_852=m
1092 +CONFIG_NLS_CODEPAGE_855=m
1093 +CONFIG_NLS_CODEPAGE_857=m
1094 +CONFIG_NLS_CODEPAGE_860=m
1095 +CONFIG_NLS_CODEPAGE_861=m
1096 +CONFIG_NLS_CODEPAGE_862=m
1097 +CONFIG_NLS_CODEPAGE_863=m
1098 +CONFIG_NLS_CODEPAGE_864=m
1099 +CONFIG_NLS_CODEPAGE_865=m
1100 +CONFIG_NLS_CODEPAGE_866=m
1101 +CONFIG_NLS_CODEPAGE_869=m
1102 +CONFIG_NLS_CODEPAGE_936=m
1103 +CONFIG_NLS_CODEPAGE_950=m
1104 +CONFIG_NLS_CODEPAGE_932=m
1105 +CONFIG_NLS_CODEPAGE_949=m
1106 +CONFIG_NLS_CODEPAGE_874=m
1107 +CONFIG_NLS_ISO8859_8=m
1108 +CONFIG_NLS_CODEPAGE_1250=m
1109 +CONFIG_NLS_CODEPAGE_1251=m
1110 +CONFIG_NLS_ASCII=y
1111 +CONFIG_NLS_ISO8859_1=m
1112 +CONFIG_NLS_ISO8859_2=m
1113 +CONFIG_NLS_ISO8859_3=m
1114 +CONFIG_NLS_ISO8859_4=m
1115 +CONFIG_NLS_ISO8859_5=m
1116 +CONFIG_NLS_ISO8859_6=m
1117 +CONFIG_NLS_ISO8859_7=m
1118 +CONFIG_NLS_ISO8859_9=m
1119 +CONFIG_NLS_ISO8859_13=m
1120 +CONFIG_NLS_ISO8859_14=m
1121 +CONFIG_NLS_ISO8859_15=m
1122 +CONFIG_NLS_KOI8_R=m
1123 +CONFIG_NLS_KOI8_U=m
1124 +CONFIG_NLS_UTF8=m
1125 +CONFIG_PRINTK_TIME=y
1126 +CONFIG_DETECT_HUNG_TASK=y
1127 +CONFIG_TIMER_STATS=y
1128 +CONFIG_DEBUG_STACK_USAGE=y
1129 +CONFIG_DEBUG_INFO=y
1130 +CONFIG_DEBUG_MEMORY_INIT=y
1131 +CONFIG_BOOT_PRINTK_DELAY=y
1132 +CONFIG_LATENCYTOP=y
1133 +CONFIG_SYSCTL_SYSCALL_CHECK=y
1134 +CONFIG_IRQSOFF_TRACER=y
1135 +CONFIG_SCHED_TRACER=y
1136 +CONFIG_STACK_TRACER=y
1137 +CONFIG_BLK_DEV_IO_TRACE=y
1138 +CONFIG_FUNCTION_PROFILER=y
1139 +CONFIG_KGDB=y
1140 +CONFIG_KGDB_KDB=y
1141 +CONFIG_KDB_KEYBOARD=y
1142 +CONFIG_STRICT_DEVMEM=y
1143 +CONFIG_CRYPTO_AUTHENC=m
1144 +CONFIG_CRYPTO_SEQIV=m
1145 +CONFIG_CRYPTO_CBC=y
1146 +CONFIG_CRYPTO_HMAC=y
1147 +CONFIG_CRYPTO_XCBC=m
1148 +CONFIG_CRYPTO_MD5=y
1149 +CONFIG_CRYPTO_SHA1=y
1150 +CONFIG_CRYPTO_SHA256=m
1151 +CONFIG_CRYPTO_SHA512=m
1152 +CONFIG_CRYPTO_TGR192=m
1153 +CONFIG_CRYPTO_WP512=m
1154 +CONFIG_CRYPTO_CAST5=m
1155 +CONFIG_CRYPTO_DES=y
1156 +CONFIG_CRYPTO_DEFLATE=m
1157 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
1158 +# CONFIG_CRYPTO_HW is not set
1159 +CONFIG_CRC_ITU_T=y
1160 +CONFIG_LIBCRC32C=y
1161 diff --git a/arch/arm/configs/bcmrpi_emergency_defconfig b/arch/arm/configs/bcmrpi_emergency_defconfig
1162 new file mode 100644
1163 index 0000000..3b40c49
1164 --- /dev/null
1165 +++ b/arch/arm/configs/bcmrpi_emergency_defconfig
1166 @@ -0,0 +1,532 @@
1167 +CONFIG_EXPERIMENTAL=y
1168 +# CONFIG_LOCALVERSION_AUTO is not set
1169 +CONFIG_SYSVIPC=y
1170 +CONFIG_POSIX_MQUEUE=y
1171 +CONFIG_BSD_PROCESS_ACCT=y
1172 +CONFIG_BSD_PROCESS_ACCT_V3=y
1173 +CONFIG_FHANDLE=y
1174 +CONFIG_AUDIT=y
1175 +CONFIG_IKCONFIG=y
1176 +CONFIG_IKCONFIG_PROC=y
1177 +CONFIG_BLK_DEV_INITRD=y
1178 +CONFIG_INITRAMFS_SOURCE="../target_fs"
1179 +CONFIG_CGROUP_FREEZER=y
1180 +CONFIG_CGROUP_DEVICE=y
1181 +CONFIG_CGROUP_CPUACCT=y
1182 +CONFIG_RESOURCE_COUNTERS=y
1183 +CONFIG_BLK_CGROUP=y
1184 +CONFIG_NAMESPACES=y
1185 +CONFIG_SCHED_AUTOGROUP=y
1186 +CONFIG_EMBEDDED=y
1187 +# CONFIG_COMPAT_BRK is not set
1188 +CONFIG_SLAB=y
1189 +CONFIG_PROFILING=y
1190 +CONFIG_OPROFILE=m
1191 +CONFIG_KPROBES=y
1192 +CONFIG_MODULES=y
1193 +CONFIG_MODULE_UNLOAD=y
1194 +CONFIG_MODVERSIONS=y
1195 +CONFIG_MODULE_SRCVERSION_ALL=y
1196 +# CONFIG_BLK_DEV_BSG is not set
1197 +CONFIG_BLK_DEV_THROTTLING=y
1198 +CONFIG_CFQ_GROUP_IOSCHED=y
1199 +CONFIG_ARCH_BCM2708=y
1200 +CONFIG_NO_HZ=y
1201 +CONFIG_HIGH_RES_TIMERS=y
1202 +CONFIG_AEABI=y
1203 +CONFIG_SECCOMP=y
1204 +CONFIG_CC_STACKPROTECTOR=y
1205 +CONFIG_ZBOOT_ROM_TEXT=0x0
1206 +CONFIG_ZBOOT_ROM_BSS=0x0
1207 +CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait"
1208 +CONFIG_KEXEC=y
1209 +CONFIG_CPU_IDLE=y
1210 +CONFIG_VFP=y
1211 +CONFIG_BINFMT_MISC=m
1212 +CONFIG_NET=y
1213 +CONFIG_PACKET=y
1214 +CONFIG_UNIX=y
1215 +CONFIG_XFRM_USER=y
1216 +CONFIG_NET_KEY=m
1217 +CONFIG_INET=y
1218 +CONFIG_IP_MULTICAST=y
1219 +CONFIG_IP_PNP=y
1220 +CONFIG_IP_PNP_DHCP=y
1221 +CONFIG_IP_PNP_RARP=y
1222 +CONFIG_SYN_COOKIES=y
1223 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
1224 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
1225 +# CONFIG_INET_XFRM_MODE_BEET is not set
1226 +# CONFIG_INET_LRO is not set
1227 +# CONFIG_INET_DIAG is not set
1228 +# CONFIG_IPV6 is not set
1229 +CONFIG_NET_PKTGEN=m
1230 +CONFIG_IRDA=m
1231 +CONFIG_IRLAN=m
1232 +CONFIG_IRCOMM=m
1233 +CONFIG_IRDA_ULTRA=y
1234 +CONFIG_IRDA_CACHE_LAST_LSAP=y
1235 +CONFIG_IRDA_FAST_RR=y
1236 +CONFIG_IRTTY_SIR=m
1237 +CONFIG_KINGSUN_DONGLE=m
1238 +CONFIG_KSDAZZLE_DONGLE=m
1239 +CONFIG_KS959_DONGLE=m
1240 +CONFIG_USB_IRDA=m
1241 +CONFIG_SIGMATEL_FIR=m
1242 +CONFIG_MCS_FIR=m
1243 +CONFIG_BT=m
1244 +CONFIG_BT_L2CAP=y
1245 +CONFIG_BT_SCO=y
1246 +CONFIG_BT_RFCOMM=m
1247 +CONFIG_BT_RFCOMM_TTY=y
1248 +CONFIG_BT_BNEP=m
1249 +CONFIG_BT_BNEP_MC_FILTER=y
1250 +CONFIG_BT_BNEP_PROTO_FILTER=y
1251 +CONFIG_BT_HIDP=m
1252 +CONFIG_BT_HCIBTUSB=m
1253 +CONFIG_BT_HCIBCM203X=m
1254 +CONFIG_BT_HCIBPA10X=m
1255 +CONFIG_BT_HCIBFUSB=m
1256 +CONFIG_BT_HCIVHCI=m
1257 +CONFIG_BT_MRVL=m
1258 +CONFIG_BT_MRVL_SDIO=m
1259 +CONFIG_BT_ATH3K=m
1260 +CONFIG_CFG80211=m
1261 +CONFIG_MAC80211=m
1262 +CONFIG_MAC80211_RC_PID=y
1263 +CONFIG_MAC80211_MESH=y
1264 +CONFIG_WIMAX=m
1265 +CONFIG_NET_9P=m
1266 +CONFIG_NFC=m
1267 +CONFIG_NFC_PN533=m
1268 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
1269 +CONFIG_BLK_DEV_LOOP=y
1270 +CONFIG_BLK_DEV_CRYPTOLOOP=m
1271 +CONFIG_BLK_DEV_NBD=m
1272 +CONFIG_BLK_DEV_RAM=y
1273 +CONFIG_CDROM_PKTCDVD=m
1274 +CONFIG_MISC_DEVICES=y
1275 +CONFIG_SCSI=y
1276 +# CONFIG_SCSI_PROC_FS is not set
1277 +CONFIG_BLK_DEV_SD=y
1278 +CONFIG_BLK_DEV_SR=m
1279 +CONFIG_SCSI_MULTI_LUN=y
1280 +# CONFIG_SCSI_LOWLEVEL is not set
1281 +CONFIG_MD=y
1282 +CONFIG_NETDEVICES=y
1283 +CONFIG_TUN=m
1284 +CONFIG_PHYLIB=m
1285 +CONFIG_MDIO_BITBANG=m
1286 +CONFIG_NET_ETHERNET=y
1287 +# CONFIG_NETDEV_1000 is not set
1288 +# CONFIG_NETDEV_10000 is not set
1289 +CONFIG_LIBERTAS_THINFIRM=m
1290 +CONFIG_LIBERTAS_THINFIRM_USB=m
1291 +CONFIG_AT76C50X_USB=m
1292 +CONFIG_USB_ZD1201=m
1293 +CONFIG_USB_NET_RNDIS_WLAN=m
1294 +CONFIG_RTL8187=m
1295 +CONFIG_MAC80211_HWSIM=m
1296 +CONFIG_ATH_COMMON=m
1297 +CONFIG_ATH9K=m
1298 +CONFIG_ATH9K_HTC=m
1299 +CONFIG_CARL9170=m
1300 +CONFIG_B43=m
1301 +CONFIG_B43LEGACY=m
1302 +CONFIG_HOSTAP=m
1303 +CONFIG_IWM=m
1304 +CONFIG_LIBERTAS=m
1305 +CONFIG_LIBERTAS_USB=m
1306 +CONFIG_LIBERTAS_SDIO=m
1307 +CONFIG_P54_COMMON=m
1308 +CONFIG_P54_USB=m
1309 +CONFIG_RT2X00=m
1310 +CONFIG_RT2500USB=m
1311 +CONFIG_RT73USB=m
1312 +CONFIG_RT2800USB=m
1313 +CONFIG_RT2800USB_RT53XX=y
1314 +CONFIG_RTL8192CU=m
1315 +CONFIG_WL1251=m
1316 +CONFIG_WL12XX_MENU=m
1317 +CONFIG_ZD1211RW=m
1318 +CONFIG_MWIFIEX=m
1319 +CONFIG_MWIFIEX_SDIO=m
1320 +CONFIG_WIMAX_I2400M_USB=m
1321 +CONFIG_USB_CATC=m
1322 +CONFIG_USB_KAWETH=m
1323 +CONFIG_USB_PEGASUS=m
1324 +CONFIG_USB_RTL8150=m
1325 +CONFIG_USB_USBNET=y
1326 +CONFIG_USB_NET_AX8817X=m
1327 +CONFIG_USB_NET_CDCETHER=m
1328 +CONFIG_USB_NET_CDC_EEM=m
1329 +CONFIG_USB_NET_DM9601=m
1330 +CONFIG_USB_NET_SMSC75XX=m
1331 +CONFIG_USB_NET_SMSC95XX=y
1332 +CONFIG_USB_NET_GL620A=m
1333 +CONFIG_USB_NET_NET1080=m
1334 +CONFIG_USB_NET_PLUSB=m
1335 +CONFIG_USB_NET_MCS7830=m
1336 +CONFIG_USB_NET_CDC_SUBSET=m
1337 +CONFIG_USB_ALI_M5632=y
1338 +CONFIG_USB_AN2720=y
1339 +CONFIG_USB_KC2190=y
1340 +# CONFIG_USB_NET_ZAURUS is not set
1341 +CONFIG_USB_NET_CX82310_ETH=m
1342 +CONFIG_USB_NET_KALMIA=m
1343 +CONFIG_USB_NET_INT51X1=m
1344 +CONFIG_USB_IPHETH=m
1345 +CONFIG_USB_SIERRA_NET=m
1346 +CONFIG_USB_VL600=m
1347 +CONFIG_PPP=m
1348 +CONFIG_PPP_ASYNC=m
1349 +CONFIG_PPP_SYNC_TTY=m
1350 +CONFIG_PPP_DEFLATE=m
1351 +CONFIG_PPP_BSDCOMP=m
1352 +CONFIG_SLIP=m
1353 +CONFIG_SLIP_COMPRESSED=y
1354 +CONFIG_NETCONSOLE=m
1355 +CONFIG_INPUT_POLLDEV=m
1356 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
1357 +CONFIG_INPUT_JOYDEV=m
1358 +CONFIG_INPUT_EVDEV=m
1359 +# CONFIG_INPUT_KEYBOARD is not set
1360 +# CONFIG_INPUT_MOUSE is not set
1361 +CONFIG_INPUT_MISC=y
1362 +CONFIG_INPUT_AD714X=m
1363 +CONFIG_INPUT_ATI_REMOTE=m
1364 +CONFIG_INPUT_ATI_REMOTE2=m
1365 +CONFIG_INPUT_KEYSPAN_REMOTE=m
1366 +CONFIG_INPUT_POWERMATE=m
1367 +CONFIG_INPUT_YEALINK=m
1368 +CONFIG_INPUT_CM109=m
1369 +CONFIG_INPUT_UINPUT=m
1370 +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
1371 +CONFIG_INPUT_ADXL34X=m
1372 +CONFIG_INPUT_CMA3000=m
1373 +CONFIG_SERIO=m
1374 +CONFIG_SERIO_RAW=m
1375 +CONFIG_GAMEPORT=m
1376 +CONFIG_GAMEPORT_NS558=m
1377 +CONFIG_GAMEPORT_L4=m
1378 +CONFIG_VT_HW_CONSOLE_BINDING=y
1379 +# CONFIG_LEGACY_PTYS is not set
1380 +# CONFIG_DEVKMEM is not set
1381 +CONFIG_SERIAL_AMBA_PL011=y
1382 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
1383 +# CONFIG_HW_RANDOM is not set
1384 +CONFIG_RAW_DRIVER=y
1385 +CONFIG_GPIO_SYSFS=y
1386 +# CONFIG_HWMON is not set
1387 +CONFIG_WATCHDOG=y
1388 +CONFIG_BCM2708_WDT=m
1389 +# CONFIG_MFD_SUPPORT is not set
1390 +CONFIG_FB=y
1391 +CONFIG_FB_BCM2708=y
1392 +CONFIG_FRAMEBUFFER_CONSOLE=y
1393 +CONFIG_LOGO=y
1394 +# CONFIG_LOGO_LINUX_MONO is not set
1395 +# CONFIG_LOGO_LINUX_VGA16 is not set
1396 +CONFIG_SOUND=y
1397 +CONFIG_SND=m
1398 +CONFIG_SND_SEQUENCER=m
1399 +CONFIG_SND_SEQ_DUMMY=m
1400 +CONFIG_SND_MIXER_OSS=m
1401 +CONFIG_SND_PCM_OSS=m
1402 +CONFIG_SND_SEQUENCER_OSS=y
1403 +CONFIG_SND_HRTIMER=m
1404 +CONFIG_SND_DUMMY=m
1405 +CONFIG_SND_ALOOP=m
1406 +CONFIG_SND_VIRMIDI=m
1407 +CONFIG_SND_MTPAV=m
1408 +CONFIG_SND_SERIAL_U16550=m
1409 +CONFIG_SND_MPU401=m
1410 +CONFIG_SND_BCM2835=m
1411 +CONFIG_SND_USB_AUDIO=m
1412 +CONFIG_SND_USB_UA101=m
1413 +CONFIG_SND_USB_CAIAQ=m
1414 +CONFIG_SND_USB_6FIRE=m
1415 +CONFIG_SOUND_PRIME=m
1416 +CONFIG_HID_PID=y
1417 +CONFIG_USB_HIDDEV=y
1418 +CONFIG_HID_A4TECH=m
1419 +CONFIG_HID_ACRUX=m
1420 +CONFIG_HID_APPLE=m
1421 +CONFIG_HID_BELKIN=m
1422 +CONFIG_HID_CHERRY=m
1423 +CONFIG_HID_CHICONY=m
1424 +CONFIG_HID_CYPRESS=m
1425 +CONFIG_HID_DRAGONRISE=m
1426 +CONFIG_HID_EMS_FF=m
1427 +CONFIG_HID_ELECOM=m
1428 +CONFIG_HID_EZKEY=m
1429 +CONFIG_HID_HOLTEK=m
1430 +CONFIG_HID_KEYTOUCH=m
1431 +CONFIG_HID_KYE=m
1432 +CONFIG_HID_UCLOGIC=m
1433 +CONFIG_HID_WALTOP=m
1434 +CONFIG_HID_GYRATION=m
1435 +CONFIG_HID_TWINHAN=m
1436 +CONFIG_HID_KENSINGTON=m
1437 +CONFIG_HID_LCPOWER=m
1438 +CONFIG_HID_LOGITECH=m
1439 +CONFIG_HID_MAGICMOUSE=m
1440 +CONFIG_HID_MICROSOFT=m
1441 +CONFIG_HID_MONTEREY=m
1442 +CONFIG_HID_MULTITOUCH=m
1443 +CONFIG_HID_NTRIG=m
1444 +CONFIG_HID_ORTEK=m
1445 +CONFIG_HID_PANTHERLORD=m
1446 +CONFIG_HID_PETALYNX=m
1447 +CONFIG_HID_PICOLCD=m
1448 +CONFIG_HID_QUANTA=m
1449 +CONFIG_HID_ROCCAT=m
1450 +CONFIG_HID_SAMSUNG=m
1451 +CONFIG_HID_SONY=m
1452 +CONFIG_HID_SPEEDLINK=m
1453 +CONFIG_HID_SUNPLUS=m
1454 +CONFIG_HID_GREENASIA=m
1455 +CONFIG_HID_SMARTJOYPLUS=m
1456 +CONFIG_HID_TOPSEED=m
1457 +CONFIG_HID_THRUSTMASTER=m
1458 +CONFIG_HID_WACOM=m
1459 +CONFIG_HID_WIIMOTE=m
1460 +CONFIG_HID_ZEROPLUS=m
1461 +CONFIG_HID_ZYDACRON=m
1462 +CONFIG_USB=y
1463 +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
1464 +CONFIG_USB_MON=m
1465 +CONFIG_USB_DWCOTG=y
1466 +CONFIG_USB_STORAGE=y
1467 +CONFIG_USB_STORAGE_REALTEK=m
1468 +CONFIG_USB_STORAGE_DATAFAB=m
1469 +CONFIG_USB_STORAGE_FREECOM=m
1470 +CONFIG_USB_STORAGE_ISD200=m
1471 +CONFIG_USB_STORAGE_USBAT=m
1472 +CONFIG_USB_STORAGE_SDDR09=m
1473 +CONFIG_USB_STORAGE_SDDR55=m
1474 +CONFIG_USB_STORAGE_JUMPSHOT=m
1475 +CONFIG_USB_STORAGE_ALAUDA=m
1476 +CONFIG_USB_STORAGE_ONETOUCH=m
1477 +CONFIG_USB_STORAGE_KARMA=m
1478 +CONFIG_USB_STORAGE_CYPRESS_ATACB=m
1479 +CONFIG_USB_STORAGE_ENE_UB6250=m
1480 +CONFIG_USB_UAS=y
1481 +CONFIG_USB_LIBUSUAL=y
1482 +CONFIG_USB_MDC800=m
1483 +CONFIG_USB_MICROTEK=m
1484 +CONFIG_USB_SERIAL=m
1485 +CONFIG_USB_SERIAL_GENERIC=y
1486 +CONFIG_USB_SERIAL_AIRCABLE=m
1487 +CONFIG_USB_SERIAL_ARK3116=m
1488 +CONFIG_USB_SERIAL_BELKIN=m
1489 +CONFIG_USB_SERIAL_CH341=m
1490 +CONFIG_USB_SERIAL_WHITEHEAT=m
1491 +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
1492 +CONFIG_USB_SERIAL_CP210X=m
1493 +CONFIG_USB_SERIAL_CYPRESS_M8=m
1494 +CONFIG_USB_SERIAL_EMPEG=m
1495 +CONFIG_USB_SERIAL_FTDI_SIO=m
1496 +CONFIG_USB_SERIAL_FUNSOFT=m
1497 +CONFIG_USB_SERIAL_VISOR=m
1498 +CONFIG_USB_SERIAL_IPAQ=m
1499 +CONFIG_USB_SERIAL_IR=m
1500 +CONFIG_USB_SERIAL_EDGEPORT=m
1501 +CONFIG_USB_SERIAL_EDGEPORT_TI=m
1502 +CONFIG_USB_SERIAL_GARMIN=m
1503 +CONFIG_USB_SERIAL_IPW=m
1504 +CONFIG_USB_SERIAL_IUU=m
1505 +CONFIG_USB_SERIAL_KEYSPAN_PDA=m
1506 +CONFIG_USB_SERIAL_KEYSPAN=m
1507 +CONFIG_USB_SERIAL_KLSI=m
1508 +CONFIG_USB_SERIAL_KOBIL_SCT=m
1509 +CONFIG_USB_SERIAL_MCT_U232=m
1510 +CONFIG_USB_SERIAL_MOS7720=m
1511 +CONFIG_USB_SERIAL_MOS7840=m
1512 +CONFIG_USB_SERIAL_MOTOROLA=m
1513 +CONFIG_USB_SERIAL_NAVMAN=m
1514 +CONFIG_USB_SERIAL_PL2303=m
1515 +CONFIG_USB_SERIAL_OTI6858=m
1516 +CONFIG_USB_SERIAL_QCAUX=m
1517 +CONFIG_USB_SERIAL_QUALCOMM=m
1518 +CONFIG_USB_SERIAL_SPCP8X5=m
1519 +CONFIG_USB_SERIAL_HP4X=m
1520 +CONFIG_USB_SERIAL_SAFE=m
1521 +CONFIG_USB_SERIAL_SIEMENS_MPI=m
1522 +CONFIG_USB_SERIAL_SIERRAWIRELESS=m
1523 +CONFIG_USB_SERIAL_SYMBOL=m
1524 +CONFIG_USB_SERIAL_TI=m
1525 +CONFIG_USB_SERIAL_CYBERJACK=m
1526 +CONFIG_USB_SERIAL_XIRCOM=m
1527 +CONFIG_USB_SERIAL_OPTION=m
1528 +CONFIG_USB_SERIAL_OMNINET=m
1529 +CONFIG_USB_SERIAL_OPTICON=m
1530 +CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m
1531 +CONFIG_USB_SERIAL_ZIO=m
1532 +CONFIG_USB_SERIAL_SSU100=m
1533 +CONFIG_USB_SERIAL_DEBUG=m
1534 +CONFIG_USB_EMI62=m
1535 +CONFIG_USB_EMI26=m
1536 +CONFIG_USB_ADUTUX=m
1537 +CONFIG_USB_SEVSEG=m
1538 +CONFIG_USB_RIO500=m
1539 +CONFIG_USB_LEGOTOWER=m
1540 +CONFIG_USB_LCD=m
1541 +CONFIG_USB_LED=m
1542 +CONFIG_USB_CYPRESS_CY7C63=m
1543 +CONFIG_USB_CYTHERM=m
1544 +CONFIG_USB_IDMOUSE=m
1545 +CONFIG_USB_FTDI_ELAN=m
1546 +CONFIG_USB_APPLEDISPLAY=m
1547 +CONFIG_USB_LD=m
1548 +CONFIG_USB_TRANCEVIBRATOR=m
1549 +CONFIG_USB_IOWARRIOR=m
1550 +CONFIG_USB_TEST=m
1551 +CONFIG_USB_ISIGHTFW=m
1552 +CONFIG_USB_YUREX=m
1553 +CONFIG_MMC=y
1554 +CONFIG_MMC_SDHCI=y
1555 +CONFIG_MMC_SDHCI_PLTFM=y
1556 +CONFIG_MMC_SDHCI_BCM2708=y
1557 +CONFIG_MMC_SDHCI_BCM2708_DMA=y
1558 +CONFIG_LEDS_GPIO=y
1559 +CONFIG_LEDS_TRIGGER_TIMER=m
1560 +CONFIG_LEDS_TRIGGER_HEARTBEAT=m
1561 +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
1562 +CONFIG_UIO=m
1563 +CONFIG_UIO_PDRV=m
1564 +CONFIG_UIO_PDRV_GENIRQ=m
1565 +# CONFIG_IOMMU_SUPPORT is not set
1566 +CONFIG_EXT4_FS=y
1567 +CONFIG_EXT4_FS_POSIX_ACL=y
1568 +CONFIG_EXT4_FS_SECURITY=y
1569 +CONFIG_REISERFS_FS=m
1570 +CONFIG_REISERFS_FS_XATTR=y
1571 +CONFIG_REISERFS_FS_POSIX_ACL=y
1572 +CONFIG_REISERFS_FS_SECURITY=y
1573 +CONFIG_JFS_FS=m
1574 +CONFIG_JFS_POSIX_ACL=y
1575 +CONFIG_JFS_SECURITY=y
1576 +CONFIG_JFS_STATISTICS=y
1577 +CONFIG_XFS_FS=m
1578 +CONFIG_XFS_QUOTA=y
1579 +CONFIG_XFS_POSIX_ACL=y
1580 +CONFIG_XFS_RT=y
1581 +CONFIG_GFS2_FS=m
1582 +CONFIG_OCFS2_FS=m
1583 +CONFIG_BTRFS_FS=m
1584 +CONFIG_BTRFS_FS_POSIX_ACL=y
1585 +CONFIG_NILFS2_FS=m
1586 +CONFIG_FANOTIFY=y
1587 +CONFIG_AUTOFS4_FS=y
1588 +CONFIG_FUSE_FS=m
1589 +CONFIG_CUSE=m
1590 +CONFIG_FSCACHE=y
1591 +CONFIG_FSCACHE_STATS=y
1592 +CONFIG_FSCACHE_HISTOGRAM=y
1593 +CONFIG_CACHEFILES=y
1594 +CONFIG_ISO9660_FS=m
1595 +CONFIG_JOLIET=y
1596 +CONFIG_ZISOFS=y
1597 +CONFIG_UDF_FS=m
1598 +CONFIG_MSDOS_FS=y
1599 +CONFIG_VFAT_FS=y
1600 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
1601 +CONFIG_NTFS_FS=m
1602 +CONFIG_TMPFS=y
1603 +CONFIG_TMPFS_POSIX_ACL=y
1604 +CONFIG_CONFIGFS_FS=y
1605 +CONFIG_SQUASHFS=m
1606 +CONFIG_SQUASHFS_XATTR=y
1607 +CONFIG_SQUASHFS_LZO=y
1608 +CONFIG_SQUASHFS_XZ=y
1609 +CONFIG_NFS_FS=y
1610 +CONFIG_NFS_V3=y
1611 +CONFIG_NFS_V3_ACL=y
1612 +CONFIG_NFS_V4=y
1613 +CONFIG_ROOT_NFS=y
1614 +CONFIG_NFS_FSCACHE=y
1615 +CONFIG_CIFS=m
1616 +CONFIG_CIFS_WEAK_PW_HASH=y
1617 +CONFIG_CIFS_XATTR=y
1618 +CONFIG_CIFS_POSIX=y
1619 +CONFIG_9P_FS=m
1620 +CONFIG_9P_FS_POSIX_ACL=y
1621 +CONFIG_PARTITION_ADVANCED=y
1622 +CONFIG_MAC_PARTITION=y
1623 +CONFIG_EFI_PARTITION=y
1624 +CONFIG_NLS_DEFAULT="utf8"
1625 +CONFIG_NLS_CODEPAGE_437=y
1626 +CONFIG_NLS_CODEPAGE_737=m
1627 +CONFIG_NLS_CODEPAGE_775=m
1628 +CONFIG_NLS_CODEPAGE_850=m
1629 +CONFIG_NLS_CODEPAGE_852=m
1630 +CONFIG_NLS_CODEPAGE_855=m
1631 +CONFIG_NLS_CODEPAGE_857=m
1632 +CONFIG_NLS_CODEPAGE_860=m
1633 +CONFIG_NLS_CODEPAGE_861=m
1634 +CONFIG_NLS_CODEPAGE_862=m
1635 +CONFIG_NLS_CODEPAGE_863=m
1636 +CONFIG_NLS_CODEPAGE_864=m
1637 +CONFIG_NLS_CODEPAGE_865=m
1638 +CONFIG_NLS_CODEPAGE_866=m
1639 +CONFIG_NLS_CODEPAGE_869=m
1640 +CONFIG_NLS_CODEPAGE_936=m
1641 +CONFIG_NLS_CODEPAGE_950=m
1642 +CONFIG_NLS_CODEPAGE_932=m
1643 +CONFIG_NLS_CODEPAGE_949=m
1644 +CONFIG_NLS_CODEPAGE_874=m
1645 +CONFIG_NLS_ISO8859_8=m
1646 +CONFIG_NLS_CODEPAGE_1250=m
1647 +CONFIG_NLS_CODEPAGE_1251=m
1648 +CONFIG_NLS_ASCII=y
1649 +CONFIG_NLS_ISO8859_1=m
1650 +CONFIG_NLS_ISO8859_2=m
1651 +CONFIG_NLS_ISO8859_3=m
1652 +CONFIG_NLS_ISO8859_4=m
1653 +CONFIG_NLS_ISO8859_5=m
1654 +CONFIG_NLS_ISO8859_6=m
1655 +CONFIG_NLS_ISO8859_7=m
1656 +CONFIG_NLS_ISO8859_9=m
1657 +CONFIG_NLS_ISO8859_13=m
1658 +CONFIG_NLS_ISO8859_14=m
1659 +CONFIG_NLS_ISO8859_15=m
1660 +CONFIG_NLS_KOI8_R=m
1661 +CONFIG_NLS_KOI8_U=m
1662 +CONFIG_NLS_UTF8=m
1663 +CONFIG_PRINTK_TIME=y
1664 +CONFIG_DETECT_HUNG_TASK=y
1665 +CONFIG_TIMER_STATS=y
1666 +CONFIG_DEBUG_STACK_USAGE=y
1667 +CONFIG_DEBUG_INFO=y
1668 +CONFIG_DEBUG_MEMORY_INIT=y
1669 +CONFIG_BOOT_PRINTK_DELAY=y
1670 +CONFIG_LATENCYTOP=y
1671 +CONFIG_SYSCTL_SYSCALL_CHECK=y
1672 +CONFIG_IRQSOFF_TRACER=y
1673 +CONFIG_SCHED_TRACER=y
1674 +CONFIG_STACK_TRACER=y
1675 +CONFIG_BLK_DEV_IO_TRACE=y
1676 +CONFIG_FUNCTION_PROFILER=y
1677 +CONFIG_KGDB=y
1678 +CONFIG_KGDB_KDB=y
1679 +CONFIG_KDB_KEYBOARD=y
1680 +CONFIG_STRICT_DEVMEM=y
1681 +CONFIG_CRYPTO_AUTHENC=m
1682 +CONFIG_CRYPTO_SEQIV=m
1683 +CONFIG_CRYPTO_CBC=y
1684 +CONFIG_CRYPTO_HMAC=y
1685 +CONFIG_CRYPTO_XCBC=m
1686 +CONFIG_CRYPTO_MD5=y
1687 +CONFIG_CRYPTO_SHA1=y
1688 +CONFIG_CRYPTO_SHA256=m
1689 +CONFIG_CRYPTO_SHA512=m
1690 +CONFIG_CRYPTO_TGR192=m
1691 +CONFIG_CRYPTO_WP512=m
1692 +CONFIG_CRYPTO_CAST5=m
1693 +CONFIG_CRYPTO_DES=y
1694 +CONFIG_CRYPTO_DEFLATE=m
1695 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
1696 +# CONFIG_CRYPTO_HW is not set
1697 +CONFIG_CRC_ITU_T=y
1698 +CONFIG_LIBCRC32C=y
1699 diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
1700 index 92f7b15..7b5ed03 100644
1701 --- a/arch/arm/kernel/process.c
1702 +++ b/arch/arm/kernel/process.c
1703 @@ -176,6 +176,16 @@ void arch_cpu_idle(void)
1704 default_idle();
1705 }
1706
1707 +char bcm2708_reboot_mode = 'h';
1708 +
1709 +int __init reboot_setup(char *str)
1710 +{
1711 + bcm2708_reboot_mode = str[0];
1712 + return 1;
1713 +}
1714 +
1715 +__setup("reboot=", reboot_setup);
1716 +
1717 /*
1718 * Called by kexec, immediately prior to machine_kexec().
1719 *
1720 diff --git a/arch/arm/mach-bcm2708/Kconfig b/arch/arm/mach-bcm2708/Kconfig
1721 new file mode 100644
1722 index 0000000..9355841
1723 --- /dev/null
1724 +++ b/arch/arm/mach-bcm2708/Kconfig
1725 @@ -0,0 +1,34 @@
1726 +menu "Broadcom BCM2708 Implementations"
1727 + depends on ARCH_BCM2708
1728 +
1729 +config MACH_BCM2708
1730 + bool "Broadcom BCM2708 Development Platform"
1731 + select NEED_MACH_MEMORY_H
1732 + select NEED_MACH_IO_H
1733 + select CPU_V6
1734 + help
1735 + Include support for the Broadcom(R) BCM2708 platform.
1736 +
1737 +config BCM2708_GPIO
1738 + bool "BCM2708 gpio support"
1739 + depends on MACH_BCM2708
1740 + select ARCH_REQUIRE_GPIOLIB
1741 + default y
1742 + help
1743 + Include support for the Broadcom(R) BCM2708 gpio.
1744 +
1745 +config BCM2708_VCMEM
1746 + bool "Videocore Memory"
1747 + depends on MACH_BCM2708
1748 + default y
1749 + help
1750 + Helper for videocore memory access and total size allocation.
1751 +
1752 +config BCM2708_NOL2CACHE
1753 + bool "Videocore L2 cache disable"
1754 + depends on MACH_BCM2708
1755 + default n
1756 + help
1757 + Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt.
1758 +
1759 +endmenu
1760 diff --git a/arch/arm/mach-bcm2708/Makefile b/arch/arm/mach-bcm2708/Makefile
1761 new file mode 100644
1762 index 0000000..a722f3f
1763 --- /dev/null
1764 +++ b/arch/arm/mach-bcm2708/Makefile
1765 @@ -0,0 +1,7 @@
1766 +#
1767 +# Makefile for the linux kernel.
1768 +#
1769 +
1770 +obj-$(CONFIG_MACH_BCM2708) += clock.o bcm2708.o armctrl.o vcio.o power.o dma.o
1771 +obj-$(CONFIG_BCM2708_GPIO) += bcm2708_gpio.o
1772 +obj-$(CONFIG_BCM2708_VCMEM) += vc_mem.o
1773 diff --git a/arch/arm/mach-bcm2708/Makefile.boot b/arch/arm/mach-bcm2708/Makefile.boot
1774 new file mode 100644
1775 index 0000000..67039c3
1776 --- /dev/null
1777 +++ b/arch/arm/mach-bcm2708/Makefile.boot
1778 @@ -0,0 +1,3 @@
1779 + zreladdr-y := 0x00008000
1780 +params_phys-y := 0x00000100
1781 +initrd_phys-y := 0x00800000
1782 diff --git a/arch/arm/mach-bcm2708/armctrl.c b/arch/arm/mach-bcm2708/armctrl.c
1783 new file mode 100644
1784 index 0000000..da18725
1785 --- /dev/null
1786 +++ b/arch/arm/mach-bcm2708/armctrl.c
1787 @@ -0,0 +1,208 @@
1788 +/*
1789 + * linux/arch/arm/mach-bcm2708/armctrl.c
1790 + *
1791 + * Copyright (C) 2010 Broadcom
1792 + *
1793 + * This program is free software; you can redistribute it and/or modify
1794 + * it under the terms of the GNU General Public License as published by
1795 + * the Free Software Foundation; either version 2 of the License, or
1796 + * (at your option) any later version.
1797 + *
1798 + * This program is distributed in the hope that it will be useful,
1799 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1800 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1801 + * GNU General Public License for more details.
1802 + *
1803 + * You should have received a copy of the GNU General Public License
1804 + * along with this program; if not, write to the Free Software
1805 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1806 + */
1807 +#include <linux/init.h>
1808 +#include <linux/list.h>
1809 +#include <linux/io.h>
1810 +#include <linux/version.h>
1811 +#include <linux/syscore_ops.h>
1812 +#include <linux/interrupt.h>
1813 +
1814 +#include <asm/mach/irq.h>
1815 +#include <mach/hardware.h>
1816 +#include "armctrl.h"
1817 +
1818 +/* For support of kernels >= 3.0 assume only one VIC for now*/
1819 +static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = {
1820 + INTERRUPT_VC_JPEG,
1821 + INTERRUPT_VC_USB,
1822 + INTERRUPT_VC_3D,
1823 + INTERRUPT_VC_DMA2,
1824 + INTERRUPT_VC_DMA3,
1825 + INTERRUPT_VC_I2C,
1826 + INTERRUPT_VC_SPI,
1827 + INTERRUPT_VC_I2SPCM,
1828 + INTERRUPT_VC_SDIO,
1829 + INTERRUPT_VC_UART,
1830 + INTERRUPT_VC_ARASANSDIO
1831 +};
1832 +
1833 +static void armctrl_mask_irq(struct irq_data *d)
1834 +{
1835 + static const unsigned int disables[4] = {
1836 + ARM_IRQ_DIBL1,
1837 + ARM_IRQ_DIBL2,
1838 + ARM_IRQ_DIBL3,
1839 + 0
1840 + };
1841 +
1842 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
1843 + writel(1 << (data & 0x1f), __io_address(disables[(data >> 5) & 0x3]));
1844 +}
1845 +
1846 +static void armctrl_unmask_irq(struct irq_data *d)
1847 +{
1848 + static const unsigned int enables[4] = {
1849 + ARM_IRQ_ENBL1,
1850 + ARM_IRQ_ENBL2,
1851 + ARM_IRQ_ENBL3,
1852 + 0
1853 + };
1854 +
1855 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
1856 + writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3]));
1857 +}
1858 +
1859 +#if defined(CONFIG_PM)
1860 +
1861 +/* for kernels 3.xx use the new syscore_ops apis but for older kernels use the sys dev class */
1862 +
1863 +/* Static defines
1864 + * struct armctrl_device - VIC PM device (< 3.xx)
1865 + * @sysdev: The system device which is registered. (< 3.xx)
1866 + * @irq: The IRQ number for the base of the VIC.
1867 + * @base: The register base for the VIC.
1868 + * @resume_sources: A bitmask of interrupts for resume.
1869 + * @resume_irqs: The IRQs enabled for resume.
1870 + * @int_select: Save for VIC_INT_SELECT.
1871 + * @int_enable: Save for VIC_INT_ENABLE.
1872 + * @soft_int: Save for VIC_INT_SOFT.
1873 + * @protect: Save for VIC_PROTECT.
1874 + */
1875 +struct armctrl_info {
1876 + void __iomem *base;
1877 + int irq;
1878 + u32 resume_sources;
1879 + u32 resume_irqs;
1880 + u32 int_select;
1881 + u32 int_enable;
1882 + u32 soft_int;
1883 + u32 protect;
1884 +} armctrl;
1885 +
1886 +static int armctrl_suspend(void)
1887 +{
1888 + return 0;
1889 +}
1890 +
1891 +static void armctrl_resume(void)
1892 +{
1893 + return;
1894 +}
1895 +
1896 +/**
1897 + * armctrl_pm_register - Register a VIC for later power management control
1898 + * @base: The base address of the VIC.
1899 + * @irq: The base IRQ for the VIC.
1900 + * @resume_sources: bitmask of interrupts allowed for resume sources.
1901 + *
1902 + * For older kernels (< 3.xx) do -
1903 + * Register the VIC with the system device tree so that it can be notified
1904 + * of suspend and resume requests and ensure that the correct actions are
1905 + * taken to re-instate the settings on resume.
1906 + */
1907 +static void __init armctrl_pm_register(void __iomem * base, unsigned int irq,
1908 + u32 resume_sources)
1909 +{
1910 + armctrl.base = base;
1911 + armctrl.resume_sources = resume_sources;
1912 + armctrl.irq = irq;
1913 +}
1914 +
1915 +static int armctrl_set_wake(struct irq_data *d, unsigned int on)
1916 +{
1917 + unsigned int off = d->irq & 31;
1918 + u32 bit = 1 << off;
1919 +
1920 + if (!(bit & armctrl.resume_sources))
1921 + return -EINVAL;
1922 +
1923 + if (on)
1924 + armctrl.resume_irqs |= bit;
1925 + else
1926 + armctrl.resume_irqs &= ~bit;
1927 +
1928 + return 0;
1929 +}
1930 +
1931 +#else
1932 +static inline void armctrl_pm_register(void __iomem * base, unsigned int irq,
1933 + u32 arg1)
1934 +{
1935 +}
1936 +
1937 +#define armctrl_suspend NULL
1938 +#define armctrl_resume NULL
1939 +#define armctrl_set_wake NULL
1940 +#endif /* CONFIG_PM */
1941 +
1942 +static struct syscore_ops armctrl_syscore_ops = {
1943 + .suspend = armctrl_suspend,
1944 + .resume = armctrl_resume,
1945 +};
1946 +
1947 +/**
1948 + * armctrl_syscore_init - initicall to register VIC pm functions
1949 + *
1950 + * This is called via late_initcall() to register
1951 + * the resources for the VICs due to the early
1952 + * nature of the VIC's registration.
1953 +*/
1954 +static int __init armctrl_syscore_init(void)
1955 +{
1956 + register_syscore_ops(&armctrl_syscore_ops);
1957 + return 0;
1958 +}
1959 +
1960 +late_initcall(armctrl_syscore_init);
1961 +
1962 +static struct irq_chip armctrl_chip = {
1963 + .name = "ARMCTRL",
1964 + .irq_ack = armctrl_mask_irq,
1965 + .irq_mask = armctrl_mask_irq,
1966 + .irq_unmask = armctrl_unmask_irq,
1967 + .irq_set_wake = armctrl_set_wake,
1968 +};
1969 +
1970 +/**
1971 + * armctrl_init - initialise a vectored interrupt controller
1972 + * @base: iomem base address
1973 + * @irq_start: starting interrupt number, must be muliple of 32
1974 + * @armctrl_sources: bitmask of interrupt sources to allow
1975 + * @resume_sources: bitmask of interrupt sources to allow for resume
1976 + */
1977 +int __init armctrl_init(void __iomem * base, unsigned int irq_start,
1978 + u32 armctrl_sources, u32 resume_sources)
1979 +{
1980 + unsigned int irq;
1981 +
1982 + for (irq = 0; irq < NR_IRQS; irq++) {
1983 + unsigned int data = irq;
1984 + if (irq >= INTERRUPT_JPEG && irq <= INTERRUPT_ARASANSDIO)
1985 + data = remap_irqs[irq - INTERRUPT_JPEG];
1986 +
1987 + irq_set_chip(irq, &armctrl_chip);
1988 + irq_set_chip_data(irq, (void *)data);
1989 + irq_set_handler(irq, handle_level_irq);
1990 + set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_DISABLED);
1991 + }
1992 +
1993 + armctrl_pm_register(base, irq_start, resume_sources);
1994 + return 0;
1995 +}
1996 diff --git a/arch/arm/mach-bcm2708/armctrl.h b/arch/arm/mach-bcm2708/armctrl.h
1997 new file mode 100644
1998 index 0000000..0aa916e
1999 --- /dev/null
2000 +++ b/arch/arm/mach-bcm2708/armctrl.h
2001 @@ -0,0 +1,27 @@
2002 +/*
2003 + * linux/arch/arm/mach-bcm2708/armctrl.h
2004 + *
2005 + * Copyright (C) 2010 Broadcom
2006 + *
2007 + * This program is free software; you can redistribute it and/or modify
2008 + * it under the terms of the GNU General Public License as published by
2009 + * the Free Software Foundation; either version 2 of the License, or
2010 + * (at your option) any later version.
2011 + *
2012 + * This program is distributed in the hope that it will be useful,
2013 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2014 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2015 + * GNU General Public License for more details.
2016 + *
2017 + * You should have received a copy of the GNU General Public License
2018 + * along with this program; if not, write to the Free Software
2019 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2020 + */
2021 +
2022 +#ifndef __BCM2708_ARMCTRL_H
2023 +#define __BCM2708_ARMCTRL_H
2024 +
2025 +extern int __init armctrl_init(void __iomem * base, unsigned int irq_start,
2026 + u32 armctrl_sources, u32 resume_sources);
2027 +
2028 +#endif
2029 diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c
2030 new file mode 100644
2031 index 0000000..a5af6ec
2032 --- /dev/null
2033 +++ b/arch/arm/mach-bcm2708/bcm2708.c
2034 @@ -0,0 +1,720 @@
2035 +/*
2036 + * linux/arch/arm/mach-bcm2708/bcm2708.c
2037 + *
2038 + * Copyright (C) 2010 Broadcom
2039 + *
2040 + * This program is free software; you can redistribute it and/or modify
2041 + * it under the terms of the GNU General Public License as published by
2042 + * the Free Software Foundation; either version 2 of the License, or
2043 + * (at your option) any later version.
2044 + *
2045 + * This program is distributed in the hope that it will be useful,
2046 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2047 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2048 + * GNU General Public License for more details.
2049 + *
2050 + * You should have received a copy of the GNU General Public License
2051 + * along with this program; if not, write to the Free Software
2052 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2053 + */
2054 +
2055 +#include <linux/init.h>
2056 +#include <linux/device.h>
2057 +#include <linux/dma-mapping.h>
2058 +#include <linux/serial_8250.h>
2059 +#include <linux/platform_device.h>
2060 +#include <linux/syscore_ops.h>
2061 +#include <linux/interrupt.h>
2062 +#include <linux/amba/bus.h>
2063 +#include <linux/amba/clcd.h>
2064 +#include <linux/clockchips.h>
2065 +#include <linux/cnt32_to_63.h>
2066 +#include <linux/io.h>
2067 +#include <linux/module.h>
2068 +
2069 +#include <linux/version.h>
2070 +#include <linux/clkdev.h>
2071 +#include <asm/system.h>
2072 +#include <mach/hardware.h>
2073 +#include <asm/irq.h>
2074 +#include <linux/leds.h>
2075 +#include <asm/mach-types.h>
2076 +#include <linux/sched_clock.h>
2077 +
2078 +#include <asm/mach/arch.h>
2079 +#include <asm/mach/flash.h>
2080 +#include <asm/mach/irq.h>
2081 +#include <asm/mach/time.h>
2082 +#include <asm/mach/map.h>
2083 +
2084 +#include <mach/timex.h>
2085 +#include <mach/dma.h>
2086 +#include <mach/vcio.h>
2087 +#include <mach/system.h>
2088 +
2089 +#include <linux/delay.h>
2090 +
2091 +#include "bcm2708.h"
2092 +#include "armctrl.h"
2093 +#include "clock.h"
2094 +
2095 +#ifdef CONFIG_BCM_VC_CMA
2096 +#include <linux/broadcom/vc_cma.h>
2097 +#endif
2098 +
2099 +
2100 +/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to
2101 + * give us IO access only to 64Mbytes of physical memory (26 bits). We could
2102 + * represent this window by setting our dmamasks to 26 bits but, in fact
2103 + * we're not going to use addresses outside this range (they're not in real
2104 + * memory) so we don't bother.
2105 + *
2106 + * In the future we might include code to use this IOMMU to remap other
2107 + * physical addresses onto VideoCore memory then the use of 32-bits would be
2108 + * more legitimate.
2109 + */
2110 +#define DMA_MASK_BITS_COMMON 32
2111 +
2112 +/* command line parameters */
2113 +static unsigned boardrev, serial;
2114 +static unsigned uart_clock;
2115 +static unsigned disk_led_gpio = 16;
2116 +static unsigned disk_led_active_low = 1;
2117 +static unsigned reboot_part = 0;
2118 +
2119 +static void __init bcm2708_init_led(void);
2120 +
2121 +void __init bcm2708_init_irq(void)
2122 +{
2123 + armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0);
2124 +}
2125 +
2126 +static struct map_desc bcm2708_io_desc[] __initdata = {
2127 + {
2128 + .virtual = IO_ADDRESS(ARMCTRL_BASE),
2129 + .pfn = __phys_to_pfn(ARMCTRL_BASE),
2130 + .length = SZ_4K,
2131 + .type = MT_DEVICE},
2132 + {
2133 + .virtual = IO_ADDRESS(UART0_BASE),
2134 + .pfn = __phys_to_pfn(UART0_BASE),
2135 + .length = SZ_4K,
2136 + .type = MT_DEVICE},
2137 + {
2138 + .virtual = IO_ADDRESS(UART1_BASE),
2139 + .pfn = __phys_to_pfn(UART1_BASE),
2140 + .length = SZ_4K,
2141 + .type = MT_DEVICE},
2142 + {
2143 + .virtual = IO_ADDRESS(DMA_BASE),
2144 + .pfn = __phys_to_pfn(DMA_BASE),
2145 + .length = SZ_4K,
2146 + .type = MT_DEVICE},
2147 + {
2148 + .virtual = IO_ADDRESS(MCORE_BASE),
2149 + .pfn = __phys_to_pfn(MCORE_BASE),
2150 + .length = SZ_4K,
2151 + .type = MT_DEVICE},
2152 + {
2153 + .virtual = IO_ADDRESS(ST_BASE),
2154 + .pfn = __phys_to_pfn(ST_BASE),
2155 + .length = SZ_4K,
2156 + .type = MT_DEVICE},
2157 + {
2158 + .virtual = IO_ADDRESS(USB_BASE),
2159 + .pfn = __phys_to_pfn(USB_BASE),
2160 + .length = SZ_128K,
2161 + .type = MT_DEVICE},
2162 + {
2163 + .virtual = IO_ADDRESS(PM_BASE),
2164 + .pfn = __phys_to_pfn(PM_BASE),
2165 + .length = SZ_4K,
2166 + .type = MT_DEVICE},
2167 + {
2168 + .virtual = IO_ADDRESS(GPIO_BASE),
2169 + .pfn = __phys_to_pfn(GPIO_BASE),
2170 + .length = SZ_4K,
2171 + .type = MT_DEVICE}
2172 +};
2173 +
2174 +void __init bcm2708_map_io(void)
2175 +{
2176 + iotable_init(bcm2708_io_desc, ARRAY_SIZE(bcm2708_io_desc));
2177 +}
2178 +
2179 +/* The STC is a free running counter that increments at the rate of 1MHz */
2180 +#define STC_FREQ_HZ 1000000
2181 +
2182 +static inline uint32_t timer_read(void)
2183 +{
2184 + /* STC: a free running counter that increments at the rate of 1MHz */
2185 + return readl(__io_address(ST_BASE + 0x04));
2186 +}
2187 +
2188 +static unsigned long bcm2708_read_current_timer(void)
2189 +{
2190 + return timer_read();
2191 +}
2192 +
2193 +static u32 notrace bcm2708_read_sched_clock(void)
2194 +{
2195 + return timer_read();
2196 +}
2197 +
2198 +static cycle_t clksrc_read(struct clocksource *cs)
2199 +{
2200 + return timer_read();
2201 +}
2202 +
2203 +static struct clocksource clocksource_stc = {
2204 + .name = "stc",
2205 + .rating = 300,
2206 + .read = clksrc_read,
2207 + .mask = CLOCKSOURCE_MASK(32),
2208 + .flags = CLOCK_SOURCE_IS_CONTINUOUS,
2209 +};
2210 +
2211 +unsigned long frc_clock_ticks32(void)
2212 +{
2213 + return timer_read();
2214 +}
2215 +
2216 +static void __init bcm2708_clocksource_init(void)
2217 +{
2218 + if (clocksource_register_hz(&clocksource_stc, STC_FREQ_HZ)) {
2219 + printk(KERN_ERR "timer: failed to initialize clock "
2220 + "source %s\n", clocksource_stc.name);
2221 + }
2222 +}
2223 +
2224 +
2225 +/*
2226 + * These are fixed clocks.
2227 + */
2228 +static struct clk ref24_clk = {
2229 + .rate = UART0_CLOCK, /* The UART is clocked at 3MHz via APB_CLK */
2230 +};
2231 +
2232 +static struct clk osc_clk = {
2233 +#ifdef CONFIG_ARCH_BCM2708_CHIPIT
2234 + .rate = 27000000,
2235 +#else
2236 + .rate = 500000000, /* ARM clock is set from the VideoCore booter */
2237 +#endif
2238 +};
2239 +
2240 +/* warning - the USB needs a clock > 34MHz */
2241 +
2242 +#ifdef CONFIG_MMC_BCM2708
2243 +static struct clk sdhost_clk = {
2244 +#ifdef CONFIG_ARCH_BCM2708_CHIPIT
2245 + .rate = 4000000, /* 4MHz */
2246 +#else
2247 + .rate = 250000000, /* 250MHz */
2248 +#endif
2249 +};
2250 +#endif
2251 +
2252 +static struct clk_lookup lookups[] = {
2253 + { /* UART0 */
2254 + .dev_id = "dev:f1",
2255 + .clk = &ref24_clk,
2256 + },
2257 + { /* USB */
2258 + .dev_id = "bcm2708_usb",
2259 + .clk = &osc_clk,
2260 + }
2261 +};
2262 +
2263 +#define UART0_IRQ { IRQ_UART, 0 /*NO_IRQ*/ }
2264 +#define UART0_DMA { 15, 14 }
2265 +
2266 +AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
2267 +
2268 +static struct amba_device *amba_devs[] __initdata = {
2269 + &uart0_device,
2270 +};
2271 +
2272 +static struct resource bcm2708_dmaman_resources[] = {
2273 + {
2274 + .start = DMA_BASE,
2275 + .end = DMA_BASE + SZ_4K - 1,
2276 + .flags = IORESOURCE_MEM,
2277 + }
2278 +};
2279 +
2280 +static struct platform_device bcm2708_dmaman_device = {
2281 + .name = BCM_DMAMAN_DRIVER_NAME,
2282 + .id = 0, /* first bcm2708_dma */
2283 + .resource = bcm2708_dmaman_resources,
2284 + .num_resources = ARRAY_SIZE(bcm2708_dmaman_resources),
2285 +};
2286 +
2287 +static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2288 +
2289 +static struct platform_device bcm2708_fb_device = {
2290 + .name = "bcm2708_fb",
2291 + .id = -1, /* only one bcm2708_fb */
2292 + .resource = NULL,
2293 + .num_resources = 0,
2294 + .dev = {
2295 + .dma_mask = &fb_dmamask,
2296 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
2297 + },
2298 +};
2299 +
2300 +static struct plat_serial8250_port bcm2708_uart1_platform_data[] = {
2301 + {
2302 + .mapbase = UART1_BASE + 0x40,
2303 + .irq = IRQ_AUX,
2304 + .uartclk = 125000000,
2305 + .regshift = 2,
2306 + .iotype = UPIO_MEM,
2307 + .flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_SKIP_TEST,
2308 + .type = PORT_8250,
2309 + },
2310 + {},
2311 +};
2312 +
2313 +static struct platform_device bcm2708_uart1_device = {
2314 + .name = "serial8250",
2315 + .id = PLAT8250_DEV_PLATFORM,
2316 + .dev = {
2317 + .platform_data = bcm2708_uart1_platform_data,
2318 + },
2319 +};
2320 +
2321 +static struct resource bcm2708_usb_resources[] = {
2322 + [0] = {
2323 + .start = USB_BASE,
2324 + .end = USB_BASE + SZ_128K - 1,
2325 + .flags = IORESOURCE_MEM,
2326 + },
2327 + [1] = {
2328 + .start = IRQ_USB,
2329 + .end = IRQ_USB,
2330 + .flags = IORESOURCE_IRQ,
2331 + },
2332 +};
2333 +
2334 +static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2335 +
2336 +static struct platform_device bcm2708_usb_device = {
2337 + .name = "bcm2708_usb",
2338 + .id = -1, /* only one bcm2708_usb */
2339 + .resource = bcm2708_usb_resources,
2340 + .num_resources = ARRAY_SIZE(bcm2708_usb_resources),
2341 + .dev = {
2342 + .dma_mask = &usb_dmamask,
2343 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
2344 + },
2345 +};
2346 +
2347 +static struct resource bcm2708_vcio_resources[] = {
2348 + [0] = { /* mailbox/semaphore/doorbell access */
2349 + .start = MCORE_BASE,
2350 + .end = MCORE_BASE + SZ_4K - 1,
2351 + .flags = IORESOURCE_MEM,
2352 + },
2353 +};
2354 +
2355 +static u64 vcio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2356 +
2357 +static struct platform_device bcm2708_vcio_device = {
2358 + .name = BCM_VCIO_DRIVER_NAME,
2359 + .id = -1, /* only one VideoCore I/O area */
2360 + .resource = bcm2708_vcio_resources,
2361 + .num_resources = ARRAY_SIZE(bcm2708_vcio_resources),
2362 + .dev = {
2363 + .dma_mask = &vcio_dmamask,
2364 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
2365 + },
2366 +};
2367 +
2368 +#ifdef CONFIG_BCM2708_GPIO
2369 +#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio"
2370 +
2371 +static struct resource bcm2708_gpio_resources[] = {
2372 + [0] = { /* general purpose I/O */
2373 + .start = GPIO_BASE,
2374 + .end = GPIO_BASE + SZ_4K - 1,
2375 + .flags = IORESOURCE_MEM,
2376 + },
2377 +};
2378 +
2379 +static u64 gpio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2380 +
2381 +static struct platform_device bcm2708_gpio_device = {
2382 + .name = BCM_GPIO_DRIVER_NAME,
2383 + .id = -1, /* only one VideoCore I/O area */
2384 + .resource = bcm2708_gpio_resources,
2385 + .num_resources = ARRAY_SIZE(bcm2708_gpio_resources),
2386 + .dev = {
2387 + .dma_mask = &gpio_dmamask,
2388 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
2389 + },
2390 +};
2391 +#endif
2392 +
2393 +static struct resource bcm2708_systemtimer_resources[] = {
2394 + [0] = { /* system timer access */
2395 + .start = ST_BASE,
2396 + .end = ST_BASE + SZ_4K - 1,
2397 + .flags = IORESOURCE_MEM,
2398 + },
2399 + {
2400 + .start = IRQ_TIMER3,
2401 + .end = IRQ_TIMER3,
2402 + .flags = IORESOURCE_IRQ,
2403 + }
2404 +
2405 +};
2406 +
2407 +static u64 systemtimer_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2408 +
2409 +static struct platform_device bcm2708_systemtimer_device = {
2410 + .name = "bcm2708_systemtimer",
2411 + .id = -1, /* only one VideoCore I/O area */
2412 + .resource = bcm2708_systemtimer_resources,
2413 + .num_resources = ARRAY_SIZE(bcm2708_systemtimer_resources),
2414 + .dev = {
2415 + .dma_mask = &systemtimer_dmamask,
2416 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
2417 + },
2418 +};
2419 +
2420 +#ifdef CONFIG_MMC_SDHCI_BCM2708 /* Arasan emmc SD */
2421 +static struct resource bcm2708_emmc_resources[] = {
2422 + [0] = {
2423 + .start = EMMC_BASE,
2424 + .end = EMMC_BASE + SZ_256 - 1, /* we only need this area */
2425 + /* the memory map actually makes SZ_4K available */
2426 + .flags = IORESOURCE_MEM,
2427 + },
2428 + [1] = {
2429 + .start = IRQ_ARASANSDIO,
2430 + .end = IRQ_ARASANSDIO,
2431 + .flags = IORESOURCE_IRQ,
2432 + },
2433 +};
2434 +
2435 +static u64 bcm2708_emmc_dmamask = 0xffffffffUL;
2436 +
2437 +struct platform_device bcm2708_emmc_device = {
2438 + .name = "bcm2708_sdhci",
2439 + .id = 0,
2440 + .num_resources = ARRAY_SIZE(bcm2708_emmc_resources),
2441 + .resource = bcm2708_emmc_resources,
2442 + .dev = {
2443 + .dma_mask = &bcm2708_emmc_dmamask,
2444 + .coherent_dma_mask = 0xffffffffUL},
2445 +};
2446 +#endif /* CONFIG_MMC_SDHCI_BCM2708 */
2447 +
2448 +static struct resource bcm2708_powerman_resources[] = {
2449 + [0] = {
2450 + .start = PM_BASE,
2451 + .end = PM_BASE + SZ_256 - 1,
2452 + .flags = IORESOURCE_MEM,
2453 + },
2454 +};
2455 +
2456 +static u64 powerman_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2457 +
2458 +struct platform_device bcm2708_powerman_device = {
2459 + .name = "bcm2708_powerman",
2460 + .id = 0,
2461 + .num_resources = ARRAY_SIZE(bcm2708_powerman_resources),
2462 + .resource = bcm2708_powerman_resources,
2463 + .dev = {
2464 + .dma_mask = &powerman_dmamask,
2465 + .coherent_dma_mask = 0xffffffffUL},
2466 +};
2467 +
2468 +int __init bcm_register_device(struct platform_device *pdev)
2469 +{
2470 + int ret;
2471 +
2472 + ret = platform_device_register(pdev);
2473 + if (ret)
2474 + pr_debug("Unable to register platform device '%s': %d\n",
2475 + pdev->name, ret);
2476 +
2477 + return ret;
2478 +}
2479 +
2480 +int calc_rsts(int partition)
2481 +{
2482 + return PM_PASSWORD |
2483 + ((partition & (1 << 0)) << 0) |
2484 + ((partition & (1 << 1)) << 1) |
2485 + ((partition & (1 << 2)) << 2) |
2486 + ((partition & (1 << 3)) << 3) |
2487 + ((partition & (1 << 4)) << 4) |
2488 + ((partition & (1 << 5)) << 5);
2489 +}
2490 +
2491 +static void bcm2708_restart(enum reboot_mode mode, const char *cmd)
2492 +{
2493 + extern char bcm2708_reboot_mode;
2494 + uint32_t pm_rstc, pm_wdog;
2495 + uint32_t timeout = 10;
2496 + uint32_t pm_rsts = 0;
2497 +
2498 + if(bcm2708_reboot_mode == 'q')
2499 + {
2500 + // NOOBS < 1.3 booting with reboot=q
2501 + pm_rsts = readl(__io_address(PM_RSTS));
2502 + pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRQ_SET;
2503 + }
2504 + else if(bcm2708_reboot_mode == 'p')
2505 + {
2506 + // NOOBS < 1.3 halting
2507 + pm_rsts = readl(__io_address(PM_RSTS));
2508 + pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRH_SET;
2509 + }
2510 + else
2511 + {
2512 + pm_rsts = calc_rsts(reboot_part);
2513 + }
2514 +
2515 + writel(pm_rsts, __io_address(PM_RSTS));
2516 +
2517 + /* Setup watchdog for reset */
2518 + pm_rstc = readl(__io_address(PM_RSTC));
2519 +
2520 + pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0)
2521 + pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET;
2522 +
2523 + writel(pm_wdog, __io_address(PM_WDOG));
2524 + writel(pm_rstc, __io_address(PM_RSTC));
2525 +}
2526 +
2527 +/* We can't really power off, but if we do the normal reset scheme, and indicate to bootcode.bin not to reboot, then most of the chip will be powered off */
2528 +static void bcm2708_power_off(void)
2529 +{
2530 + extern char bcm2708_reboot_mode;
2531 + if(bcm2708_reboot_mode == 'q')
2532 + {
2533 + // NOOBS < v1.3
2534 + bcm2708_restart('p', "");
2535 + }
2536 + else
2537 + {
2538 + /* partition 63 is special code for HALT the bootloader knows not to boot*/
2539 + reboot_part = 63;
2540 + /* continue with normal reset mechanism */
2541 + bcm2708_restart(0, "");
2542 + }
2543 +}
2544 +
2545 +void __init bcm2708_init(void)
2546 +{
2547 + int i;
2548 +
2549 +#if defined(CONFIG_BCM_VC_CMA)
2550 + vc_cma_early_init();
2551 +#endif
2552 + printk("bcm2708.uart_clock = %d\n", uart_clock);
2553 + pm_power_off = bcm2708_power_off;
2554 +
2555 + if (uart_clock)
2556 + lookups[0].clk->rate = uart_clock;
2557 +
2558 + for (i = 0; i < ARRAY_SIZE(lookups); i++)
2559 + clkdev_add(&lookups[i]);
2560 +
2561 + bcm_register_device(&bcm2708_dmaman_device);
2562 + bcm_register_device(&bcm2708_vcio_device);
2563 +#ifdef CONFIG_BCM2708_GPIO
2564 + bcm_register_device(&bcm2708_gpio_device);
2565 +#endif
2566 + bcm_register_device(&bcm2708_systemtimer_device);
2567 + bcm_register_device(&bcm2708_fb_device);
2568 + bcm_register_device(&bcm2708_usb_device);
2569 + bcm_register_device(&bcm2708_uart1_device);
2570 + bcm_register_device(&bcm2708_powerman_device);
2571 +
2572 +#ifdef CONFIG_MMC_SDHCI_BCM2708
2573 + bcm_register_device(&bcm2708_emmc_device);
2574 +#endif
2575 + bcm2708_init_led();
2576 +
2577 + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
2578 + struct amba_device *d = amba_devs[i];
2579 + amba_device_register(d, &iomem_resource);
2580 + }
2581 + system_rev = boardrev;
2582 + system_serial_low = serial;
2583 +}
2584 +
2585 +static void timer_set_mode(enum clock_event_mode mode,
2586 + struct clock_event_device *clk)
2587 +{
2588 + switch (mode) {
2589 + case CLOCK_EVT_MODE_ONESHOT: /* Leave the timer disabled, .set_next_event will enable it */
2590 + case CLOCK_EVT_MODE_SHUTDOWN:
2591 + break;
2592 + case CLOCK_EVT_MODE_PERIODIC:
2593 +
2594 + case CLOCK_EVT_MODE_UNUSED:
2595 + case CLOCK_EVT_MODE_RESUME:
2596 +
2597 + default:
2598 + printk(KERN_ERR "timer_set_mode: unhandled mode:%d\n",
2599 + (int)mode);
2600 + break;
2601 + }
2602 +
2603 +}
2604 +
2605 +static int timer_set_next_event(unsigned long cycles,
2606 + struct clock_event_device *unused)
2607 +{
2608 + unsigned long stc;
2609 + do {
2610 + stc = readl(__io_address(ST_BASE + 0x04));
2611 + /* We could take a FIQ here, which may push ST above STC3 */
2612 + writel(stc + cycles, __io_address(ST_BASE + 0x18));
2613 + } while ((signed long) (readl(__io_address(ST_BASE + 0x04)) - stc)
2614 + >= (signed long) cycles);
2615 + return 0;
2616 +}
2617 +
2618 +static struct clock_event_device timer0_clockevent = {
2619 + .name = "timer0",
2620 + .shift = 32,
2621 + .features = CLOCK_EVT_FEAT_ONESHOT,
2622 + .set_mode = timer_set_mode,
2623 + .set_next_event = timer_set_next_event,
2624 +};
2625 +
2626 +/*
2627 + * IRQ handler for the timer
2628 + */
2629 +static irqreturn_t bcm2708_timer_interrupt(int irq, void *dev_id)
2630 +{
2631 + struct clock_event_device *evt = &timer0_clockevent;
2632 +
2633 + writel(1 << 3, __io_address(ST_BASE + 0x00)); /* stcs clear timer int */
2634 +
2635 + evt->event_handler(evt);
2636 +
2637 + return IRQ_HANDLED;
2638 +}
2639 +
2640 +static struct irqaction bcm2708_timer_irq = {
2641 + .name = "BCM2708 Timer Tick",
2642 + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
2643 + .handler = bcm2708_timer_interrupt,
2644 +};
2645 +
2646 +/*
2647 + * Set up timer interrupt, and return the current time in seconds.
2648 + */
2649 +
2650 +static struct delay_timer bcm2708_delay_timer = {
2651 + .read_current_timer = bcm2708_read_current_timer,
2652 + .freq = STC_FREQ_HZ,
2653 +};
2654 +
2655 +static void __init bcm2708_timer_init(void)
2656 +{
2657 + /* init high res timer */
2658 + bcm2708_clocksource_init();
2659 +
2660 + /*
2661 + * Initialise to a known state (all timers off)
2662 + */
2663 + writel(0, __io_address(ARM_T_CONTROL));
2664 + /*
2665 + * Make irqs happen for the system timer
2666 + */
2667 + setup_irq(IRQ_TIMER3, &bcm2708_timer_irq);
2668 +
2669 + setup_sched_clock(bcm2708_read_sched_clock, 32, STC_FREQ_HZ);
2670 +
2671 + timer0_clockevent.mult =
2672 + div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift);
2673 + timer0_clockevent.max_delta_ns =
2674 + clockevent_delta2ns(0xffffffff, &timer0_clockevent);
2675 + timer0_clockevent.min_delta_ns =
2676 + clockevent_delta2ns(0xf, &timer0_clockevent);
2677 +
2678 + timer0_clockevent.cpumask = cpumask_of(0);
2679 + clockevents_register_device(&timer0_clockevent);
2680 +
2681 + register_current_timer_delay(&bcm2708_delay_timer);
2682 +}
2683 +
2684 +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
2685 +#include <linux/leds.h>
2686 +
2687 +static struct gpio_led bcm2708_leds[] = {
2688 + [0] = {
2689 + .gpio = 16,
2690 + .name = "led0",
2691 + .default_trigger = "mmc0",
2692 + .active_low = 1,
2693 + },
2694 +};
2695 +
2696 +static struct gpio_led_platform_data bcm2708_led_pdata = {
2697 + .num_leds = ARRAY_SIZE(bcm2708_leds),
2698 + .leds = bcm2708_leds,
2699 +};
2700 +
2701 +static struct platform_device bcm2708_led_device = {
2702 + .name = "leds-gpio",
2703 + .id = -1,
2704 + .dev = {
2705 + .platform_data = &bcm2708_led_pdata,
2706 + },
2707 +};
2708 +
2709 +static void __init bcm2708_init_led(void)
2710 +{
2711 + bcm2708_leds[0].gpio = disk_led_gpio;
2712 + bcm2708_leds[0].active_low = disk_led_active_low;
2713 + platform_device_register(&bcm2708_led_device);
2714 +}
2715 +#else
2716 +static inline void bcm2708_init_led(void)
2717 +{
2718 +}
2719 +#endif
2720 +
2721 +void __init bcm2708_init_early(void)
2722 +{
2723 + /*
2724 + * Some devices allocate their coherent buffers from atomic
2725 + * context. Increase size of atomic coherent pool to make sure such
2726 + * the allocations won't fail.
2727 + */
2728 + init_dma_coherent_pool_size(SZ_4M);
2729 +}
2730 +
2731 +static void __init board_reserve(void)
2732 +{
2733 +#if defined(CONFIG_BCM_VC_CMA)
2734 + vc_cma_reserve();
2735 +#endif
2736 +}
2737 +
2738 +MACHINE_START(BCM2708, "BCM2708")
2739 + /* Maintainer: Broadcom Europe Ltd. */
2740 + .map_io = bcm2708_map_io,
2741 + .init_irq = bcm2708_init_irq,
2742 + .init_time = bcm2708_timer_init,
2743 + .init_machine = bcm2708_init,
2744 + .init_early = bcm2708_init_early,
2745 + .reserve = board_reserve,
2746 + .restart = bcm2708_restart,
2747 +MACHINE_END
2748 +
2749 +module_param(boardrev, uint, 0644);
2750 +module_param(serial, uint, 0644);
2751 +module_param(uart_clock, uint, 0644);
2752 +module_param(disk_led_gpio, uint, 0644);
2753 +module_param(disk_led_active_low, uint, 0644);
2754 +module_param(reboot_part, uint, 0644);
2755 diff --git a/arch/arm/mach-bcm2708/bcm2708.h b/arch/arm/mach-bcm2708/bcm2708.h
2756 new file mode 100644
2757 index 0000000..e339a93
2758 --- /dev/null
2759 +++ b/arch/arm/mach-bcm2708/bcm2708.h
2760 @@ -0,0 +1,49 @@
2761 +/*
2762 + * linux/arch/arm/mach-bcm2708/bcm2708.h
2763 + *
2764 + * BCM2708 machine support header
2765 + *
2766 + * Copyright (C) 2010 Broadcom
2767 + *
2768 + * This program is free software; you can redistribute it and/or modify
2769 + * it under the terms of the GNU General Public License as published by
2770 + * the Free Software Foundation; either version 2 of the License, or
2771 + * (at your option) any later version.
2772 + *
2773 + * This program is distributed in the hope that it will be useful,
2774 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2775 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2776 + * GNU General Public License for more details.
2777 + *
2778 + * You should have received a copy of the GNU General Public License
2779 + * along with this program; if not, write to the Free Software
2780 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2781 + */
2782 +
2783 +#ifndef __BCM2708_BCM2708_H
2784 +#define __BCM2708_BCM2708_H
2785 +
2786 +#include <linux/amba/bus.h>
2787 +
2788 +extern void __init bcm2708_init(void);
2789 +extern void __init bcm2708_init_irq(void);
2790 +extern void __init bcm2708_map_io(void);
2791 +extern struct sys_timer bcm2708_timer;
2792 +extern unsigned int mmc_status(struct device *dev);
2793 +
2794 +#define AMBA_DEVICE(name, busid, base, plat) \
2795 +static struct amba_device name##_device = { \
2796 + .dev = { \
2797 + .coherent_dma_mask = ~0, \
2798 + .init_name = busid, \
2799 + .platform_data = plat, \
2800 + }, \
2801 + .res = { \
2802 + .start = base##_BASE, \
2803 + .end = (base##_BASE) + SZ_4K - 1,\
2804 + .flags = IORESOURCE_MEM, \
2805 + }, \
2806 + .irq = base##_IRQ, \
2807 +}
2808 +
2809 +#endif
2810 diff --git a/arch/arm/mach-bcm2708/bcm2708_gpio.c b/arch/arm/mach-bcm2708/bcm2708_gpio.c
2811 new file mode 100644
2812 index 0000000..120929ff
2813 --- /dev/null
2814 +++ b/arch/arm/mach-bcm2708/bcm2708_gpio.c
2815 @@ -0,0 +1,361 @@
2816 +/*
2817 + * linux/arch/arm/mach-bcm2708/bcm2708_gpio.c
2818 + *
2819 + * Copyright (C) 2010 Broadcom
2820 + *
2821 + * This program is free software; you can redistribute it and/or modify
2822 + * it under the terms of the GNU General Public License version 2 as
2823 + * published by the Free Software Foundation.
2824 + *
2825 + */
2826 +
2827 +#include <linux/spinlock.h>
2828 +#include <linux/module.h>
2829 +#include <linux/list.h>
2830 +#include <linux/io.h>
2831 +#include <linux/irq.h>
2832 +#include <linux/interrupt.h>
2833 +#include <linux/slab.h>
2834 +#include <mach/gpio.h>
2835 +#include <linux/gpio.h>
2836 +#include <linux/platform_device.h>
2837 +#include <mach/platform.h>
2838 +
2839 +#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio"
2840 +#define DRIVER_NAME BCM_GPIO_DRIVER_NAME
2841 +#define BCM_GPIO_USE_IRQ 1
2842 +
2843 +#define GPIOFSEL(x) (0x00+(x)*4)
2844 +#define GPIOSET(x) (0x1c+(x)*4)
2845 +#define GPIOCLR(x) (0x28+(x)*4)
2846 +#define GPIOLEV(x) (0x34+(x)*4)
2847 +#define GPIOEDS(x) (0x40+(x)*4)
2848 +#define GPIOREN(x) (0x4c+(x)*4)
2849 +#define GPIOFEN(x) (0x58+(x)*4)
2850 +#define GPIOHEN(x) (0x64+(x)*4)
2851 +#define GPIOLEN(x) (0x70+(x)*4)
2852 +#define GPIOAREN(x) (0x7c+(x)*4)
2853 +#define GPIOAFEN(x) (0x88+(x)*4)
2854 +#define GPIOUD(x) (0x94+(x)*4)
2855 +#define GPIOUDCLK(x) (0x98+(x)*4)
2856 +
2857 +enum { GPIO_FSEL_INPUT, GPIO_FSEL_OUTPUT,
2858 + GPIO_FSEL_ALT5, GPIO_FSEL_ALT_4,
2859 + GPIO_FSEL_ALT0, GPIO_FSEL_ALT1,
2860 + GPIO_FSEL_ALT2, GPIO_FSEL_ALT3,
2861 +};
2862 +
2863 + /* Each of the two spinlocks protects a different set of hardware
2864 + * regiters and data structurs. This decouples the code of the IRQ from
2865 + * the GPIO code. This also makes the case of a GPIO routine call from
2866 + * the IRQ code simpler.
2867 + */
2868 +static DEFINE_SPINLOCK(lock); /* GPIO registers */
2869 +
2870 +struct bcm2708_gpio {
2871 + struct list_head list;
2872 + void __iomem *base;
2873 + struct gpio_chip gc;
2874 + unsigned long rising;
2875 + unsigned long falling;
2876 + unsigned long high;
2877 + unsigned long low;
2878 +};
2879 +
2880 +static int bcm2708_set_function(struct gpio_chip *gc, unsigned offset,
2881 + int function)
2882 +{
2883 + struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
2884 + unsigned long flags;
2885 + unsigned gpiodir;
2886 + unsigned gpio_bank = offset / 10;
2887 + unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3;
2888 +
2889 +//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set_function %p (%d,%d)\n", gc, offset, function);
2890 + if (offset >= BCM2708_NR_GPIOS)
2891 + return -EINVAL;
2892 +
2893 + spin_lock_irqsave(&lock, flags);
2894 +
2895 + gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank));
2896 + gpiodir &= ~(7 << gpio_field_offset);
2897 + gpiodir |= function << gpio_field_offset;
2898 + writel(gpiodir, gpio->base + GPIOFSEL(gpio_bank));
2899 + spin_unlock_irqrestore(&lock, flags);
2900 + gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank));
2901 +
2902 + return 0;
2903 +}
2904 +
2905 +static int bcm2708_gpio_dir_in(struct gpio_chip *gc, unsigned offset)
2906 +{
2907 + return bcm2708_set_function(gc, offset, GPIO_FSEL_INPUT);
2908 +}
2909 +
2910 +static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
2911 +static int bcm2708_gpio_dir_out(struct gpio_chip *gc, unsigned offset,
2912 + int value)
2913 +{
2914 + int ret;
2915 + ret = bcm2708_set_function(gc, offset, GPIO_FSEL_OUTPUT);
2916 + if (ret >= 0)
2917 + bcm2708_gpio_set(gc, offset, value);
2918 + return ret;
2919 +}
2920 +
2921 +static int bcm2708_gpio_get(struct gpio_chip *gc, unsigned offset)
2922 +{
2923 + struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
2924 + unsigned gpio_bank = offset / 32;
2925 + unsigned gpio_field_offset = (offset - 32 * gpio_bank);
2926 + unsigned lev;
2927 +
2928 + if (offset >= BCM2708_NR_GPIOS)
2929 + return 0;
2930 + lev = readl(gpio->base + GPIOLEV(gpio_bank));
2931 +//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_get %p (%d)=%d\n", gc, offset, 0x1 & (lev>>gpio_field_offset));
2932 + return 0x1 & (lev >> gpio_field_offset);
2933 +}
2934 +
2935 +static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
2936 +{
2937 + struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
2938 + unsigned gpio_bank = offset / 32;
2939 + unsigned gpio_field_offset = (offset - 32 * gpio_bank);
2940 +//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set %p (%d=%d)\n", gc, offset, value);
2941 + if (offset >= BCM2708_NR_GPIOS)
2942 + return;
2943 + if (value)
2944 + writel(1 << gpio_field_offset, gpio->base + GPIOSET(gpio_bank));
2945 + else
2946 + writel(1 << gpio_field_offset, gpio->base + GPIOCLR(gpio_bank));
2947 +}
2948 +
2949 +/*************************************************************************************************************************
2950 + * bcm2708 GPIO IRQ
2951 + */
2952 +
2953 +#if BCM_GPIO_USE_IRQ
2954 +
2955 +static int bcm2708_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
2956 +{
2957 + return gpio_to_irq(gpio);
2958 +}
2959 +
2960 +static int bcm2708_gpio_irq_set_type(struct irq_data *d, unsigned type)
2961 +{
2962 + unsigned irq = d->irq;
2963 + struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
2964 +
2965 + gpio->rising &= ~(1 << irq_to_gpio(irq));
2966 + gpio->falling &= ~(1 << irq_to_gpio(irq));
2967 + gpio->high &= ~(1 << irq_to_gpio(irq));
2968 + gpio->low &= ~(1 << irq_to_gpio(irq));
2969 +
2970 + if (type & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
2971 + return -EINVAL;
2972 +
2973 + if (type & IRQ_TYPE_EDGE_RISING)
2974 + gpio->rising |= (1 << irq_to_gpio(irq));
2975 + if (type & IRQ_TYPE_EDGE_FALLING)
2976 + gpio->falling |= (1 << irq_to_gpio(irq));
2977 + if (type & IRQ_TYPE_LEVEL_HIGH)
2978 + gpio->high |= (1 << irq_to_gpio(irq));
2979 + if (type & IRQ_TYPE_LEVEL_LOW)
2980 + gpio->low |= (1 << irq_to_gpio(irq));
2981 + return 0;
2982 +}
2983 +
2984 +static void bcm2708_gpio_irq_mask(struct irq_data *d)
2985 +{
2986 + unsigned irq = d->irq;
2987 + struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
2988 + unsigned gn = irq_to_gpio(irq);
2989 + unsigned gb = gn / 32;
2990 + unsigned long rising = readl(gpio->base + GPIOREN(gb));
2991 + unsigned long falling = readl(gpio->base + GPIOFEN(gb));
2992 + unsigned long high = readl(gpio->base + GPIOHEN(gb));
2993 + unsigned long low = readl(gpio->base + GPIOLEN(gb));
2994 +
2995 + gn = gn % 32;
2996 +
2997 + writel(rising & ~(1 << gn), gpio->base + GPIOREN(gb));
2998 + writel(falling & ~(1 << gn), gpio->base + GPIOFEN(gb));
2999 + writel(high & ~(1 << gn), gpio->base + GPIOHEN(gb));
3000 + writel(low & ~(1 << gn), gpio->base + GPIOLEN(gb));
3001 +}
3002 +
3003 +static void bcm2708_gpio_irq_unmask(struct irq_data *d)
3004 +{
3005 + unsigned irq = d->irq;
3006 + struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
3007 + unsigned gn = irq_to_gpio(irq);
3008 + unsigned gb = gn / 32;
3009 + unsigned long rising = readl(gpio->base + GPIOREN(gb));
3010 + unsigned long falling = readl(gpio->base + GPIOFEN(gb));
3011 + unsigned long high = readl(gpio->base + GPIOHEN(gb));
3012 + unsigned long low = readl(gpio->base + GPIOLEN(gb));
3013 +
3014 + gn = gn % 32;
3015 +
3016 + writel(1 << gn, gpio->base + GPIOEDS(gb));
3017 +
3018 + if (gpio->rising & (1 << gn)) {
3019 + writel(rising | (1 << gn), gpio->base + GPIOREN(gb));
3020 + } else {
3021 + writel(rising & ~(1 << gn), gpio->base + GPIOREN(gb));
3022 + }
3023 +
3024 + if (gpio->falling & (1 << gn)) {
3025 + writel(falling | (1 << gn), gpio->base + GPIOFEN(gb));
3026 + } else {
3027 + writel(falling & ~(1 << gn), gpio->base + GPIOFEN(gb));
3028 + }
3029 +
3030 + if (gpio->high & (1 << gn)) {
3031 + writel(high | (1 << gn), gpio->base + GPIOHEN(gb));
3032 + } else {
3033 + writel(high & ~(1 << gn), gpio->base + GPIOHEN(gb));
3034 + }
3035 +
3036 + if (gpio->low & (1 << gn)) {
3037 + writel(low | (1 << gn), gpio->base + GPIOLEN(gb));
3038 + } else {
3039 + writel(low & ~(1 << gn), gpio->base + GPIOLEN(gb));
3040 + }
3041 +}
3042 +
3043 +static struct irq_chip bcm2708_irqchip = {
3044 + .name = "GPIO",
3045 + .irq_enable = bcm2708_gpio_irq_unmask,
3046 + .irq_disable = bcm2708_gpio_irq_mask,
3047 + .irq_unmask = bcm2708_gpio_irq_unmask,
3048 + .irq_mask = bcm2708_gpio_irq_mask,
3049 + .irq_set_type = bcm2708_gpio_irq_set_type,
3050 +};
3051 +
3052 +static irqreturn_t bcm2708_gpio_interrupt(int irq, void *dev_id)
3053 +{
3054 + unsigned long edsr;
3055 + unsigned bank;
3056 + int i;
3057 + unsigned gpio;
3058 + for (bank = 0; bank <= 1; bank++) {
3059 + edsr = readl(__io_address(GPIO_BASE) + GPIOEDS(bank));
3060 + for_each_set_bit(i, &edsr, 32) {
3061 + gpio = i + bank * 32;
3062 + generic_handle_irq(gpio_to_irq(gpio));
3063 + }
3064 + writel(0xffffffff, __io_address(GPIO_BASE) + GPIOEDS(bank));
3065 + }
3066 + return IRQ_HANDLED;
3067 +}
3068 +
3069 +static struct irqaction bcm2708_gpio_irq = {
3070 + .name = "BCM2708 GPIO catchall handler",
3071 + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
3072 + .handler = bcm2708_gpio_interrupt,
3073 +};
3074 +
3075 +static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb)
3076 +{
3077 + unsigned irq;
3078 +
3079 + ucb->gc.to_irq = bcm2708_gpio_to_irq;
3080 +
3081 + for (irq = GPIO_IRQ_START; irq < (GPIO_IRQ_START + GPIO_IRQS); irq++) {
3082 + irq_set_chip_data(irq, ucb);
3083 + irq_set_chip(irq, &bcm2708_irqchip);
3084 + set_irq_flags(irq, IRQF_VALID);
3085 + }
3086 + setup_irq(IRQ_GPIO3, &bcm2708_gpio_irq);
3087 +}
3088 +
3089 +#else
3090 +
3091 +static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb)
3092 +{
3093 +}
3094 +
3095 +#endif /* #if BCM_GPIO_USE_IRQ ***************************************************************************************************************** */
3096 +
3097 +static int bcm2708_gpio_probe(struct platform_device *dev)
3098 +{
3099 + struct bcm2708_gpio *ucb;
3100 + struct resource *res;
3101 + int err = 0;
3102 +
3103 + printk(KERN_INFO DRIVER_NAME ": bcm2708_gpio_probe %p\n", dev);
3104 +
3105 + ucb = kzalloc(sizeof(*ucb), GFP_KERNEL);
3106 + if (NULL == ucb) {
3107 + printk(KERN_ERR DRIVER_NAME ": failed to allocate "
3108 + "mailbox memory\n");
3109 + err = -ENOMEM;
3110 + goto err;
3111 + }
3112 +
3113 + res = platform_get_resource(dev, IORESOURCE_MEM, 0);
3114 +
3115 + platform_set_drvdata(dev, ucb);
3116 + ucb->base = __io_address(GPIO_BASE);
3117 +
3118 + ucb->gc.label = "bcm2708_gpio";
3119 + ucb->gc.base = 0;
3120 + ucb->gc.ngpio = BCM2708_NR_GPIOS;
3121 + ucb->gc.owner = THIS_MODULE;
3122 +
3123 + ucb->gc.direction_input = bcm2708_gpio_dir_in;
3124 + ucb->gc.direction_output = bcm2708_gpio_dir_out;
3125 + ucb->gc.get = bcm2708_gpio_get;
3126 + ucb->gc.set = bcm2708_gpio_set;
3127 + ucb->gc.can_sleep = 0;
3128 +
3129 + bcm2708_gpio_irq_init(ucb);
3130 +
3131 + err = gpiochip_add(&ucb->gc);
3132 + if (err)
3133 + goto err;
3134 +
3135 +err:
3136 + return err;
3137 +
3138 +}
3139 +
3140 +static int bcm2708_gpio_remove(struct platform_device *dev)
3141 +{
3142 + int err = 0;
3143 + struct bcm2708_gpio *ucb = platform_get_drvdata(dev);
3144 +
3145 + printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_remove %p\n", dev);
3146 +
3147 + err = gpiochip_remove(&ucb->gc);
3148 +
3149 + platform_set_drvdata(dev, NULL);
3150 + kfree(ucb);
3151 +
3152 + return err;
3153 +}
3154 +
3155 +static struct platform_driver bcm2708_gpio_driver = {
3156 + .probe = bcm2708_gpio_probe,
3157 + .remove = bcm2708_gpio_remove,
3158 + .driver = {
3159 + .name = "bcm2708_gpio"},
3160 +};
3161 +
3162 +static int __init bcm2708_gpio_init(void)
3163 +{
3164 + return platform_driver_register(&bcm2708_gpio_driver);
3165 +}
3166 +
3167 +static void __exit bcm2708_gpio_exit(void)
3168 +{
3169 + platform_driver_unregister(&bcm2708_gpio_driver);
3170 +}
3171 +
3172 +module_init(bcm2708_gpio_init);
3173 +module_exit(bcm2708_gpio_exit);
3174 +
3175 +MODULE_DESCRIPTION("Broadcom BCM2708 GPIO driver");
3176 +MODULE_LICENSE("GPL");
3177 diff --git a/arch/arm/mach-bcm2708/clock.c b/arch/arm/mach-bcm2708/clock.c
3178 new file mode 100644
3179 index 0000000..4fc556e
3180 --- /dev/null
3181 +++ b/arch/arm/mach-bcm2708/clock.c
3182 @@ -0,0 +1,61 @@
3183 +/*
3184 + * linux/arch/arm/mach-bcm2708/clock.c
3185 + *
3186 + * Copyright (C) 2010 Broadcom
3187 + *
3188 + * This program is free software; you can redistribute it and/or modify
3189 + * it under the terms of the GNU General Public License as published by
3190 + * the Free Software Foundation; either version 2 of the License, or
3191 + * (at your option) any later version.
3192 + *
3193 + * This program is distributed in the hope that it will be useful,
3194 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3195 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3196 + * GNU General Public License for more details.
3197 + *
3198 + * You should have received a copy of the GNU General Public License
3199 + * along with this program; if not, write to the Free Software
3200 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3201 + */
3202 +#include <linux/module.h>
3203 +#include <linux/kernel.h>
3204 +#include <linux/device.h>
3205 +#include <linux/list.h>
3206 +#include <linux/errno.h>
3207 +#include <linux/err.h>
3208 +#include <linux/string.h>
3209 +#include <linux/clk.h>
3210 +#include <linux/mutex.h>
3211 +
3212 +#include <asm/clkdev.h>
3213 +
3214 +#include "clock.h"
3215 +
3216 +int clk_enable(struct clk *clk)
3217 +{
3218 + return 0;
3219 +}
3220 +EXPORT_SYMBOL(clk_enable);
3221 +
3222 +void clk_disable(struct clk *clk)
3223 +{
3224 +}
3225 +EXPORT_SYMBOL(clk_disable);
3226 +
3227 +unsigned long clk_get_rate(struct clk *clk)
3228 +{
3229 + return clk->rate;
3230 +}
3231 +EXPORT_SYMBOL(clk_get_rate);
3232 +
3233 +long clk_round_rate(struct clk *clk, unsigned long rate)
3234 +{
3235 + return clk->rate;
3236 +}
3237 +EXPORT_SYMBOL(clk_round_rate);
3238 +
3239 +int clk_set_rate(struct clk *clk, unsigned long rate)
3240 +{
3241 + return -EIO;
3242 +}
3243 +EXPORT_SYMBOL(clk_set_rate);
3244 diff --git a/arch/arm/mach-bcm2708/clock.h b/arch/arm/mach-bcm2708/clock.h
3245 new file mode 100644
3246 index 0000000..5f9d725
3247 --- /dev/null
3248 +++ b/arch/arm/mach-bcm2708/clock.h
3249 @@ -0,0 +1,24 @@
3250 +/*
3251 + * linux/arch/arm/mach-bcm2708/clock.h
3252 + *
3253 + * Copyright (C) 2010 Broadcom
3254 + *
3255 + * This program is free software; you can redistribute it and/or modify
3256 + * it under the terms of the GNU General Public License as published by
3257 + * the Free Software Foundation; either version 2 of the License, or
3258 + * (at your option) any later version.
3259 + *
3260 + * This program is distributed in the hope that it will be useful,
3261 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3262 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3263 + * GNU General Public License for more details.
3264 + *
3265 + * You should have received a copy of the GNU General Public License
3266 + * along with this program; if not, write to the Free Software
3267 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3268 + */
3269 +struct module;
3270 +
3271 +struct clk {
3272 + unsigned long rate;
3273 +};
3274 diff --git a/arch/arm/mach-bcm2708/dma.c b/arch/arm/mach-bcm2708/dma.c
3275 new file mode 100644
3276 index 0000000..51d147a
3277 --- /dev/null
3278 +++ b/arch/arm/mach-bcm2708/dma.c
3279 @@ -0,0 +1,399 @@
3280 +/*
3281 + * linux/arch/arm/mach-bcm2708/dma.c
3282 + *
3283 + * Copyright (C) 2010 Broadcom
3284 + *
3285 + * This program is free software; you can redistribute it and/or modify
3286 + * it under the terms of the GNU General Public License version 2 as
3287 + * published by the Free Software Foundation.
3288 + */
3289 +
3290 +#include <linux/slab.h>
3291 +#include <linux/device.h>
3292 +#include <linux/platform_device.h>
3293 +#include <linux/module.h>
3294 +#include <linux/scatterlist.h>
3295 +
3296 +#include <mach/dma.h>
3297 +#include <mach/irqs.h>
3298 +
3299 +/*****************************************************************************\
3300 + * *
3301 + * Configuration *
3302 + * *
3303 +\*****************************************************************************/
3304 +
3305 +#define CACHE_LINE_MASK 31
3306 +#define DRIVER_NAME BCM_DMAMAN_DRIVER_NAME
3307 +#define DEFAULT_DMACHAN_BITMAP 0x10 /* channel 4 only */
3308 +
3309 +/* valid only for channels 0 - 14, 15 has its own base address */
3310 +#define BCM2708_DMA_CHAN(n) ((n)<<8) /* base address */
3311 +#define BCM2708_DMA_CHANIO(dma_base, n) \
3312 + ((void __iomem *)((char *)(dma_base)+BCM2708_DMA_CHAN(n)))
3313 +
3314 +
3315 +/*****************************************************************************\
3316 + * *
3317 + * DMA Auxilliary Functions *
3318 + * *
3319 +\*****************************************************************************/
3320 +
3321 +/* A DMA buffer on an arbitrary boundary may separate a cache line into a
3322 + section inside the DMA buffer and another section outside it.
3323 + Even if we flush DMA buffers from the cache there is always the chance that
3324 + during a DMA someone will access the part of a cache line that is outside
3325 + the DMA buffer - which will then bring in unwelcome data.
3326 + Without being able to dictate our own buffer pools we must insist that
3327 + DMA buffers consist of a whole number of cache lines.
3328 +*/
3329 +
3330 +extern int
3331 +bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len)
3332 +{
3333 + int i;
3334 +
3335 + for (i = 0; i < sg_len; i++) {
3336 + if (sg_ptr[i].offset & CACHE_LINE_MASK ||
3337 + sg_ptr[i].length & CACHE_LINE_MASK)
3338 + return 0;
3339 + }
3340 +
3341 + return 1;
3342 +}
3343 +EXPORT_SYMBOL_GPL(bcm_sg_suitable_for_dma);
3344 +
3345 +extern void
3346 +bcm_dma_start(void __iomem *dma_chan_base, dma_addr_t control_block)
3347 +{
3348 + dsb(); /* ARM data synchronization (push) operation */
3349 +
3350 + writel(control_block, dma_chan_base + BCM2708_DMA_ADDR);
3351 + writel(BCM2708_DMA_ACTIVE, dma_chan_base + BCM2708_DMA_CS);
3352 +}
3353 +
3354 +extern void bcm_dma_wait_idle(void __iomem *dma_chan_base)
3355 +{
3356 + dsb();
3357 +
3358 + /* ugly busy wait only option for now */
3359 + while (readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE)
3360 + cpu_relax();
3361 +}
3362 +
3363 +EXPORT_SYMBOL_GPL(bcm_dma_start);
3364 +
3365 +/* Complete an ongoing DMA (assuming its results are to be ignored)
3366 + Does nothing if there is no DMA in progress.
3367 + This routine waits for the current AXI transfer to complete before
3368 + terminating the current DMA. If the current transfer is hung on a DREQ used
3369 + by an uncooperative peripheral the AXI transfer may never complete. In this
3370 + case the routine times out and return a non-zero error code.
3371 + Use of this routine doesn't guarantee that the ongoing or aborted DMA
3372 + does not produce an interrupt.
3373 +*/
3374 +extern int
3375 +bcm_dma_abort(void __iomem *dma_chan_base)
3376 +{
3377 + unsigned long int cs;
3378 + int rc = 0;
3379 +
3380 + cs = readl(dma_chan_base + BCM2708_DMA_CS);
3381 +
3382 + if (BCM2708_DMA_ACTIVE & cs) {
3383 + long int timeout = 10000;
3384 +
3385 + /* write 0 to the active bit - pause the DMA */
3386 + writel(0, dma_chan_base + BCM2708_DMA_CS);
3387 +
3388 + /* wait for any current AXI transfer to complete */
3389 + while (0 != (cs & BCM2708_DMA_ISPAUSED) && --timeout >= 0)
3390 + cs = readl(dma_chan_base + BCM2708_DMA_CS);
3391 +
3392 + if (0 != (cs & BCM2708_DMA_ISPAUSED)) {
3393 + /* we'll un-pause when we set of our next DMA */
3394 + rc = -ETIMEDOUT;
3395 +
3396 + } else if (BCM2708_DMA_ACTIVE & cs) {
3397 + /* terminate the control block chain */
3398 + writel(0, dma_chan_base + BCM2708_DMA_NEXTCB);
3399 +
3400 + /* abort the whole DMA */
3401 + writel(BCM2708_DMA_ABORT | BCM2708_DMA_ACTIVE,
3402 + dma_chan_base + BCM2708_DMA_CS);
3403 + }
3404 + }
3405 +
3406 + return rc;
3407 +}
3408 +EXPORT_SYMBOL_GPL(bcm_dma_abort);
3409 +
3410 +
3411 +/***************************************************************************** \
3412 + * *
3413 + * DMA Manager Device Methods *
3414 + * *
3415 +\*****************************************************************************/
3416 +
3417 +struct vc_dmaman {
3418 + void __iomem *dma_base;
3419 + u32 chan_available; /* bitmap of available channels */
3420 + u32 has_feature[BCM_DMA_FEATURE_COUNT]; /* bitmap of feature presence */
3421 +};
3422 +
3423 +static void vc_dmaman_init(struct vc_dmaman *dmaman, void __iomem *dma_base,
3424 + u32 chans_available)
3425 +{
3426 + dmaman->dma_base = dma_base;
3427 + dmaman->chan_available = chans_available;
3428 + dmaman->has_feature[BCM_DMA_FEATURE_FAST_ORD] = 0x0c; /* chans 2 & 3 */
3429 + dmaman->has_feature[BCM_DMA_FEATURE_BULK_ORD] = 0x01; /* chan 0 */
3430 +}
3431 +
3432 +static int vc_dmaman_chan_alloc(struct vc_dmaman *dmaman,
3433 + unsigned preferred_feature_set)
3434 +{
3435 + u32 chans;
3436 + int feature;
3437 +
3438 + chans = dmaman->chan_available;
3439 + for (feature = 0; feature < BCM_DMA_FEATURE_COUNT; feature++)
3440 + /* select the subset of available channels with the desired
3441 + feature so long as some of the candidate channels have that
3442 + feature */
3443 + if ((preferred_feature_set & (1 << feature)) &&
3444 + (chans & dmaman->has_feature[feature]))
3445 + chans &= dmaman->has_feature[feature];
3446 +
3447 + if (chans) {
3448 + int chan = 0;
3449 + /* return the ordinal of the first channel in the bitmap */
3450 + while (chans != 0 && (chans & 1) == 0) {
3451 + chans >>= 1;
3452 + chan++;
3453 + }
3454 + /* claim the channel */
3455 + dmaman->chan_available &= ~(1 << chan);
3456 + return chan;
3457 + } else
3458 + return -ENOMEM;
3459 +}
3460 +
3461 +static int vc_dmaman_chan_free(struct vc_dmaman *dmaman, int chan)
3462 +{
3463 + if (chan < 0)
3464 + return -EINVAL;
3465 + else if ((1 << chan) & dmaman->chan_available)
3466 + return -EIDRM;
3467 + else {
3468 + dmaman->chan_available |= (1 << chan);
3469 + return 0;
3470 + }
3471 +}
3472 +
3473 +/*****************************************************************************\
3474 + * *
3475 + * DMA IRQs *
3476 + * *
3477 +\*****************************************************************************/
3478 +
3479 +static unsigned char bcm_dma_irqs[] = {
3480 + IRQ_DMA0,
3481 + IRQ_DMA1,
3482 + IRQ_DMA2,
3483 + IRQ_DMA3,
3484 + IRQ_DMA4,
3485 + IRQ_DMA5,
3486 + IRQ_DMA6,
3487 + IRQ_DMA7,
3488 + IRQ_DMA8,
3489 + IRQ_DMA9,
3490 + IRQ_DMA10,
3491 + IRQ_DMA11,
3492 + IRQ_DMA12
3493 +};
3494 +
3495 +
3496 +/***************************************************************************** \
3497 + * *
3498 + * DMA Manager Monitor *
3499 + * *
3500 +\*****************************************************************************/
3501 +
3502 +static struct device *dmaman_dev; /* we assume there's only one! */
3503 +
3504 +extern int bcm_dma_chan_alloc(unsigned preferred_feature_set,
3505 + void __iomem **out_dma_base, int *out_dma_irq)
3506 +{
3507 + if (!dmaman_dev)
3508 + return -ENODEV;
3509 + else {
3510 + struct vc_dmaman *dmaman = dev_get_drvdata(dmaman_dev);
3511 + int rc;
3512 +
3513 + device_lock(dmaman_dev);
3514 + rc = vc_dmaman_chan_alloc(dmaman, preferred_feature_set);
3515 + if (rc >= 0) {
3516 + *out_dma_base = BCM2708_DMA_CHANIO(dmaman->dma_base,
3517 + rc);
3518 + *out_dma_irq = bcm_dma_irqs[rc];
3519 + }
3520 + device_unlock(dmaman_dev);
3521 +
3522 + return rc;
3523 + }
3524 +}
3525 +EXPORT_SYMBOL_GPL(bcm_dma_chan_alloc);
3526 +
3527 +extern int bcm_dma_chan_free(int channel)
3528 +{
3529 + if (dmaman_dev) {
3530 + struct vc_dmaman *dmaman = dev_get_drvdata(dmaman_dev);
3531 + int rc;
3532 +
3533 + device_lock(dmaman_dev);
3534 + rc = vc_dmaman_chan_free(dmaman, channel);
3535 + device_unlock(dmaman_dev);
3536 +
3537 + return rc;
3538 + } else
3539 + return -ENODEV;
3540 +}
3541 +EXPORT_SYMBOL_GPL(bcm_dma_chan_free);
3542 +
3543 +static int dev_dmaman_register(const char *dev_name, struct device *dev)
3544 +{
3545 + int rc = dmaman_dev ? -EINVAL : 0;
3546 + dmaman_dev = dev;
3547 + return rc;
3548 +}
3549 +
3550 +static void dev_dmaman_deregister(const char *dev_name, struct device *dev)
3551 +{
3552 + dmaman_dev = NULL;
3553 +}
3554 +
3555 +/*****************************************************************************\
3556 + * *
3557 + * DMA Device *
3558 + * *
3559 +\*****************************************************************************/
3560 +
3561 +static int dmachans = -1; /* module parameter */
3562 +
3563 +static int bcm_dmaman_probe(struct platform_device *pdev)
3564 +{
3565 + int ret = 0;
3566 + struct vc_dmaman *dmaman;
3567 + struct resource *dma_res = NULL;
3568 + void __iomem *dma_base = NULL;
3569 + int have_dma_region = 0;
3570 +
3571 + dmaman = kzalloc(sizeof(*dmaman), GFP_KERNEL);
3572 + if (NULL == dmaman) {
3573 + printk(KERN_ERR DRIVER_NAME ": failed to allocate "
3574 + "DMA management memory\n");
3575 + ret = -ENOMEM;
3576 + } else {
3577 +
3578 + dma_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3579 + if (dma_res == NULL) {
3580 + printk(KERN_ERR DRIVER_NAME ": failed to obtain memory "
3581 + "resource\n");
3582 + ret = -ENODEV;
3583 + } else if (!request_mem_region(dma_res->start,
3584 + resource_size(dma_res),
3585 + DRIVER_NAME)) {
3586 + dev_err(&pdev->dev, "cannot obtain DMA region\n");
3587 + ret = -EBUSY;
3588 + } else {
3589 + have_dma_region = 1;
3590 + dma_base = ioremap(dma_res->start,
3591 + resource_size(dma_res));
3592 + if (!dma_base) {
3593 + dev_err(&pdev->dev, "cannot map DMA region\n");
3594 + ret = -ENOMEM;
3595 + } else {
3596 + /* use module parameter if one was provided */
3597 + if (dmachans > 0)
3598 + vc_dmaman_init(dmaman, dma_base,
3599 + dmachans);
3600 + else
3601 + vc_dmaman_init(dmaman, dma_base,
3602 + DEFAULT_DMACHAN_BITMAP);
3603 +
3604 + platform_set_drvdata(pdev, dmaman);
3605 + dev_dmaman_register(DRIVER_NAME, &pdev->dev);
3606 +
3607 + printk(KERN_INFO DRIVER_NAME ": DMA manager "
3608 + "at %p\n", dma_base);
3609 + }
3610 + }
3611 + }
3612 + if (ret != 0) {
3613 + if (dma_base)
3614 + iounmap(dma_base);
3615 + if (dma_res && have_dma_region)
3616 + release_mem_region(dma_res->start,
3617 + resource_size(dma_res));
3618 + if (dmaman)
3619 + kfree(dmaman);
3620 + }
3621 + return ret;
3622 +}
3623 +
3624 +static int bcm_dmaman_remove(struct platform_device *pdev)
3625 +{
3626 + struct vc_dmaman *dmaman = platform_get_drvdata(pdev);
3627 +
3628 + platform_set_drvdata(pdev, NULL);
3629 + dev_dmaman_deregister(DRIVER_NAME, &pdev->dev);
3630 + kfree(dmaman);
3631 +
3632 + return 0;
3633 +}
3634 +
3635 +static struct platform_driver bcm_dmaman_driver = {
3636 + .probe = bcm_dmaman_probe,
3637 + .remove = bcm_dmaman_remove,
3638 +
3639 + .driver = {
3640 + .name = DRIVER_NAME,
3641 + .owner = THIS_MODULE,
3642 + },
3643 +};
3644 +
3645 +/*****************************************************************************\
3646 + * *
3647 + * Driver init/exit *
3648 + * *
3649 +\*****************************************************************************/
3650 +
3651 +static int __init bcm_dmaman_drv_init(void)
3652 +{
3653 + int ret;
3654 +
3655 + ret = platform_driver_register(&bcm_dmaman_driver);
3656 + if (ret != 0) {
3657 + printk(KERN_ERR DRIVER_NAME ": failed to register "
3658 + "on platform\n");
3659 + }
3660 +
3661 + return ret;
3662 +}
3663 +
3664 +static void __exit bcm_dmaman_drv_exit(void)
3665 +{
3666 + platform_driver_unregister(&bcm_dmaman_driver);
3667 +}
3668 +
3669 +module_init(bcm_dmaman_drv_init);
3670 +module_exit(bcm_dmaman_drv_exit);
3671 +
3672 +module_param(dmachans, int, 0644);
3673 +
3674 +MODULE_AUTHOR("Gray Girling <grayg@broadcom.com>");
3675 +MODULE_DESCRIPTION("DMA channel manager driver");
3676 +MODULE_LICENSE("GPL");
3677 +
3678 +MODULE_PARM_DESC(dmachans, "Bitmap of DMA channels available to the ARM");
3679 diff --git a/arch/arm/mach-bcm2708/include/mach/arm_control.h b/arch/arm/mach-bcm2708/include/mach/arm_control.h
3680 new file mode 100644
3681 index 0000000..a82bb92
3682 --- /dev/null
3683 +++ b/arch/arm/mach-bcm2708/include/mach/arm_control.h
3684 @@ -0,0 +1,419 @@
3685 +/*
3686 + * linux/arch/arm/mach-bcm2708/arm_control.h
3687 + *
3688 + * Copyright (C) 2010 Broadcom
3689 + *
3690 + * This program is free software; you can redistribute it and/or modify
3691 + * it under the terms of the GNU General Public License as published by
3692 + * the Free Software Foundation; either version 2 of the License, or
3693 + * (at your option) any later version.
3694 + *
3695 + * This program is distributed in the hope that it will be useful,
3696 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3697 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3698 + * GNU General Public License for more details.
3699 + *
3700 + * You should have received a copy of the GNU General Public License
3701 + * along with this program; if not, write to the Free Software
3702 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3703 + */
3704 +
3705 +#ifndef __BCM2708_ARM_CONTROL_H
3706 +#define __BCM2708_ARM_CONTROL_H
3707 +
3708 +/*
3709 + * Definitions and addresses for the ARM CONTROL logic
3710 + * This file is manually generated.
3711 + */
3712 +
3713 +#define ARM_BASE 0x7E00B000
3714 +
3715 +/* Basic configuration */
3716 +#define ARM_CONTROL0 HW_REGISTER_RW(ARM_BASE+0x000)
3717 +#define ARM_C0_SIZ128M 0x00000000
3718 +#define ARM_C0_SIZ256M 0x00000001
3719 +#define ARM_C0_SIZ512M 0x00000002
3720 +#define ARM_C0_SIZ1G 0x00000003
3721 +#define ARM_C0_BRESP0 0x00000000
3722 +#define ARM_C0_BRESP1 0x00000004
3723 +#define ARM_C0_BRESP2 0x00000008
3724 +#define ARM_C0_BOOTHI 0x00000010
3725 +#define ARM_C0_UNUSED05 0x00000020 /* free */
3726 +#define ARM_C0_FULLPERI 0x00000040
3727 +#define ARM_C0_UNUSED78 0x00000180 /* free */
3728 +#define ARM_C0_JTAGMASK 0x00000E00
3729 +#define ARM_C0_JTAGOFF 0x00000000
3730 +#define ARM_C0_JTAGBASH 0x00000800 /* Debug on GPIO off */
3731 +#define ARM_C0_JTAGGPIO 0x00000C00 /* Debug on GPIO on */
3732 +#define ARM_C0_APROTMSK 0x0000F000
3733 +#define ARM_C0_DBG0SYNC 0x00010000 /* VPU0 halt sync */
3734 +#define ARM_C0_DBG1SYNC 0x00020000 /* VPU1 halt sync */
3735 +#define ARM_C0_SWDBGREQ 0x00040000 /* HW debug request */
3736 +#define ARM_C0_PASSHALT 0x00080000 /* ARM halt passed to debugger */
3737 +#define ARM_C0_PRIO_PER 0x00F00000 /* per priority mask */
3738 +#define ARM_C0_PRIO_L2 0x0F000000
3739 +#define ARM_C0_PRIO_UC 0xF0000000
3740 +
3741 +#define ARM_C0_APROTPASS 0x0000A000 /* Translate 1:1 */
3742 +#define ARM_C0_APROTUSER 0x00000000 /* Only user mode */
3743 +#define ARM_C0_APROTSYST 0x0000F000 /* Only system mode */
3744 +
3745 +
3746 +#define ARM_CONTROL1 HW_REGISTER_RW(ARM_BASE+0x440)
3747 +#define ARM_C1_TIMER 0x00000001 /* re-route timer IRQ to VC */
3748 +#define ARM_C1_MAIL 0x00000002 /* re-route Mail IRQ to VC */
3749 +#define ARM_C1_BELL0 0x00000004 /* re-route Doorbell 0 to VC */
3750 +#define ARM_C1_BELL1 0x00000008 /* re-route Doorbell 1 to VC */
3751 +#define ARM_C1_PERSON 0x00000100 /* peripherals on */
3752 +#define ARM_C1_REQSTOP 0x00000200 /* ASYNC bridge request stop */
3753 +
3754 +#define ARM_STATUS HW_REGISTER_RW(ARM_BASE+0x444)
3755 +#define ARM_S_ACKSTOP 0x80000000 /* Bridge stopped */
3756 +#define ARM_S_READPEND 0x000003FF /* pending reads counter */
3757 +#define ARM_S_WRITPEND 0x000FFC00 /* pending writes counter */
3758 +
3759 +#define ARM_ERRHALT HW_REGISTER_RW(ARM_BASE+0x448)
3760 +#define ARM_EH_PERIBURST 0x00000001 /* Burst write seen on peri bus */
3761 +#define ARM_EH_ILLADDRS1 0x00000002 /* Address bits 25-27 error */
3762 +#define ARM_EH_ILLADDRS2 0x00000004 /* Address bits 31-28 error */
3763 +#define ARM_EH_VPU0HALT 0x00000008 /* VPU0 halted & in debug mode */
3764 +#define ARM_EH_VPU1HALT 0x00000010 /* VPU1 halted & in debug mode */
3765 +#define ARM_EH_ARMHALT 0x00000020 /* ARM in halted debug mode */
3766 +
3767 +#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C)
3768 +#define ARM_ID HW_REGISTER_RW(ARM_BASE+0x44C)
3769 +#define ARM_IDVAL 0x364D5241
3770 +
3771 +/* Translation memory */
3772 +#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100)
3773 +/* 32 locations: 0x100.. 0x17F */
3774 +/* 32 spare means we CAN go to 64 pages.... */
3775 +
3776 +
3777 +/* Interrupts */
3778 +#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200) /* Top IRQ bits */
3779 +#define ARM_I0_TIMER 0x00000001 /* timer IRQ */
3780 +#define ARM_I0_MAIL 0x00000002 /* Mail IRQ */
3781 +#define ARM_I0_BELL0 0x00000004 /* Doorbell 0 */
3782 +#define ARM_I0_BELL1 0x00000008 /* Doorbell 1 */
3783 +#define ARM_I0_BANK1 0x00000100 /* Bank1 IRQ */
3784 +#define ARM_I0_BANK2 0x00000200 /* Bank2 IRQ */
3785 +
3786 +#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) /* All bank1 IRQ bits */
3787 +/* todo: all I1_interrupt sources */
3788 +#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) /* All bank2 IRQ bits */
3789 +/* todo: all I2_interrupt sources */
3790 +
3791 +#define ARM_IRQ_FAST HW_REGISTER_RW(ARM_BASE+0x20C) /* FIQ control */
3792 +#define ARM_IF_INDEX 0x0000007F /* FIQ select */
3793 +#define ARM_IF_ENABLE 0x00000080 /* FIQ enable */
3794 +#define ARM_IF_VCMASK 0x0000003F /* FIQ = (index from VC source) */
3795 +#define ARM_IF_TIMER 0x00000040 /* FIQ = ARM timer */
3796 +#define ARM_IF_MAIL 0x00000041 /* FIQ = ARM Mail */
3797 +#define ARM_IF_BELL0 0x00000042 /* FIQ = ARM Doorbell 0 */
3798 +#define ARM_IF_BELL1 0x00000043 /* FIQ = ARM Doorbell 1 */
3799 +#define ARM_IF_VP0HALT 0x00000044 /* FIQ = VPU0 Halt seen */
3800 +#define ARM_IF_VP1HALT 0x00000045 /* FIQ = VPU1 Halt seen */
3801 +#define ARM_IF_ILLEGAL 0x00000046 /* FIQ = Illegal access seen */
3802 +
3803 +#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) /* Bank1 enable bits */
3804 +#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) /* Bank2 enable bits */
3805 +#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) /* ARM irqs enable bits */
3806 +#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) /* Bank1 disable bits */
3807 +#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) /* Bank2 disable bits */
3808 +#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) /* ARM irqs disable bits */
3809 +#define ARM_IE_TIMER 0x00000001 /* Timer IRQ */
3810 +#define ARM_IE_MAIL 0x00000002 /* Mail IRQ */
3811 +#define ARM_IE_BELL0 0x00000004 /* Doorbell 0 */
3812 +#define ARM_IE_BELL1 0x00000008 /* Doorbell 1 */
3813 +#define ARM_IE_VP0HALT 0x00000010 /* VPU0 Halt */
3814 +#define ARM_IE_VP1HALT 0x00000020 /* VPU1 Halt */
3815 +#define ARM_IE_ILLEGAL 0x00000040 /* Illegal access seen */
3816 +
3817 +/* Timer */
3818 +/* For reg. fields see sp804 spec. */
3819 +#define ARM_T_LOAD HW_REGISTER_RW(ARM_BASE+0x400)
3820 +#define ARM_T_VALUE HW_REGISTER_RW(ARM_BASE+0x404)
3821 +#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408)
3822 +#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C)
3823 +#define ARM_T_RAWIRQ HW_REGISTER_RW(ARM_BASE+0x410)
3824 +#define ARM_T_MSKIRQ HW_REGISTER_RW(ARM_BASE+0x414)
3825 +#define ARM_T_RELOAD HW_REGISTER_RW(ARM_BASE+0x418)
3826 +#define ARM_T_PREDIV HW_REGISTER_RW(ARM_BASE+0x41c)
3827 +#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420)
3828 +
3829 +#define TIMER_CTRL_ONESHOT (1 << 0)
3830 +#define TIMER_CTRL_32BIT (1 << 1)
3831 +#define TIMER_CTRL_DIV1 (0 << 2)
3832 +#define TIMER_CTRL_DIV16 (1 << 2)
3833 +#define TIMER_CTRL_DIV256 (2 << 2)
3834 +#define TIMER_CTRL_IE (1 << 5)
3835 +#define TIMER_CTRL_PERIODIC (1 << 6)
3836 +#define TIMER_CTRL_ENABLE (1 << 7)
3837 +#define TIMER_CTRL_DBGHALT (1 << 8)
3838 +#define TIMER_CTRL_ENAFREE (1 << 9)
3839 +#define TIMER_CTRL_FREEDIV_SHIFT 16)
3840 +#define TIMER_CTRL_FREEDIV_MASK 0xff
3841 +
3842 +/* Semaphores, Doorbells, Mailboxes */
3843 +#define ARM_SBM_OWN0 (ARM_BASE+0x800)
3844 +#define ARM_SBM_OWN1 (ARM_BASE+0x900)
3845 +#define ARM_SBM_OWN2 (ARM_BASE+0xA00)
3846 +#define ARM_SBM_OWN3 (ARM_BASE+0xB00)
3847 +
3848 +/* MAILBOXES
3849 + * Register flags are common across all
3850 + * owner registers. See end of this section
3851 + *
3852 + * Semaphores, Doorbells, Mailboxes Owner 0
3853 + *
3854 + */
3855 +
3856 +#define ARM_0_SEMS HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
3857 +#define ARM_0_SEM0 HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
3858 +#define ARM_0_SEM1 HW_REGISTER_RW(ARM_SBM_OWN0+0x04)
3859 +#define ARM_0_SEM2 HW_REGISTER_RW(ARM_SBM_OWN0+0x08)
3860 +#define ARM_0_SEM3 HW_REGISTER_RW(ARM_SBM_OWN0+0x0C)
3861 +#define ARM_0_SEM4 HW_REGISTER_RW(ARM_SBM_OWN0+0x10)
3862 +#define ARM_0_SEM5 HW_REGISTER_RW(ARM_SBM_OWN0+0x14)
3863 +#define ARM_0_SEM6 HW_REGISTER_RW(ARM_SBM_OWN0+0x18)
3864 +#define ARM_0_SEM7 HW_REGISTER_RW(ARM_SBM_OWN0+0x1C)
3865 +#define ARM_0_BELL0 HW_REGISTER_RW(ARM_SBM_OWN0+0x40)
3866 +#define ARM_0_BELL1 HW_REGISTER_RW(ARM_SBM_OWN0+0x44)
3867 +#define ARM_0_BELL2 HW_REGISTER_RW(ARM_SBM_OWN0+0x48)
3868 +#define ARM_0_BELL3 HW_REGISTER_RW(ARM_SBM_OWN0+0x4C)
3869 +/* MAILBOX 0 access in Owner 0 area */
3870 +/* Some addresses should ONLY be used by owner 0 */
3871 +#define ARM_0_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) */
3872 +#define ARM_0_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) Normal read */
3873 +#define ARM_0_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN0+0x90) /* none-pop read */
3874 +#define ARM_0_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN0+0x94) /* Sender read (only LS 2 bits) */
3875 +#define ARM_0_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN0+0x98) /* Status read */
3876 +#define ARM_0_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0x9C) /* Config read/write */
3877 +/* MAILBOX 1 access in Owner 0 area */
3878 +/* Owner 0 should only WRITE to this mailbox */
3879 +#define ARM_0_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) /* .. 0xAC (4 locations) */
3880 +/*#define ARM_0_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) */ /* DO NOT USE THIS !!!!! */
3881 +/*#define ARM_0_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) */ /* DO NOT USE THIS !!!!! */
3882 +/*#define ARM_0_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) */ /* DO NOT USE THIS !!!!! */
3883 +#define ARM_0_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN0+0xB8) /* Status read */
3884 +/*#define ARM_0_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) */ /* DO NOT USE THIS !!!!! */
3885 +/* General SEM, BELL, MAIL config/status */
3886 +#define ARM_0_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE0) /* semaphore clear/debug register */
3887 +#define ARM_0_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE4) /* Doorbells clear/debug register */
3888 +#define ARM_0_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xF8) /* ALL interrupts */
3889 +#define ARM_0_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xFC) /* IRQS pending for owner 0 */
3890 +
3891 +/* Semaphores, Doorbells, Mailboxes Owner 1 */
3892 +#define ARM_1_SEMS HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
3893 +#define ARM_1_SEM0 HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
3894 +#define ARM_1_SEM1 HW_REGISTER_RW(ARM_SBM_OWN1+0x04)
3895 +#define ARM_1_SEM2 HW_REGISTER_RW(ARM_SBM_OWN1+0x08)
3896 +#define ARM_1_SEM3 HW_REGISTER_RW(ARM_SBM_OWN1+0x0C)
3897 +#define ARM_1_SEM4 HW_REGISTER_RW(ARM_SBM_OWN1+0x10)
3898 +#define ARM_1_SEM5 HW_REGISTER_RW(ARM_SBM_OWN1+0x14)
3899 +#define ARM_1_SEM6 HW_REGISTER_RW(ARM_SBM_OWN1+0x18)
3900 +#define ARM_1_SEM7 HW_REGISTER_RW(ARM_SBM_OWN1+0x1C)
3901 +#define ARM_1_BELL0 HW_REGISTER_RW(ARM_SBM_OWN1+0x40)
3902 +#define ARM_1_BELL1 HW_REGISTER_RW(ARM_SBM_OWN1+0x44)
3903 +#define ARM_1_BELL2 HW_REGISTER_RW(ARM_SBM_OWN1+0x48)
3904 +#define ARM_1_BELL3 HW_REGISTER_RW(ARM_SBM_OWN1+0x4C)
3905 +/* MAILBOX 0 access in Owner 0 area */
3906 +/* Owner 1 should only WRITE to this mailbox */
3907 +#define ARM_1_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0x80) /* .. 0x8C (4 locations) */
3908 +/*#define ARM_1_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN1+0x80) */ /* DO NOT USE THIS !!!!! */
3909 +/*#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) */ /* DO NOT USE THIS !!!!! */
3910 +/*#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) */ /* DO NOT USE THIS !!!!! */
3911 +#define ARM_1_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN1+0x98) /* Status read */
3912 +/*#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) */ /* DO NOT USE THIS !!!!! */
3913 +/* MAILBOX 1 access in Owner 0 area */
3914 +#define ARM_1_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) */
3915 +#define ARM_1_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) Normal read */
3916 +#define ARM_1_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN1+0xB0) /* none-pop read */
3917 +#define ARM_1_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN1+0xB4) /* Sender read (only LS 2 bits) */
3918 +#define ARM_1_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN1+0xB8) /* Status read */
3919 +#define ARM_1_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0xBC)
3920 +/* General SEM, BELL, MAIL config/status */
3921 +#define ARM_1_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE0) /* semaphore clear/debug register */
3922 +#define ARM_1_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE4) /* Doorbells clear/debug register */
3923 +#define ARM_1_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xFC) /* IRQS pending for owner 1 */
3924 +#define ARM_1_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xF8) /* ALL interrupts */
3925 +
3926 +/* Semaphores, Doorbells, Mailboxes Owner 2 */
3927 +#define ARM_2_SEMS HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
3928 +#define ARM_2_SEM0 HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
3929 +#define ARM_2_SEM1 HW_REGISTER_RW(ARM_SBM_OWN2+0x04)
3930 +#define ARM_2_SEM2 HW_REGISTER_RW(ARM_SBM_OWN2+0x08)
3931 +#define ARM_2_SEM3 HW_REGISTER_RW(ARM_SBM_OWN2+0x0C)
3932 +#define ARM_2_SEM4 HW_REGISTER_RW(ARM_SBM_OWN2+0x10)
3933 +#define ARM_2_SEM5 HW_REGISTER_RW(ARM_SBM_OWN2+0x14)
3934 +#define ARM_2_SEM6 HW_REGISTER_RW(ARM_SBM_OWN2+0x18)
3935 +#define ARM_2_SEM7 HW_REGISTER_RW(ARM_SBM_OWN2+0x1C)
3936 +#define ARM_2_BELL0 HW_REGISTER_RW(ARM_SBM_OWN2+0x40)
3937 +#define ARM_2_BELL1 HW_REGISTER_RW(ARM_SBM_OWN2+0x44)
3938 +#define ARM_2_BELL2 HW_REGISTER_RW(ARM_SBM_OWN2+0x48)
3939 +#define ARM_2_BELL3 HW_REGISTER_RW(ARM_SBM_OWN2+0x4C)
3940 +/* MAILBOX 0 access in Owner 2 area */
3941 +/* Owner 2 should only WRITE to this mailbox */
3942 +#define ARM_2_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0x80) /* .. 0x8C (4 locations) */
3943 +/*#define ARM_2_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN2+0x80) */ /* DO NOT USE THIS !!!!! */
3944 +/*#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90) */ /* DO NOT USE THIS !!!!! */
3945 +/*#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94) */ /* DO NOT USE THIS !!!!! */
3946 +#define ARM_2_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN2+0x98) /* Status read */
3947 +/*#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C) */ /* DO NOT USE THIS !!!!! */
3948 +/* MAILBOX 1 access in Owner 2 area */
3949 +/* Owner 2 should only WRITE to this mailbox */
3950 +#define ARM_2_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) /* .. 0xAC (4 locations) */
3951 +/*#define ARM_2_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) */ /* DO NOT USE THIS !!!!! */
3952 +/*#define ARM_2_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) */ /* DO NOT USE THIS !!!!! */
3953 +/*#define ARM_2_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) */ /* DO NOT USE THIS !!!!! */
3954 +#define ARM_2_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN2+0xB8) /* Status read */
3955 +/*#define ARM_2_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) */ /* DO NOT USE THIS !!!!! */
3956 +/* General SEM, BELL, MAIL config/status */
3957 +#define ARM_2_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE0) /* semaphore clear/debug register */
3958 +#define ARM_2_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE4) /* Doorbells clear/debug register */
3959 +#define ARM_2_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xFC) /* IRQS pending for owner 2 */
3960 +#define ARM_2_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xF8) /* ALL interrupts */
3961 +
3962 +/* Semaphores, Doorbells, Mailboxes Owner 3 */
3963 +#define ARM_3_SEMS HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
3964 +#define ARM_3_SEM0 HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
3965 +#define ARM_3_SEM1 HW_REGISTER_RW(ARM_SBM_OWN3+0x04)
3966 +#define ARM_3_SEM2 HW_REGISTER_RW(ARM_SBM_OWN3+0x08)
3967 +#define ARM_3_SEM3 HW_REGISTER_RW(ARM_SBM_OWN3+0x0C)
3968 +#define ARM_3_SEM4 HW_REGISTER_RW(ARM_SBM_OWN3+0x10)
3969 +#define ARM_3_SEM5 HW_REGISTER_RW(ARM_SBM_OWN3+0x14)
3970 +#define ARM_3_SEM6 HW_REGISTER_RW(ARM_SBM_OWN3+0x18)
3971 +#define ARM_3_SEM7 HW_REGISTER_RW(ARM_SBM_OWN3+0x1C)
3972 +#define ARM_3_BELL0 HW_REGISTER_RW(ARM_SBM_OWN3+0x40)
3973 +#define ARM_3_BELL1 HW_REGISTER_RW(ARM_SBM_OWN3+0x44)
3974 +#define ARM_3_BELL2 HW_REGISTER_RW(ARM_SBM_OWN3+0x48)
3975 +#define ARM_3_BELL3 HW_REGISTER_RW(ARM_SBM_OWN3+0x4C)
3976 +/* MAILBOX 0 access in Owner 3 area */
3977 +/* Owner 3 should only WRITE to this mailbox */
3978 +#define ARM_3_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0x80) /* .. 0x8C (4 locations) */
3979 +/*#define ARM_3_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN3+0x80) */ /* DO NOT USE THIS !!!!! */
3980 +/*#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90) */ /* DO NOT USE THIS !!!!! */
3981 +/*#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94) */ /* DO NOT USE THIS !!!!! */
3982 +#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98) /* Status read */
3983 +/*#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C) */ /* DO NOT USE THIS !!!!! */
3984 +/* MAILBOX 1 access in Owner 3 area */
3985 +/* Owner 3 should only WRITE to this mailbox */
3986 +#define ARM_3_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) /* .. 0xAC (4 locations) */
3987 +/*#define ARM_3_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) */ /* DO NOT USE THIS !!!!! */
3988 +/*#define ARM_3_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) */ /* DO NOT USE THIS !!!!! */
3989 +/*#define ARM_3_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) */ /* DO NOT USE THIS !!!!! */
3990 +#define ARM_3_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN3+0xB8) /* Status read */
3991 +/*#define ARM_3_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) */ /* DO NOT USE THIS !!!!! */
3992 +/* General SEM, BELL, MAIL config/status */
3993 +#define ARM_3_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE0) /* semaphore clear/debug register */
3994 +#define ARM_3_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE4) /* Doorbells clear/debug register */
3995 +#define ARM_3_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xFC) /* IRQS pending for owner 3 */
3996 +#define ARM_3_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xF8) /* ALL interrupts */
3997 +
3998 +
3999 +
4000 +/* Mailbox flags. Valid for all owners */
4001 +
4002 +/* Mailbox status register (...0x98) */
4003 +#define ARM_MS_FULL 0x80000000
4004 +#define ARM_MS_EMPTY 0x40000000
4005 +#define ARM_MS_LEVEL 0x400000FF /* Max. value depdnds on mailbox depth parameter */
4006 +
4007 +/* MAILBOX config/status register (...0x9C) */
4008 +/* ANY write to this register clears the error bits! */
4009 +#define ARM_MC_IHAVEDATAIRQEN 0x00000001 /* mailbox irq enable: has data */
4010 +#define ARM_MC_IHAVESPACEIRQEN 0x00000002 /* mailbox irq enable: has space */
4011 +#define ARM_MC_OPPISEMPTYIRQEN 0x00000004 /* mailbox irq enable: Opp. is empty */
4012 +#define ARM_MC_MAIL_CLEAR 0x00000008 /* mailbox clear write 1, then 0 */
4013 +#define ARM_MC_IHAVEDATAIRQPEND 0x00000010 /* mailbox irq pending: has space */
4014 +#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 /* mailbox irq pending: Opp. is empty */
4015 +#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 /* mailbox irq pending */
4016 +/* Bit 7 is unused */
4017 +#define ARM_MC_ERRNOOWN 0x00000100 /* error : none owner read from mailbox */
4018 +#define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */
4019 +#define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */
4020 +
4021 +/* Semaphore clear/debug register (...0xE0) */
4022 +#define ARM_SD_OWN0 0x00000003 /* Owner of sem 0 */
4023 +#define ARM_SD_OWN1 0x0000000C /* Owner of sem 1 */
4024 +#define ARM_SD_OWN2 0x00000030 /* Owner of sem 2 */
4025 +#define ARM_SD_OWN3 0x000000C0 /* Owner of sem 3 */
4026 +#define ARM_SD_OWN4 0x00000300 /* Owner of sem 4 */
4027 +#define ARM_SD_OWN5 0x00000C00 /* Owner of sem 5 */
4028 +#define ARM_SD_OWN6 0x00003000 /* Owner of sem 6 */
4029 +#define ARM_SD_OWN7 0x0000C000 /* Owner of sem 7 */
4030 +#define ARM_SD_SEM0 0x00010000 /* Status of sem 0 */
4031 +#define ARM_SD_SEM1 0x00020000 /* Status of sem 1 */
4032 +#define ARM_SD_SEM2 0x00040000 /* Status of sem 2 */
4033 +#define ARM_SD_SEM3 0x00080000 /* Status of sem 3 */
4034 +#define ARM_SD_SEM4 0x00100000 /* Status of sem 4 */
4035 +#define ARM_SD_SEM5 0x00200000 /* Status of sem 5 */
4036 +#define ARM_SD_SEM6 0x00400000 /* Status of sem 6 */
4037 +#define ARM_SD_SEM7 0x00800000 /* Status of sem 7 */
4038 +
4039 +/* Doorbells clear/debug register (...0xE4) */
4040 +#define ARM_BD_OWN0 0x00000003 /* Owner of doorbell 0 */
4041 +#define ARM_BD_OWN1 0x0000000C /* Owner of doorbell 1 */
4042 +#define ARM_BD_OWN2 0x00000030 /* Owner of doorbell 2 */
4043 +#define ARM_BD_OWN3 0x000000C0 /* Owner of doorbell 3 */
4044 +#define ARM_BD_BELL0 0x00000100 /* Status of doorbell 0 */
4045 +#define ARM_BD_BELL1 0x00000200 /* Status of doorbell 1 */
4046 +#define ARM_BD_BELL2 0x00000400 /* Status of doorbell 2 */
4047 +#define ARM_BD_BELL3 0x00000800 /* Status of doorbell 3 */
4048 +
4049 +/* MY IRQS register (...0xF8) */
4050 +#define ARM_MYIRQ_BELL 0x00000001 /* This owner has a doorbell IRQ */
4051 +#define ARM_MYIRQ_MAIL 0x00000002 /* This owner has a mailbox IRQ */
4052 +
4053 +/* ALL IRQS register (...0xF8) */
4054 +#define ARM_AIS_BELL0 0x00000001 /* Doorbell 0 IRQ pending */
4055 +#define ARM_AIS_BELL1 0x00000002 /* Doorbell 1 IRQ pending */
4056 +#define ARM_AIS_BELL2 0x00000004 /* Doorbell 2 IRQ pending */
4057 +#define ARM_AIS_BELL3 0x00000008 /* Doorbell 3 IRQ pending */
4058 +#define ARM_AIS0_HAVEDATA 0x00000010 /* MAIL 0 has data IRQ pending */
4059 +#define ARM_AIS0_HAVESPAC 0x00000020 /* MAIL 0 has space IRQ pending */
4060 +#define ARM_AIS0_OPPEMPTY 0x00000040 /* MAIL 0 opposite is empty IRQ */
4061 +#define ARM_AIS1_HAVEDATA 0x00000080 /* MAIL 1 has data IRQ pending */
4062 +#define ARM_AIS1_HAVESPAC 0x00000100 /* MAIL 1 has space IRQ pending */
4063 +#define ARM_AIS1_OPPEMPTY 0x00000200 /* MAIL 1 opposite is empty IRQ */
4064 +/* Note that bell-0, bell-1 and MAIL0 IRQ go only to the ARM */
4065 +/* Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC */
4066 +/* */
4067 +/* ARM JTAG BASH */
4068 +/* */
4069 +#define AJB_BASE 0x7e2000c0
4070 +
4071 +#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00)
4072 +#define AJB_BITS0 0x000000
4073 +#define AJB_BITS4 0x000004
4074 +#define AJB_BITS8 0x000008
4075 +#define AJB_BITS12 0x00000C
4076 +#define AJB_BITS16 0x000010
4077 +#define AJB_BITS20 0x000014
4078 +#define AJB_BITS24 0x000018
4079 +#define AJB_BITS28 0x00001C
4080 +#define AJB_BITS32 0x000020
4081 +#define AJB_BITS34 0x000022
4082 +#define AJB_OUT_MS 0x000040
4083 +#define AJB_OUT_LS 0x000000
4084 +#define AJB_INV_CLK 0x000080
4085 +#define AJB_D0_RISE 0x000100
4086 +#define AJB_D0_FALL 0x000000
4087 +#define AJB_D1_RISE 0x000200
4088 +#define AJB_D1_FALL 0x000000
4089 +#define AJB_IN_RISE 0x000400
4090 +#define AJB_IN_FALL 0x000000
4091 +#define AJB_ENABLE 0x000800
4092 +#define AJB_HOLD0 0x000000
4093 +#define AJB_HOLD1 0x001000
4094 +#define AJB_HOLD2 0x002000
4095 +#define AJB_HOLD3 0x003000
4096 +#define AJB_RESETN 0x004000
4097 +#define AJB_CLKSHFT 16
4098 +#define AJB_BUSY 0x80000000
4099 +#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04)
4100 +#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08)
4101 +#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c)
4102 +
4103 +#endif
4104 diff --git a/arch/arm/mach-bcm2708/include/mach/arm_power.h b/arch/arm/mach-bcm2708/include/mach/arm_power.h
4105 new file mode 100644
4106 index 0000000..aae9136
4107 --- /dev/null
4108 +++ b/arch/arm/mach-bcm2708/include/mach/arm_power.h
4109 @@ -0,0 +1,60 @@
4110 +/*
4111 + * linux/arch/arm/mach-bcm2708/include/mach/arm_power.h
4112 + *
4113 + * Copyright (C) 2010 Broadcom
4114 + *
4115 + * This program is free software; you can redistribute it and/or modify
4116 + * it under the terms of the GNU General Public License as published by
4117 + * the Free Software Foundation; either version 2 of the License, or
4118 + * (at your option) any later version.
4119 + *
4120 + * This program is distributed in the hope that it will be useful,
4121 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4122 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4123 + * GNU General Public License for more details.
4124 + *
4125 + * You should have received a copy of the GNU General Public License
4126 + * along with this program; if not, write to the Free Software
4127 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4128 + */
4129 +
4130 +#ifndef _ARM_POWER_H
4131 +#define _ARM_POWER_H
4132 +
4133 +/* Use meaningful names on each side */
4134 +#ifdef __VIDEOCORE__
4135 +#define PREFIX(x) ARM_##x
4136 +#else
4137 +#define PREFIX(x) BCM_##x
4138 +#endif
4139 +
4140 +enum {
4141 + PREFIX(POWER_SDCARD_BIT),
4142 + PREFIX(POWER_UART_BIT),
4143 + PREFIX(POWER_MINIUART_BIT),
4144 + PREFIX(POWER_USB_BIT),
4145 + PREFIX(POWER_I2C0_BIT),
4146 + PREFIX(POWER_I2C1_BIT),
4147 + PREFIX(POWER_I2C2_BIT),
4148 + PREFIX(POWER_SPI_BIT),
4149 + PREFIX(POWER_CCP2TX_BIT),
4150 +
4151 + PREFIX(POWER_MAX)
4152 +};
4153 +
4154 +enum {
4155 + PREFIX(POWER_SDCARD) = (1 << PREFIX(POWER_SDCARD_BIT)),
4156 + PREFIX(POWER_UART) = (1 << PREFIX(POWER_UART_BIT)),
4157 + PREFIX(POWER_MINIUART) = (1 << PREFIX(POWER_MINIUART_BIT)),
4158 + PREFIX(POWER_USB) = (1 << PREFIX(POWER_USB_BIT)),
4159 + PREFIX(POWER_I2C0) = (1 << PREFIX(POWER_I2C0_BIT)),
4160 + PREFIX(POWER_I2C1_MASK) = (1 << PREFIX(POWER_I2C1_BIT)),
4161 + PREFIX(POWER_I2C2_MASK) = (1 << PREFIX(POWER_I2C2_BIT)),
4162 + PREFIX(POWER_SPI_MASK) = (1 << PREFIX(POWER_SPI_BIT)),
4163 + PREFIX(POWER_CCP2TX_MASK) = (1 << PREFIX(POWER_CCP2TX_BIT)),
4164 +
4165 + PREFIX(POWER_MASK) = (1 << PREFIX(POWER_MAX)) - 1,
4166 + PREFIX(POWER_NONE) = 0
4167 +};
4168 +
4169 +#endif
4170 diff --git a/arch/arm/mach-bcm2708/include/mach/clkdev.h b/arch/arm/mach-bcm2708/include/mach/clkdev.h
4171 new file mode 100644
4172 index 0000000..04b37a8
4173 --- /dev/null
4174 +++ b/arch/arm/mach-bcm2708/include/mach/clkdev.h
4175 @@ -0,0 +1,7 @@
4176 +#ifndef __ASM_MACH_CLKDEV_H
4177 +#define __ASM_MACH_CLKDEV_H
4178 +
4179 +#define __clk_get(clk) ({ 1; })
4180 +#define __clk_put(clk) do { } while (0)
4181 +
4182 +#endif
4183 diff --git a/arch/arm/mach-bcm2708/include/mach/debug-macro.S b/arch/arm/mach-bcm2708/include/mach/debug-macro.S
4184 new file mode 100644
4185 index 0000000..b24304a
4186 --- /dev/null
4187 +++ b/arch/arm/mach-bcm2708/include/mach/debug-macro.S
4188 @@ -0,0 +1,22 @@
4189 +/* arch/arm/mach-bcm2708/include/mach/debug-macro.S
4190 + *
4191 + * Debugging macro include header
4192 + *
4193 + * Copyright (C) 2010 Broadcom
4194 + * Copyright (C) 1994-1999 Russell King
4195 + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
4196 + *
4197 + * This program is free software; you can redistribute it and/or modify
4198 + * it under the terms of the GNU General Public License version 2 as
4199 + * published by the Free Software Foundation.
4200 + *
4201 +*/
4202 +
4203 +#include <mach/platform.h>
4204 +
4205 + .macro addruart, rp, rv, tmp
4206 + ldr \rp, =UART0_BASE
4207 + ldr \rv, =IO_ADDRESS(UART0_BASE)
4208 + .endm
4209 +
4210 +#include <debug/pl01x.S>
4211 diff --git a/arch/arm/mach-bcm2708/include/mach/dma.h b/arch/arm/mach-bcm2708/include/mach/dma.h
4212 new file mode 100644
4213 index 0000000..ac7a4a0
4214 --- /dev/null
4215 +++ b/arch/arm/mach-bcm2708/include/mach/dma.h
4216 @@ -0,0 +1,86 @@
4217 +/*
4218 + * linux/arch/arm/mach-bcm2708/include/mach/dma.h
4219 + *
4220 + * Copyright (C) 2010 Broadcom
4221 + *
4222 + * This program is free software; you can redistribute it and/or modify
4223 + * it under the terms of the GNU General Public License version 2 as
4224 + * published by the Free Software Foundation.
4225 + */
4226 +
4227 +
4228 +#ifndef _MACH_BCM2708_DMA_H
4229 +#define _MACH_BCM2708_DMA_H
4230 +
4231 +#define BCM_DMAMAN_DRIVER_NAME "bcm2708_dma"
4232 +
4233 +/* DMA CS Control and Status bits */
4234 +#define BCM2708_DMA_ACTIVE (1 << 0)
4235 +#define BCM2708_DMA_INT (1 << 2)
4236 +#define BCM2708_DMA_ISPAUSED (1 << 4) /* Pause requested or not active */
4237 +#define BCM2708_DMA_ISHELD (1 << 5) /* Is held by DREQ flow control */
4238 +#define BCM2708_DMA_ERR (1 << 8)
4239 +#define BCM2708_DMA_ABORT (1 << 30) /* stop current CB, go to next, WO */
4240 +#define BCM2708_DMA_RESET (1 << 31) /* WO, self clearing */
4241 +
4242 +/* DMA control block "info" field bits */
4243 +#define BCM2708_DMA_INT_EN (1 << 0)
4244 +#define BCM2708_DMA_TDMODE (1 << 1)
4245 +#define BCM2708_DMA_WAIT_RESP (1 << 3)
4246 +#define BCM2708_DMA_D_INC (1 << 4)
4247 +#define BCM2708_DMA_D_WIDTH (1 << 5)
4248 +#define BCM2708_DMA_D_DREQ (1 << 6)
4249 +#define BCM2708_DMA_S_INC (1 << 8)
4250 +#define BCM2708_DMA_S_WIDTH (1 << 9)
4251 +#define BCM2708_DMA_S_DREQ (1 << 10)
4252 +
4253 +#define BCM2708_DMA_BURST(x) (((x)&0xf) << 12)
4254 +#define BCM2708_DMA_PER_MAP(x) ((x) << 16)
4255 +#define BCM2708_DMA_WAITS(x) (((x)&0x1f) << 21)
4256 +
4257 +#define BCM2708_DMA_DREQ_EMMC 11
4258 +#define BCM2708_DMA_DREQ_SDHOST 13
4259 +
4260 +#define BCM2708_DMA_CS 0x00 /* Control and Status */
4261 +#define BCM2708_DMA_ADDR 0x04
4262 +/* the current control block appears in the following registers - read only */
4263 +#define BCM2708_DMA_INFO 0x08
4264 +#define BCM2708_DMA_NEXTCB 0x1C
4265 +#define BCM2708_DMA_DEBUG 0x20
4266 +
4267 +#define BCM2708_DMA4_CS (BCM2708_DMA_CHAN(4)+BCM2708_DMA_CS)
4268 +#define BCM2708_DMA4_ADDR (BCM2708_DMA_CHAN(4)+BCM2708_DMA_ADDR)
4269 +
4270 +#define BCM2708_DMA_TDMODE_LEN(w, h) ((h) << 16 | (w))
4271 +
4272 +struct bcm2708_dma_cb {
4273 + unsigned long info;
4274 + unsigned long src;
4275 + unsigned long dst;
4276 + unsigned long length;
4277 + unsigned long stride;
4278 + unsigned long next;
4279 + unsigned long pad[2];
4280 +};
4281 +
4282 +extern int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len);
4283 +extern void bcm_dma_start(void __iomem *dma_chan_base,
4284 + dma_addr_t control_block);
4285 +extern void bcm_dma_wait_idle(void __iomem *dma_chan_base);
4286 +extern int /*rc*/ bcm_dma_abort(void __iomem *dma_chan_base);
4287 +
4288 +/* When listing features we can ask for when allocating DMA channels give
4289 + those with higher priority smaller ordinal numbers */
4290 +#define BCM_DMA_FEATURE_FAST_ORD 0
4291 +#define BCM_DMA_FEATURE_BULK_ORD 1
4292 +#define BCM_DMA_FEATURE_FAST (1<<BCM_DMA_FEATURE_FAST_ORD)
4293 +#define BCM_DMA_FEATURE_BULK (1<<BCM_DMA_FEATURE_BULK_ORD)
4294 +#define BCM_DMA_FEATURE_COUNT 2
4295 +
4296 +/* return channel no or -ve error */
4297 +extern int bcm_dma_chan_alloc(unsigned preferred_feature_set,
4298 + void __iomem **out_dma_base, int *out_dma_irq);
4299 +extern int bcm_dma_chan_free(int channel);
4300 +
4301 +
4302 +#endif /* _MACH_BCM2708_DMA_H */
4303 diff --git a/arch/arm/mach-bcm2708/include/mach/entry-macro.S b/arch/arm/mach-bcm2708/include/mach/entry-macro.S
4304 new file mode 100644
4305 index 0000000..79b62d9
4306 --- /dev/null
4307 +++ b/arch/arm/mach-bcm2708/include/mach/entry-macro.S
4308 @@ -0,0 +1,69 @@
4309 +/*
4310 + * arch/arm/mach-bcm2708/include/mach/entry-macro.S
4311 + *
4312 + * Low-level IRQ helper macros for BCM2708 platforms
4313 + *
4314 + * Copyright (C) 2010 Broadcom
4315 + *
4316 + * This program is free software; you can redistribute it and/or modify
4317 + * it under the terms of the GNU General Public License as published by
4318 + * the Free Software Foundation; either version 2 of the License, or
4319 + * (at your option) any later version.
4320 + *
4321 + * This program is distributed in the hope that it will be useful,
4322 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4323 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4324 + * GNU General Public License for more details.
4325 + *
4326 + * You should have received a copy of the GNU General Public License
4327 + * along with this program; if not, write to the Free Software
4328 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4329 + */
4330 +#include <mach/hardware.h>
4331 +
4332 + .macro disable_fiq
4333 + .endm
4334 +
4335 + .macro get_irqnr_preamble, base, tmp
4336 + ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE)
4337 + .endm
4338 +
4339 + .macro arch_ret_to_user, tmp1, tmp2
4340 + .endm
4341 +
4342 + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
4343 + /* get masked status */
4344 + ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)]
4345 + mov \irqnr, #(ARM_IRQ0_BASE + 31)
4346 + and \tmp, \irqstat, #0x300 @ save bits 8 and 9
4347 + /* clear bits 8 and 9, and test */
4348 + bics \irqstat, \irqstat, #0x300
4349 + bne 1010f
4350 +
4351 + tst \tmp, #0x100
4352 + ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)]
4353 + movne \irqnr, #(ARM_IRQ1_BASE + 31)
4354 + @ Mask out the interrupts also present in PEND0 - see SW-5809
4355 + bicne \irqstat, #((1<<7) | (1<<9) | (1<<10))
4356 + bicne \irqstat, #((1<<18) | (1<<19))
4357 + bne 1010f
4358 +
4359 + tst \tmp, #0x200
4360 + ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)]
4361 + movne \irqnr, #(ARM_IRQ2_BASE + 31)
4362 + @ Mask out the interrupts also present in PEND0 - see SW-5809
4363 + bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25))
4364 + bicne \irqstat, #((1<<30))
4365 + beq 1020f
4366 +
4367 +1010:
4368 + @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
4369 + @ N.B. CLZ is an ARM5 instruction.
4370 + sub \tmp, \irqstat, #1
4371 + eor \irqstat, \irqstat, \tmp
4372 + clz \tmp, \irqstat
4373 + sub \irqnr, \tmp
4374 +
4375 +1020: @ EQ will be set if no irqs pending
4376 +
4377 + .endm
4378 diff --git a/arch/arm/mach-bcm2708/include/mach/frc.h b/arch/arm/mach-bcm2708/include/mach/frc.h
4379 new file mode 100644
4380 index 0000000..dd51e07
4381 --- /dev/null
4382 +++ b/arch/arm/mach-bcm2708/include/mach/frc.h
4383 @@ -0,0 +1,38 @@
4384 +/*
4385 + * arch/arm/mach-bcm2708/include/mach/timex.h
4386 + *
4387 + * BCM2708 free running counter (timer)
4388 + *
4389 + * Copyright (C) 2010 Broadcom
4390 + *
4391 + * This program is free software; you can redistribute it and/or modify
4392 + * it under the terms of the GNU General Public License as published by
4393 + * the Free Software Foundation; either version 2 of the License, or
4394 + * (at your option) any later version.
4395 + *
4396 + * This program is distributed in the hope that it will be useful,
4397 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4398 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4399 + * GNU General Public License for more details.
4400 + *
4401 + * You should have received a copy of the GNU General Public License
4402 + * along with this program; if not, write to the Free Software
4403 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4404 + */
4405 +
4406 +#ifndef _MACH_FRC_H
4407 +#define _MACH_FRC_H
4408 +
4409 +#define FRC_TICK_RATE (1000000)
4410 +
4411 +/*! Free running counter incrementing at the CLOCK_TICK_RATE
4412 + (slightly faster than frc_clock_ticks63()
4413 + */
4414 +extern unsigned long frc_clock_ticks32(void);
4415 +
4416 +/*! Free running counter incrementing at the CLOCK_TICK_RATE
4417 + * Note - top bit should be ignored (see cnt32_to_63)
4418 + */
4419 +extern unsigned long long frc_clock_ticks63(void);
4420 +
4421 +#endif
4422 diff --git a/arch/arm/mach-bcm2708/include/mach/gpio.h b/arch/arm/mach-bcm2708/include/mach/gpio.h
4423 new file mode 100644
4424 index 0000000..7965a97
4425 --- /dev/null
4426 +++ b/arch/arm/mach-bcm2708/include/mach/gpio.h
4427 @@ -0,0 +1,17 @@
4428 +/*
4429 + * arch/arm/mach-bcm2708/include/mach/gpio.h
4430 + *
4431 + * This file is licensed under the terms of the GNU General Public
4432 + * License version 2. This program is licensed "as is" without any
4433 + * warranty of any kind, whether express or implied.
4434 + */
4435 +
4436 +#ifndef __ASM_ARCH_GPIO_H
4437 +#define __ASM_ARCH_GPIO_H
4438 +
4439 +#define BCM2708_NR_GPIOS 54 // number of gpio lines
4440 +
4441 +#define gpio_to_irq(x) ((x) + GPIO_IRQ_START)
4442 +#define irq_to_gpio(x) ((x) - GPIO_IRQ_START)
4443 +
4444 +#endif
4445 diff --git a/arch/arm/mach-bcm2708/include/mach/hardware.h b/arch/arm/mach-bcm2708/include/mach/hardware.h
4446 new file mode 100644
4447 index 0000000..c2954e8
4448 --- /dev/null
4449 +++ b/arch/arm/mach-bcm2708/include/mach/hardware.h
4450 @@ -0,0 +1,28 @@
4451 +/*
4452 + * arch/arm/mach-bcm2708/include/mach/hardware.h
4453 + *
4454 + * This file contains the hardware definitions of the BCM2708 devices.
4455 + *
4456 + * Copyright (C) 2010 Broadcom
4457 + *
4458 + * This program is free software; you can redistribute it and/or modify
4459 + * it under the terms of the GNU General Public License as published by
4460 + * the Free Software Foundation; either version 2 of the License, or
4461 + * (at your option) any later version.
4462 + *
4463 + * This program is distributed in the hope that it will be useful,
4464 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4465 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4466 + * GNU General Public License for more details.
4467 + *
4468 + * You should have received a copy of the GNU General Public License
4469 + * along with this program; if not, write to the Free Software
4470 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4471 + */
4472 +#ifndef __ASM_ARCH_HARDWARE_H
4473 +#define __ASM_ARCH_HARDWARE_H
4474 +
4475 +#include <asm/sizes.h>
4476 +#include <mach/platform.h>
4477 +
4478 +#endif
4479 diff --git a/arch/arm/mach-bcm2708/include/mach/io.h b/arch/arm/mach-bcm2708/include/mach/io.h
4480 new file mode 100644
4481 index 0000000..e6eb84d
4482 --- /dev/null
4483 +++ b/arch/arm/mach-bcm2708/include/mach/io.h
4484 @@ -0,0 +1,27 @@
4485 +/*
4486 + * arch/arm/mach-bcm2708/include/mach/io.h
4487 + *
4488 + * Copyright (C) 2003 ARM Limited
4489 + *
4490 + * This program is free software; you can redistribute it and/or modify
4491 + * it under the terms of the GNU General Public License as published by
4492 + * the Free Software Foundation; either version 2 of the License, or
4493 + * (at your option) any later version.
4494 + *
4495 + * This program is distributed in the hope that it will be useful,
4496 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4497 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4498 + * GNU General Public License for more details.
4499 + *
4500 + * You should have received a copy of the GNU General Public License
4501 + * along with this program; if not, write to the Free Software
4502 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4503 + */
4504 +#ifndef __ASM_ARM_ARCH_IO_H
4505 +#define __ASM_ARM_ARCH_IO_H
4506 +
4507 +#define IO_SPACE_LIMIT 0xffffffff
4508 +
4509 +#define __io(a) __typesafe_io(a)
4510 +
4511 +#endif
4512 diff --git a/arch/arm/mach-bcm2708/include/mach/irqs.h b/arch/arm/mach-bcm2708/include/mach/irqs.h
4513 new file mode 100644
4514 index 0000000..faf5d1a
4515 --- /dev/null
4516 +++ b/arch/arm/mach-bcm2708/include/mach/irqs.h
4517 @@ -0,0 +1,194 @@
4518 +/*
4519 + * arch/arm/mach-bcm2708/include/mach/irqs.h
4520 + *
4521 + * Copyright (C) 2010 Broadcom
4522 + * Copyright (C) 2003 ARM Limited
4523 + * Copyright (C) 2000 Deep Blue Solutions Ltd.
4524 + *
4525 + * This program is free software; you can redistribute it and/or modify
4526 + * it under the terms of the GNU General Public License as published by
4527 + * the Free Software Foundation; either version 2 of the License, or
4528 + * (at your option) any later version.
4529 + *
4530 + * This program is distributed in the hope that it will be useful,
4531 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4532 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4533 + * GNU General Public License for more details.
4534 + *
4535 + * You should have received a copy of the GNU General Public License
4536 + * along with this program; if not, write to the Free Software
4537 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4538 + */
4539 +
4540 +#ifndef _BCM2708_IRQS_H_
4541 +#define _BCM2708_IRQS_H_
4542 +
4543 +#include <mach/platform.h>
4544 +
4545 +/*
4546 + * IRQ interrupts definitions are the same as the INT definitions
4547 + * held within platform.h
4548 + */
4549 +#define IRQ_ARMCTRL_START 0
4550 +#define IRQ_TIMER0 (IRQ_ARMCTRL_START + INTERRUPT_TIMER0)
4551 +#define IRQ_TIMER1 (IRQ_ARMCTRL_START + INTERRUPT_TIMER1)
4552 +#define IRQ_TIMER2 (IRQ_ARMCTRL_START + INTERRUPT_TIMER2)
4553 +#define IRQ_TIMER3 (IRQ_ARMCTRL_START + INTERRUPT_TIMER3)
4554 +#define IRQ_CODEC0 (IRQ_ARMCTRL_START + INTERRUPT_CODEC0)
4555 +#define IRQ_CODEC1 (IRQ_ARMCTRL_START + INTERRUPT_CODEC1)
4556 +#define IRQ_CODEC2 (IRQ_ARMCTRL_START + INTERRUPT_CODEC2)
4557 +#define IRQ_JPEG (IRQ_ARMCTRL_START + INTERRUPT_JPEG)
4558 +#define IRQ_ISP (IRQ_ARMCTRL_START + INTERRUPT_ISP)
4559 +#define IRQ_USB (IRQ_ARMCTRL_START + INTERRUPT_USB)
4560 +#define IRQ_3D (IRQ_ARMCTRL_START + INTERRUPT_3D)
4561 +#define IRQ_TRANSPOSER (IRQ_ARMCTRL_START + INTERRUPT_TRANSPOSER)
4562 +#define IRQ_MULTICORESYNC0 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC0)
4563 +#define IRQ_MULTICORESYNC1 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC1)
4564 +#define IRQ_MULTICORESYNC2 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC2)
4565 +#define IRQ_MULTICORESYNC3 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC3)
4566 +#define IRQ_DMA0 (IRQ_ARMCTRL_START + INTERRUPT_DMA0)
4567 +#define IRQ_DMA1 (IRQ_ARMCTRL_START + INTERRUPT_DMA1)
4568 +#define IRQ_DMA2 (IRQ_ARMCTRL_START + INTERRUPT_DMA2)
4569 +#define IRQ_DMA3 (IRQ_ARMCTRL_START + INTERRUPT_DMA3)
4570 +#define IRQ_DMA4 (IRQ_ARMCTRL_START + INTERRUPT_DMA4)
4571 +#define IRQ_DMA5 (IRQ_ARMCTRL_START + INTERRUPT_DMA5)
4572 +#define IRQ_DMA6 (IRQ_ARMCTRL_START + INTERRUPT_DMA6)
4573 +#define IRQ_DMA7 (IRQ_ARMCTRL_START + INTERRUPT_DMA7)
4574 +#define IRQ_DMA8 (IRQ_ARMCTRL_START + INTERRUPT_DMA8)
4575 +#define IRQ_DMA9 (IRQ_ARMCTRL_START + INTERRUPT_DMA9)
4576 +#define IRQ_DMA10 (IRQ_ARMCTRL_START + INTERRUPT_DMA10)
4577 +#define IRQ_DMA11 (IRQ_ARMCTRL_START + INTERRUPT_DMA11)
4578 +#define IRQ_DMA12 (IRQ_ARMCTRL_START + INTERRUPT_DMA12)
4579 +#define IRQ_AUX (IRQ_ARMCTRL_START + INTERRUPT_AUX)
4580 +#define IRQ_ARM (IRQ_ARMCTRL_START + INTERRUPT_ARM)
4581 +#define IRQ_VPUDMA (IRQ_ARMCTRL_START + INTERRUPT_VPUDMA)
4582 +#define IRQ_HOSTPORT (IRQ_ARMCTRL_START + INTERRUPT_HOSTPORT)
4583 +#define IRQ_VIDEOSCALER (IRQ_ARMCTRL_START + INTERRUPT_VIDEOSCALER)
4584 +#define IRQ_CCP2TX (IRQ_ARMCTRL_START + INTERRUPT_CCP2TX)
4585 +#define IRQ_SDC (IRQ_ARMCTRL_START + INTERRUPT_SDC)
4586 +#define IRQ_DSI0 (IRQ_ARMCTRL_START + INTERRUPT_DSI0)
4587 +#define IRQ_AVE (IRQ_ARMCTRL_START + INTERRUPT_AVE)
4588 +#define IRQ_CAM0 (IRQ_ARMCTRL_START + INTERRUPT_CAM0)
4589 +#define IRQ_CAM1 (IRQ_ARMCTRL_START + INTERRUPT_CAM1)
4590 +#define IRQ_HDMI0 (IRQ_ARMCTRL_START + INTERRUPT_HDMI0)
4591 +#define IRQ_HDMI1 (IRQ_ARMCTRL_START + INTERRUPT_HDMI1)
4592 +#define IRQ_PIXELVALVE1 (IRQ_ARMCTRL_START + INTERRUPT_PIXELVALVE1)
4593 +#define IRQ_I2CSPISLV (IRQ_ARMCTRL_START + INTERRUPT_I2CSPISLV)
4594 +#define IRQ_DSI1 (IRQ_ARMCTRL_START + INTERRUPT_DSI1)
4595 +#define IRQ_PWA0 (IRQ_ARMCTRL_START + INTERRUPT_PWA0)
4596 +#define IRQ_PWA1 (IRQ_ARMCTRL_START + INTERRUPT_PWA1)
4597 +#define IRQ_CPR (IRQ_ARMCTRL_START + INTERRUPT_CPR)
4598 +#define IRQ_SMI (IRQ_ARMCTRL_START + INTERRUPT_SMI)
4599 +#define IRQ_GPIO0 (IRQ_ARMCTRL_START + INTERRUPT_GPIO0)
4600 +#define IRQ_GPIO1 (IRQ_ARMCTRL_START + INTERRUPT_GPIO1)
4601 +#define IRQ_GPIO2 (IRQ_ARMCTRL_START + INTERRUPT_GPIO2)
4602 +#define IRQ_GPIO3 (IRQ_ARMCTRL_START + INTERRUPT_GPIO3)
4603 +#define IRQ_I2C (IRQ_ARMCTRL_START + INTERRUPT_I2C)
4604 +#define IRQ_SPI (IRQ_ARMCTRL_START + INTERRUPT_SPI)
4605 +#define IRQ_I2SPCM (IRQ_ARMCTRL_START + INTERRUPT_I2SPCM)
4606 +#define IRQ_SDIO (IRQ_ARMCTRL_START + INTERRUPT_SDIO)
4607 +#define IRQ_UART (IRQ_ARMCTRL_START + INTERRUPT_UART)
4608 +#define IRQ_SLIMBUS (IRQ_ARMCTRL_START + INTERRUPT_SLIMBUS)
4609 +#define IRQ_VEC (IRQ_ARMCTRL_START + INTERRUPT_VEC)
4610 +#define IRQ_CPG (IRQ_ARMCTRL_START + INTERRUPT_CPG)
4611 +#define IRQ_RNG (IRQ_ARMCTRL_START + INTERRUPT_RNG)
4612 +#define IRQ_ARASANSDIO (IRQ_ARMCTRL_START + INTERRUPT_ARASANSDIO)
4613 +#define IRQ_AVSPMON (IRQ_ARMCTRL_START + INTERRUPT_AVSPMON)
4614 +
4615 +#define IRQ_ARM_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_TIMER)
4616 +#define IRQ_ARM_MAILBOX (IRQ_ARMCTRL_START + INTERRUPT_ARM_MAILBOX)
4617 +#define IRQ_ARM_DOORBELL_0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_0)
4618 +#define IRQ_ARM_DOORBELL_1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_1)
4619 +#define IRQ_VPU0_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU0_HALTED)
4620 +#define IRQ_VPU1_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU1_HALTED)
4621 +#define IRQ_ILLEGAL_TYPE0 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE0)
4622 +#define IRQ_ILLEGAL_TYPE1 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE1)
4623 +#define IRQ_PENDING1 (IRQ_ARMCTRL_START + INTERRUPT_PENDING1)
4624 +#define IRQ_PENDING2 (IRQ_ARMCTRL_START + INTERRUPT_PENDING2)
4625 +
4626 +/*
4627 + * FIQ interrupts definitions are the same as the INT definitions.
4628 + */
4629 +#define FIQ_TIMER0 INT_TIMER0
4630 +#define FIQ_TIMER1 INT_TIMER1
4631 +#define FIQ_TIMER2 INT_TIMER2
4632 +#define FIQ_TIMER3 INT_TIMER3
4633 +#define FIQ_CODEC0 INT_CODEC0
4634 +#define FIQ_CODEC1 INT_CODEC1
4635 +#define FIQ_CODEC2 INT_CODEC2
4636 +#define FIQ_JPEG INT_JPEG
4637 +#define FIQ_ISP INT_ISP
4638 +#define FIQ_USB INT_USB
4639 +#define FIQ_3D INT_3D
4640 +#define FIQ_TRANSPOSER INT_TRANSPOSER
4641 +#define FIQ_MULTICORESYNC0 INT_MULTICORESYNC0
4642 +#define FIQ_MULTICORESYNC1 INT_MULTICORESYNC1
4643 +#define FIQ_MULTICORESYNC2 INT_MULTICORESYNC2
4644 +#define FIQ_MULTICORESYNC3 INT_MULTICORESYNC3
4645 +#define FIQ_DMA0 INT_DMA0
4646 +#define FIQ_DMA1 INT_DMA1
4647 +#define FIQ_DMA2 INT_DMA2
4648 +#define FIQ_DMA3 INT_DMA3
4649 +#define FIQ_DMA4 INT_DMA4
4650 +#define FIQ_DMA5 INT_DMA5
4651 +#define FIQ_DMA6 INT_DMA6
4652 +#define FIQ_DMA7 INT_DMA7
4653 +#define FIQ_DMA8 INT_DMA8
4654 +#define FIQ_DMA9 INT_DMA9
4655 +#define FIQ_DMA10 INT_DMA10
4656 +#define FIQ_DMA11 INT_DMA11
4657 +#define FIQ_DMA12 INT_DMA12
4658 +#define FIQ_AUX INT_AUX
4659 +#define FIQ_ARM INT_ARM
4660 +#define FIQ_VPUDMA INT_VPUDMA
4661 +#define FIQ_HOSTPORT INT_HOSTPORT
4662 +#define FIQ_VIDEOSCALER INT_VIDEOSCALER
4663 +#define FIQ_CCP2TX INT_CCP2TX
4664 +#define FIQ_SDC INT_SDC
4665 +#define FIQ_DSI0 INT_DSI0
4666 +#define FIQ_AVE INT_AVE
4667 +#define FIQ_CAM0 INT_CAM0
4668 +#define FIQ_CAM1 INT_CAM1
4669 +#define FIQ_HDMI0 INT_HDMI0
4670 +#define FIQ_HDMI1 INT_HDMI1
4671 +#define FIQ_PIXELVALVE1 INT_PIXELVALVE1
4672 +#define FIQ_I2CSPISLV INT_I2CSPISLV
4673 +#define FIQ_DSI1 INT_DSI1
4674 +#define FIQ_PWA0 INT_PWA0
4675 +#define FIQ_PWA1 INT_PWA1
4676 +#define FIQ_CPR INT_CPR
4677 +#define FIQ_SMI INT_SMI
4678 +#define FIQ_GPIO0 INT_GPIO0
4679 +#define FIQ_GPIO1 INT_GPIO1
4680 +#define FIQ_GPIO2 INT_GPIO2
4681 +#define FIQ_GPIO3 INT_GPIO3
4682 +#define FIQ_I2C INT_I2C
4683 +#define FIQ_SPI INT_SPI
4684 +#define FIQ_I2SPCM INT_I2SPCM
4685 +#define FIQ_SDIO INT_SDIO
4686 +#define FIQ_UART INT_UART
4687 +#define FIQ_SLIMBUS INT_SLIMBUS
4688 +#define FIQ_VEC INT_VEC
4689 +#define FIQ_CPG INT_CPG
4690 +#define FIQ_RNG INT_RNG
4691 +#define FIQ_ARASANSDIO INT_ARASANSDIO
4692 +#define FIQ_AVSPMON INT_AVSPMON
4693 +
4694 +#define FIQ_ARM_TIMER INT_ARM_TIMER
4695 +#define FIQ_ARM_MAILBOX INT_ARM_MAILBOX
4696 +#define FIQ_ARM_DOORBELL_0 INT_ARM_DOORBELL_0
4697 +#define FIQ_ARM_DOORBELL_1 INT_ARM_DOORBELL_1
4698 +#define FIQ_VPU0_HALTED INT_VPU0_HALTED
4699 +#define FIQ_VPU1_HALTED INT_VPU1_HALTED
4700 +#define FIQ_ILLEGAL_TYPE0 INT_ILLEGAL_TYPE0
4701 +#define FIQ_ILLEGAL_TYPE1 INT_ILLEGAL_TYPE1
4702 +#define FIQ_PENDING1 INT_PENDING1
4703 +#define FIQ_PENDING2 INT_PENDING2
4704 +
4705 +#define HARD_IRQS (64 + 21)
4706 +#define GPIO_IRQ_START (HARD_IRQS)
4707 +#define GPIO_IRQS (32*5)
4708 +#define SPARE_IRQS (64)
4709 +#define NR_IRQS (HARD_IRQS+GPIO_IRQS+SPARE_IRQS)
4710 +
4711 +#endif /* _BCM2708_IRQS_H_ */
4712 diff --git a/arch/arm/mach-bcm2708/include/mach/memory.h b/arch/arm/mach-bcm2708/include/mach/memory.h
4713 new file mode 100644
4714 index 0000000..521540d
4715 --- /dev/null
4716 +++ b/arch/arm/mach-bcm2708/include/mach/memory.h
4717 @@ -0,0 +1,57 @@
4718 +/*
4719 + * arch/arm/mach-bcm2708/include/mach/memory.h
4720 + *
4721 + * Copyright (C) 2010 Broadcom
4722 + *
4723 + * This program is free software; you can redistribute it and/or modify
4724 + * it under the terms of the GNU General Public License as published by
4725 + * the Free Software Foundation; either version 2 of the License, or
4726 + * (at your option) any later version.
4727 + *
4728 + * This program is distributed in the hope that it will be useful,
4729 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4730 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4731 + * GNU General Public License for more details.
4732 + *
4733 + * You should have received a copy of the GNU General Public License
4734 + * along with this program; if not, write to the Free Software
4735 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4736 + */
4737 +#ifndef __ASM_ARCH_MEMORY_H
4738 +#define __ASM_ARCH_MEMORY_H
4739 +
4740 +/* Memory overview:
4741 +
4742 + [ARMcore] <--virtual addr-->
4743 + [ARMmmu] <--physical addr-->
4744 + [GERTmap] <--bus add-->
4745 + [VCperiph]
4746 +
4747 +*/
4748 +
4749 +/*
4750 + * Physical DRAM offset.
4751 + */
4752 +#define PLAT_PHYS_OFFSET UL(0x00000000)
4753 +#define VC_ARMMEM_OFFSET UL(0x00000000) /* offset in VC of ARM memory */
4754 +
4755 +#ifdef CONFIG_BCM2708_NOL2CACHE
4756 + #define _REAL_BUS_OFFSET UL(0xC0000000) /* don't use L1 or L2 caches */
4757 +#else
4758 + #define _REAL_BUS_OFFSET UL(0x40000000) /* use L2 cache */
4759 +#endif
4760 +
4761 +/* We're using the memory at 64M in the VideoCore for Linux - this adjustment
4762 + * will provide the offset into this area as well as setting the bits that
4763 + * stop the L1 and L2 cache from being used
4764 + *
4765 + * WARNING: this only works because the ARM is given memory at a fixed location
4766 + * (ARMMEM_OFFSET)
4767 + */
4768 +#define BUS_OFFSET (VC_ARMMEM_OFFSET + _REAL_BUS_OFFSET)
4769 +#define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET))
4770 +#define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET))
4771 +#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - PLAT_PHYS_OFFSET))
4772 +#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - PLAT_PHYS_OFFSET))
4773 +
4774 +#endif
4775 diff --git a/arch/arm/mach-bcm2708/include/mach/platform.h b/arch/arm/mach-bcm2708/include/mach/platform.h
4776 new file mode 100644
4777 index 0000000..110ce07
4778 --- /dev/null
4779 +++ b/arch/arm/mach-bcm2708/include/mach/platform.h
4780 @@ -0,0 +1,220 @@
4781 +/*
4782 + * arch/arm/mach-bcm2708/include/mach/platform.h
4783 + *
4784 + * Copyright (C) 2010 Broadcom
4785 + *
4786 + * This program is free software; you can redistribute it and/or modify
4787 + * it under the terms of the GNU General Public License as published by
4788 + * the Free Software Foundation; either version 2 of the License, or
4789 + * (at your option) any later version.
4790 + *
4791 + * This program is distributed in the hope that it will be useful,
4792 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4793 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4794 + * GNU General Public License for more details.
4795 + *
4796 + * You should have received a copy of the GNU General Public License
4797 + * along with this program; if not, write to the Free Software
4798 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4799 + */
4800 +
4801 +#ifndef _BCM2708_PLATFORM_H
4802 +#define _BCM2708_PLATFORM_H
4803 +
4804 +
4805 +/* macros to get at IO space when running virtually */
4806 +#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
4807 +
4808 +#define __io_address(n) IOMEM(IO_ADDRESS(n))
4809 +
4810 +
4811 +/*
4812 + * SDRAM
4813 + */
4814 +#define BCM2708_SDRAM_BASE 0x00000000
4815 +
4816 +/*
4817 + * Logic expansion modules
4818 + *
4819 + */
4820 +
4821 +
4822 +/* ------------------------------------------------------------------------
4823 + * BCM2708 ARMCTRL Registers
4824 + * ------------------------------------------------------------------------
4825 + */
4826 +
4827 +#define HW_REGISTER_RW(addr) (addr)
4828 +#define HW_REGISTER_RO(addr) (addr)
4829 +
4830 +#include "arm_control.h"
4831 +#undef ARM_BASE
4832 +
4833 +/*
4834 + * Definitions and addresses for the ARM CONTROL logic
4835 + * This file is manually generated.
4836 + */
4837 +
4838 +#define BCM2708_PERI_BASE 0x20000000
4839 +#define ST_BASE (BCM2708_PERI_BASE + 0x3000) /* System Timer */
4840 +#define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */
4841 +#define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */
4842 +#define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */
4843 +#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */
4844 +#define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */
4845 +#define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */
4846 +#define UART1_BASE (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */
4847 +#define EMMC_BASE (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */
4848 +#define SMI_BASE (BCM2708_PERI_BASE + 0x600000) /* SMI */
4849 +#define USB_BASE (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */
4850 +#define MCORE_BASE (BCM2708_PERI_BASE + 0x0000) /* Fake frame buffer device (actually the multicore sync block*/
4851 +
4852 +#define ARMCTRL_BASE (ARM_BASE + 0x000)
4853 +#define ARMCTRL_IC_BASE (ARM_BASE + 0x200) /* ARM interrupt controller */
4854 +#define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */
4855 +#define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */
4856 +
4857 +
4858 +/*
4859 + * Interrupt assignments
4860 + */
4861 +
4862 +#define ARM_IRQ1_BASE 0
4863 +#define INTERRUPT_TIMER0 (ARM_IRQ1_BASE + 0)
4864 +#define INTERRUPT_TIMER1 (ARM_IRQ1_BASE + 1)
4865 +#define INTERRUPT_TIMER2 (ARM_IRQ1_BASE + 2)
4866 +#define INTERRUPT_TIMER3 (ARM_IRQ1_BASE + 3)
4867 +#define INTERRUPT_CODEC0 (ARM_IRQ1_BASE + 4)
4868 +#define INTERRUPT_CODEC1 (ARM_IRQ1_BASE + 5)
4869 +#define INTERRUPT_CODEC2 (ARM_IRQ1_BASE + 6)
4870 +#define INTERRUPT_VC_JPEG (ARM_IRQ1_BASE + 7)
4871 +#define INTERRUPT_ISP (ARM_IRQ1_BASE + 8)
4872 +#define INTERRUPT_VC_USB (ARM_IRQ1_BASE + 9)
4873 +#define INTERRUPT_VC_3D (ARM_IRQ1_BASE + 10)
4874 +#define INTERRUPT_TRANSPOSER (ARM_IRQ1_BASE + 11)
4875 +#define INTERRUPT_MULTICORESYNC0 (ARM_IRQ1_BASE + 12)
4876 +#define INTERRUPT_MULTICORESYNC1 (ARM_IRQ1_BASE + 13)
4877 +#define INTERRUPT_MULTICORESYNC2 (ARM_IRQ1_BASE + 14)
4878 +#define INTERRUPT_MULTICORESYNC3 (ARM_IRQ1_BASE + 15)
4879 +#define INTERRUPT_DMA0 (ARM_IRQ1_BASE + 16)
4880 +#define INTERRUPT_DMA1 (ARM_IRQ1_BASE + 17)
4881 +#define INTERRUPT_VC_DMA2 (ARM_IRQ1_BASE + 18)
4882 +#define INTERRUPT_VC_DMA3 (ARM_IRQ1_BASE + 19)
4883 +#define INTERRUPT_DMA4 (ARM_IRQ1_BASE + 20)
4884 +#define INTERRUPT_DMA5 (ARM_IRQ1_BASE + 21)
4885 +#define INTERRUPT_DMA6 (ARM_IRQ1_BASE + 22)
4886 +#define INTERRUPT_DMA7 (ARM_IRQ1_BASE + 23)
4887 +#define INTERRUPT_DMA8 (ARM_IRQ1_BASE + 24)
4888 +#define INTERRUPT_DMA9 (ARM_IRQ1_BASE + 25)
4889 +#define INTERRUPT_DMA10 (ARM_IRQ1_BASE + 26)
4890 +#define INTERRUPT_DMA11 (ARM_IRQ1_BASE + 27)
4891 +#define INTERRUPT_DMA12 (ARM_IRQ1_BASE + 28)
4892 +#define INTERRUPT_AUX (ARM_IRQ1_BASE + 29)
4893 +#define INTERRUPT_ARM (ARM_IRQ1_BASE + 30)
4894 +#define INTERRUPT_VPUDMA (ARM_IRQ1_BASE + 31)
4895 +
4896 +#define ARM_IRQ2_BASE 32
4897 +#define INTERRUPT_HOSTPORT (ARM_IRQ2_BASE + 0)
4898 +#define INTERRUPT_VIDEOSCALER (ARM_IRQ2_BASE + 1)
4899 +#define INTERRUPT_CCP2TX (ARM_IRQ2_BASE + 2)
4900 +#define INTERRUPT_SDC (ARM_IRQ2_BASE + 3)
4901 +#define INTERRUPT_DSI0 (ARM_IRQ2_BASE + 4)
4902 +#define INTERRUPT_AVE (ARM_IRQ2_BASE + 5)
4903 +#define INTERRUPT_CAM0 (ARM_IRQ2_BASE + 6)
4904 +#define INTERRUPT_CAM1 (ARM_IRQ2_BASE + 7)
4905 +#define INTERRUPT_HDMI0 (ARM_IRQ2_BASE + 8)
4906 +#define INTERRUPT_HDMI1 (ARM_IRQ2_BASE + 9)
4907 +#define INTERRUPT_PIXELVALVE1 (ARM_IRQ2_BASE + 10)
4908 +#define INTERRUPT_I2CSPISLV (ARM_IRQ2_BASE + 11)
4909 +#define INTERRUPT_DSI1 (ARM_IRQ2_BASE + 12)
4910 +#define INTERRUPT_PWA0 (ARM_IRQ2_BASE + 13)
4911 +#define INTERRUPT_PWA1 (ARM_IRQ2_BASE + 14)
4912 +#define INTERRUPT_CPR (ARM_IRQ2_BASE + 15)
4913 +#define INTERRUPT_SMI (ARM_IRQ2_BASE + 16)
4914 +#define INTERRUPT_GPIO0 (ARM_IRQ2_BASE + 17)
4915 +#define INTERRUPT_GPIO1 (ARM_IRQ2_BASE + 18)
4916 +#define INTERRUPT_GPIO2 (ARM_IRQ2_BASE + 19)
4917 +#define INTERRUPT_GPIO3 (ARM_IRQ2_BASE + 20)
4918 +#define INTERRUPT_VC_I2C (ARM_IRQ2_BASE + 21)
4919 +#define INTERRUPT_VC_SPI (ARM_IRQ2_BASE + 22)
4920 +#define INTERRUPT_VC_I2SPCM (ARM_IRQ2_BASE + 23)
4921 +#define INTERRUPT_VC_SDIO (ARM_IRQ2_BASE + 24)
4922 +#define INTERRUPT_VC_UART (ARM_IRQ2_BASE + 25)
4923 +#define INTERRUPT_SLIMBUS (ARM_IRQ2_BASE + 26)
4924 +#define INTERRUPT_VEC (ARM_IRQ2_BASE + 27)
4925 +#define INTERRUPT_CPG (ARM_IRQ2_BASE + 28)
4926 +#define INTERRUPT_RNG (ARM_IRQ2_BASE + 29)
4927 +#define INTERRUPT_VC_ARASANSDIO (ARM_IRQ2_BASE + 30)
4928 +#define INTERRUPT_AVSPMON (ARM_IRQ2_BASE + 31)
4929 +
4930 +#define ARM_IRQ0_BASE 64
4931 +#define INTERRUPT_ARM_TIMER (ARM_IRQ0_BASE + 0)
4932 +#define INTERRUPT_ARM_MAILBOX (ARM_IRQ0_BASE + 1)
4933 +#define INTERRUPT_ARM_DOORBELL_0 (ARM_IRQ0_BASE + 2)
4934 +#define INTERRUPT_ARM_DOORBELL_1 (ARM_IRQ0_BASE + 3)
4935 +#define INTERRUPT_VPU0_HALTED (ARM_IRQ0_BASE + 4)
4936 +#define INTERRUPT_VPU1_HALTED (ARM_IRQ0_BASE + 5)
4937 +#define INTERRUPT_ILLEGAL_TYPE0 (ARM_IRQ0_BASE + 6)
4938 +#define INTERRUPT_ILLEGAL_TYPE1 (ARM_IRQ0_BASE + 7)
4939 +#define INTERRUPT_PENDING1 (ARM_IRQ0_BASE + 8)
4940 +#define INTERRUPT_PENDING2 (ARM_IRQ0_BASE + 9)
4941 +#define INTERRUPT_JPEG (ARM_IRQ0_BASE + 10)
4942 +#define INTERRUPT_USB (ARM_IRQ0_BASE + 11)
4943 +#define INTERRUPT_3D (ARM_IRQ0_BASE + 12)
4944 +#define INTERRUPT_DMA2 (ARM_IRQ0_BASE + 13)
4945 +#define INTERRUPT_DMA3 (ARM_IRQ0_BASE + 14)
4946 +#define INTERRUPT_I2C (ARM_IRQ0_BASE + 15)
4947 +#define INTERRUPT_SPI (ARM_IRQ0_BASE + 16)
4948 +#define INTERRUPT_I2SPCM (ARM_IRQ0_BASE + 17)
4949 +#define INTERRUPT_SDIO (ARM_IRQ0_BASE + 18)
4950 +#define INTERRUPT_UART (ARM_IRQ0_BASE + 19)
4951 +#define INTERRUPT_ARASANSDIO (ARM_IRQ0_BASE + 20)
4952 +
4953 +#define MAXIRQNUM (32 + 32 + 20)
4954 +#define MAXFIQNUM (32 + 32 + 20)
4955 +
4956 +#define MAX_TIMER 2
4957 +#define MAX_PERIOD 699050
4958 +#define TICKS_PER_uSEC 1
4959 +
4960 +/*
4961 + * These are useconds NOT ticks.
4962 + *
4963 + */
4964 +#define mSEC_1 1000
4965 +#define mSEC_5 (mSEC_1 * 5)
4966 +#define mSEC_10 (mSEC_1 * 10)
4967 +#define mSEC_25 (mSEC_1 * 25)
4968 +#define SEC_1 (mSEC_1 * 1000)
4969 +
4970 +/*
4971 + * Watchdog
4972 + */
4973 +#define PM_RSTC (PM_BASE+0x1c)
4974 +#define PM_RSTS (PM_BASE+0x20)
4975 +#define PM_WDOG (PM_BASE+0x24)
4976 +
4977 +#define PM_WDOG_RESET 0000000000
4978 +#define PM_PASSWORD 0x5a000000
4979 +#define PM_WDOG_TIME_SET 0x000fffff
4980 +#define PM_RSTC_WRCFG_CLR 0xffffffcf
4981 +#define PM_RSTC_WRCFG_SET 0x00000030
4982 +#define PM_RSTC_WRCFG_FULL_RESET 0x00000020
4983 +#define PM_RSTC_RESET 0x00000102
4984 +
4985 +#define PM_RSTS_HADPOR_SET 0x00001000
4986 +#define PM_RSTS_HADSRH_SET 0x00000400
4987 +#define PM_RSTS_HADSRF_SET 0x00000200
4988 +#define PM_RSTS_HADSRQ_SET 0x00000100
4989 +#define PM_RSTS_HADWRH_SET 0x00000040
4990 +#define PM_RSTS_HADWRF_SET 0x00000020
4991 +#define PM_RSTS_HADWRQ_SET 0x00000010
4992 +#define PM_RSTS_HADDRH_SET 0x00000004
4993 +#define PM_RSTS_HADDRF_SET 0x00000002
4994 +#define PM_RSTS_HADDRQ_SET 0x00000001
4995 +
4996 +#define UART0_CLOCK 3000000
4997 +
4998 +#endif
4999 +
5000 +/* END */
5001 diff --git a/arch/arm/mach-bcm2708/include/mach/power.h b/arch/arm/mach-bcm2708/include/mach/power.h
5002 new file mode 100644
5003 index 0000000..52b3b02
5004 --- /dev/null
5005 +++ b/arch/arm/mach-bcm2708/include/mach/power.h
5006 @@ -0,0 +1,26 @@
5007 +/*
5008 + * linux/arch/arm/mach-bcm2708/power.h
5009 + *
5010 + * Copyright (C) 2010 Broadcom
5011 + *
5012 + * This program is free software; you can redistribute it and/or modify
5013 + * it under the terms of the GNU General Public License version 2 as
5014 + * published by the Free Software Foundation.
5015 + *
5016 + * This device provides a shared mechanism for controlling the power to
5017 + * VideoCore subsystems.
5018 + */
5019 +
5020 +#ifndef _MACH_BCM2708_POWER_H
5021 +#define _MACH_BCM2708_POWER_H
5022 +
5023 +#include <linux/types.h>
5024 +#include <mach/arm_power.h>
5025 +
5026 +typedef unsigned int BCM_POWER_HANDLE_T;
5027 +
5028 +extern int bcm_power_open(BCM_POWER_HANDLE_T *handle);
5029 +extern int bcm_power_request(BCM_POWER_HANDLE_T handle, uint32_t request);
5030 +extern int bcm_power_close(BCM_POWER_HANDLE_T handle);
5031 +
5032 +#endif
5033 diff --git a/arch/arm/mach-bcm2708/include/mach/system.h b/arch/arm/mach-bcm2708/include/mach/system.h
5034 new file mode 100644
5035 index 0000000..2d0b821
5036 --- /dev/null
5037 +++ b/arch/arm/mach-bcm2708/include/mach/system.h
5038 @@ -0,0 +1,38 @@
5039 +/*
5040 + * arch/arm/mach-bcm2708/include/mach/system.h
5041 + *
5042 + * Copyright (C) 2010 Broadcom
5043 + * Copyright (C) 2003 ARM Limited
5044 + * Copyright (C) 2000 Deep Blue Solutions Ltd
5045 + *
5046 + * This program is free software; you can redistribute it and/or modify
5047 + * it under the terms of the GNU General Public License as published by
5048 + * the Free Software Foundation; either version 2 of the License, or
5049 + * (at your option) any later version.
5050 + *
5051 + * This program is distributed in the hope that it will be useful,
5052 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5053 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5054 + * GNU General Public License for more details.
5055 + *
5056 + * You should have received a copy of the GNU General Public License
5057 + * along with this program; if not, write to the Free Software
5058 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5059 + */
5060 +#ifndef __ASM_ARCH_SYSTEM_H
5061 +#define __ASM_ARCH_SYSTEM_H
5062 +
5063 +#include <linux/io.h>
5064 +#include <mach/hardware.h>
5065 +#include <mach/platform.h>
5066 +
5067 +static inline void arch_idle(void)
5068 +{
5069 + /*
5070 + * This should do all the clock switching
5071 + * and wait for interrupt tricks
5072 + */
5073 + cpu_do_idle();
5074 +}
5075 +
5076 +#endif
5077 diff --git a/arch/arm/mach-bcm2708/include/mach/timex.h b/arch/arm/mach-bcm2708/include/mach/timex.h
5078 new file mode 100644
5079 index 0000000..64a660c
5080 --- /dev/null
5081 +++ b/arch/arm/mach-bcm2708/include/mach/timex.h
5082 @@ -0,0 +1,23 @@
5083 +/*
5084 + * arch/arm/mach-bcm2708/include/mach/timex.h
5085 + *
5086 + * BCM2708 sysem clock frequency
5087 + *
5088 + * Copyright (C) 2010 Broadcom
5089 + *
5090 + * This program is free software; you can redistribute it and/or modify
5091 + * it under the terms of the GNU General Public License as published by
5092 + * the Free Software Foundation; either version 2 of the License, or
5093 + * (at your option) any later version.
5094 + *
5095 + * This program is distributed in the hope that it will be useful,
5096 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5097 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5098 + * GNU General Public License for more details.
5099 + *
5100 + * You should have received a copy of the GNU General Public License
5101 + * along with this program; if not, write to the Free Software
5102 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5103 + */
5104 +
5105 +#define CLOCK_TICK_RATE (1000000)
5106 diff --git a/arch/arm/mach-bcm2708/include/mach/uncompress.h b/arch/arm/mach-bcm2708/include/mach/uncompress.h
5107 new file mode 100644
5108 index 0000000..d634813
5109 --- /dev/null
5110 +++ b/arch/arm/mach-bcm2708/include/mach/uncompress.h
5111 @@ -0,0 +1,84 @@
5112 +/*
5113 + * arch/arm/mach-bcn2708/include/mach/uncompress.h
5114 + *
5115 + * Copyright (C) 2010 Broadcom
5116 + * Copyright (C) 2003 ARM Limited
5117 + *
5118 + * This program is free software; you can redistribute it and/or modify
5119 + * it under the terms of the GNU General Public License as published by
5120 + * the Free Software Foundation; either version 2 of the License, or
5121 + * (at your option) any later version.
5122 + *
5123 + * This program is distributed in the hope that it will be useful,
5124 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5125 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5126 + * GNU General Public License for more details.
5127 + *
5128 + * You should have received a copy of the GNU General Public License
5129 + * along with this program; if not, write to the Free Software
5130 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5131 + */
5132 +
5133 +#include <linux/io.h>
5134 +#include <linux/amba/serial.h>
5135 +#include <mach/hardware.h>
5136 +
5137 +#define UART_BAUD 115200
5138 +
5139 +#define BCM2708_UART_DR __io(UART0_BASE + UART01x_DR)
5140 +#define BCM2708_UART_FR __io(UART0_BASE + UART01x_FR)
5141 +#define BCM2708_UART_IBRD __io(UART0_BASE + UART011_IBRD)
5142 +#define BCM2708_UART_FBRD __io(UART0_BASE + UART011_FBRD)
5143 +#define BCM2708_UART_LCRH __io(UART0_BASE + UART011_LCRH)
5144 +#define BCM2708_UART_CR __io(UART0_BASE + UART011_CR)
5145 +
5146 +/*
5147 + * This does not append a newline
5148 + */
5149 +static inline void putc(int c)
5150 +{
5151 + while (__raw_readl(BCM2708_UART_FR) & UART01x_FR_TXFF)
5152 + barrier();
5153 +
5154 + __raw_writel(c, BCM2708_UART_DR);
5155 +}
5156 +
5157 +static inline void flush(void)
5158 +{
5159 + int fr;
5160 +
5161 + do {
5162 + fr = __raw_readl(BCM2708_UART_FR);
5163 + barrier();
5164 + } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE);
5165 +}
5166 +
5167 +static inline void arch_decomp_setup(void)
5168 +{
5169 + int temp, div, rem, frac;
5170 +
5171 + temp = 16 * UART_BAUD;
5172 + div = UART0_CLOCK / temp;
5173 + rem = UART0_CLOCK % temp;
5174 + temp = (8 * rem) / UART_BAUD;
5175 + frac = (temp >> 1) + (temp & 1);
5176 +
5177 + /* Make sure the UART is disabled before we start */
5178 + __raw_writel(0, BCM2708_UART_CR);
5179 +
5180 + /* Set the baud rate */
5181 + __raw_writel(div, BCM2708_UART_IBRD);
5182 + __raw_writel(frac, BCM2708_UART_FBRD);
5183 +
5184 + /* Set the UART to 8n1, FIFO enabled */
5185 + __raw_writel(UART01x_LCRH_WLEN_8 | UART01x_LCRH_FEN, BCM2708_UART_LCRH);
5186 +
5187 + /* Enable the UART */
5188 + __raw_writel(UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_RXE,
5189 + BCM2708_UART_CR);
5190 +}
5191 +
5192 +/*
5193 + * nothing to do
5194 + */
5195 +#define arch_decomp_wdog()
5196 diff --git a/arch/arm/mach-bcm2708/include/mach/vc_mem.h b/arch/arm/mach-bcm2708/include/mach/vc_mem.h
5197 new file mode 100644
5198 index 0000000..4a4a338
5199 --- /dev/null
5200 +++ b/arch/arm/mach-bcm2708/include/mach/vc_mem.h
5201 @@ -0,0 +1,35 @@
5202 +/*****************************************************************************
5203 +* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved.
5204 +*
5205 +* Unless you and Broadcom execute a separate written software license
5206 +* agreement governing use of this software, this software is licensed to you
5207 +* under the terms of the GNU General Public License version 2, available at
5208 +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
5209 +*
5210 +* Notwithstanding the above, under no circumstances may you combine this
5211 +* software in any way with any other Broadcom software provided under a
5212 +* license other than the GPL, without Broadcom's express prior written
5213 +* consent.
5214 +*****************************************************************************/
5215 +
5216 +#if !defined( VC_MEM_H )
5217 +#define VC_MEM_H
5218 +
5219 +#include <linux/ioctl.h>
5220 +
5221 +#define VC_MEM_IOC_MAGIC 'v'
5222 +
5223 +#define VC_MEM_IOC_MEM_PHYS_ADDR _IOR( VC_MEM_IOC_MAGIC, 0, unsigned long )
5224 +#define VC_MEM_IOC_MEM_SIZE _IOR( VC_MEM_IOC_MAGIC, 1, unsigned int )
5225 +#define VC_MEM_IOC_MEM_BASE _IOR( VC_MEM_IOC_MAGIC, 2, unsigned int )
5226 +#define VC_MEM_IOC_MEM_LOAD _IOR( VC_MEM_IOC_MAGIC, 3, unsigned int )
5227 +
5228 +#if defined( __KERNEL__ )
5229 +#define VC_MEM_TO_ARM_ADDR_MASK 0x3FFFFFFF
5230 +
5231 +extern unsigned long mm_vc_mem_phys_addr;
5232 +extern unsigned int mm_vc_mem_size;
5233 +extern int vc_mem_get_current_size( void );
5234 +#endif
5235 +
5236 +#endif /* VC_MEM_H */
5237 diff --git a/arch/arm/mach-bcm2708/include/mach/vcio.h b/arch/arm/mach-bcm2708/include/mach/vcio.h
5238 new file mode 100644
5239 index 0000000..9935e02
5240 --- /dev/null
5241 +++ b/arch/arm/mach-bcm2708/include/mach/vcio.h
5242 @@ -0,0 +1,141 @@
5243 +/*
5244 + * arch/arm/mach-bcm2708/include/mach/vcio.h
5245 + *
5246 + * Copyright (C) 2010 Broadcom
5247 + *
5248 + * This program is free software; you can redistribute it and/or modify
5249 + * it under the terms of the GNU General Public License as published by
5250 + * the Free Software Foundation; either version 2 of the License, or
5251 + * (at your option) any later version.
5252 + *
5253 + * This program is distributed in the hope that it will be useful,
5254 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5255 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5256 + * GNU General Public License for more details.
5257 + *
5258 + * You should have received a copy of the GNU General Public License
5259 + * along with this program; if not, write to the Free Software
5260 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5261 + */
5262 +#ifndef _MACH_BCM2708_VCIO_H
5263 +#define _MACH_BCM2708_VCIO_H
5264 +
5265 +/* Routines to handle I/O via the VideoCore "ARM control" registers
5266 + * (semaphores, doorbells, mailboxes)
5267 + */
5268 +
5269 +#define BCM_VCIO_DRIVER_NAME "bcm2708_vcio"
5270 +
5271 +/* Constants shared with the ARM identifying separate mailbox channels */
5272 +#define MBOX_CHAN_POWER 0 /* for use by the power management interface */
5273 +#define MBOX_CHAN_FB 1 /* for use by the frame buffer */
5274 +#define MBOX_CHAN_VCHIQ 3 /* for use by the VCHIQ interface */
5275 +#define MBOX_CHAN_PROPERTY 8 /* for use by the property channel */
5276 +#define MBOX_CHAN_COUNT 9
5277 +
5278 +/* Mailbox property tags */
5279 +enum {
5280 + VCMSG_PROPERTY_END = 0x00000000,
5281 + VCMSG_GET_FIRMWARE_REVISION = 0x00000001,
5282 + VCMSG_GET_BOARD_MODEL = 0x00010001,
5283 + VCMSG_GET_BOARD_REVISION = 0x00020002,
5284 + VCMSG_GET_BOARD_MAC_ADDRESS = 0x00020003,
5285 + VCMSG_GET_BOARD_SERIAL = 0x00020004,
5286 + VCMSG_GET_ARM_MEMORY = 0x00020005,
5287 + VCMSG_GET_VC_MEMORY = 0x00020006,
5288 + VCMSG_GET_CLOCKS = 0x00020007,
5289 + VCMSG_GET_COMMAND_LINE = 0x00050001,
5290 + VCMSG_GET_DMA_CHANNELS = 0x00060001,
5291 + VCMSG_GET_POWER_STATE = 0x00020001,
5292 + VCMSG_GET_TIMING = 0x00020002,
5293 + VCMSG_SET_POWER_STATE = 0x00028001,
5294 + VCMSG_GET_CLOCK_STATE = 0x00030001,
5295 + VCMSG_SET_CLOCK_STATE = 0x00038001,
5296 + VCMSG_GET_CLOCK_RATE = 0x00030002,
5297 + VCMSG_SET_CLOCK_RATE = 0x00038002,
5298 + VCMSG_GET_VOLTAGE = 0x00030003,
5299 + VCMSG_SET_VOLTAGE = 0x00038003,
5300 + VCMSG_GET_MAX_CLOCK = 0x00030004,
5301 + VCMSG_GET_MAX_VOLTAGE = 0x00030005,
5302 + VCMSG_GET_TEMPERATURE = 0x00030006,
5303 + VCMSG_GET_MIN_CLOCK = 0x00030007,
5304 + VCMSG_GET_MIN_VOLTAGE = 0x00030008,
5305 + VCMSG_GET_TURBO = 0x00030009,
5306 + VCMSG_SET_TURBO = 0x00038009,
5307 + VCMSG_SET_ALLOCATE_BUFFER = 0x00040001,
5308 + VCMSG_SET_RELEASE_BUFFER = 0x00048001,
5309 + VCMSG_SET_BLANK_SCREEN = 0x00040002,
5310 + VCMSG_TST_BLANK_SCREEN = 0x00044002,
5311 + VCMSG_GET_PHYSICAL_WIDTH_HEIGHT = 0x00040003,
5312 + VCMSG_TST_PHYSICAL_WIDTH_HEIGHT = 0x00044003,
5313 + VCMSG_SET_PHYSICAL_WIDTH_HEIGHT = 0x00048003,
5314 + VCMSG_GET_VIRTUAL_WIDTH_HEIGHT = 0x00040004,
5315 + VCMSG_TST_VIRTUAL_WIDTH_HEIGHT = 0x00044004,
5316 + VCMSG_SET_VIRTUAL_WIDTH_HEIGHT = 0x00048004,
5317 + VCMSG_GET_DEPTH = 0x00040005,
5318 + VCMSG_TST_DEPTH = 0x00044005,
5319 + VCMSG_SET_DEPTH = 0x00048005,
5320 + VCMSG_GET_PIXEL_ORDER = 0x00040006,
5321 + VCMSG_TST_PIXEL_ORDER = 0x00044006,
5322 + VCMSG_SET_PIXEL_ORDER = 0x00048006,
5323 + VCMSG_GET_ALPHA_MODE = 0x00040007,
5324 + VCMSG_TST_ALPHA_MODE = 0x00044007,
5325 + VCMSG_SET_ALPHA_MODE = 0x00048007,
5326 + VCMSG_GET_PITCH = 0x00040008,
5327 + VCMSG_TST_PITCH = 0x00044008,
5328 + VCMSG_SET_PITCH = 0x00048008,
5329 + VCMSG_GET_VIRTUAL_OFFSET = 0x00040009,
5330 + VCMSG_TST_VIRTUAL_OFFSET = 0x00044009,
5331 + VCMSG_SET_VIRTUAL_OFFSET = 0x00048009,
5332 + VCMSG_GET_OVERSCAN = 0x0004000a,
5333 + VCMSG_TST_OVERSCAN = 0x0004400a,
5334 + VCMSG_SET_OVERSCAN = 0x0004800a,
5335 + VCMSG_GET_PALETTE = 0x0004000b,
5336 + VCMSG_TST_PALETTE = 0x0004400b,
5337 + VCMSG_SET_PALETTE = 0x0004800b,
5338 + VCMSG_GET_LAYER = 0x0004000c,
5339 + VCMSG_TST_LAYER = 0x0004400c,
5340 + VCMSG_SET_LAYER = 0x0004800c,
5341 + VCMSG_GET_TRANSFORM = 0x0004000d,
5342 + VCMSG_TST_TRANSFORM = 0x0004400d,
5343 + VCMSG_SET_TRANSFORM = 0x0004800d,
5344 +};
5345 +
5346 +extern int /*rc*/ bcm_mailbox_read(unsigned chan, uint32_t *data28);
5347 +extern int /*rc*/ bcm_mailbox_write(unsigned chan, uint32_t data28);
5348 +extern int /*rc*/ bcm_mailbox_property(void *data, int size);
5349 +
5350 +#include <linux/ioctl.h>
5351 +
5352 +/*
5353 + * The major device number. We can't rely on dynamic
5354 + * registration any more, because ioctls need to know
5355 + * it.
5356 + */
5357 +#define MAJOR_NUM 100
5358 +
5359 +/*
5360 + * Set the message of the device driver
5361 + */
5362 +#define IOCTL_MBOX_PROPERTY _IOWR(MAJOR_NUM, 0, char *)
5363 +/*
5364 + * _IOWR means that we're creating an ioctl command
5365 + * number for passing information from a user process
5366 + * to the kernel module and from the kernel module to user process
5367 + *
5368 + * The first arguments, MAJOR_NUM, is the major device
5369 + * number we're using.
5370 + *
5371 + * The second argument is the number of the command
5372 + * (there could be several with different meanings).
5373 + *
5374 + * The third argument is the type we want to get from
5375 + * the process to the kernel.
5376 + */
5377 +
5378 +/*
5379 + * The name of the device file
5380 + */
5381 +#define DEVICE_FILE_NAME "char_dev"
5382 +
5383 +#endif
5384 diff --git a/arch/arm/mach-bcm2708/include/mach/vmalloc.h b/arch/arm/mach-bcm2708/include/mach/vmalloc.h
5385 new file mode 100644
5386 index 0000000..502c617
5387 --- /dev/null
5388 +++ b/arch/arm/mach-bcm2708/include/mach/vmalloc.h
5389 @@ -0,0 +1,20 @@
5390 +/*
5391 + * arch/arm/mach-bcm2708/include/mach/vmalloc.h
5392 + *
5393 + * Copyright (C) 2010 Broadcom
5394 + *
5395 + * This program is free software; you can redistribute it and/or modify
5396 + * it under the terms of the GNU General Public License as published by
5397 + * the Free Software Foundation; either version 2 of the License, or
5398 + * (at your option) any later version.
5399 + *
5400 + * This program is distributed in the hope that it will be useful,
5401 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5402 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5403 + * GNU General Public License for more details.
5404 + *
5405 + * You should have received a copy of the GNU General Public License
5406 + * along with this program; if not, write to the Free Software
5407 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5408 + */
5409 +#define VMALLOC_END (0xe8000000)
5410 diff --git a/arch/arm/mach-bcm2708/power.c b/arch/arm/mach-bcm2708/power.c
5411 new file mode 100644
5412 index 0000000..256bf1a
5413 --- /dev/null
5414 +++ b/arch/arm/mach-bcm2708/power.c
5415 @@ -0,0 +1,194 @@
5416 +/*
5417 + * linux/arch/arm/mach-bcm2708/power.c
5418 + *
5419 + * Copyright (C) 2010 Broadcom
5420 + *
5421 + * This program is free software; you can redistribute it and/or modify
5422 + * it under the terms of the GNU General Public License version 2 as
5423 + * published by the Free Software Foundation.
5424 + *
5425 + * This device provides a shared mechanism for controlling the power to
5426 + * VideoCore subsystems.
5427 + */
5428 +
5429 +#include <linux/module.h>
5430 +#include <linux/semaphore.h>
5431 +#include <linux/bug.h>
5432 +#include <mach/power.h>
5433 +#include <mach/vcio.h>
5434 +#include <mach/arm_power.h>
5435 +
5436 +#define DRIVER_NAME "bcm2708_power"
5437 +
5438 +#define BCM_POWER_MAXCLIENTS 4
5439 +#define BCM_POWER_NOCLIENT (1<<31)
5440 +
5441 +/* Some drivers expect there devices to be permanently powered */
5442 +#define BCM_POWER_ALWAYS_ON (BCM_POWER_USB)
5443 +
5444 +#if 1
5445 +#define DPRINTK printk
5446 +#else
5447 +#define DPRINTK if (0) printk
5448 +#endif
5449 +
5450 +struct state_struct {
5451 + uint32_t global_request;
5452 + uint32_t client_request[BCM_POWER_MAXCLIENTS];
5453 + struct semaphore client_mutex;
5454 + struct semaphore mutex;
5455 +} g_state;
5456 +
5457 +int bcm_power_open(BCM_POWER_HANDLE_T *handle)
5458 +{
5459 + BCM_POWER_HANDLE_T i;
5460 + int ret = -EBUSY;
5461 +
5462 + down(&g_state.client_mutex);
5463 +
5464 + for (i = 0; i < BCM_POWER_MAXCLIENTS; i++) {
5465 + if (g_state.client_request[i] == BCM_POWER_NOCLIENT) {
5466 + g_state.client_request[i] = BCM_POWER_NONE;
5467 + *handle = i;
5468 + ret = 0;
5469 + break;
5470 + }
5471 + }
5472 +
5473 + up(&g_state.client_mutex);
5474 +
5475 + DPRINTK("bcm_power_open() -> %d\n", *handle);
5476 +
5477 + return ret;
5478 +}
5479 +EXPORT_SYMBOL_GPL(bcm_power_open);
5480 +
5481 +int bcm_power_request(BCM_POWER_HANDLE_T handle, uint32_t request)
5482 +{
5483 + int rc = 0;
5484 +
5485 + DPRINTK("bcm_power_request(%d, %x)\n", handle, request);
5486 +
5487 + if ((handle < BCM_POWER_MAXCLIENTS) &&
5488 + (g_state.client_request[handle] != BCM_POWER_NOCLIENT)) {
5489 + if (down_interruptible(&g_state.mutex) != 0) {
5490 + DPRINTK("bcm_power_request -> interrupted\n");
5491 + return -EINTR;
5492 + }
5493 +
5494 + if (request != g_state.client_request[handle]) {
5495 + uint32_t others_request = 0;
5496 + uint32_t global_request;
5497 + BCM_POWER_HANDLE_T i;
5498 +
5499 + for (i = 0; i < BCM_POWER_MAXCLIENTS; i++) {
5500 + if (i != handle)
5501 + others_request |=
5502 + g_state.client_request[i];
5503 + }
5504 + others_request &= ~BCM_POWER_NOCLIENT;
5505 +
5506 + global_request = request | others_request;
5507 + if (global_request != g_state.global_request) {
5508 + uint32_t actual;
5509 +
5510 + /* Send a request to VideoCore */
5511 + bcm_mailbox_write(MBOX_CHAN_POWER,
5512 + global_request << 4);
5513 +
5514 + /* Wait for a response during power-up */
5515 + if (global_request & ~g_state.global_request) {
5516 + rc = bcm_mailbox_read(MBOX_CHAN_POWER,
5517 + &actual);
5518 + DPRINTK
5519 + ("bcm_mailbox_read -> %08x, %d\n",
5520 + actual, rc);
5521 + actual >>= 4;
5522 + } else {
5523 + rc = 0;
5524 + actual = global_request;
5525 + }
5526 +
5527 + if (rc == 0) {
5528 + if (actual != global_request) {
5529 + printk(KERN_ERR
5530 + "%s: prev global %x, new global %x, actual %x, request %x, others_request %x\n",
5531 + __func__,
5532 + g_state.global_request,
5533 + global_request, actual, request, others_request);
5534 + /* A failure */
5535 + BUG_ON((others_request & actual)
5536 + != others_request);
5537 + request &= actual;
5538 + rc = -EIO;
5539 + }
5540 +
5541 + g_state.global_request = actual;
5542 + g_state.client_request[handle] =
5543 + request;
5544 + }
5545 + }
5546 + }
5547 + up(&g_state.mutex);
5548 + } else {
5549 + rc = -EINVAL;
5550 + }
5551 + DPRINTK("bcm_power_request -> %d\n", rc);
5552 + return rc;
5553 +}
5554 +EXPORT_SYMBOL_GPL(bcm_power_request);
5555 +
5556 +int bcm_power_close(BCM_POWER_HANDLE_T handle)
5557 +{
5558 + int rc;
5559 +
5560 + DPRINTK("bcm_power_close(%d)\n", handle);
5561 +
5562 + rc = bcm_power_request(handle, BCM_POWER_NONE);
5563 + if (rc == 0)
5564 + g_state.client_request[handle] = BCM_POWER_NOCLIENT;
5565 +
5566 + return rc;
5567 +}
5568 +EXPORT_SYMBOL_GPL(bcm_power_close);
5569 +
5570 +static int __init bcm_power_init(void)
5571 +{
5572 +#if defined(BCM_POWER_ALWAYS_ON)
5573 + BCM_POWER_HANDLE_T always_on_handle;
5574 +#endif
5575 + int rc = 0;
5576 + int i;
5577 +
5578 + printk(KERN_INFO "bcm_power: Broadcom power driver\n");
5579 + bcm_mailbox_write(MBOX_CHAN_POWER, 0);
5580 +
5581 + for (i = 0; i < BCM_POWER_MAXCLIENTS; i++)
5582 + g_state.client_request[i] = BCM_POWER_NOCLIENT;
5583 +
5584 + sema_init(&g_state.client_mutex, 1);
5585 + sema_init(&g_state.mutex, 1);
5586 +
5587 + g_state.global_request = 0;
5588 +
5589 +#if defined(BCM_POWER_ALWAYS_ON)
5590 + if (BCM_POWER_ALWAYS_ON) {
5591 + bcm_power_open(&always_on_handle);
5592 + bcm_power_request(always_on_handle, BCM_POWER_ALWAYS_ON);
5593 + }
5594 +#endif
5595 +
5596 + return rc;
5597 +}
5598 +
5599 +static void __exit bcm_power_exit(void)
5600 +{
5601 + bcm_mailbox_write(MBOX_CHAN_POWER, 0);
5602 +}
5603 +
5604 +arch_initcall(bcm_power_init); /* Initialize early */
5605 +module_exit(bcm_power_exit);
5606 +
5607 +MODULE_AUTHOR("Phil Elwell");
5608 +MODULE_DESCRIPTION("Interface to BCM2708 power management");
5609 +MODULE_LICENSE("GPL");
5610 diff --git a/arch/arm/mach-bcm2708/vc_mem.c b/arch/arm/mach-bcm2708/vc_mem.c
5611 new file mode 100644
5612 index 0000000..2adac12
5613 --- /dev/null
5614 +++ b/arch/arm/mach-bcm2708/vc_mem.c
5615 @@ -0,0 +1,432 @@
5616 +/*****************************************************************************
5617 +* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved.
5618 +*
5619 +* Unless you and Broadcom execute a separate written software license
5620 +* agreement governing use of this software, this software is licensed to you
5621 +* under the terms of the GNU General Public License version 2, available at
5622 +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
5623 +*
5624 +* Notwithstanding the above, under no circumstances may you combine this
5625 +* software in any way with any other Broadcom software provided under a
5626 +* license other than the GPL, without Broadcom's express prior written
5627 +* consent.
5628 +*****************************************************************************/
5629 +
5630 +#include <linux/kernel.h>
5631 +#include <linux/module.h>
5632 +#include <linux/fs.h>
5633 +#include <linux/device.h>
5634 +#include <linux/cdev.h>
5635 +#include <linux/mm.h>
5636 +#include <linux/slab.h>
5637 +#include <linux/debugfs.h>
5638 +#include <asm/uaccess.h>
5639 +#include <linux/dma-mapping.h>
5640 +
5641 +#ifdef CONFIG_ARCH_KONA
5642 +#include <chal/chal_ipc.h>
5643 +#elif CONFIG_ARCH_BCM2708
5644 +#else
5645 +#include <csp/chal_ipc.h>
5646 +#endif
5647 +
5648 +#include "mach/vc_mem.h"
5649 +#include <mach/vcio.h>
5650 +
5651 +#define DRIVER_NAME "vc-mem"
5652 +
5653 +// Device (/dev) related variables
5654 +static dev_t vc_mem_devnum = 0;
5655 +static struct class *vc_mem_class = NULL;
5656 +static struct cdev vc_mem_cdev;
5657 +static int vc_mem_inited = 0;
5658 +
5659 +#ifdef CONFIG_DEBUG_FS
5660 +static struct dentry *vc_mem_debugfs_entry;
5661 +#endif
5662 +
5663 +/*
5664 + * Videocore memory addresses and size
5665 + *
5666 + * Drivers that wish to know the videocore memory addresses and sizes should
5667 + * use these variables instead of the MM_IO_BASE and MM_ADDR_IO defines in
5668 + * headers. This allows the other drivers to not be tied down to a a certain
5669 + * address/size at compile time.
5670 + *
5671 + * In the future, the goal is to have the videocore memory virtual address and
5672 + * size be calculated at boot time rather than at compile time. The decision of
5673 + * where the videocore memory resides and its size would be in the hands of the
5674 + * bootloader (and/or kernel). When that happens, the values of these variables
5675 + * would be calculated and assigned in the init function.
5676 + */
5677 +// in the 2835 VC in mapped above ARM, but ARM has full access to VC space
5678 +unsigned long mm_vc_mem_phys_addr = 0x00000000;
5679 +unsigned int mm_vc_mem_size = 0;
5680 +unsigned int mm_vc_mem_base = 0;
5681 +
5682 +EXPORT_SYMBOL(mm_vc_mem_phys_addr);
5683 +EXPORT_SYMBOL(mm_vc_mem_size);
5684 +EXPORT_SYMBOL(mm_vc_mem_base);
5685 +
5686 +static uint phys_addr = 0;
5687 +static uint mem_size = 0;
5688 +static uint mem_base = 0;
5689 +
5690 +
5691 +/****************************************************************************
5692 +*
5693 +* vc_mem_open
5694 +*
5695 +***************************************************************************/
5696 +
5697 +static int
5698 +vc_mem_open(struct inode *inode, struct file *file)
5699 +{
5700 + (void) inode;
5701 + (void) file;
5702 +
5703 + pr_debug("%s: called file = 0x%p\n", __func__, file);
5704 +
5705 + return 0;
5706 +}
5707 +
5708 +/****************************************************************************
5709 +*
5710 +* vc_mem_release
5711 +*
5712 +***************************************************************************/
5713 +
5714 +static int
5715 +vc_mem_release(struct inode *inode, struct file *file)
5716 +{
5717 + (void) inode;
5718 + (void) file;
5719 +
5720 + pr_debug("%s: called file = 0x%p\n", __func__, file);
5721 +
5722 + return 0;
5723 +}
5724 +
5725 +/****************************************************************************
5726 +*
5727 +* vc_mem_get_size
5728 +*
5729 +***************************************************************************/
5730 +
5731 +static void
5732 +vc_mem_get_size(void)
5733 +{
5734 +}
5735 +
5736 +/****************************************************************************
5737 +*
5738 +* vc_mem_get_base
5739 +*
5740 +***************************************************************************/
5741 +
5742 +static void
5743 +vc_mem_get_base(void)
5744 +{
5745 +}
5746 +
5747 +/****************************************************************************
5748 +*
5749 +* vc_mem_get_current_size
5750 +*
5751 +***************************************************************************/
5752 +
5753 +int
5754 +vc_mem_get_current_size(void)
5755 +{
5756 + return mm_vc_mem_size;
5757 +}
5758 +
5759 +EXPORT_SYMBOL_GPL(vc_mem_get_current_size);
5760 +
5761 +/****************************************************************************
5762 +*
5763 +* vc_mem_ioctl
5764 +*
5765 +***************************************************************************/
5766 +
5767 +static long
5768 +vc_mem_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
5769 +{
5770 + int rc = 0;
5771 +
5772 + (void) cmd;
5773 + (void) arg;
5774 +
5775 + pr_debug("%s: called file = 0x%p\n", __func__, file);
5776 +
5777 + switch (cmd) {
5778 + case VC_MEM_IOC_MEM_PHYS_ADDR:
5779 + {
5780 + pr_debug("%s: VC_MEM_IOC_MEM_PHYS_ADDR=0x%p\n",
5781 + __func__, (void *) mm_vc_mem_phys_addr);
5782 +
5783 + if (copy_to_user((void *) arg, &mm_vc_mem_phys_addr,
5784 + sizeof (mm_vc_mem_phys_addr)) != 0) {
5785 + rc = -EFAULT;
5786 + }
5787 + break;
5788 + }
5789 + case VC_MEM_IOC_MEM_SIZE:
5790 + {
5791 + // Get the videocore memory size first
5792 + vc_mem_get_size();
5793 +
5794 + pr_debug("%s: VC_MEM_IOC_MEM_SIZE=%u\n", __func__,
5795 + mm_vc_mem_size);
5796 +
5797 + if (copy_to_user((void *) arg, &mm_vc_mem_size,
5798 + sizeof (mm_vc_mem_size)) != 0) {
5799 + rc = -EFAULT;
5800 + }
5801 + break;
5802 + }
5803 + case VC_MEM_IOC_MEM_BASE:
5804 + {
5805 + // Get the videocore memory base
5806 + vc_mem_get_base();
5807 +
5808 + pr_debug("%s: VC_MEM_IOC_MEM_BASE=%u\n", __func__,
5809 + mm_vc_mem_base);
5810 +
5811 + if (copy_to_user((void *) arg, &mm_vc_mem_base,
5812 + sizeof (mm_vc_mem_base)) != 0) {
5813 + rc = -EFAULT;
5814 + }
5815 + break;
5816 + }
5817 + case VC_MEM_IOC_MEM_LOAD:
5818 + {
5819 + // Get the videocore memory base
5820 + vc_mem_get_base();
5821 +
5822 + pr_debug("%s: VC_MEM_IOC_MEM_LOAD=%u\n", __func__,
5823 + mm_vc_mem_base);
5824 +
5825 + if (copy_to_user((void *) arg, &mm_vc_mem_base,
5826 + sizeof (mm_vc_mem_base)) != 0) {
5827 + rc = -EFAULT;
5828 + }
5829 + break;
5830 + }
5831 + default:
5832 + {
5833 + return -ENOTTY;
5834 + }
5835 + }
5836 + pr_debug("%s: file = 0x%p returning %d\n", __func__, file, rc);
5837 +
5838 + return rc;
5839 +}
5840 +
5841 +/****************************************************************************
5842 +*
5843 +* vc_mem_mmap
5844 +*
5845 +***************************************************************************/
5846 +
5847 +static int
5848 +vc_mem_mmap(struct file *filp, struct vm_area_struct *vma)
5849 +{
5850 + int rc = 0;
5851 + unsigned long length = vma->vm_end - vma->vm_start;
5852 + unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
5853 +
5854 + pr_debug("%s: vm_start = 0x%08lx vm_end = 0x%08lx vm_pgoff = 0x%08lx\n",
5855 + __func__, (long) vma->vm_start, (long) vma->vm_end,
5856 + (long) vma->vm_pgoff);
5857 +
5858 + if (offset + length > mm_vc_mem_size) {
5859 + pr_err("%s: length %ld is too big\n", __func__, length);
5860 + return -EINVAL;
5861 + }
5862 + // Do not cache the memory map
5863 + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
5864 +
5865 + rc = remap_pfn_range(vma, vma->vm_start,
5866 + (mm_vc_mem_phys_addr >> PAGE_SHIFT) +
5867 + vma->vm_pgoff, length, vma->vm_page_prot);
5868 + if (rc != 0) {
5869 + pr_err("%s: remap_pfn_range failed (rc=%d)\n", __func__, rc);
5870 + }
5871 +
5872 + return rc;
5873 +}
5874 +
5875 +/****************************************************************************
5876 +*
5877 +* File Operations for the driver.
5878 +*
5879 +***************************************************************************/
5880 +
5881 +static const struct file_operations vc_mem_fops = {
5882 + .owner = THIS_MODULE,
5883 + .open = vc_mem_open,
5884 + .release = vc_mem_release,
5885 + .unlocked_ioctl = vc_mem_ioctl,
5886 + .mmap = vc_mem_mmap,
5887 +};
5888 +
5889 +#ifdef CONFIG_DEBUG_FS
5890 +static void vc_mem_debugfs_deinit(void)
5891 +{
5892 + debugfs_remove_recursive(vc_mem_debugfs_entry);
5893 + vc_mem_debugfs_entry = NULL;
5894 +}
5895 +
5896 +
5897 +static int vc_mem_debugfs_init(
5898 + struct device *dev)
5899 +{
5900 + vc_mem_debugfs_entry = debugfs_create_dir(DRIVER_NAME, NULL);
5901 + if (!vc_mem_debugfs_entry) {
5902 + dev_warn(dev, "could not create debugfs entry\n");
5903 + return -EFAULT;
5904 + }
5905 +
5906 + if (!debugfs_create_x32("vc_mem_phys_addr",
5907 + 0444,
5908 + vc_mem_debugfs_entry,
5909 + (u32 *)&mm_vc_mem_phys_addr)) {
5910 + dev_warn(dev, "%s:could not create vc_mem_phys entry\n",
5911 + __func__);
5912 + goto fail;
5913 + }
5914 +
5915 + if (!debugfs_create_x32("vc_mem_size",
5916 + 0444,
5917 + vc_mem_debugfs_entry,
5918 + (u32 *)&mm_vc_mem_size)) {
5919 + dev_warn(dev, "%s:could not create vc_mem_size entry\n",
5920 + __func__);
5921 + goto fail;
5922 + }
5923 +
5924 + if (!debugfs_create_x32("vc_mem_base",
5925 + 0444,
5926 + vc_mem_debugfs_entry,
5927 + (u32 *)&mm_vc_mem_base)) {
5928 + dev_warn(dev, "%s:could not create vc_mem_base entry\n",
5929 + __func__);
5930 + goto fail;
5931 + }
5932 +
5933 + return 0;
5934 +
5935 +fail:
5936 + vc_mem_debugfs_deinit();
5937 + return -EFAULT;
5938 +}
5939 +
5940 +#endif /* CONFIG_DEBUG_FS */
5941 +
5942 +
5943 +/****************************************************************************
5944 +*
5945 +* vc_mem_init
5946 +*
5947 +***************************************************************************/
5948 +
5949 +static int __init
5950 +vc_mem_init(void)
5951 +{
5952 + int rc = -EFAULT;
5953 + struct device *dev;
5954 +
5955 + pr_debug("%s: called\n", __func__);
5956 +
5957 + mm_vc_mem_phys_addr = phys_addr;
5958 + mm_vc_mem_size = mem_size;
5959 + mm_vc_mem_base = mem_base;
5960 +
5961 + vc_mem_get_size();
5962 +
5963 + pr_info("vc-mem: phys_addr:0x%08lx mem_base=0x%08x mem_size:0x%08x(%u MiB)\n",
5964 + mm_vc_mem_phys_addr, mm_vc_mem_base, mm_vc_mem_size, mm_vc_mem_size / (1024 * 1024));
5965 +
5966 + if ((rc = alloc_chrdev_region(&vc_mem_devnum, 0, 1, DRIVER_NAME)) < 0) {
5967 + pr_err("%s: alloc_chrdev_region failed (rc=%d)\n",
5968 + __func__, rc);
5969 + goto out_err;
5970 + }
5971 +
5972 + cdev_init(&vc_mem_cdev, &vc_mem_fops);
5973 + if ((rc = cdev_add(&vc_mem_cdev, vc_mem_devnum, 1)) != 0) {
5974 + pr_err("%s: cdev_add failed (rc=%d)\n", __func__, rc);
5975 + goto out_unregister;
5976 + }
5977 +
5978 + vc_mem_class = class_create(THIS_MODULE, DRIVER_NAME);
5979 + if (IS_ERR(vc_mem_class)) {
5980 + rc = PTR_ERR(vc_mem_class);
5981 + pr_err("%s: class_create failed (rc=%d)\n", __func__, rc);
5982 + goto out_cdev_del;
5983 + }
5984 +
5985 + dev = device_create(vc_mem_class, NULL, vc_mem_devnum, NULL,
5986 + DRIVER_NAME);
5987 + if (IS_ERR(dev)) {
5988 + rc = PTR_ERR(dev);
5989 + pr_err("%s: device_create failed (rc=%d)\n", __func__, rc);
5990 + goto out_class_destroy;
5991 + }
5992 +
5993 +#ifdef CONFIG_DEBUG_FS
5994 + /* don't fail if the debug entries cannot be created */
5995 + vc_mem_debugfs_init(dev);
5996 +#endif
5997 +
5998 + vc_mem_inited = 1;
5999 + return 0;
6000 +
6001 + device_destroy(vc_mem_class, vc_mem_devnum);
6002 +
6003 + out_class_destroy:
6004 + class_destroy(vc_mem_class);
6005 + vc_mem_class = NULL;
6006 +
6007 + out_cdev_del:
6008 + cdev_del(&vc_mem_cdev);
6009 +
6010 + out_unregister:
6011 + unregister_chrdev_region(vc_mem_devnum, 1);
6012 +
6013 + out_err:
6014 + return -1;
6015 +}
6016 +
6017 +/****************************************************************************
6018 +*
6019 +* vc_mem_exit
6020 +*
6021 +***************************************************************************/
6022 +
6023 +static void __exit
6024 +vc_mem_exit(void)
6025 +{
6026 + pr_debug("%s: called\n", __func__);
6027 +
6028 + if (vc_mem_inited) {
6029 +#if CONFIG_DEBUG_FS
6030 + vc_mem_debugfs_deinit();
6031 +#endif
6032 + device_destroy(vc_mem_class, vc_mem_devnum);
6033 + class_destroy(vc_mem_class);
6034 + cdev_del(&vc_mem_cdev);
6035 + unregister_chrdev_region(vc_mem_devnum, 1);
6036 + }
6037 +}
6038 +
6039 +module_init(vc_mem_init);
6040 +module_exit(vc_mem_exit);
6041 +MODULE_LICENSE("GPL");
6042 +MODULE_AUTHOR("Broadcom Corporation");
6043 +
6044 +module_param(phys_addr, uint, 0644);
6045 +module_param(mem_size, uint, 0644);
6046 +module_param(mem_base, uint, 0644);
6047 +
6048 diff --git a/arch/arm/mach-bcm2708/vcio.c b/arch/arm/mach-bcm2708/vcio.c
6049 new file mode 100644
6050 index 0000000..5e43e85
6051 --- /dev/null
6052 +++ b/arch/arm/mach-bcm2708/vcio.c
6053 @@ -0,0 +1,474 @@
6054 +/*
6055 + * linux/arch/arm/mach-bcm2708/vcio.c
6056 + *
6057 + * Copyright (C) 2010 Broadcom
6058 + *
6059 + * This program is free software; you can redistribute it and/or modify
6060 + * it under the terms of the GNU General Public License version 2 as
6061 + * published by the Free Software Foundation.
6062 + *
6063 + * This device provides a shared mechanism for writing to the mailboxes,
6064 + * semaphores, doorbells etc. that are shared between the ARM and the
6065 + * VideoCore processor
6066 + */
6067 +
6068 +#if defined(CONFIG_SERIAL_BCM_MBOX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
6069 +#define SUPPORT_SYSRQ
6070 +#endif
6071 +
6072 +#include <linux/module.h>
6073 +#include <linux/console.h>
6074 +#include <linux/serial_core.h>
6075 +#include <linux/serial.h>
6076 +#include <linux/errno.h>
6077 +#include <linux/device.h>
6078 +#include <linux/init.h>
6079 +#include <linux/mm.h>
6080 +#include <linux/dma-mapping.h>
6081 +#include <linux/platform_device.h>
6082 +#include <linux/sysrq.h>
6083 +#include <linux/delay.h>
6084 +#include <linux/slab.h>
6085 +#include <linux/interrupt.h>
6086 +#include <linux/irq.h>
6087 +
6088 +#include <linux/io.h>
6089 +
6090 +#include <mach/vcio.h>
6091 +#include <mach/platform.h>
6092 +
6093 +#include <asm/uaccess.h>
6094 +
6095 +
6096 +#define DRIVER_NAME BCM_VCIO_DRIVER_NAME
6097 +
6098 +/* ----------------------------------------------------------------------
6099 + * Mailbox
6100 + * -------------------------------------------------------------------- */
6101 +
6102 +/* offsets from a mail box base address */
6103 +#define MAIL_WRT 0x00 /* write - and next 4 words */
6104 +#define MAIL_RD 0x00 /* read - and next 4 words */
6105 +#define MAIL_POL 0x10 /* read without popping the fifo */
6106 +#define MAIL_SND 0x14 /* sender ID (bottom two bits) */
6107 +#define MAIL_STA 0x18 /* status */
6108 +#define MAIL_CNF 0x1C /* configuration */
6109 +
6110 +#define MBOX_MSG(chan, data28) (((data28) & ~0xf) | ((chan) & 0xf))
6111 +#define MBOX_MSG_LSB(chan, data28) (((data28) << 4) | ((chan) & 0xf))
6112 +#define MBOX_CHAN(msg) ((msg) & 0xf)
6113 +#define MBOX_DATA28(msg) ((msg) & ~0xf)
6114 +#define MBOX_DATA28_LSB(msg) (((uint32_t)msg) >> 4)
6115 +
6116 +#define MBOX_MAGIC 0xd0d0c0de
6117 +
6118 +struct vc_mailbox {
6119 + struct device *dev; /* parent device */
6120 + void __iomem *status;
6121 + void __iomem *config;
6122 + void __iomem *read;
6123 + void __iomem *write;
6124 + uint32_t msg[MBOX_CHAN_COUNT];
6125 + struct semaphore sema[MBOX_CHAN_COUNT];
6126 + uint32_t magic;
6127 +};
6128 +
6129 +static void mbox_init(struct vc_mailbox *mbox_out, struct device *dev,
6130 + uint32_t addr_mbox)
6131 +{
6132 + int i;
6133 +
6134 + mbox_out->dev = dev;
6135 + mbox_out->status = __io_address(addr_mbox + MAIL_STA);
6136 + mbox_out->config = __io_address(addr_mbox + MAIL_CNF);
6137 + mbox_out->read = __io_address(addr_mbox + MAIL_RD);
6138 + /* Write to the other mailbox */
6139 + mbox_out->write =
6140 + __io_address((addr_mbox ^ ARM_0_MAIL0_WRT ^ ARM_0_MAIL1_WRT) +
6141 + MAIL_WRT);
6142 +
6143 + for (i = 0; i < MBOX_CHAN_COUNT; i++) {
6144 + mbox_out->msg[i] = 0;
6145 + sema_init(&mbox_out->sema[i], 0);
6146 + }
6147 +
6148 + /* Enable the interrupt on data reception */
6149 + writel(ARM_MC_IHAVEDATAIRQEN, mbox_out->config);
6150 +
6151 + mbox_out->magic = MBOX_MAGIC;
6152 +}
6153 +
6154 +static int mbox_write(struct vc_mailbox *mbox, unsigned chan, uint32_t data28)
6155 +{
6156 + int rc;
6157 +
6158 + if (mbox->magic != MBOX_MAGIC)
6159 + rc = -EINVAL;
6160 + else {
6161 + /* wait for the mailbox FIFO to have some space in it */
6162 + while (0 != (readl(mbox->status) & ARM_MS_FULL))
6163 + cpu_relax();
6164 +
6165 + writel(MBOX_MSG(chan, data28), mbox->write);
6166 + rc = 0;
6167 + }
6168 + return rc;
6169 +}
6170 +
6171 +static int mbox_read(struct vc_mailbox *mbox, unsigned chan, uint32_t *data28)
6172 +{
6173 + int rc;
6174 +
6175 + if (mbox->magic != MBOX_MAGIC)
6176 + rc = -EINVAL;
6177 + else {
6178 + down(&mbox->sema[chan]);
6179 + *data28 = MBOX_DATA28(mbox->msg[chan]);
6180 + mbox->msg[chan] = 0;
6181 + rc = 0;
6182 + }
6183 + return rc;
6184 +}
6185 +
6186 +static irqreturn_t mbox_irq(int irq, void *dev_id)
6187 +{
6188 + /* wait for the mailbox FIFO to have some data in it */
6189 + struct vc_mailbox *mbox = (struct vc_mailbox *) dev_id;
6190 + int status = readl(mbox->status);
6191 + int ret = IRQ_NONE;
6192 +
6193 + while (!(status & ARM_MS_EMPTY)) {
6194 + uint32_t msg = readl(mbox->read);
6195 + int chan = MBOX_CHAN(msg);
6196 + if (chan < MBOX_CHAN_COUNT) {
6197 + if (mbox->msg[chan]) {
6198 + /* Overflow */
6199 + printk(KERN_ERR DRIVER_NAME
6200 + ": mbox chan %d overflow - drop %08x\n",
6201 + chan, msg);
6202 + } else {
6203 + mbox->msg[chan] = (msg | 0xf);
6204 + up(&mbox->sema[chan]);
6205 + }
6206 + } else {
6207 + printk(KERN_ERR DRIVER_NAME
6208 + ": invalid channel selector (msg %08x)\n", msg);
6209 + }
6210 + ret = IRQ_HANDLED;
6211 + status = readl(mbox->status);
6212 + }
6213 + return ret;
6214 +}
6215 +
6216 +static struct irqaction mbox_irqaction = {
6217 + .name = "ARM Mailbox IRQ",
6218 + .flags = IRQF_DISABLED | IRQF_IRQPOLL,
6219 + .handler = mbox_irq,
6220 +};
6221 +
6222 +/* ----------------------------------------------------------------------
6223 + * Mailbox Methods
6224 + * -------------------------------------------------------------------- */
6225 +
6226 +static struct device *mbox_dev; /* we assume there's only one! */
6227 +
6228 +static int dev_mbox_write(struct device *dev, unsigned chan, uint32_t data28)
6229 +{
6230 + int rc;
6231 +
6232 + struct vc_mailbox *mailbox = dev_get_drvdata(dev);
6233 + device_lock(dev);
6234 + rc = mbox_write(mailbox, chan, data28);
6235 + device_unlock(dev);
6236 +
6237 + return rc;
6238 +}
6239 +
6240 +static int dev_mbox_read(struct device *dev, unsigned chan, uint32_t *data28)
6241 +{
6242 + int rc;
6243 +
6244 + struct vc_mailbox *mailbox = dev_get_drvdata(dev);
6245 + device_lock(dev);
6246 + rc = mbox_read(mailbox, chan, data28);
6247 + device_unlock(dev);
6248 +
6249 + return rc;
6250 +}
6251 +
6252 +extern int bcm_mailbox_write(unsigned chan, uint32_t data28)
6253 +{
6254 + if (mbox_dev)
6255 + return dev_mbox_write(mbox_dev, chan, data28);
6256 + else
6257 + return -ENODEV;
6258 +}
6259 +EXPORT_SYMBOL_GPL(bcm_mailbox_write);
6260 +
6261 +extern int bcm_mailbox_read(unsigned chan, uint32_t *data28)
6262 +{
6263 + if (mbox_dev)
6264 + return dev_mbox_read(mbox_dev, chan, data28);
6265 + else
6266 + return -ENODEV;
6267 +}
6268 +EXPORT_SYMBOL_GPL(bcm_mailbox_read);
6269 +
6270 +static void dev_mbox_register(const char *dev_name, struct device *dev)
6271 +{
6272 + mbox_dev = dev;
6273 +}
6274 +
6275 +static int mbox_copy_from_user(void *dst, const void *src, int size)
6276 +{
6277 + if ( (uint32_t)src < TASK_SIZE)
6278 + {
6279 + return copy_from_user(dst, src, size);
6280 + }
6281 + else
6282 + {
6283 + memcpy( dst, src, size );
6284 + return 0;
6285 + }
6286 +}
6287 +
6288 +static int mbox_copy_to_user(void *dst, const void *src, int size)
6289 +{
6290 + if ( (uint32_t)dst < TASK_SIZE)
6291 + {
6292 + return copy_to_user(dst, src, size);
6293 + }
6294 + else
6295 + {
6296 + memcpy( dst, src, size );
6297 + return 0;
6298 + }
6299 +}
6300 +
6301 +static DEFINE_MUTEX(mailbox_lock);
6302 +extern int bcm_mailbox_property(void *data, int size)
6303 +{
6304 + uint32_t success;
6305 + dma_addr_t mem_bus; /* the memory address accessed from videocore */
6306 + void *mem_kern; /* the memory address accessed from driver */
6307 + int s = 0;
6308 +
6309 + mutex_lock(&mailbox_lock);
6310 + /* allocate some memory for the messages communicating with GPU */
6311 + mem_kern = dma_alloc_coherent(NULL, PAGE_ALIGN(size), &mem_bus, GFP_ATOMIC);
6312 + if (mem_kern) {
6313 + /* create the message */
6314 + mbox_copy_from_user(mem_kern, data, size);
6315 +
6316 + /* send the message */
6317 + wmb();
6318 + s = bcm_mailbox_write(MBOX_CHAN_PROPERTY, (uint32_t)mem_bus);
6319 + if (s == 0) {
6320 + s = bcm_mailbox_read(MBOX_CHAN_PROPERTY, &success);
6321 + }
6322 + if (s == 0) {
6323 + /* copy the response */
6324 + rmb();
6325 + mbox_copy_to_user(data, mem_kern, size);
6326 + }
6327 + dma_free_coherent(NULL, PAGE_ALIGN(size), mem_kern, mem_bus);
6328 + } else {
6329 + s = -ENOMEM;
6330 + }
6331 + if (s != 0)
6332 + printk(KERN_ERR DRIVER_NAME ": %s failed (%d)\n", __func__, s);
6333 +
6334 + mutex_unlock(&mailbox_lock);
6335 + return s;
6336 +}
6337 +EXPORT_SYMBOL_GPL(bcm_mailbox_property);
6338 +
6339 +/* ----------------------------------------------------------------------
6340 + * Platform Device for Mailbox
6341 + * -------------------------------------------------------------------- */
6342 +
6343 +/*
6344 + * Is the device open right now? Used to prevent
6345 + * concurent access into the same device
6346 + */
6347 +static int Device_Open = 0;
6348 +
6349 +/*
6350 + * This is called whenever a process attempts to open the device file
6351 + */
6352 +static int device_open(struct inode *inode, struct file *file)
6353 +{
6354 + /*
6355 + * We don't want to talk to two processes at the same time
6356 + */
6357 + if (Device_Open)
6358 + return -EBUSY;
6359 +
6360 + Device_Open++;
6361 + /*
6362 + * Initialize the message
6363 + */
6364 + try_module_get(THIS_MODULE);
6365 + return 0;
6366 +}
6367 +
6368 +static int device_release(struct inode *inode, struct file *file)
6369 +{
6370 + /*
6371 + * We're now ready for our next caller
6372 + */
6373 + Device_Open--;
6374 +
6375 + module_put(THIS_MODULE);
6376 + return 0;
6377 +}
6378 +
6379 +/*
6380 + * This function is called whenever a process tries to do an ioctl on our
6381 + * device file. We get two extra parameters (additional to the inode and file
6382 + * structures, which all device functions get): the number of the ioctl called
6383 + * and the parameter given to the ioctl function.
6384 + *
6385 + * If the ioctl is write or read/write (meaning output is returned to the
6386 + * calling process), the ioctl call returns the output of this function.
6387 + *
6388 + */
6389 +static long device_ioctl(struct file *file, /* see include/linux/fs.h */
6390 + unsigned int ioctl_num, /* number and param for ioctl */
6391 + unsigned long ioctl_param)
6392 +{
6393 + unsigned size;
6394 + /*
6395 + * Switch according to the ioctl called
6396 + */
6397 + switch (ioctl_num) {
6398 + case IOCTL_MBOX_PROPERTY:
6399 + /*
6400 + * Receive a pointer to a message (in user space) and set that
6401 + * to be the device's message. Get the parameter given to
6402 + * ioctl by the process.
6403 + */
6404 + mbox_copy_from_user(&size, (void *)ioctl_param, sizeof size);
6405 + return bcm_mailbox_property((void *)ioctl_param, size);
6406 + break;
6407 + default:
6408 + printk(KERN_ERR DRIVER_NAME "unknown ioctl: %d\n", ioctl_num);
6409 + return -EINVAL;
6410 + }
6411 +
6412 + return 0;
6413 +}
6414 +
6415 +/* Module Declarations */
6416 +
6417 +/*
6418 + * This structure will hold the functions to be called
6419 + * when a process does something to the device we
6420 + * created. Since a pointer to this structure is kept in
6421 + * the devices table, it can't be local to
6422 + * init_module. NULL is for unimplemented functios.
6423 + */
6424 +struct file_operations fops = {
6425 + .unlocked_ioctl = device_ioctl,
6426 + .open = device_open,
6427 + .release = device_release, /* a.k.a. close */
6428 +};
6429 +
6430 +static int bcm_vcio_probe(struct platform_device *pdev)
6431 +{
6432 + int ret = 0;
6433 + struct vc_mailbox *mailbox;
6434 +
6435 + mailbox = kzalloc(sizeof(*mailbox), GFP_KERNEL);
6436 + if (NULL == mailbox) {
6437 + printk(KERN_ERR DRIVER_NAME ": failed to allocate "
6438 + "mailbox memory\n");
6439 + ret = -ENOMEM;
6440 + } else {
6441 + struct resource *res;
6442 +
6443 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
6444 + if (res == NULL) {
6445 + printk(KERN_ERR DRIVER_NAME ": failed to obtain memory "
6446 + "resource\n");
6447 + ret = -ENODEV;
6448 + kfree(mailbox);
6449 + } else {
6450 + /* should be based on the registers from res really */
6451 + mbox_init(mailbox, &pdev->dev, ARM_0_MAIL0_RD);
6452 +
6453 + platform_set_drvdata(pdev, mailbox);
6454 + dev_mbox_register(DRIVER_NAME, &pdev->dev);
6455 +
6456 + mbox_irqaction.dev_id = mailbox;
6457 + setup_irq(IRQ_ARM_MAILBOX, &mbox_irqaction);
6458 + printk(KERN_INFO DRIVER_NAME ": mailbox at %p\n",
6459 + __io_address(ARM_0_MAIL0_RD));
6460 + }
6461 + }
6462 +
6463 + if (ret == 0) {
6464 + /*
6465 + * Register the character device
6466 + */
6467 + ret = register_chrdev(MAJOR_NUM, DEVICE_FILE_NAME, &fops);
6468 +
6469 + /*
6470 + * Negative values signify an error
6471 + */
6472 + if (ret < 0) {
6473 + printk(KERN_ERR DRIVER_NAME
6474 + "Failed registering the character device %d\n", ret);
6475 + return ret;
6476 + }
6477 + }
6478 + return ret;
6479 +}
6480 +
6481 +static int bcm_vcio_remove(struct platform_device *pdev)
6482 +{
6483 + struct vc_mailbox *mailbox = platform_get_drvdata(pdev);
6484 +
6485 + platform_set_drvdata(pdev, NULL);
6486 + kfree(mailbox);
6487 +
6488 + return 0;
6489 +}
6490 +
6491 +static struct platform_driver bcm_mbox_driver = {
6492 + .probe = bcm_vcio_probe,
6493 + .remove = bcm_vcio_remove,
6494 +
6495 + .driver = {
6496 + .name = DRIVER_NAME,
6497 + .owner = THIS_MODULE,
6498 + },
6499 +};
6500 +
6501 +static int __init bcm_mbox_init(void)
6502 +{
6503 + int ret;
6504 +
6505 + printk(KERN_INFO "mailbox: Broadcom VideoCore Mailbox driver\n");
6506 +
6507 + ret = platform_driver_register(&bcm_mbox_driver);
6508 + if (ret != 0) {
6509 + printk(KERN_ERR DRIVER_NAME ": failed to register "
6510 + "on platform\n");
6511 + }
6512 +
6513 + return ret;
6514 +}
6515 +
6516 +static void __exit bcm_mbox_exit(void)
6517 +{
6518 + platform_driver_unregister(&bcm_mbox_driver);
6519 +}
6520 +
6521 +arch_initcall(bcm_mbox_init); /* Initialize early */
6522 +module_exit(bcm_mbox_exit);
6523 +
6524 +MODULE_AUTHOR("Gray Girling");
6525 +MODULE_DESCRIPTION("ARM I/O to VideoCore processor");
6526 +MODULE_LICENSE("GPL");
6527 +MODULE_ALIAS("platform:bcm-mbox");
6528 diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
6529 index ca8ecde..4afbeda 100644
6530 --- a/arch/arm/mm/Kconfig
6531 +++ b/arch/arm/mm/Kconfig
6532 @@ -358,7 +358,7 @@ config CPU_PJ4B
6533
6534 # ARMv6
6535 config CPU_V6
6536 - bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
6537 + bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || MACH_BCM2708
6538 select CPU_32v6
6539 select CPU_ABRT_EV6
6540 select CPU_CACHE_V6
6541 diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
6542 index 32b3558..4712ccb 100644
6543 --- a/arch/arm/mm/proc-v6.S
6544 +++ b/arch/arm/mm/proc-v6.S
6545 @@ -73,10 +73,19 @@ ENDPROC(cpu_v6_reset)
6546 *
6547 * IRQs are already disabled.
6548 */
6549 +
6550 +/* See jira SW-5991 for details of this workaround */
6551 ENTRY(cpu_v6_do_idle)
6552 - mov r1, #0
6553 - mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
6554 - mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
6555 + .align 5
6556 + mov r1, #2
6557 +1: subs r1, #1
6558 + nop
6559 + mcreq p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
6560 + mcreq p15, 0, r1, c7, c0, 4 @ wait for interrupt
6561 + nop
6562 + nop
6563 + nop
6564 + bne 1b
6565 mov pc, lr
6566
6567 ENTRY(cpu_v6_dcache_clean_area)
6568 diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
6569 index a10297d..c9ddd87 100644
6570 --- a/arch/arm/tools/mach-types
6571 +++ b/arch/arm/tools/mach-types
6572 @@ -522,6 +522,7 @@ torbreck MACH_TORBRECK TORBRECK 3090
6573 prima2_evb MACH_PRIMA2_EVB PRIMA2_EVB 3103
6574 paz00 MACH_PAZ00 PAZ00 3128
6575 acmenetusfoxg20 MACH_ACMENETUSFOXG20 ACMENETUSFOXG20 3129
6576 +bcm2708 MACH_BCM2708 BCM2708 3138
6577 ag5evm MACH_AG5EVM AG5EVM 3189
6578 ics_if_voip MACH_ICS_IF_VOIP ICS_IF_VOIP 3206
6579 wlf_cragg_6410 MACH_WLF_CRAGG_6410 WLF_CRAGG_6410 3207
6580 diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
6581 index 1384f67..bad4c9b 100644
6582 --- a/drivers/mmc/host/Kconfig
6583 +++ b/drivers/mmc/host/Kconfig
6584 @@ -272,6 +272,27 @@ config MMC_SDHCI_BCM_KONA
6585
6586 If you have a controller with this interface, say Y or M here.
6587
6588 +config MMC_SDHCI_BCM2708
6589 + tristate "SDHCI support on BCM2708"
6590 + depends on MMC_SDHCI && MACH_BCM2708
6591 + select MMC_SDHCI_IO_ACCESSORS
6592 + help
6593 + This selects the Secure Digital Host Controller Interface (SDHCI)
6594 + often referrered to as the eMMC block.
6595 +
6596 + If you have a controller with this interface, say Y or M here.
6597 +
6598 + If unsure, say N.
6599 +
6600 +config MMC_SDHCI_BCM2708_DMA
6601 + bool "DMA support on BCM2708 Arasan controller"
6602 + depends on MMC_SDHCI_BCM2708
6603 + help
6604 + Enable DMA support on the Arasan SDHCI controller in Broadcom 2708
6605 + based chips.
6606 +
6607 + If unsure, say N.
6608 +
6609 config MMC_SDHCI_BCM2835
6610 tristate "SDHCI platform support for the BCM2835 SD/MMC Controller"
6611 depends on ARCH_BCM2835
6612 diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
6613 index 3483b6b..11460d7 100644
6614 --- a/drivers/mmc/host/Makefile
6615 +++ b/drivers/mmc/host/Makefile
6616 @@ -16,6 +16,7 @@ obj-$(CONFIG_MMC_SDHCI_PXAV2) += sdhci-pxav2.o
6617 obj-$(CONFIG_MMC_SDHCI_S3C) += sdhci-s3c.o
6618 obj-$(CONFIG_MMC_SDHCI_SIRF) += sdhci-sirf.o
6619 obj-$(CONFIG_MMC_SDHCI_SPEAR) += sdhci-spear.o
6620 +obj-$(CONFIG_MMC_SDHCI_BCM2708) += sdhci-bcm2708.o
6621 obj-$(CONFIG_MMC_WBSD) += wbsd.o
6622 obj-$(CONFIG_MMC_AU1X) += au1xmmc.o
6623 obj-$(CONFIG_MMC_OMAP) += omap.o
6624 diff --git a/drivers/mmc/host/sdhci-bcm2708.c b/drivers/mmc/host/sdhci-bcm2708.c
6625 new file mode 100644
6626 index 0000000..d8ef77c
6627 --- /dev/null
6628 +++ b/drivers/mmc/host/sdhci-bcm2708.c
6629 @@ -0,0 +1,1424 @@
6630 +/*
6631 + * sdhci-bcm2708.c Support for SDHCI device on BCM2708
6632 + * Copyright (c) 2010 Broadcom
6633 + *
6634 + * This program is free software; you can redistribute it and/or modify
6635 + * it under the terms of the GNU General Public License version 2 as
6636 + * published by the Free Software Foundation.
6637 + *
6638 + * This program is distributed in the hope that it will be useful,
6639 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6640 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6641 + * GNU General Public License for more details.
6642 + *
6643 + * You should have received a copy of the GNU General Public License
6644 + * along with this program; if not, write to the Free Software
6645 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
6646 + */
6647 +
6648 +/* Supports:
6649 + * SDHCI platform device - Arasan SD controller in BCM2708
6650 + *
6651 + * Inspired by sdhci-pci.c, by Pierre Ossman
6652 + */
6653 +
6654 +#include <linux/delay.h>
6655 +#include <linux/highmem.h>
6656 +#include <linux/platform_device.h>
6657 +#include <linux/module.h>
6658 +#include <linux/mmc/mmc.h>
6659 +#include <linux/mmc/host.h>
6660 +#include <linux/mmc/sd.h>
6661 +
6662 +#include <linux/io.h>
6663 +#include <linux/dma-mapping.h>
6664 +#include <mach/dma.h>
6665 +
6666 +#include "sdhci.h"
6667 +
6668 +/*****************************************************************************\
6669 + * *
6670 + * Configuration *
6671 + * *
6672 +\*****************************************************************************/
6673 +
6674 +#define DRIVER_NAME "bcm2708_sdhci"
6675 +
6676 +/* for the time being insist on DMA mode - PIO seems not to work */
6677 +#ifndef CONFIG_MMC_SDHCI_BCM2708_DMA
6678 +#warning Non-DMA (PIO) version of this driver currently unavailable
6679 +#endif
6680 +#undef CONFIG_MMC_SDHCI_BCM2708_DMA
6681 +#define CONFIG_MMC_SDHCI_BCM2708_DMA y
6682 +
6683 +#define USE_SYNC_AFTER_DMA
6684 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
6685 +/* #define CHECK_DMA_USE */
6686 +#endif
6687 +//#define LOG_REGISTERS
6688 +
6689 +#define USE_SCHED_TIME
6690 +#define USE_SPACED_WRITES_2CLK 1 /* space consecutive register writes */
6691 +#define USE_SOFTWARE_TIMEOUTS 1 /* not hardware timeouts */
6692 +#define SOFTWARE_ERASE_TIMEOUT_SEC 30
6693 +
6694 +#define SDHCI_BCM_DMA_CHAN 4 /* this default is normally overriden */
6695 +#define SDHCI_BCM_DMA_WAITS 0 /* delays slowing DMA transfers: 0-31 */
6696 +/* We are worried that SD card DMA use may be blocking the AXI bus for others */
6697 +
6698 +/*! TODO: obtain these from the physical address */
6699 +#define DMA_SDHCI_BASE 0x7e300000 /* EMMC register block on Videocore */
6700 +#define DMA_SDHCI_BUFFER (DMA_SDHCI_BASE + SDHCI_BUFFER)
6701 +
6702 +#define BCM2708_SDHCI_SLEEP_TIMEOUT 1000 /* msecs */
6703 +
6704 +/* Mhz clock that the EMMC core is running at. Should match the platform clockman settings */
6705 +#define BCM2708_EMMC_CLOCK_FREQ 80000000
6706 +
6707 +/*****************************************************************************\
6708 + * *
6709 + * Debug *
6710 + * *
6711 +\*****************************************************************************/
6712 +
6713 +
6714 +
6715 +#define DBG(f, x...) \
6716 + pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
6717 +// printk(KERN_INFO DRIVER_NAME " [%s()]: " f, __func__,## x)//GRAYG
6718 +
6719 +
6720 +/*****************************************************************************\
6721 + * *
6722 + * High Precision Time *
6723 + * *
6724 +\*****************************************************************************/
6725 +
6726 +#ifdef USE_SCHED_TIME
6727 +
6728 +#include <mach/frc.h>
6729 +
6730 +typedef unsigned long hptime_t;
6731 +
6732 +#define FMT_HPT "lu"
6733 +
6734 +static inline hptime_t hptime(void)
6735 +{
6736 + return frc_clock_ticks32();
6737 +}
6738 +
6739 +#define HPTIME_CLK_NS 1000ul
6740 +
6741 +#else
6742 +
6743 +typedef unsigned long hptime_t;
6744 +
6745 +#define FMT_HPT "lu"
6746 +
6747 +static inline hptime_t hptime(void)
6748 +{
6749 + return jiffies;
6750 +}
6751 +
6752 +#define HPTIME_CLK_NS (1000000000ul/HZ)
6753 +
6754 +#endif
6755 +
6756 +static inline unsigned long int since_ns(hptime_t t)
6757 +{
6758 + return (unsigned long)((hptime() - t) * HPTIME_CLK_NS);
6759 +}
6760 +
6761 +#if 0
6762 +static void hptime_test(void)
6763 +{
6764 + hptime_t now;
6765 + hptime_t later;
6766 +
6767 + now = hptime();
6768 + msleep(10);
6769 + later = hptime();
6770 +
6771 + printk(KERN_INFO DRIVER_NAME": 10ms = %"FMT_HPT" clks "
6772 + "(from %"FMT_HPT" to %"FMT_HPT") = %luns\n",
6773 + later-now, now, later,
6774 + (unsigned long)(HPTIME_CLK_NS * (later - now)));
6775 +
6776 + now = hptime();
6777 + msleep(1000);
6778 + later = hptime();
6779 +
6780 + printk(KERN_INFO DRIVER_NAME": 1s = %"FMT_HPT" clks "
6781 + "(from %"FMT_HPT" to %"FMT_HPT") = %luns\n",
6782 + later-now, now, later,
6783 + (unsigned long)(HPTIME_CLK_NS * (later - now)));
6784 +}
6785 +#endif
6786 +
6787 +/*****************************************************************************\
6788 + * *
6789 + * SDHCI core callbacks *
6790 + * *
6791 +\*****************************************************************************/
6792 +
6793 +
6794 +#ifdef CHECK_DMA_USE
6795 +/*#define CHECK_DMA_REG_USE*/
6796 +#endif
6797 +
6798 +#ifdef CHECK_DMA_REG_USE
6799 +/* we don't expect anything to be using these registers during a
6800 + DMA (except the IRQ status) - so check */
6801 +static void check_dma_reg_use(struct sdhci_host *host, int reg);
6802 +#else
6803 +#define check_dma_reg_use(host, reg)
6804 +#endif
6805 +
6806 +
6807 +static inline u32 sdhci_bcm2708_raw_readl(struct sdhci_host *host, int reg)
6808 +{
6809 + return readl(host->ioaddr + reg);
6810 +}
6811 +
6812 +u32 sdhci_bcm2708_readl(struct sdhci_host *host, int reg)
6813 +{
6814 + u32 l = sdhci_bcm2708_raw_readl(host, reg);
6815 +
6816 +#ifdef LOG_REGISTERS
6817 + printk(KERN_ERR "%s: readl from 0x%02x, value 0x%08x\n",
6818 + mmc_hostname(host->mmc), reg, l);
6819 +#endif
6820 + check_dma_reg_use(host, reg);
6821 +
6822 + return l;
6823 +}
6824 +
6825 +u16 sdhci_bcm2708_readw(struct sdhci_host *host, int reg)
6826 +{
6827 + u32 l = sdhci_bcm2708_raw_readl(host, reg & ~3);
6828 + u32 w = l >> (reg << 3 & 0x18) & 0xffff;
6829 +
6830 +#ifdef LOG_REGISTERS
6831 + printk(KERN_ERR "%s: readw from 0x%02x, value 0x%04x\n",
6832 + mmc_hostname(host->mmc), reg, w);
6833 +#endif
6834 + check_dma_reg_use(host, reg);
6835 +
6836 + return (u16)w;
6837 +}
6838 +
6839 +u8 sdhci_bcm2708_readb(struct sdhci_host *host, int reg)
6840 +{
6841 + u32 l = sdhci_bcm2708_raw_readl(host, reg & ~3);
6842 + u32 b = l >> (reg << 3 & 0x18) & 0xff;
6843 +
6844 +#ifdef LOG_REGISTERS
6845 + printk(KERN_ERR "%s: readb from 0x%02x, value 0x%02x\n",
6846 + mmc_hostname(host->mmc), reg, b);
6847 +#endif
6848 + check_dma_reg_use(host, reg);
6849 +
6850 + return (u8)b;
6851 +}
6852 +
6853 +
6854 +static void sdhci_bcm2708_raw_writel(struct sdhci_host *host, u32 val, int reg)
6855 +{
6856 + u32 ier;
6857 +
6858 +#if USE_SPACED_WRITES_2CLK
6859 + static bool timeout_disabled = false;
6860 + unsigned int ns_2clk = 0;
6861 +
6862 + /* The Arasan has a bugette whereby it may lose the content of
6863 + * successive writes to registers that are within two SD-card clock
6864 + * cycles of each other (a clock domain crossing problem).
6865 + * It seems, however, that the data register does not have this problem.
6866 + * (Which is just as well - otherwise we'd have to nobble the DMA engine
6867 + * too)
6868 + */
6869 + if (reg != SDHCI_BUFFER && host->clock != 0) {
6870 + /* host->clock is the clock freq in Hz */
6871 + static hptime_t last_write_hpt;
6872 + hptime_t now = hptime();
6873 + ns_2clk = 2000000000/host->clock;
6874 +
6875 + if (now == last_write_hpt || now == last_write_hpt+1) {
6876 + /* we can't guarantee any significant time has
6877 + * passed - we'll have to wait anyway ! */
6878 + udelay((ns_2clk+1000-1)/1000);
6879 + } else
6880 + {
6881 + /* we must have waited at least this many ns: */
6882 + unsigned int ns_wait = HPTIME_CLK_NS *
6883 + (last_write_hpt - now - 1);
6884 + if (ns_wait < ns_2clk)
6885 + udelay((ns_2clk-ns_wait+500)/1000);
6886 + }
6887 + last_write_hpt = now;
6888 + }
6889 +#if USE_SOFTWARE_TIMEOUTS
6890 + /* The Arasan is clocked for timeouts using the SD clock which is too
6891 + * fast for ERASE commands and causes issues. So we disable timeouts
6892 + * for ERASE */
6893 + if (host->cmd != NULL && host->cmd->opcode == MMC_ERASE &&
6894 + reg == (SDHCI_COMMAND & ~3)) {
6895 + mod_timer(&host->timer,
6896 + jiffies + SOFTWARE_ERASE_TIMEOUT_SEC * HZ);
6897 + ier = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE);
6898 + ier &= ~SDHCI_INT_DATA_TIMEOUT;
6899 + writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE);
6900 + timeout_disabled = true;
6901 + udelay((ns_2clk+1000-1)/1000);
6902 + } else if (timeout_disabled) {
6903 + ier = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE);
6904 + ier |= SDHCI_INT_DATA_TIMEOUT;
6905 + writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE);
6906 + timeout_disabled = false;
6907 + udelay((ns_2clk+1000-1)/1000);
6908 + }
6909 +#endif
6910 + writel(val, host->ioaddr + reg);
6911 +#else
6912 + void __iomem * regaddr = host->ioaddr + reg;
6913 +
6914 + writel(val, regaddr);
6915 +
6916 + if (reg != SDHCI_BUFFER && reg != SDHCI_INT_STATUS && host->clock != 0)
6917 + {
6918 + int timeout = 100000;
6919 + while (val != readl(regaddr) && --timeout > 0)
6920 + continue;
6921 +
6922 + if (timeout <= 0)
6923 + printk(KERN_ERR "%s: writing 0x%X to reg 0x%X "
6924 + "always gives 0x%X\n",
6925 + mmc_hostname(host->mmc),
6926 + val, reg, readl(regaddr));
6927 + BUG_ON(timeout <= 0);
6928 + }
6929 +#endif
6930 +}
6931 +
6932 +
6933 +void sdhci_bcm2708_writel(struct sdhci_host *host, u32 val, int reg)
6934 +{
6935 +#ifdef LOG_REGISTERS
6936 + printk(KERN_ERR "%s: writel to 0x%02x, value 0x%08x\n",
6937 + mmc_hostname(host->mmc), reg, val);
6938 +#endif
6939 + check_dma_reg_use(host, reg);
6940 +
6941 + sdhci_bcm2708_raw_writel(host, val, reg);
6942 +}
6943 +
6944 +void sdhci_bcm2708_writew(struct sdhci_host *host, u16 val, int reg)
6945 +{
6946 + static u32 shadow = 0;
6947 +
6948 + u32 p = reg == SDHCI_COMMAND ? shadow :
6949 + sdhci_bcm2708_raw_readl(host, reg & ~3);
6950 + u32 s = reg << 3 & 0x18;
6951 + u32 l = val << s;
6952 + u32 m = 0xffff << s;
6953 +
6954 +#ifdef LOG_REGISTERS
6955 + printk(KERN_ERR "%s: writew to 0x%02x, value 0x%04x\n",
6956 + mmc_hostname(host->mmc), reg, val);
6957 +#endif
6958 +
6959 + if (reg == SDHCI_TRANSFER_MODE)
6960 + shadow = (p & ~m) | l;
6961 + else {
6962 + check_dma_reg_use(host, reg);
6963 + sdhci_bcm2708_raw_writel(host, (p & ~m) | l, reg & ~3);
6964 + }
6965 +}
6966 +
6967 +void sdhci_bcm2708_writeb(struct sdhci_host *host, u8 val, int reg)
6968 +{
6969 + u32 p = sdhci_bcm2708_raw_readl(host, reg & ~3);
6970 + u32 s = reg << 3 & 0x18;
6971 + u32 l = val << s;
6972 + u32 m = 0xff << s;
6973 +
6974 +#ifdef LOG_REGISTERS
6975 + printk(KERN_ERR "%s: writeb to 0x%02x, value 0x%02x\n",
6976 + mmc_hostname(host->mmc), reg, val);
6977 +#endif
6978 +
6979 + check_dma_reg_use(host, reg);
6980 + sdhci_bcm2708_raw_writel(host, (p & ~m) | l, reg & ~3);
6981 +}
6982 +
6983 +static unsigned int sdhci_bcm2708_get_max_clock(struct sdhci_host *host)
6984 +{
6985 + return 20000000; // this value is in Hz (20MHz)
6986 +}
6987 +
6988 +static unsigned int sdhci_bcm2708_get_timeout_clock(struct sdhci_host *host)
6989 +{
6990 + if(host->clock)
6991 + return (host->clock / 1000); // this value is in kHz (100MHz)
6992 + else
6993 + return (sdhci_bcm2708_get_max_clock(host) / 1000);
6994 +}
6995 +
6996 +static void sdhci_bcm2708_set_clock(struct sdhci_host *host, unsigned int clock)
6997 +{
6998 + int div = 0;
6999 + u16 clk = 0;
7000 + unsigned long timeout;
7001 +
7002 + if (clock == host->clock)
7003 + return;
7004 +
7005 + sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
7006 +
7007 + if (clock == 0)
7008 + goto out;
7009 +
7010 + if (BCM2708_EMMC_CLOCK_FREQ <= clock)
7011 + div = 1;
7012 + else {
7013 + for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
7014 + if ((BCM2708_EMMC_CLOCK_FREQ / div) <= clock)
7015 + break;
7016 + }
7017 + }
7018 +
7019 + DBG( "desired SD clock: %d, actual: %d\n",
7020 + clock, BCM2708_EMMC_CLOCK_FREQ / div);
7021 +
7022 + clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
7023 + clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
7024 + << SDHCI_DIVIDER_HI_SHIFT;
7025 + clk |= SDHCI_CLOCK_INT_EN;
7026 +
7027 + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
7028 +
7029 + timeout = 20;
7030 + while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7031 + & SDHCI_CLOCK_INT_STABLE)) {
7032 + if (timeout == 0) {
7033 + printk(KERN_ERR "%s: Internal clock never "
7034 + "stabilised.\n", mmc_hostname(host->mmc));
7035 + return;
7036 + }
7037 + timeout--;
7038 + mdelay(1);
7039 + }
7040 +
7041 + clk |= SDHCI_CLOCK_CARD_EN;
7042 + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
7043 +out:
7044 + host->clock = clock;
7045 + }
7046 +
7047 +/*****************************************************************************\
7048 + * *
7049 + * DMA Operation *
7050 + * *
7051 +\*****************************************************************************/
7052 +
7053 +struct sdhci_bcm2708_priv {
7054 + int dma_chan;
7055 + int dma_irq;
7056 + void __iomem *dma_chan_base;
7057 + struct bcm2708_dma_cb *cb_base; /* DMA control blocks */
7058 + dma_addr_t cb_handle;
7059 + /* tracking scatter gather progress */
7060 + unsigned sg_ix; /* scatter gather list index */
7061 + unsigned sg_done; /* bytes in current sg_ix done */
7062 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7063 + unsigned char dma_wanted; /* DMA transfer requested */
7064 + unsigned char dma_waits; /* wait states in DMAs */
7065 +#ifdef CHECK_DMA_USE
7066 + unsigned char dmas_pending; /* no of unfinished DMAs */
7067 + hptime_t when_started;
7068 + hptime_t when_reset;
7069 + hptime_t when_stopped;
7070 +#endif
7071 +#endif
7072 + /* signalling the end of a transfer */
7073 + void (*complete)(struct sdhci_host *);
7074 +};
7075 +
7076 +#define SDHCI_HOST_PRIV(host) \
7077 + (struct sdhci_bcm2708_priv *)((struct sdhci_host *)(host)+1)
7078 +
7079 +
7080 +
7081 +#ifdef CHECK_DMA_REG_USE
7082 +static void check_dma_reg_use(struct sdhci_host *host, int reg)
7083 +{
7084 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7085 + if (host_priv->dma_wanted && reg != SDHCI_INT_STATUS) {
7086 + printk(KERN_INFO"%s: accessing register 0x%x during DMA\n",
7087 + mmc_hostname(host->mmc), reg);
7088 + }
7089 +}
7090 +#endif
7091 +
7092 +
7093 +
7094 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7095 +
7096 +static void sdhci_clear_set_irqgen(struct sdhci_host *host, u32 clear, u32 set)
7097 +{
7098 + u32 ier;
7099 +
7100 + ier = sdhci_bcm2708_raw_readl(host, SDHCI_SIGNAL_ENABLE);
7101 + ier &= ~clear;
7102 + ier |= set;
7103 + /* change which requests generate IRQs - makes no difference to
7104 + the content of SDHCI_INT_STATUS, or the need to acknowledge IRQs */
7105 + sdhci_bcm2708_raw_writel(host, ier, SDHCI_SIGNAL_ENABLE);
7106 +}
7107 +
7108 +static void sdhci_signal_irqs(struct sdhci_host *host, u32 irqs)
7109 +{
7110 + sdhci_clear_set_irqgen(host, 0, irqs);
7111 +}
7112 +
7113 +static void sdhci_unsignal_irqs(struct sdhci_host *host, u32 irqs)
7114 +{
7115 + sdhci_clear_set_irqgen(host, irqs, 0);
7116 +}
7117 +
7118 +
7119 +
7120 +static void schci_bcm2708_cb_read(struct sdhci_bcm2708_priv *host,
7121 + int ix,
7122 + dma_addr_t dma_addr, unsigned len,
7123 + int /*bool*/ is_last)
7124 +{
7125 + struct bcm2708_dma_cb *cb = &host->cb_base[ix];
7126 + unsigned char dmawaits = host->dma_waits;
7127 +
7128 + cb->info = BCM2708_DMA_PER_MAP(BCM2708_DMA_DREQ_EMMC) |
7129 + BCM2708_DMA_WAITS(dmawaits) |
7130 + BCM2708_DMA_S_DREQ |
7131 + BCM2708_DMA_D_WIDTH |
7132 + BCM2708_DMA_D_INC;
7133 + cb->src = DMA_SDHCI_BUFFER; /* DATA register DMA address */
7134 + cb->dst = dma_addr;
7135 + cb->length = len;
7136 + cb->stride = 0;
7137 +
7138 + if (is_last) {
7139 + cb->info |= BCM2708_DMA_INT_EN |
7140 + BCM2708_DMA_WAIT_RESP;
7141 + cb->next = 0;
7142 + } else
7143 + cb->next = host->cb_handle +
7144 + (ix+1)*sizeof(struct bcm2708_dma_cb);
7145 +
7146 + cb->pad[0] = 0;
7147 + cb->pad[1] = 0;
7148 +}
7149 +
7150 +static void schci_bcm2708_cb_write(struct sdhci_bcm2708_priv *host,
7151 + int ix,
7152 + dma_addr_t dma_addr, unsigned len,
7153 + int /*bool*/ is_last)
7154 +{
7155 + struct bcm2708_dma_cb *cb = &host->cb_base[ix];
7156 + unsigned char dmawaits = host->dma_waits;
7157 +
7158 + /* We can make arbitrarily large writes as long as we specify DREQ to
7159 + pace the delivery of bytes to the Arasan hardware */
7160 + cb->info = BCM2708_DMA_PER_MAP(BCM2708_DMA_DREQ_EMMC) |
7161 + BCM2708_DMA_WAITS(dmawaits) |
7162 + BCM2708_DMA_D_DREQ |
7163 + BCM2708_DMA_S_WIDTH |
7164 + BCM2708_DMA_S_INC;
7165 + cb->src = dma_addr;
7166 + cb->dst = DMA_SDHCI_BUFFER; /* DATA register DMA address */
7167 + cb->length = len;
7168 + cb->stride = 0;
7169 +
7170 + if (is_last) {
7171 + cb->info |= BCM2708_DMA_INT_EN |
7172 + BCM2708_DMA_WAIT_RESP;
7173 + cb->next = 0;
7174 + } else
7175 + cb->next = host->cb_handle +
7176 + (ix+1)*sizeof(struct bcm2708_dma_cb);
7177 +
7178 + cb->pad[0] = 0;
7179 + cb->pad[1] = 0;
7180 +}
7181 +
7182 +
7183 +static void schci_bcm2708_dma_go(struct sdhci_host *host)
7184 +{
7185 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7186 + void __iomem *dma_chan_base = host_priv->dma_chan_base;
7187 +
7188 + BUG_ON(host_priv->dma_wanted);
7189 +#ifdef CHECK_DMA_USE
7190 + if (host_priv->dma_wanted)
7191 + printk(KERN_ERR "%s: DMA already in progress - "
7192 + "now %"FMT_HPT", last started %lu "
7193 + "reset %lu stopped %lu\n",
7194 + mmc_hostname(host->mmc),
7195 + hptime(), since_ns(host_priv->when_started),
7196 + since_ns(host_priv->when_reset),
7197 + since_ns(host_priv->when_stopped));
7198 + else if (host_priv->dmas_pending > 0)
7199 + printk(KERN_INFO "%s: note - new DMA when %d reset DMAs "
7200 + "already in progress - "
7201 + "now %"FMT_HPT", started %lu reset %lu stopped %lu\n",
7202 + mmc_hostname(host->mmc),
7203 + host_priv->dmas_pending,
7204 + hptime(), since_ns(host_priv->when_started),
7205 + since_ns(host_priv->when_reset),
7206 + since_ns(host_priv->when_stopped));
7207 + host_priv->dmas_pending += 1;
7208 + host_priv->when_started = hptime();
7209 +#endif
7210 + host_priv->dma_wanted = 1;
7211 + DBG("PDMA go - base %p handle %08X\n", dma_chan_base,
7212 + host_priv->cb_handle);
7213 + bcm_dma_start(dma_chan_base, host_priv->cb_handle);
7214 +}
7215 +
7216 +
7217 +static void
7218 +sdhci_platdma_read(struct sdhci_host *host, dma_addr_t dma_addr, size_t len)
7219 +{
7220 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7221 +
7222 + DBG("PDMA to read %d bytes\n", len);
7223 + host_priv->sg_done += len;
7224 + schci_bcm2708_cb_read(host_priv, 0, dma_addr, len, 1/*TRUE*/);
7225 + schci_bcm2708_dma_go(host);
7226 +}
7227 +
7228 +
7229 +static void
7230 +sdhci_platdma_write(struct sdhci_host *host, dma_addr_t dma_addr, size_t len)
7231 +{
7232 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7233 +
7234 + DBG("PDMA to write %d bytes\n", len);
7235 + //BUG_ON(0 != (len & 0x1ff));
7236 +
7237 + host_priv->sg_done += len;
7238 + schci_bcm2708_cb_write(host_priv, 0, dma_addr, len, 1/*TRUE*/);
7239 + schci_bcm2708_dma_go(host);
7240 +}
7241 +
7242 +/*! space is avaiable to receive into or data is available to write
7243 + Platform DMA exported function
7244 +*/
7245 +void
7246 +sdhci_bcm2708_platdma_avail(struct sdhci_host *host, unsigned int *ref_intmask,
7247 + void(*completion_callback)(struct sdhci_host *host))
7248 +{
7249 + struct mmc_data *data = host->data;
7250 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7251 + int sg_ix;
7252 + size_t bytes;
7253 + dma_addr_t addr;
7254 +
7255 + BUG_ON(NULL == data);
7256 + BUG_ON(0 == data->blksz);
7257 +
7258 + host_priv->complete = completion_callback;
7259 +
7260 + sg_ix = host_priv->sg_ix;
7261 + BUG_ON(sg_ix >= data->sg_len);
7262 +
7263 + /* we can DMA blocks larger than blksz - it may hang the DMA
7264 + channel but we are its only user */
7265 + bytes = sg_dma_len(&data->sg[sg_ix]) - host_priv->sg_done;
7266 + addr = sg_dma_address(&data->sg[sg_ix]) + host_priv->sg_done;
7267 +
7268 + if (bytes > 0) {
7269 + /* We're going to poll for read/write available state until
7270 + we finish this DMA
7271 + */
7272 +
7273 + if (data->flags & MMC_DATA_READ) {
7274 + if (*ref_intmask & SDHCI_INT_DATA_AVAIL) {
7275 + sdhci_unsignal_irqs(host, SDHCI_INT_DATA_AVAIL |
7276 + SDHCI_INT_SPACE_AVAIL);
7277 + sdhci_platdma_read(host, addr, bytes);
7278 + }
7279 + } else {
7280 + if (*ref_intmask & SDHCI_INT_SPACE_AVAIL) {
7281 + sdhci_unsignal_irqs(host, SDHCI_INT_DATA_AVAIL |
7282 + SDHCI_INT_SPACE_AVAIL);
7283 + sdhci_platdma_write(host, addr, bytes);
7284 + }
7285 + }
7286 + }
7287 + /* else:
7288 + we have run out of bytes that need transferring (e.g. we may be in
7289 + the middle of the last DMA transfer), or
7290 + it is also possible that we've been called when another IRQ is
7291 + signalled, even though we've turned off signalling of our own IRQ */
7292 +
7293 + *ref_intmask &= ~SDHCI_INT_DATA_END;
7294 + /* don't let the main sdhci driver act on this .. we'll deal with it
7295 + when we respond to the DMA - if one is currently in progress */
7296 +}
7297 +
7298 +/* is it possible to DMA the given mmc_data structure?
7299 + Platform DMA exported function
7300 +*/
7301 +int /*bool*/
7302 +sdhci_bcm2708_platdma_dmaable(struct sdhci_host *host, struct mmc_data *data)
7303 +{
7304 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7305 + int ok = bcm_sg_suitable_for_dma(data->sg, data->sg_len);
7306 +
7307 + if (!ok)
7308 + DBG("Reverting to PIO - bad cache alignment\n");
7309 +
7310 + else {
7311 + host_priv->sg_ix = 0; /* first SG index */
7312 + host_priv->sg_done = 0; /* no bytes done */
7313 + }
7314 +
7315 + return ok;
7316 +}
7317 +
7318 +#include <mach/arm_control.h> //GRAYG
7319 +/*! the current SD transacton has been abandonned
7320 + We need to tidy up if we were in the middle of a DMA
7321 + Platform DMA exported function
7322 +*/
7323 +void
7324 +sdhci_bcm2708_platdma_reset(struct sdhci_host *host, struct mmc_data *data)
7325 +{
7326 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7327 + unsigned long flags;
7328 +
7329 + BUG_ON(NULL == host);
7330 +
7331 + spin_lock_irqsave(&host->lock, flags);
7332 +
7333 + if (host_priv->dma_wanted) {
7334 + if (NULL == data) {
7335 + printk(KERN_ERR "%s: ongoing DMA reset - no data!\n",
7336 + mmc_hostname(host->mmc));
7337 + BUG_ON(NULL == data);
7338 + } else {
7339 + struct scatterlist *sg;
7340 + int sg_len;
7341 + int sg_todo;
7342 + int rc;
7343 + unsigned long cs;
7344 +
7345 + sg = data->sg;
7346 + sg_len = data->sg_len;
7347 + sg_todo = sg_dma_len(&sg[host_priv->sg_ix]);
7348 +
7349 + cs = readl(host_priv->dma_chan_base + BCM2708_DMA_CS);
7350 +
7351 + if (!(BCM2708_DMA_ACTIVE & cs))
7352 + printk(KERN_INFO "%s: missed completion of "
7353 + "cmd %d DMA (%d/%d [%d]/[%d]) - "
7354 + "ignoring it\n",
7355 + mmc_hostname(host->mmc),
7356 + host->last_cmdop,
7357 + host_priv->sg_done, sg_todo,
7358 + host_priv->sg_ix+1, sg_len);
7359 + else
7360 + printk(KERN_INFO "%s: resetting ongoing cmd %d"
7361 + "DMA before %d/%d [%d]/[%d] complete\n",
7362 + mmc_hostname(host->mmc),
7363 + host->last_cmdop,
7364 + host_priv->sg_done, sg_todo,
7365 + host_priv->sg_ix+1, sg_len);
7366 +#ifdef CHECK_DMA_USE
7367 + printk(KERN_INFO "%s: now %"FMT_HPT" started %lu "
7368 + "last reset %lu last stopped %lu\n",
7369 + mmc_hostname(host->mmc),
7370 + hptime(), since_ns(host_priv->when_started),
7371 + since_ns(host_priv->when_reset),
7372 + since_ns(host_priv->when_stopped));
7373 + { unsigned long info, debug;
7374 + void __iomem *base;
7375 + unsigned long pend0, pend1, pend2;
7376 +
7377 + base = host_priv->dma_chan_base;
7378 + cs = readl(base + BCM2708_DMA_CS);
7379 + info = readl(base + BCM2708_DMA_INFO);
7380 + debug = readl(base + BCM2708_DMA_DEBUG);
7381 + printk(KERN_INFO "%s: DMA%d CS=%08lX TI=%08lX "
7382 + "DEBUG=%08lX\n",
7383 + mmc_hostname(host->mmc),
7384 + host_priv->dma_chan,
7385 + cs, info, debug);
7386 + pend0 = readl(__io_address(ARM_IRQ_PEND0));
7387 + pend1 = readl(__io_address(ARM_IRQ_PEND1));
7388 + pend2 = readl(__io_address(ARM_IRQ_PEND2));
7389 +
7390 + printk(KERN_INFO "%s: PEND0=%08lX "
7391 + "PEND1=%08lX PEND2=%08lX\n",
7392 + mmc_hostname(host->mmc),
7393 + pend0, pend1, pend2);
7394 +
7395 + //gintsts = readl(__io_address(GINTSTS));
7396 + //gintmsk = readl(__io_address(GINTMSK));
7397 + //printk(KERN_INFO "%s: USB GINTSTS=%08lX"
7398 + // "GINTMSK=%08lX\n",
7399 + // mmc_hostname(host->mmc), gintsts, gintmsk);
7400 + }
7401 +#endif
7402 + rc = bcm_dma_abort(host_priv->dma_chan_base);
7403 + BUG_ON(rc != 0);
7404 + }
7405 + host_priv->dma_wanted = 0;
7406 +#ifdef CHECK_DMA_USE
7407 + host_priv->when_reset = hptime();
7408 +#endif
7409 + }
7410 +
7411 + spin_unlock_irqrestore(&host->lock, flags);
7412 +}
7413 +
7414 +
7415 +static void sdhci_bcm2708_dma_complete_irq(struct sdhci_host *host,
7416 + u32 dma_cs)
7417 +{
7418 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7419 + struct mmc_data *data;
7420 + struct scatterlist *sg;
7421 + int sg_len;
7422 + int sg_ix;
7423 + int sg_todo;
7424 + unsigned long flags;
7425 +
7426 + BUG_ON(NULL == host);
7427 +
7428 + spin_lock_irqsave(&host->lock, flags);
7429 + data = host->data;
7430 +
7431 +#ifdef CHECK_DMA_USE
7432 + if (host_priv->dmas_pending <= 0)
7433 + DBG("on completion no DMA in progress - "
7434 + "now %"FMT_HPT" started %lu reset %lu stopped %lu\n",
7435 + hptime(), since_ns(host_priv->when_started),
7436 + since_ns(host_priv->when_reset),
7437 + since_ns(host_priv->when_stopped));
7438 + else if (host_priv->dmas_pending > 1)
7439 + DBG("still %d DMA in progress after completion - "
7440 + "now %"FMT_HPT" started %lu reset %lu stopped %lu\n",
7441 + host_priv->dmas_pending - 1,
7442 + hptime(), since_ns(host_priv->when_started),
7443 + since_ns(host_priv->when_reset),
7444 + since_ns(host_priv->when_stopped));
7445 + BUG_ON(host_priv->dmas_pending <= 0);
7446 + host_priv->dmas_pending -= 1;
7447 + host_priv->when_stopped = hptime();
7448 +#endif
7449 + host_priv->dma_wanted = 0;
7450 +
7451 + if (NULL == data) {
7452 + DBG("PDMA unused completion - status 0x%X\n", dma_cs);
7453 + spin_unlock_irqrestore(&host->lock, flags);
7454 + return;
7455 + }
7456 + sg = data->sg;
7457 + sg_len = data->sg_len;
7458 + sg_todo = sg_dma_len(&sg[host_priv->sg_ix]);
7459 +
7460 + DBG("PDMA complete %d/%d [%d]/[%d]..\n",
7461 + host_priv->sg_done, sg_todo,
7462 + host_priv->sg_ix+1, sg_len);
7463 +
7464 + BUG_ON(host_priv->sg_done > sg_todo);
7465 +
7466 + if (host_priv->sg_done >= sg_todo) {
7467 + host_priv->sg_ix++;
7468 + host_priv->sg_done = 0;
7469 + }
7470 +
7471 + sg_ix = host_priv->sg_ix;
7472 + if (sg_ix < sg_len) {
7473 + u32 irq_mask;
7474 + /* Set off next DMA if we've got the capacity */
7475 +
7476 + if (data->flags & MMC_DATA_READ)
7477 + irq_mask = SDHCI_INT_DATA_AVAIL;
7478 + else
7479 + irq_mask = SDHCI_INT_SPACE_AVAIL;
7480 +
7481 + /* We have to use the interrupt status register on the BCM2708
7482 + rather than the SDHCI_PRESENT_STATE register because latency
7483 + in the glue logic means that the information retrieved from
7484 + the latter is not always up-to-date w.r.t the DMA engine -
7485 + it may not indicate that a read or a write is ready yet */
7486 + if (sdhci_bcm2708_raw_readl(host, SDHCI_INT_STATUS) &
7487 + irq_mask) {
7488 + size_t bytes = sg_dma_len(&sg[sg_ix]) -
7489 + host_priv->sg_done;
7490 + dma_addr_t addr = sg_dma_address(&data->sg[sg_ix]) +
7491 + host_priv->sg_done;
7492 +
7493 + /* acknowledge interrupt */
7494 + sdhci_bcm2708_raw_writel(host, irq_mask,
7495 + SDHCI_INT_STATUS);
7496 +
7497 + BUG_ON(0 == bytes);
7498 +
7499 + if (data->flags & MMC_DATA_READ)
7500 + sdhci_platdma_read(host, addr, bytes);
7501 + else
7502 + sdhci_platdma_write(host, addr, bytes);
7503 + } else {
7504 + DBG("PDMA - wait avail\n");
7505 + /* may generate an IRQ if already present */
7506 + sdhci_signal_irqs(host, SDHCI_INT_DATA_AVAIL |
7507 + SDHCI_INT_SPACE_AVAIL);
7508 + }
7509 + } else {
7510 +#ifdef USE_SYNC_AFTER_DMA
7511 + /* On the Arasan controller the stop command (which will be
7512 + scheduled after this completes) does not seem to work
7513 + properly if we allow it to be issued when we are
7514 + transferring data to/from the SD card.
7515 + We get CRC and DEND errors unless we wait for
7516 + the SD controller to finish reading/writing to the card. */
7517 + u32 state_mask;
7518 + int timeout=1000000;
7519 + hptime_t now = hptime();
7520 +
7521 + DBG("PDMA over - sync card\n");
7522 + if (data->flags & MMC_DATA_READ)
7523 + state_mask = SDHCI_DOING_READ;
7524 + else
7525 + state_mask = SDHCI_DOING_WRITE;
7526 +
7527 + while (0 != (sdhci_bcm2708_raw_readl(host,
7528 + SDHCI_PRESENT_STATE) &
7529 + state_mask) && --timeout > 0)
7530 + continue;
7531 +
7532 + if (1000000-timeout > 4000) /*ave. is about 3250*/
7533 + DBG("%s: note - long %s sync %luns - "
7534 + "%d its.\n",
7535 + mmc_hostname(host->mmc),
7536 + data->flags & MMC_DATA_READ? "read": "write",
7537 + since_ns(now), 1000000-timeout);
7538 + if (timeout <= 0)
7539 + printk(KERN_ERR"%s: final %s to SD card still "
7540 + "running\n",
7541 + mmc_hostname(host->mmc),
7542 + data->flags & MMC_DATA_READ? "read": "write");
7543 +#endif
7544 + if (host_priv->complete) {
7545 + (*host_priv->complete)(host);
7546 + DBG("PDMA %s complete\n",
7547 + data->flags & MMC_DATA_READ?"read":"write");
7548 + sdhci_signal_irqs(host, SDHCI_INT_DATA_AVAIL |
7549 + SDHCI_INT_SPACE_AVAIL);
7550 + }
7551 + }
7552 + spin_unlock_irqrestore(&host->lock, flags);
7553 +}
7554 +
7555 +static irqreturn_t sdhci_bcm2708_dma_irq(int irq, void *dev_id)
7556 +{
7557 + irqreturn_t result = IRQ_NONE;
7558 + struct sdhci_host *host = dev_id;
7559 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7560 + u32 dma_cs; /* control and status register */
7561 + unsigned long flags;
7562 +
7563 + BUG_ON(NULL == dev_id);
7564 + BUG_ON(NULL == host_priv->dma_chan_base);
7565 +
7566 + spin_lock_irqsave(&host->lock, flags);
7567 +
7568 + dma_cs = readl(host_priv->dma_chan_base + BCM2708_DMA_CS);
7569 +
7570 + if (dma_cs & BCM2708_DMA_ERR) {
7571 + unsigned long debug;
7572 + debug = readl(host_priv->dma_chan_base +
7573 + BCM2708_DMA_DEBUG);
7574 + printk(KERN_ERR "%s: DMA error - CS %lX DEBUG %lX\n",
7575 + mmc_hostname(host->mmc), (unsigned long)dma_cs,
7576 + (unsigned long)debug);
7577 + /* reset error */
7578 + writel(debug, host_priv->dma_chan_base +
7579 + BCM2708_DMA_DEBUG);
7580 + }
7581 + if (dma_cs & BCM2708_DMA_INT) {
7582 + /* acknowledge interrupt */
7583 + writel(BCM2708_DMA_INT,
7584 + host_priv->dma_chan_base + BCM2708_DMA_CS);
7585 +
7586 + dsb(); /* ARM data synchronization (push) operation */
7587 +
7588 + if (!host_priv->dma_wanted) {
7589 + /* ignore this interrupt - it was reset */
7590 + printk(KERN_INFO "%s: DMA IRQ %X ignored - "
7591 + "results were reset\n",
7592 + mmc_hostname(host->mmc), dma_cs);
7593 +#ifdef CHECK_DMA_USE
7594 + printk(KERN_INFO "%s: now %"FMT_HPT
7595 + " started %lu reset %lu stopped %lu\n",
7596 + mmc_hostname(host->mmc), hptime(),
7597 + since_ns(host_priv->when_started),
7598 + since_ns(host_priv->when_reset),
7599 + since_ns(host_priv->when_stopped));
7600 + host_priv->dmas_pending--;
7601 +#endif
7602 + } else
7603 + sdhci_bcm2708_dma_complete_irq(host, dma_cs);
7604 +
7605 + result = IRQ_HANDLED;
7606 + }
7607 +
7608 + spin_unlock_irqrestore(&host->lock, flags);
7609 +
7610 + return result;
7611 +}
7612 +#endif /* CONFIG_MMC_SDHCI_BCM2708_DMA */
7613 +
7614 +
7615 +/***************************************************************************** \
7616 + * *
7617 + * Device Attributes *
7618 + * *
7619 +\*****************************************************************************/
7620 +
7621 +
7622 +/**
7623 + * Show the DMA-using status
7624 + */
7625 +static ssize_t attr_dma_show(struct device *_dev,
7626 + struct device_attribute *attr, char *buf)
7627 +{
7628 + struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev);
7629 +
7630 + if (host) {
7631 + int use_dma = (host->flags & SDHCI_USE_PLATDMA? 1:0);
7632 + return sprintf(buf, "%d\n", use_dma);
7633 + } else
7634 + return -EINVAL;
7635 +}
7636 +
7637 +/**
7638 + * Set the DMA-using status
7639 + */
7640 +static ssize_t attr_dma_store(struct device *_dev,
7641 + struct device_attribute *attr,
7642 + const char *buf, size_t count)
7643 +{
7644 + struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev);
7645 +
7646 + if (host) {
7647 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7648 + int on = simple_strtol(buf, NULL, 0);
7649 + if (on) {
7650 + host->flags |= SDHCI_USE_PLATDMA;
7651 + printk(KERN_INFO "%s: DMA enabled\n",
7652 + mmc_hostname(host->mmc));
7653 + } else {
7654 + host->flags &= ~(SDHCI_USE_PLATDMA | SDHCI_REQ_USE_DMA);
7655 + printk(KERN_INFO "%s: DMA disabled\n",
7656 + mmc_hostname(host->mmc));
7657 + }
7658 +#endif
7659 + return count;
7660 + } else
7661 + return -EINVAL;
7662 +}
7663 +
7664 +static DEVICE_ATTR(use_dma, S_IRUGO | S_IWUGO, attr_dma_show, attr_dma_store);
7665 +
7666 +
7667 +/**
7668 + * Show the DMA wait states used
7669 + */
7670 +static ssize_t attr_dmawait_show(struct device *_dev,
7671 + struct device_attribute *attr, char *buf)
7672 +{
7673 + struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev);
7674 +
7675 + if (host) {
7676 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7677 + int dmawait = host_priv->dma_waits;
7678 + return sprintf(buf, "%d\n", dmawait);
7679 + } else
7680 + return -EINVAL;
7681 +}
7682 +
7683 +/**
7684 + * Set the DMA wait state used
7685 + */
7686 +static ssize_t attr_dmawait_store(struct device *_dev,
7687 + struct device_attribute *attr,
7688 + const char *buf, size_t count)
7689 +{
7690 + struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev);
7691 +
7692 + if (host) {
7693 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7694 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7695 + int dma_waits = simple_strtol(buf, NULL, 0);
7696 + if (dma_waits >= 0 && dma_waits < 32)
7697 + host_priv->dma_waits = dma_waits;
7698 + else
7699 + printk(KERN_ERR "%s: illegal dma_waits value - %d",
7700 + mmc_hostname(host->mmc), dma_waits);
7701 +#endif
7702 + return count;
7703 + } else
7704 + return -EINVAL;
7705 +}
7706 +
7707 +static DEVICE_ATTR(dma_wait, S_IRUGO | S_IWUGO,
7708 + attr_dmawait_show, attr_dmawait_store);
7709 +
7710 +
7711 +/**
7712 + * Show the DMA-using status
7713 + */
7714 +static ssize_t attr_status_show(struct device *_dev,
7715 + struct device_attribute *attr, char *buf)
7716 +{
7717 + struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev);
7718 +
7719 + if (host) {
7720 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7721 + return sprintf(buf,
7722 + "present: yes\n"
7723 + "power: %s\n"
7724 + "clock: %u Hz\n"
7725 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7726 + "dma: %s (%d waits)\n",
7727 +#else
7728 + "dma: unconfigured\n",
7729 +#endif
7730 + "always on",
7731 + host->clock
7732 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7733 + , (host->flags & SDHCI_USE_PLATDMA)? "on": "off"
7734 + , host_priv->dma_waits
7735 +#endif
7736 + );
7737 + } else
7738 + return -EINVAL;
7739 +}
7740 +
7741 +static DEVICE_ATTR(status, S_IRUGO, attr_status_show, NULL);
7742 +
7743 +/***************************************************************************** \
7744 + * *
7745 + * Power Management *
7746 + * *
7747 +\*****************************************************************************/
7748 +
7749 +
7750 +#ifdef CONFIG_PM
7751 +static int sdhci_bcm2708_suspend(struct platform_device *dev, pm_message_t state)
7752 +{
7753 + struct sdhci_host *host = (struct sdhci_host *)
7754 + platform_get_drvdata(dev);
7755 + int ret = 0;
7756 +
7757 + if (host->mmc) {
7758 + ret = mmc_suspend_host(host->mmc);
7759 + }
7760 +
7761 + return ret;
7762 +}
7763 +
7764 +static int sdhci_bcm2708_resume(struct platform_device *dev)
7765 +{
7766 + struct sdhci_host *host = (struct sdhci_host *)
7767 + platform_get_drvdata(dev);
7768 + int ret = 0;
7769 +
7770 + if (host->mmc) {
7771 + ret = mmc_resume_host(host->mmc);
7772 + }
7773 +
7774 + return ret;
7775 +}
7776 +#endif
7777 +
7778 +
7779 +/*****************************************************************************\
7780 + * *
7781 + * Device quirk functions. Implemented as local ops because the flags *
7782 + * field is out of space with newer kernels. This implementation can be *
7783 + * back ported to older kernels as well. *
7784 +\****************************************************************************/
7785 +static unsigned int sdhci_bcm2708_quirk_extra_ints(struct sdhci_host *host)
7786 +{
7787 + return 1;
7788 +}
7789 +
7790 +static unsigned int sdhci_bcm2708_quirk_spurious_crc(struct sdhci_host *host)
7791 +{
7792 + return 1;
7793 +}
7794 +
7795 +static unsigned int sdhci_bcm2708_quirk_voltage_broken(struct sdhci_host *host)
7796 +{
7797 + return 1;
7798 +}
7799 +
7800 +static unsigned int sdhci_bcm2708_uhs_broken(struct sdhci_host *host)
7801 +{
7802 + return 1;
7803 +}
7804 +
7805 +/***************************************************************************** \
7806 + * *
7807 + * Device ops *
7808 + * *
7809 +\*****************************************************************************/
7810 +
7811 +static struct sdhci_ops sdhci_bcm2708_ops = {
7812 +#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
7813 + .read_l = sdhci_bcm2708_readl,
7814 + .read_w = sdhci_bcm2708_readw,
7815 + .read_b = sdhci_bcm2708_readb,
7816 + .write_l = sdhci_bcm2708_writel,
7817 + .write_w = sdhci_bcm2708_writew,
7818 + .write_b = sdhci_bcm2708_writeb,
7819 +#else
7820 +#error The BCM2708 SDHCI driver needs CONFIG_MMC_SDHCI_IO_ACCESSORS to be set
7821 +#endif
7822 + //.enable_dma = NULL,
7823 + .set_clock = sdhci_bcm2708_set_clock,
7824 + .get_max_clock = sdhci_bcm2708_get_max_clock,
7825 + //.get_min_clock = NULL,
7826 + .get_timeout_clock = sdhci_bcm2708_get_timeout_clock,
7827 +
7828 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7829 + // Platform DMA operations
7830 + .pdma_able = sdhci_bcm2708_platdma_dmaable,
7831 + .pdma_avail = sdhci_bcm2708_platdma_avail,
7832 + .pdma_reset = sdhci_bcm2708_platdma_reset,
7833 +#endif
7834 + .extra_ints = sdhci_bcm2708_quirk_extra_ints,
7835 + .spurious_crc_acmd51 = sdhci_bcm2708_quirk_spurious_crc,
7836 + .voltage_broken = sdhci_bcm2708_quirk_voltage_broken,
7837 + .uhs_broken = sdhci_bcm2708_uhs_broken,
7838 +};
7839 +
7840 +/*****************************************************************************\
7841 + * *
7842 + * Device probing/removal *
7843 + * *
7844 +\*****************************************************************************/
7845 +
7846 +static int sdhci_bcm2708_probe(struct platform_device *pdev)
7847 +{
7848 + struct sdhci_host *host;
7849 + struct resource *iomem;
7850 + struct sdhci_bcm2708_priv *host_priv;
7851 + int ret;
7852 +
7853 + BUG_ON(pdev == NULL);
7854 +
7855 + iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7856 + if (!iomem) {
7857 + ret = -ENOMEM;
7858 + goto err;
7859 + }
7860 +
7861 + if (resource_size(iomem) != 0x100)
7862 + dev_err(&pdev->dev, "Invalid iomem size. You may "
7863 + "experience problems.\n");
7864 +
7865 + if (pdev->dev.parent)
7866 + host = sdhci_alloc_host(pdev->dev.parent,
7867 + sizeof(struct sdhci_bcm2708_priv));
7868 + else
7869 + host = sdhci_alloc_host(&pdev->dev,
7870 + sizeof(struct sdhci_bcm2708_priv));
7871 +
7872 + if (IS_ERR(host)) {
7873 + ret = PTR_ERR(host);
7874 + goto err;
7875 + }
7876 +
7877 + host->hw_name = "BCM2708_Arasan";
7878 + host->ops = &sdhci_bcm2708_ops;
7879 + host->irq = platform_get_irq(pdev, 0);
7880 +
7881 + host->quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
7882 + SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
7883 + SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
7884 + SDHCI_QUIRK_NONSTANDARD_CLOCK;
7885 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7886 + host->flags = SDHCI_USE_PLATDMA;
7887 +#endif
7888 +
7889 + if (!request_mem_region(iomem->start, resource_size(iomem),
7890 + mmc_hostname(host->mmc))) {
7891 + dev_err(&pdev->dev, "cannot request region\n");
7892 + ret = -EBUSY;
7893 + goto err_request;
7894 + }
7895 +
7896 + host->ioaddr = ioremap(iomem->start, resource_size(iomem));
7897 + if (!host->ioaddr) {
7898 + dev_err(&pdev->dev, "failed to remap registers\n");
7899 + ret = -ENOMEM;
7900 + goto err_remap;
7901 + }
7902 +
7903 + host_priv = SDHCI_HOST_PRIV(host);
7904 +
7905 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7906 + host_priv->dma_wanted = 0;
7907 +#ifdef CHECK_DMA_USE
7908 + host_priv->dmas_pending = 0;
7909 + host_priv->when_started = 0;
7910 + host_priv->when_reset = 0;
7911 + host_priv->when_stopped = 0;
7912 +#endif
7913 + host_priv->sg_ix = 0;
7914 + host_priv->sg_done = 0;
7915 + host_priv->complete = NULL;
7916 + host_priv->dma_waits = SDHCI_BCM_DMA_WAITS;
7917 +
7918 + host_priv->cb_base = dma_alloc_writecombine(&pdev->dev, SZ_4K,
7919 + &host_priv->cb_handle,
7920 + GFP_KERNEL);
7921 + if (!host_priv->cb_base) {
7922 + dev_err(&pdev->dev, "cannot allocate DMA CBs\n");
7923 + ret = -ENOMEM;
7924 + goto err_alloc_cb;
7925 + }
7926 +
7927 + ret = bcm_dma_chan_alloc(BCM_DMA_FEATURE_FAST,
7928 + &host_priv->dma_chan_base,
7929 + &host_priv->dma_irq);
7930 + if (ret < 0) {
7931 + dev_err(&pdev->dev, "couldn't allocate a DMA channel\n");
7932 + goto err_add_dma;
7933 + }
7934 + host_priv->dma_chan = ret;
7935 +
7936 + ret = request_irq(host_priv->dma_irq, sdhci_bcm2708_dma_irq,
7937 + IRQF_SHARED, DRIVER_NAME " (dma)", host);
7938 + if (ret) {
7939 + dev_err(&pdev->dev, "cannot set DMA IRQ\n");
7940 + goto err_add_dma_irq;
7941 + }
7942 + DBG("DMA CBs %p handle %08X DMA%d %p DMA IRQ %d\n",
7943 + host_priv->cb_base, (unsigned)host_priv->cb_handle,
7944 + host_priv->dma_chan, host_priv->dma_chan_base,
7945 + host_priv->dma_irq);
7946 +
7947 + host->mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
7948 +#endif
7949 +
7950 + ret = sdhci_add_host(host);
7951 + if (ret)
7952 + goto err_add_host;
7953 +
7954 + platform_set_drvdata(pdev, host);
7955 + ret = device_create_file(&pdev->dev, &dev_attr_use_dma);
7956 + ret = device_create_file(&pdev->dev, &dev_attr_dma_wait);
7957 + ret = device_create_file(&pdev->dev, &dev_attr_status);
7958 +
7959 + printk(KERN_INFO "%s: BCM2708 SDHC host at 0x%08llx DMA %d IRQ %d\n",
7960 + mmc_hostname(host->mmc), (unsigned long long)iomem->start,
7961 + host_priv->dma_chan, host_priv->dma_irq);
7962 +
7963 + return 0;
7964 +
7965 +err_add_host:
7966 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7967 + free_irq(host_priv->dma_irq, host);
7968 +err_add_dma_irq:
7969 + bcm_dma_chan_free(host_priv->dma_chan);
7970 +err_add_dma:
7971 + dma_free_writecombine(&pdev->dev, SZ_4K, host_priv->cb_base,
7972 + host_priv->cb_handle);
7973 +err_alloc_cb:
7974 +#endif
7975 + iounmap(host->ioaddr);
7976 +err_remap:
7977 + release_mem_region(iomem->start, resource_size(iomem));
7978 +err_request:
7979 + sdhci_free_host(host);
7980 +err:
7981 + dev_err(&pdev->dev, "probe failed, err %d\n", ret);
7982 + return ret;
7983 +}
7984 +
7985 +static int sdhci_bcm2708_remove(struct platform_device *pdev)
7986 +{
7987 + struct sdhci_host *host = platform_get_drvdata(pdev);
7988 + struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7989 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7990 + int dead;
7991 + u32 scratch;
7992 +
7993 + dead = 0;
7994 + scratch = sdhci_bcm2708_readl(host, SDHCI_INT_STATUS);
7995 + if (scratch == (u32)-1)
7996 + dead = 1;
7997 +
7998 + device_remove_file(&pdev->dev, &dev_attr_status);
7999 + device_remove_file(&pdev->dev, &dev_attr_dma_wait);
8000 + device_remove_file(&pdev->dev, &dev_attr_use_dma);
8001 +
8002 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
8003 + free_irq(host_priv->dma_irq, host);
8004 + dma_free_writecombine(&pdev->dev, SZ_4K, host_priv->cb_base,
8005 + host_priv->cb_handle);
8006 +#endif
8007 + sdhci_remove_host(host, dead);
8008 + iounmap(host->ioaddr);
8009 + release_mem_region(iomem->start, resource_size(iomem));
8010 + sdhci_free_host(host);
8011 + platform_set_drvdata(pdev, NULL);
8012 +
8013 + return 0;
8014 +}
8015 +
8016 +static struct platform_driver sdhci_bcm2708_driver = {
8017 + .driver = {
8018 + .name = DRIVER_NAME,
8019 + .owner = THIS_MODULE,
8020 + },
8021 + .probe = sdhci_bcm2708_probe,
8022 + .remove = sdhci_bcm2708_remove,
8023 +
8024 +#ifdef CONFIG_PM
8025 + .suspend = sdhci_bcm2708_suspend,
8026 + .resume = sdhci_bcm2708_resume,
8027 +#endif
8028 +
8029 +};
8030 +
8031 +/*****************************************************************************\
8032 + * *
8033 + * Driver init/exit *
8034 + * *
8035 +\*****************************************************************************/
8036 +
8037 +static int __init sdhci_drv_init(void)
8038 +{
8039 + return platform_driver_register(&sdhci_bcm2708_driver);
8040 +}
8041 +
8042 +static void __exit sdhci_drv_exit(void)
8043 +{
8044 + platform_driver_unregister(&sdhci_bcm2708_driver);
8045 +}
8046 +
8047 +module_init(sdhci_drv_init);
8048 +module_exit(sdhci_drv_exit);
8049 +
8050 +MODULE_DESCRIPTION("Secure Digital Host Controller Interface platform driver");
8051 +MODULE_AUTHOR("Broadcom <info@broadcom.com>");
8052 +MODULE_LICENSE("GPL v2");
8053 +MODULE_ALIAS("platform:"DRIVER_NAME);
8054 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
8055 index 9ddef47..b78afa2 100644
8056 --- a/drivers/mmc/host/sdhci.c
8057 +++ b/drivers/mmc/host/sdhci.c
8058 @@ -28,6 +28,7 @@
8059 #include <linux/mmc/mmc.h>
8060 #include <linux/mmc/host.h>
8061 #include <linux/mmc/card.h>
8062 +#include <linux/mmc/sd.h>
8063 #include <linux/mmc/slot-gpio.h>
8064
8065 #include "sdhci.h"
8066 @@ -326,7 +327,7 @@ static void sdhci_read_block_pio(struct sdhci_host *host)
8067 u32 uninitialized_var(scratch);
8068 u8 *buf;
8069
8070 - DBG("PIO reading\n");
8071 + DBG("PIO reading %db\n", host->data->blksz);
8072
8073 blksize = host->data->blksz;
8074 chunk = 0;
8075 @@ -371,7 +372,7 @@ static void sdhci_write_block_pio(struct sdhci_host *host)
8076 u32 scratch;
8077 u8 *buf;
8078
8079 - DBG("PIO writing\n");
8080 + DBG("PIO writing %db\n", host->data->blksz);
8081
8082 blksize = host->data->blksz;
8083 chunk = 0;
8084 @@ -410,19 +411,28 @@ static void sdhci_write_block_pio(struct sdhci_host *host)
8085 local_irq_restore(flags);
8086 }
8087
8088 -static void sdhci_transfer_pio(struct sdhci_host *host)
8089 +static void sdhci_transfer_pio(struct sdhci_host *host, u32 intstate)
8090 {
8091 u32 mask;
8092 + u32 state = 0;
8093 + u32 intmask;
8094 + int available;
8095
8096 BUG_ON(!host->data);
8097
8098 if (host->blocks == 0)
8099 return;
8100
8101 - if (host->data->flags & MMC_DATA_READ)
8102 + if (host->data->flags & MMC_DATA_READ) {
8103 mask = SDHCI_DATA_AVAILABLE;
8104 - else
8105 + intmask = SDHCI_INT_DATA_AVAIL;
8106 + } else {
8107 mask = SDHCI_SPACE_AVAILABLE;
8108 + intmask = SDHCI_INT_SPACE_AVAIL;
8109 + }
8110 +
8111 + /* initially we can see whether we can procede using intstate */
8112 + available = (intstate & intmask);
8113
8114 /*
8115 * Some controllers (JMicron JMB38x) mess up the buffer bits
8116 @@ -433,7 +443,7 @@ static void sdhci_transfer_pio(struct sdhci_host *host)
8117 (host->data->blocks == 1))
8118 mask = ~0;
8119
8120 - while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
8121 + while (available) {
8122 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
8123 udelay(100);
8124
8125 @@ -445,9 +455,11 @@ static void sdhci_transfer_pio(struct sdhci_host *host)
8126 host->blocks--;
8127 if (host->blocks == 0)
8128 break;
8129 + state = sdhci_readl(host, SDHCI_PRESENT_STATE);
8130 + available = state & mask;
8131 }
8132
8133 - DBG("PIO transfer complete.\n");
8134 + DBG("PIO transfer complete - %d blocks left.\n", host->blocks);
8135 }
8136
8137 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
8138 @@ -720,7 +732,9 @@ static void sdhci_set_transfer_irqs(struct sdhci_host *host)
8139 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
8140 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
8141
8142 - if (host->flags & SDHCI_REQ_USE_DMA)
8143 + /* platform DMA will begin on receipt of PIO irqs */
8144 + if ((host->flags & SDHCI_REQ_USE_DMA) &&
8145 + !(host->flags & SDHCI_USE_PLATDMA))
8146 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
8147 else
8148 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
8149 @@ -752,44 +766,25 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
8150 host->data_early = 0;
8151 host->data->bytes_xfered = 0;
8152
8153 - if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
8154 + if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA | SDHCI_USE_PLATDMA))
8155 host->flags |= SDHCI_REQ_USE_DMA;
8156
8157 /*
8158 * FIXME: This doesn't account for merging when mapping the
8159 * scatterlist.
8160 */
8161 - if (host->flags & SDHCI_REQ_USE_DMA) {
8162 - int broken, i;
8163 - struct scatterlist *sg;
8164 -
8165 - broken = 0;
8166 - if (host->flags & SDHCI_USE_ADMA) {
8167 - if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
8168 - broken = 1;
8169 - } else {
8170 - if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
8171 - broken = 1;
8172 - }
8173 -
8174 - if (unlikely(broken)) {
8175 - for_each_sg(data->sg, sg, data->sg_len, i) {
8176 - if (sg->length & 0x3) {
8177 - DBG("Reverting to PIO because of "
8178 - "transfer size (%d)\n",
8179 - sg->length);
8180 - host->flags &= ~SDHCI_REQ_USE_DMA;
8181 - break;
8182 - }
8183 - }
8184 - }
8185 - }
8186
8187 /*
8188 * The assumption here being that alignment is the same after
8189 * translation to device address space.
8190 */
8191 - if (host->flags & SDHCI_REQ_USE_DMA) {
8192 + if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_PLATDMA)) ==
8193 + (SDHCI_REQ_USE_DMA | SDHCI_USE_PLATDMA)) {
8194 +
8195 + if (! sdhci_platdma_dmaable(host, data))
8196 + host->flags &= ~SDHCI_REQ_USE_DMA;
8197 +
8198 + } else if (host->flags & SDHCI_REQ_USE_DMA) {
8199 int broken, i;
8200 struct scatterlist *sg;
8201
8202 @@ -848,7 +843,8 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
8203 */
8204 WARN_ON(1);
8205 host->flags &= ~SDHCI_REQ_USE_DMA;
8206 - } else {
8207 + } else
8208 + if (!(host->flags & SDHCI_USE_PLATDMA)) {
8209 WARN_ON(sg_cnt != 1);
8210 sdhci_writel(host, sg_dma_address(data->sg),
8211 SDHCI_DMA_ADDRESS);
8212 @@ -864,11 +860,13 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
8213 if (host->version >= SDHCI_SPEC_200) {
8214 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
8215 ctrl &= ~SDHCI_CTRL_DMA_MASK;
8216 + if (! (host->flags & SDHCI_USE_PLATDMA)) {
8217 if ((host->flags & SDHCI_REQ_USE_DMA) &&
8218 (host->flags & SDHCI_USE_ADMA))
8219 ctrl |= SDHCI_CTRL_ADMA32;
8220 else
8221 ctrl |= SDHCI_CTRL_SDMA;
8222 + }
8223 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
8224 }
8225
8226 @@ -925,7 +923,8 @@ static void sdhci_set_transfer_mode(struct sdhci_host *host,
8227
8228 if (data->flags & MMC_DATA_READ)
8229 mode |= SDHCI_TRNS_READ;
8230 - if (host->flags & SDHCI_REQ_USE_DMA)
8231 + if ((host->flags & SDHCI_REQ_USE_DMA) &&
8232 + !(host->flags & SDHCI_USE_PLATDMA))
8233 mode |= SDHCI_TRNS_DMA;
8234
8235 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
8236 @@ -941,13 +940,16 @@ static void sdhci_finish_data(struct sdhci_host *host)
8237 host->data = NULL;
8238
8239 if (host->flags & SDHCI_REQ_USE_DMA) {
8240 - if (host->flags & SDHCI_USE_ADMA)
8241 - sdhci_adma_table_post(host, data);
8242 - else {
8243 + /* we may have to abandon an ongoing platform DMA */
8244 + if (host->flags & SDHCI_USE_PLATDMA)
8245 + sdhci_platdma_reset(host, data);
8246 +
8247 + if (host->flags & (SDHCI_USE_PLATDMA | SDHCI_USE_SDMA)) {
8248 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
8249 data->sg_len, (data->flags & MMC_DATA_READ) ?
8250 DMA_FROM_DEVICE : DMA_TO_DEVICE);
8251 - }
8252 + } else if (host->flags & SDHCI_USE_ADMA)
8253 + sdhci_adma_table_post(host, data);
8254 }
8255
8256 /*
8257 @@ -1000,6 +1002,12 @@ void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
8258 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
8259 mask |= SDHCI_DATA_INHIBIT;
8260
8261 + if(host->ops->missing_status && (cmd->opcode == MMC_SEND_STATUS)) {
8262 + timeout = 5000; // Really obscenely large delay to send the status, due to bug in controller
8263 + // which might cause the STATUS command to get stuck when a data operation is in flow
8264 + mask |= SDHCI_DATA_INHIBIT;
8265 + }
8266 +
8267 /* We shouldn't wait for data inihibit for stop commands, even
8268 though they might use busy signaling */
8269 if (host->mrq->data && (cmd == host->mrq->data->stop))
8270 @@ -1017,6 +1025,8 @@ void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
8271 timeout--;
8272 mdelay(1);
8273 }
8274 + DBG("send cmd %d - wait 0x%X irq 0x%x\n", cmd->opcode, mask,
8275 + sdhci_readl(host, SDHCI_INT_STATUS));
8276
8277 timeout = jiffies;
8278 if (!cmd->data && cmd->cmd_timeout_ms > 9000)
8279 @@ -1026,6 +1036,10 @@ void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
8280 mod_timer(&host->timer, timeout);
8281
8282 host->cmd = cmd;
8283 + if (host->last_cmdop == MMC_APP_CMD)
8284 + host->last_cmdop = -cmd->opcode;
8285 + else
8286 + host->last_cmdop = cmd->opcode;
8287
8288 sdhci_prepare_data(host, cmd);
8289
8290 @@ -1505,7 +1519,7 @@ static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
8291 else
8292 ctrl &= ~SDHCI_CTRL_HISPD;
8293
8294 - if (host->version >= SDHCI_SPEC_300) {
8295 + if (host->version >= SDHCI_SPEC_300 && !(host->ops->uhs_broken)) {
8296 u16 clk, ctrl_2;
8297
8298 /* In case of UHS-I modes, set High Speed Enable */
8299 @@ -2204,7 +2218,7 @@ static void sdhci_timeout_timer(unsigned long data)
8300
8301 if (host->mrq) {
8302 pr_err("%s: Timeout waiting for hardware "
8303 - "interrupt.\n", mmc_hostname(host->mmc));
8304 + "interrupt - cmd%d.\n", mmc_hostname(host->mmc), host->last_cmdop);
8305 sdhci_dumpregs(host);
8306
8307 if (host->data) {
8308 @@ -2249,10 +2263,13 @@ static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
8309 BUG_ON(intmask == 0);
8310
8311 if (!host->cmd) {
8312 + if (!(host->ops->extra_ints)) {
8313 pr_err("%s: Got command interrupt 0x%08x even "
8314 "though no command operation was in progress.\n",
8315 mmc_hostname(host->mmc), (unsigned)intmask);
8316 sdhci_dumpregs(host);
8317 + } else
8318 + DBG("cmd irq 0x%08x cmd complete\n", (unsigned)intmask);
8319 return;
8320 }
8321
8322 @@ -2322,6 +2339,19 @@ static void sdhci_show_adma_error(struct sdhci_host *host)
8323 static void sdhci_show_adma_error(struct sdhci_host *host) { }
8324 #endif
8325
8326 +static void sdhci_data_end(struct sdhci_host *host)
8327 +{
8328 + if (host->cmd) {
8329 + /*
8330 + * Data managed to finish before the
8331 + * command completed. Make sure we do
8332 + * things in the proper order.
8333 + */
8334 + host->data_early = 1;
8335 + } else
8336 + sdhci_finish_data(host);
8337 +}
8338 +
8339 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
8340 {
8341 u32 command;
8342 @@ -2351,23 +2381,39 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
8343 }
8344 }
8345
8346 + if (!(host->ops->extra_ints)) {
8347 pr_err("%s: Got data interrupt 0x%08x even "
8348 "though no data operation was in progress.\n",
8349 mmc_hostname(host->mmc), (unsigned)intmask);
8350 sdhci_dumpregs(host);
8351 + } else
8352 + DBG("data irq 0x%08x but no data\n", (unsigned)intmask);
8353
8354 return;
8355 }
8356
8357 if (intmask & SDHCI_INT_DATA_TIMEOUT)
8358 host->data->error = -ETIMEDOUT;
8359 - else if (intmask & SDHCI_INT_DATA_END_BIT)
8360 + else if (intmask & SDHCI_INT_DATA_END_BIT) {
8361 + DBG("end error in cmd %d\n", host->last_cmdop);
8362 + if (host->ops->spurious_crc_acmd51 &&
8363 + host->last_cmdop == -SD_APP_SEND_SCR) {
8364 + DBG("ignoring spurious data_end_bit error\n");
8365 + intmask = SDHCI_INT_DATA_AVAIL|SDHCI_INT_DATA_END;
8366 + } else
8367 host->data->error = -EILSEQ;
8368 - else if ((intmask & SDHCI_INT_DATA_CRC) &&
8369 + } else if ((intmask & SDHCI_INT_DATA_CRC) &&
8370 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
8371 - != MMC_BUS_TEST_R)
8372 + != MMC_BUS_TEST_R) {
8373 + DBG("crc error in cmd %d\n", host->last_cmdop);
8374 + if (host->ops->spurious_crc_acmd51 &&
8375 + host->last_cmdop == -SD_APP_SEND_SCR) {
8376 + DBG("ignoring spurious data_crc_bit error\n");
8377 + intmask = SDHCI_INT_DATA_AVAIL|SDHCI_INT_DATA_END;
8378 + } else {
8379 host->data->error = -EILSEQ;
8380 - else if (intmask & SDHCI_INT_ADMA_ERROR) {
8381 + }
8382 + } else if (intmask & SDHCI_INT_ADMA_ERROR) {
8383 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
8384 sdhci_show_adma_error(host);
8385 host->data->error = -EIO;
8386 @@ -2375,11 +2421,18 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
8387 host->ops->adma_workaround(host, intmask);
8388 }
8389
8390 - if (host->data->error)
8391 + if (host->data->error) {
8392 + DBG("finish request early on error %d\n", host->data->error);
8393 sdhci_finish_data(host);
8394 - else {
8395 - if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
8396 - sdhci_transfer_pio(host);
8397 + } else {
8398 + if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) {
8399 + if (host->flags & SDHCI_REQ_USE_DMA) {
8400 + /* possible only in PLATDMA mode */
8401 + sdhci_platdma_avail(host, &intmask,
8402 + &sdhci_data_end);
8403 + } else
8404 + sdhci_transfer_pio(host, intmask);
8405 + }
8406
8407 /*
8408 * We currently don't do anything fancy with DMA
8409 @@ -2408,18 +2461,8 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
8410 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
8411 }
8412
8413 - if (intmask & SDHCI_INT_DATA_END) {
8414 - if (host->cmd) {
8415 - /*
8416 - * Data managed to finish before the
8417 - * command completed. Make sure we do
8418 - * things in the proper order.
8419 - */
8420 - host->data_early = 1;
8421 - } else {
8422 - sdhci_finish_data(host);
8423 - }
8424 - }
8425 + if (intmask & SDHCI_INT_DATA_END)
8426 + sdhci_data_end(host);
8427 }
8428 }
8429
8430 @@ -2475,6 +2518,22 @@ again:
8431 tasklet_schedule(&host->card_tasklet);
8432 }
8433
8434 + if (intmask & SDHCI_INT_ERROR_MASK & ~SDHCI_INT_ERROR)
8435 + DBG("controller reports error 0x%x -"
8436 + "%s%s%s%s%s%s%s%s%s%s",
8437 + intmask,
8438 + intmask & SDHCI_INT_TIMEOUT? " timeout": "",
8439 + intmask & SDHCI_INT_CRC ? " crc": "",
8440 + intmask & SDHCI_INT_END_BIT? " endbit": "",
8441 + intmask & SDHCI_INT_INDEX? " index": "",
8442 + intmask & SDHCI_INT_DATA_TIMEOUT? " data_timeout": "",
8443 + intmask & SDHCI_INT_DATA_CRC? " data_crc": "",
8444 + intmask & SDHCI_INT_DATA_END_BIT? " data_endbit": "",
8445 + intmask & SDHCI_INT_BUS_POWER? " buspower": "",
8446 + intmask & SDHCI_INT_ACMD12ERR? " acmd12": "",
8447 + intmask & SDHCI_INT_ADMA_ERROR? " adma": ""
8448 + );
8449 +
8450 if (intmask & SDHCI_INT_CMD_MASK) {
8451 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
8452 SDHCI_INT_STATUS);
8453 @@ -2489,7 +2548,13 @@ again:
8454
8455 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
8456
8457 - intmask &= ~SDHCI_INT_ERROR;
8458 + if (intmask & SDHCI_INT_ERROR_MASK) {
8459 + /* collect any uncovered errors */
8460 + sdhci_writel(host, intmask & SDHCI_INT_ERROR_MASK,
8461 + SDHCI_INT_STATUS);
8462 + }
8463 +
8464 + intmask &= ~SDHCI_INT_ERROR_MASK;
8465
8466 if (intmask & SDHCI_INT_BUS_POWER) {
8467 pr_err("%s: Card is consuming too much power!\n",
8468 @@ -2602,7 +2667,8 @@ int sdhci_resume_host(struct sdhci_host *host)
8469 {
8470 int ret = 0;
8471
8472 - if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
8473 + if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA |
8474 + SDHCI_USE_PLATDMA)) {
8475 if (host->ops->enable_dma)
8476 host->ops->enable_dma(host);
8477 }
8478 @@ -2833,14 +2899,16 @@ int sdhci_add_host(struct sdhci_host *host)
8479 host->flags &= ~SDHCI_USE_ADMA;
8480 }
8481
8482 - if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
8483 + if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA |
8484 + SDHCI_USE_PLATDMA)) {
8485 if (host->ops->enable_dma) {
8486 if (host->ops->enable_dma(host)) {
8487 pr_warning("%s: No suitable DMA "
8488 "available. Falling back to PIO.\n",
8489 mmc_hostname(mmc));
8490 host->flags &=
8491 - ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
8492 + ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA |
8493 + SDHCI_USE_PLATDMA);
8494 }
8495 }
8496 }
8497 @@ -3266,6 +3334,7 @@ int sdhci_add_host(struct sdhci_host *host)
8498
8499 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
8500 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
8501 + (host->flags & SDHCI_USE_PLATDMA) ? "platform's DMA" :
8502 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
8503 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
8504
8505 diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
8506 index 0a3ed01..6857875 100644
8507 --- a/drivers/mmc/host/sdhci.h
8508 +++ b/drivers/mmc/host/sdhci.h
8509 @@ -290,6 +290,20 @@ struct sdhci_ops {
8510 void (*platform_reset_exit)(struct sdhci_host *host, u8 mask);
8511 int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode);
8512 int (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
8513 +
8514 + int (*pdma_able)(struct sdhci_host *host,
8515 + struct mmc_data *data);
8516 + void (*pdma_avail)(struct sdhci_host *host,
8517 + unsigned int *ref_intmask,
8518 + void(*complete)(struct sdhci_host *));
8519 + void (*pdma_reset)(struct sdhci_host *host,
8520 + struct mmc_data *data);
8521 + unsigned int (*extra_ints)(struct sdhci_host *host);
8522 + unsigned int (*spurious_crc_acmd51)(struct sdhci_host *host);
8523 + unsigned int (*voltage_broken)(struct sdhci_host *host);
8524 + unsigned int (*uhs_broken)(struct sdhci_host *host);
8525 + unsigned int (*missing_status)(struct sdhci_host *host);
8526 +
8527 void (*hw_reset)(struct sdhci_host *host);
8528 void (*platform_suspend)(struct sdhci_host *host);
8529 void (*platform_resume)(struct sdhci_host *host);
8530 @@ -403,6 +417,29 @@ extern int sdhci_resume_host(struct sdhci_host *host);
8531 extern void sdhci_enable_irq_wakeups(struct sdhci_host *host);
8532 #endif
8533
8534 +static inline int /*bool*/
8535 +sdhci_platdma_dmaable(struct sdhci_host *host, struct mmc_data *data)
8536 +{
8537 + if (host->ops->pdma_able)
8538 + return host->ops->pdma_able(host, data);
8539 + else
8540 + return 1;
8541 +}
8542 +static inline void
8543 +sdhci_platdma_avail(struct sdhci_host *host, unsigned int *ref_intmask,
8544 + void(*completion_callback)(struct sdhci_host *))
8545 +{
8546 + if (host->ops->pdma_avail)
8547 + host->ops->pdma_avail(host, ref_intmask, completion_callback);
8548 +}
8549 +
8550 +static inline void
8551 +sdhci_platdma_reset(struct sdhci_host *host, struct mmc_data *data)
8552 +{
8553 + if (host->ops->pdma_reset)
8554 + host->ops->pdma_reset(host, data);
8555 +}
8556 +
8557 #ifdef CONFIG_PM_RUNTIME
8558 extern int sdhci_runtime_suspend_host(struct sdhci_host *host);
8559 extern int sdhci_runtime_resume_host(struct sdhci_host *host);
8560 diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
8561 index b569011..76fa055 100644
8562 --- a/drivers/tty/serial/amba-pl011.c
8563 +++ b/drivers/tty/serial/amba-pl011.c
8564 @@ -84,7 +84,7 @@ struct vendor_data {
8565
8566 static unsigned int get_fifosize_arm(struct amba_device *dev)
8567 {
8568 - return amba_rev(dev) < 3 ? 16 : 32;
8569 + return 16; //TODO: fix: amba_rev(dev) < 3 ? 16 : 32;
8570 }
8571
8572 static struct vendor_data vendor_arm = {
8573 diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
8574 index 362927c4..e23fffb 100644
8575 --- a/include/linux/mmc/sdhci.h
8576 +++ b/include/linux/mmc/sdhci.h
8577 @@ -133,6 +133,7 @@ struct sdhci_host {
8578 #define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */
8579 #define SDHCI_SDR104_NEEDS_TUNING (1<<10) /* SDR104/HS200 needs tuning */
8580 #define SDHCI_USING_RETUNING_TIMER (1<<11) /* Host is using a retuning timer for the card */
8581 +#define SDHCI_USE_PLATDMA (1<<12) /* Host uses 3rd party DMA */
8582
8583 unsigned int version; /* SDHCI spec. version */
8584
8585 @@ -148,6 +149,7 @@ struct sdhci_host {
8586
8587 struct mmc_request *mrq; /* Current request */
8588 struct mmc_command *cmd; /* Current command */
8589 + int last_cmdop; /* Opcode of last cmd sent */
8590 struct mmc_data *data; /* Current data request */
8591 unsigned int data_early:1; /* Data finished before cmd */
8592
8593 --
8594 1.9.1
8595
OpenWrt Source Repository