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kernel: refresh patches
[openwrt/openwrt.git] / target / linux / brcm2708 / patches-3.14 / 0001-Main-bcm2708-linux-port.patch
1 From fa45905bb2c22c8a349d30f00d9daa301fb1f2ab Mon Sep 17 00:00:00 2001
2 From: popcornmix <popcornmix@gmail.com>
3 Date: Sun, 12 May 2013 12:24:19 +0100
4 Subject: [PATCH 01/54] Main bcm2708 linux port
5
6 Signed-off-by: popcornmix <popcornmix@gmail.com>
7 ---
8 arch/arm/Kconfig | 17 +
9 arch/arm/Kconfig.debug | 8 +
10 arch/arm/Makefile | 1 +
11 arch/arm/configs/bcmrpi_cutdown_defconfig | 474 +++++++
12 arch/arm/configs/bcmrpi_defconfig | 510 ++++++++
13 arch/arm/configs/bcmrpi_emergency_defconfig | 532 ++++++++
14 arch/arm/kernel/process.c | 10 +
15 arch/arm/mach-bcm2708/Kconfig | 34 +
16 arch/arm/mach-bcm2708/Makefile | 7 +
17 arch/arm/mach-bcm2708/Makefile.boot | 3 +
18 arch/arm/mach-bcm2708/armctrl.c | 208 ++++
19 arch/arm/mach-bcm2708/armctrl.h | 27 +
20 arch/arm/mach-bcm2708/bcm2708.c | 720 +++++++++++
21 arch/arm/mach-bcm2708/bcm2708.h | 49 +
22 arch/arm/mach-bcm2708/bcm2708_gpio.c | 361 ++++++
23 arch/arm/mach-bcm2708/clock.c | 61 +
24 arch/arm/mach-bcm2708/clock.h | 24 +
25 arch/arm/mach-bcm2708/dma.c | 399 ++++++
26 arch/arm/mach-bcm2708/include/mach/arm_control.h | 419 +++++++
27 arch/arm/mach-bcm2708/include/mach/arm_power.h | 60 +
28 arch/arm/mach-bcm2708/include/mach/clkdev.h | 7 +
29 arch/arm/mach-bcm2708/include/mach/debug-macro.S | 22 +
30 arch/arm/mach-bcm2708/include/mach/dma.h | 86 ++
31 arch/arm/mach-bcm2708/include/mach/entry-macro.S | 69 ++
32 arch/arm/mach-bcm2708/include/mach/frc.h | 38 +
33 arch/arm/mach-bcm2708/include/mach/gpio.h | 17 +
34 arch/arm/mach-bcm2708/include/mach/hardware.h | 28 +
35 arch/arm/mach-bcm2708/include/mach/io.h | 27 +
36 arch/arm/mach-bcm2708/include/mach/irqs.h | 194 +++
37 arch/arm/mach-bcm2708/include/mach/memory.h | 57 +
38 arch/arm/mach-bcm2708/include/mach/platform.h | 220 ++++
39 arch/arm/mach-bcm2708/include/mach/power.h | 26 +
40 arch/arm/mach-bcm2708/include/mach/system.h | 38 +
41 arch/arm/mach-bcm2708/include/mach/timex.h | 23 +
42 arch/arm/mach-bcm2708/include/mach/uncompress.h | 84 ++
43 arch/arm/mach-bcm2708/include/mach/vc_mem.h | 35 +
44 arch/arm/mach-bcm2708/include/mach/vcio.h | 141 +++
45 arch/arm/mach-bcm2708/include/mach/vmalloc.h | 20 +
46 arch/arm/mach-bcm2708/power.c | 194 +++
47 arch/arm/mach-bcm2708/vc_mem.c | 432 +++++++
48 arch/arm/mach-bcm2708/vcio.c | 474 +++++++
49 arch/arm/mm/Kconfig | 2 +-
50 arch/arm/mm/proc-v6.S | 15 +-
51 arch/arm/tools/mach-types | 1 +
52 drivers/mmc/host/Kconfig | 21 +
53 drivers/mmc/host/Makefile | 1 +
54 drivers/mmc/host/sdhci-bcm2708.c | 1424 ++++++++++++++++++++++
55 drivers/mmc/host/sdhci.c | 203 ++-
56 drivers/mmc/host/sdhci.h | 37 +
57 drivers/tty/serial/amba-pl011.c | 2 +-
58 include/linux/mmc/sdhci.h | 2 +
59 51 files changed, 7792 insertions(+), 72 deletions(-)
60 create mode 100644 arch/arm/configs/bcmrpi_cutdown_defconfig
61 create mode 100644 arch/arm/configs/bcmrpi_defconfig
62 create mode 100644 arch/arm/configs/bcmrpi_emergency_defconfig
63 create mode 100644 arch/arm/mach-bcm2708/Kconfig
64 create mode 100644 arch/arm/mach-bcm2708/Makefile
65 create mode 100644 arch/arm/mach-bcm2708/Makefile.boot
66 create mode 100644 arch/arm/mach-bcm2708/armctrl.c
67 create mode 100644 arch/arm/mach-bcm2708/armctrl.h
68 create mode 100644 arch/arm/mach-bcm2708/bcm2708.c
69 create mode 100644 arch/arm/mach-bcm2708/bcm2708.h
70 create mode 100644 arch/arm/mach-bcm2708/bcm2708_gpio.c
71 create mode 100644 arch/arm/mach-bcm2708/clock.c
72 create mode 100644 arch/arm/mach-bcm2708/clock.h
73 create mode 100644 arch/arm/mach-bcm2708/dma.c
74 create mode 100644 arch/arm/mach-bcm2708/include/mach/arm_control.h
75 create mode 100644 arch/arm/mach-bcm2708/include/mach/arm_power.h
76 create mode 100644 arch/arm/mach-bcm2708/include/mach/clkdev.h
77 create mode 100644 arch/arm/mach-bcm2708/include/mach/debug-macro.S
78 create mode 100644 arch/arm/mach-bcm2708/include/mach/dma.h
79 create mode 100644 arch/arm/mach-bcm2708/include/mach/entry-macro.S
80 create mode 100644 arch/arm/mach-bcm2708/include/mach/frc.h
81 create mode 100644 arch/arm/mach-bcm2708/include/mach/gpio.h
82 create mode 100644 arch/arm/mach-bcm2708/include/mach/hardware.h
83 create mode 100644 arch/arm/mach-bcm2708/include/mach/io.h
84 create mode 100644 arch/arm/mach-bcm2708/include/mach/irqs.h
85 create mode 100644 arch/arm/mach-bcm2708/include/mach/memory.h
86 create mode 100644 arch/arm/mach-bcm2708/include/mach/platform.h
87 create mode 100644 arch/arm/mach-bcm2708/include/mach/power.h
88 create mode 100644 arch/arm/mach-bcm2708/include/mach/system.h
89 create mode 100644 arch/arm/mach-bcm2708/include/mach/timex.h
90 create mode 100644 arch/arm/mach-bcm2708/include/mach/uncompress.h
91 create mode 100644 arch/arm/mach-bcm2708/include/mach/vc_mem.h
92 create mode 100644 arch/arm/mach-bcm2708/include/mach/vcio.h
93 create mode 100644 arch/arm/mach-bcm2708/include/mach/vmalloc.h
94 create mode 100644 arch/arm/mach-bcm2708/power.c
95 create mode 100644 arch/arm/mach-bcm2708/vc_mem.c
96 create mode 100644 arch/arm/mach-bcm2708/vcio.c
97 create mode 100644 drivers/mmc/host/sdhci-bcm2708.c
98
99 --- a/arch/arm/Kconfig
100 +++ b/arch/arm/Kconfig
101 @@ -380,6 +380,22 @@ config ARCH_AT91
102 This enables support for systems based on Atmel
103 AT91RM9200 and AT91SAM9* processors.
104
105 +config ARCH_BCM2708
106 + bool "Broadcom BCM2708 family"
107 + select CPU_V6
108 + select ARM_AMBA
109 + select HAVE_CLK
110 + select HAVE_SCHED_CLOCK
111 + select NEED_MACH_GPIO_H
112 + select NEED_MACH_MEMORY_H
113 + select CLKDEV_LOOKUP
114 + select GENERIC_CLOCKEVENTS
115 + select ARM_ERRATA_411920
116 + select MACH_BCM2708
117 + select VC4
118 + help
119 + This enables support for Broadcom BCM2708 boards.
120 +
121 config ARCH_CLPS711X
122 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
123 select ARCH_REQUIRE_GPIOLIB
124 @@ -1054,6 +1070,7 @@ source "arch/arm/mach-virt/Kconfig"
125 source "arch/arm/mach-vt8500/Kconfig"
126
127 source "arch/arm/mach-w90x900/Kconfig"
128 +source "arch/arm/mach-bcm2708/Kconfig"
129
130 source "arch/arm/mach-zynq/Kconfig"
131
132 --- a/arch/arm/Kconfig.debug
133 +++ b/arch/arm/Kconfig.debug
134 @@ -920,6 +920,14 @@ choice
135 options; the platform specific options are deprecated
136 and will be soon removed.
137
138 + config DEBUG_BCM2708_UART0
139 + bool "Broadcom BCM2708 UART0 (PL011)"
140 + depends on MACH_BCM2708
141 + help
142 + Say Y here if you want the debug print routines to direct
143 + their output to UART 0. The port must have been initialised
144 + by the boot-loader before use.
145 +
146 endchoice
147
148 config DEBUG_EXYNOS_UART
149 --- a/arch/arm/Makefile
150 +++ b/arch/arm/Makefile
151 @@ -148,6 +148,7 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x0020
152 # by CONFIG_* macro name.
153 machine-$(CONFIG_ARCH_AT91) += at91
154 machine-$(CONFIG_ARCH_BCM) += bcm
155 +machine-$(CONFIG_ARCH_BCM2708) += bcm2708
156 machine-$(CONFIG_ARCH_BCM2835) += bcm2835
157 machine-$(CONFIG_ARCH_BERLIN) += berlin
158 machine-$(CONFIG_ARCH_CLPS711X) += clps711x
159 --- /dev/null
160 +++ b/arch/arm/configs/bcmrpi_cutdown_defconfig
161 @@ -0,0 +1,474 @@
162 +CONFIG_EXPERIMENTAL=y
163 +# CONFIG_LOCALVERSION_AUTO is not set
164 +CONFIG_SYSVIPC=y
165 +CONFIG_POSIX_MQUEUE=y
166 +CONFIG_IKCONFIG=y
167 +CONFIG_IKCONFIG_PROC=y
168 +# CONFIG_UID16 is not set
169 +# CONFIG_KALLSYMS is not set
170 +CONFIG_EMBEDDED=y
171 +# CONFIG_VM_EVENT_COUNTERS is not set
172 +# CONFIG_COMPAT_BRK is not set
173 +CONFIG_SLAB=y
174 +CONFIG_MODULES=y
175 +CONFIG_MODULE_UNLOAD=y
176 +CONFIG_MODVERSIONS=y
177 +CONFIG_MODULE_SRCVERSION_ALL=y
178 +# CONFIG_BLK_DEV_BSG is not set
179 +CONFIG_ARCH_BCM2708=y
180 +CONFIG_NO_HZ=y
181 +CONFIG_HIGH_RES_TIMERS=y
182 +CONFIG_AEABI=y
183 +CONFIG_ZBOOT_ROM_TEXT=0x0
184 +CONFIG_ZBOOT_ROM_BSS=0x0
185 +CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait"
186 +CONFIG_CPU_IDLE=y
187 +CONFIG_VFP=y
188 +CONFIG_BINFMT_MISC=m
189 +CONFIG_NET=y
190 +CONFIG_PACKET=y
191 +CONFIG_UNIX=y
192 +CONFIG_XFRM_USER=y
193 +CONFIG_NET_KEY=m
194 +CONFIG_INET=y
195 +CONFIG_IP_MULTICAST=y
196 +CONFIG_IP_PNP=y
197 +CONFIG_IP_PNP_DHCP=y
198 +CONFIG_IP_PNP_RARP=y
199 +CONFIG_SYN_COOKIES=y
200 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
201 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
202 +# CONFIG_INET_XFRM_MODE_BEET is not set
203 +# CONFIG_INET_LRO is not set
204 +# CONFIG_INET_DIAG is not set
205 +# CONFIG_IPV6 is not set
206 +CONFIG_NET_PKTGEN=m
207 +CONFIG_IRDA=m
208 +CONFIG_IRLAN=m
209 +CONFIG_IRCOMM=m
210 +CONFIG_IRDA_ULTRA=y
211 +CONFIG_IRDA_CACHE_LAST_LSAP=y
212 +CONFIG_IRDA_FAST_RR=y
213 +CONFIG_IRTTY_SIR=m
214 +CONFIG_KINGSUN_DONGLE=m
215 +CONFIG_KSDAZZLE_DONGLE=m
216 +CONFIG_KS959_DONGLE=m
217 +CONFIG_USB_IRDA=m
218 +CONFIG_SIGMATEL_FIR=m
219 +CONFIG_MCS_FIR=m
220 +CONFIG_BT=m
221 +CONFIG_BT_L2CAP=y
222 +CONFIG_BT_SCO=y
223 +CONFIG_BT_RFCOMM=m
224 +CONFIG_BT_RFCOMM_TTY=y
225 +CONFIG_BT_BNEP=m
226 +CONFIG_BT_BNEP_MC_FILTER=y
227 +CONFIG_BT_BNEP_PROTO_FILTER=y
228 +CONFIG_BT_HIDP=m
229 +CONFIG_BT_HCIBTUSB=m
230 +CONFIG_BT_HCIBCM203X=m
231 +CONFIG_BT_HCIBPA10X=m
232 +CONFIG_BT_HCIBFUSB=m
233 +CONFIG_BT_HCIVHCI=m
234 +CONFIG_BT_MRVL=m
235 +CONFIG_BT_MRVL_SDIO=m
236 +CONFIG_BT_ATH3K=m
237 +CONFIG_CFG80211=m
238 +CONFIG_MAC80211=m
239 +CONFIG_MAC80211_RC_PID=y
240 +CONFIG_MAC80211_MESH=y
241 +CONFIG_WIMAX=m
242 +CONFIG_NET_9P=m
243 +CONFIG_NFC=m
244 +CONFIG_NFC_PN533=m
245 +CONFIG_DEVTMPFS=y
246 +CONFIG_BLK_DEV_LOOP=y
247 +CONFIG_BLK_DEV_CRYPTOLOOP=m
248 +CONFIG_BLK_DEV_NBD=m
249 +CONFIG_BLK_DEV_RAM=y
250 +CONFIG_CDROM_PKTCDVD=m
251 +CONFIG_MISC_DEVICES=y
252 +CONFIG_SCSI=y
253 +# CONFIG_SCSI_PROC_FS is not set
254 +CONFIG_BLK_DEV_SD=m
255 +CONFIG_BLK_DEV_SR=m
256 +CONFIG_SCSI_MULTI_LUN=y
257 +# CONFIG_SCSI_LOWLEVEL is not set
258 +CONFIG_NETDEVICES=y
259 +CONFIG_TUN=m
260 +CONFIG_PHYLIB=m
261 +CONFIG_MDIO_BITBANG=m
262 +CONFIG_NET_ETHERNET=y
263 +# CONFIG_NETDEV_1000 is not set
264 +# CONFIG_NETDEV_10000 is not set
265 +CONFIG_LIBERTAS_THINFIRM=m
266 +CONFIG_LIBERTAS_THINFIRM_USB=m
267 +CONFIG_AT76C50X_USB=m
268 +CONFIG_USB_ZD1201=m
269 +CONFIG_USB_NET_RNDIS_WLAN=m
270 +CONFIG_RTL8187=m
271 +CONFIG_MAC80211_HWSIM=m
272 +CONFIG_ATH_COMMON=m
273 +CONFIG_ATH9K=m
274 +CONFIG_ATH9K_HTC=m
275 +CONFIG_CARL9170=m
276 +CONFIG_B43=m
277 +CONFIG_B43LEGACY=m
278 +CONFIG_HOSTAP=m
279 +CONFIG_IWM=m
280 +CONFIG_LIBERTAS=m
281 +CONFIG_LIBERTAS_USB=m
282 +CONFIG_LIBERTAS_SDIO=m
283 +CONFIG_P54_COMMON=m
284 +CONFIG_P54_USB=m
285 +CONFIG_RT2X00=m
286 +CONFIG_RT2500USB=m
287 +CONFIG_RT73USB=m
288 +CONFIG_RT2800USB=m
289 +CONFIG_RT2800USB_RT53XX=y
290 +CONFIG_RTL8192CU=m
291 +CONFIG_WL1251=m
292 +CONFIG_WL12XX_MENU=m
293 +CONFIG_ZD1211RW=m
294 +CONFIG_MWIFIEX=m
295 +CONFIG_MWIFIEX_SDIO=m
296 +CONFIG_WIMAX_I2400M_USB=m
297 +CONFIG_USB_CATC=m
298 +CONFIG_USB_KAWETH=m
299 +CONFIG_USB_PEGASUS=m
300 +CONFIG_USB_RTL8150=m
301 +CONFIG_USB_USBNET=y
302 +CONFIG_USB_NET_AX8817X=m
303 +CONFIG_USB_NET_CDCETHER=m
304 +CONFIG_USB_NET_CDC_EEM=m
305 +CONFIG_USB_NET_DM9601=m
306 +CONFIG_USB_NET_SMSC75XX=m
307 +CONFIG_USB_NET_SMSC95XX=y
308 +CONFIG_USB_NET_GL620A=m
309 +CONFIG_USB_NET_NET1080=m
310 +CONFIG_USB_NET_PLUSB=m
311 +CONFIG_USB_NET_MCS7830=m
312 +CONFIG_USB_NET_CDC_SUBSET=m
313 +CONFIG_USB_ALI_M5632=y
314 +CONFIG_USB_AN2720=y
315 +CONFIG_USB_KC2190=y
316 +# CONFIG_USB_NET_ZAURUS is not set
317 +CONFIG_USB_NET_CX82310_ETH=m
318 +CONFIG_USB_NET_KALMIA=m
319 +CONFIG_USB_NET_INT51X1=m
320 +CONFIG_USB_IPHETH=m
321 +CONFIG_USB_SIERRA_NET=m
322 +CONFIG_USB_VL600=m
323 +CONFIG_PPP=m
324 +CONFIG_PPP_ASYNC=m
325 +CONFIG_PPP_SYNC_TTY=m
326 +CONFIG_PPP_DEFLATE=m
327 +CONFIG_PPP_BSDCOMP=m
328 +CONFIG_SLIP=m
329 +CONFIG_SLIP_COMPRESSED=y
330 +CONFIG_NETCONSOLE=m
331 +CONFIG_INPUT_POLLDEV=m
332 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
333 +CONFIG_INPUT_JOYDEV=m
334 +CONFIG_INPUT_EVDEV=m
335 +# CONFIG_INPUT_KEYBOARD is not set
336 +# CONFIG_INPUT_MOUSE is not set
337 +CONFIG_INPUT_MISC=y
338 +CONFIG_INPUT_AD714X=m
339 +CONFIG_INPUT_ATI_REMOTE=m
340 +CONFIG_INPUT_ATI_REMOTE2=m
341 +CONFIG_INPUT_KEYSPAN_REMOTE=m
342 +CONFIG_INPUT_POWERMATE=m
343 +CONFIG_INPUT_YEALINK=m
344 +CONFIG_INPUT_CM109=m
345 +CONFIG_INPUT_UINPUT=m
346 +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
347 +CONFIG_INPUT_ADXL34X=m
348 +CONFIG_INPUT_CMA3000=m
349 +CONFIG_SERIO=m
350 +CONFIG_SERIO_RAW=m
351 +CONFIG_GAMEPORT=m
352 +CONFIG_GAMEPORT_NS558=m
353 +CONFIG_GAMEPORT_L4=m
354 +CONFIG_VT_HW_CONSOLE_BINDING=y
355 +# CONFIG_LEGACY_PTYS is not set
356 +# CONFIG_DEVKMEM is not set
357 +CONFIG_SERIAL_AMBA_PL011=y
358 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
359 +# CONFIG_HW_RANDOM is not set
360 +CONFIG_RAW_DRIVER=y
361 +CONFIG_GPIO_SYSFS=y
362 +# CONFIG_HWMON is not set
363 +CONFIG_WATCHDOG=y
364 +CONFIG_BCM2708_WDT=m
365 +# CONFIG_MFD_SUPPORT is not set
366 +CONFIG_FB=y
367 +CONFIG_FB_BCM2708=y
368 +CONFIG_FRAMEBUFFER_CONSOLE=y
369 +CONFIG_LOGO=y
370 +# CONFIG_LOGO_LINUX_MONO is not set
371 +# CONFIG_LOGO_LINUX_VGA16 is not set
372 +CONFIG_HID_PID=y
373 +CONFIG_USB_HIDDEV=y
374 +CONFIG_HID_A4TECH=m
375 +CONFIG_HID_ACRUX=m
376 +CONFIG_HID_APPLE=m
377 +CONFIG_HID_BELKIN=m
378 +CONFIG_HID_CHERRY=m
379 +CONFIG_HID_CHICONY=m
380 +CONFIG_HID_CYPRESS=m
381 +CONFIG_HID_DRAGONRISE=m
382 +CONFIG_HID_EMS_FF=m
383 +CONFIG_HID_ELECOM=m
384 +CONFIG_HID_EZKEY=m
385 +CONFIG_HID_HOLTEK=m
386 +CONFIG_HID_KEYTOUCH=m
387 +CONFIG_HID_KYE=m
388 +CONFIG_HID_UCLOGIC=m
389 +CONFIG_HID_WALTOP=m
390 +CONFIG_HID_GYRATION=m
391 +CONFIG_HID_TWINHAN=m
392 +CONFIG_HID_KENSINGTON=m
393 +CONFIG_HID_LCPOWER=m
394 +CONFIG_HID_LOGITECH=m
395 +CONFIG_HID_MAGICMOUSE=m
396 +CONFIG_HID_MICROSOFT=m
397 +CONFIG_HID_MONTEREY=m
398 +CONFIG_HID_MULTITOUCH=m
399 +CONFIG_HID_NTRIG=m
400 +CONFIG_HID_ORTEK=m
401 +CONFIG_HID_PANTHERLORD=m
402 +CONFIG_HID_PETALYNX=m
403 +CONFIG_HID_PICOLCD=m
404 +CONFIG_HID_QUANTA=m
405 +CONFIG_HID_ROCCAT=m
406 +CONFIG_HID_SAMSUNG=m
407 +CONFIG_HID_SONY=m
408 +CONFIG_HID_SPEEDLINK=m
409 +CONFIG_HID_SUNPLUS=m
410 +CONFIG_HID_GREENASIA=m
411 +CONFIG_HID_SMARTJOYPLUS=m
412 +CONFIG_HID_TOPSEED=m
413 +CONFIG_HID_THRUSTMASTER=m
414 +CONFIG_HID_WACOM=m
415 +CONFIG_HID_WIIMOTE=m
416 +CONFIG_HID_ZEROPLUS=m
417 +CONFIG_HID_ZYDACRON=m
418 +CONFIG_USB=y
419 +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
420 +CONFIG_USB_MON=m
421 +CONFIG_USB_DWCOTG=y
422 +CONFIG_USB_STORAGE=y
423 +CONFIG_USB_STORAGE_REALTEK=m
424 +CONFIG_USB_STORAGE_DATAFAB=m
425 +CONFIG_USB_STORAGE_FREECOM=m
426 +CONFIG_USB_STORAGE_ISD200=m
427 +CONFIG_USB_STORAGE_USBAT=m
428 +CONFIG_USB_STORAGE_SDDR09=m
429 +CONFIG_USB_STORAGE_SDDR55=m
430 +CONFIG_USB_STORAGE_JUMPSHOT=m
431 +CONFIG_USB_STORAGE_ALAUDA=m
432 +CONFIG_USB_STORAGE_ONETOUCH=m
433 +CONFIG_USB_STORAGE_KARMA=m
434 +CONFIG_USB_STORAGE_CYPRESS_ATACB=m
435 +CONFIG_USB_STORAGE_ENE_UB6250=m
436 +CONFIG_USB_UAS=m
437 +CONFIG_USB_LIBUSUAL=y
438 +CONFIG_USB_MDC800=m
439 +CONFIG_USB_MICROTEK=m
440 +CONFIG_USB_SERIAL=m
441 +CONFIG_USB_SERIAL_GENERIC=y
442 +CONFIG_USB_SERIAL_AIRCABLE=m
443 +CONFIG_USB_SERIAL_ARK3116=m
444 +CONFIG_USB_SERIAL_BELKIN=m
445 +CONFIG_USB_SERIAL_CH341=m
446 +CONFIG_USB_SERIAL_WHITEHEAT=m
447 +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
448 +CONFIG_USB_SERIAL_CP210X=m
449 +CONFIG_USB_SERIAL_CYPRESS_M8=m
450 +CONFIG_USB_SERIAL_EMPEG=m
451 +CONFIG_USB_SERIAL_FTDI_SIO=m
452 +CONFIG_USB_SERIAL_FUNSOFT=m
453 +CONFIG_USB_SERIAL_VISOR=m
454 +CONFIG_USB_SERIAL_IPAQ=m
455 +CONFIG_USB_SERIAL_IR=m
456 +CONFIG_USB_SERIAL_EDGEPORT=m
457 +CONFIG_USB_SERIAL_EDGEPORT_TI=m
458 +CONFIG_USB_SERIAL_GARMIN=m
459 +CONFIG_USB_SERIAL_IPW=m
460 +CONFIG_USB_SERIAL_IUU=m
461 +CONFIG_USB_SERIAL_KEYSPAN_PDA=m
462 +CONFIG_USB_SERIAL_KEYSPAN=m
463 +CONFIG_USB_SERIAL_KLSI=m
464 +CONFIG_USB_SERIAL_KOBIL_SCT=m
465 +CONFIG_USB_SERIAL_MCT_U232=m
466 +CONFIG_USB_SERIAL_MOS7720=m
467 +CONFIG_USB_SERIAL_MOS7840=m
468 +CONFIG_USB_SERIAL_MOTOROLA=m
469 +CONFIG_USB_SERIAL_NAVMAN=m
470 +CONFIG_USB_SERIAL_PL2303=m
471 +CONFIG_USB_SERIAL_OTI6858=m
472 +CONFIG_USB_SERIAL_QCAUX=m
473 +CONFIG_USB_SERIAL_QUALCOMM=m
474 +CONFIG_USB_SERIAL_SPCP8X5=m
475 +CONFIG_USB_SERIAL_HP4X=m
476 +CONFIG_USB_SERIAL_SAFE=m
477 +CONFIG_USB_SERIAL_SIEMENS_MPI=m
478 +CONFIG_USB_SERIAL_SIERRAWIRELESS=m
479 +CONFIG_USB_SERIAL_SYMBOL=m
480 +CONFIG_USB_SERIAL_TI=m
481 +CONFIG_USB_SERIAL_CYBERJACK=m
482 +CONFIG_USB_SERIAL_XIRCOM=m
483 +CONFIG_USB_SERIAL_OPTION=m
484 +CONFIG_USB_SERIAL_OMNINET=m
485 +CONFIG_USB_SERIAL_OPTICON=m
486 +CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m
487 +CONFIG_USB_SERIAL_ZIO=m
488 +CONFIG_USB_SERIAL_SSU100=m
489 +CONFIG_USB_SERIAL_DEBUG=m
490 +CONFIG_USB_EMI62=m
491 +CONFIG_USB_EMI26=m
492 +CONFIG_USB_ADUTUX=m
493 +CONFIG_USB_SEVSEG=m
494 +CONFIG_USB_RIO500=m
495 +CONFIG_USB_LEGOTOWER=m
496 +CONFIG_USB_LCD=m
497 +CONFIG_USB_LED=m
498 +CONFIG_USB_CYPRESS_CY7C63=m
499 +CONFIG_USB_CYTHERM=m
500 +CONFIG_USB_IDMOUSE=m
501 +CONFIG_USB_FTDI_ELAN=m
502 +CONFIG_USB_APPLEDISPLAY=m
503 +CONFIG_USB_LD=m
504 +CONFIG_USB_TRANCEVIBRATOR=m
505 +CONFIG_USB_IOWARRIOR=m
506 +CONFIG_USB_TEST=m
507 +CONFIG_USB_ISIGHTFW=m
508 +CONFIG_USB_YUREX=m
509 +CONFIG_MMC=y
510 +CONFIG_MMC_SDHCI=y
511 +CONFIG_MMC_SDHCI_PLTFM=y
512 +CONFIG_MMC_SDHCI_BCM2708=y
513 +CONFIG_MMC_SDHCI_BCM2708_DMA=y
514 +CONFIG_LEDS_GPIO=y
515 +CONFIG_LEDS_TRIGGER_TIMER=m
516 +CONFIG_LEDS_TRIGGER_HEARTBEAT=m
517 +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
518 +CONFIG_UIO=m
519 +CONFIG_UIO_PDRV=m
520 +CONFIG_UIO_PDRV_GENIRQ=m
521 +# CONFIG_IOMMU_SUPPORT is not set
522 +CONFIG_EXT4_FS=y
523 +CONFIG_EXT4_FS_POSIX_ACL=y
524 +CONFIG_EXT4_FS_SECURITY=y
525 +CONFIG_REISERFS_FS=m
526 +CONFIG_REISERFS_FS_XATTR=y
527 +CONFIG_REISERFS_FS_POSIX_ACL=y
528 +CONFIG_REISERFS_FS_SECURITY=y
529 +CONFIG_JFS_FS=m
530 +CONFIG_JFS_POSIX_ACL=y
531 +CONFIG_JFS_SECURITY=y
532 +CONFIG_XFS_FS=m
533 +CONFIG_XFS_QUOTA=y
534 +CONFIG_XFS_POSIX_ACL=y
535 +CONFIG_XFS_RT=y
536 +CONFIG_GFS2_FS=m
537 +CONFIG_OCFS2_FS=m
538 +CONFIG_BTRFS_FS=m
539 +CONFIG_BTRFS_FS_POSIX_ACL=y
540 +CONFIG_NILFS2_FS=m
541 +CONFIG_AUTOFS4_FS=y
542 +CONFIG_FUSE_FS=m
543 +CONFIG_CUSE=m
544 +CONFIG_FSCACHE=y
545 +CONFIG_CACHEFILES=y
546 +CONFIG_ISO9660_FS=m
547 +CONFIG_JOLIET=y
548 +CONFIG_ZISOFS=y
549 +CONFIG_UDF_FS=m
550 +CONFIG_MSDOS_FS=y
551 +CONFIG_VFAT_FS=y
552 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
553 +CONFIG_NTFS_FS=m
554 +CONFIG_TMPFS=y
555 +CONFIG_TMPFS_POSIX_ACL=y
556 +CONFIG_CONFIGFS_FS=y
557 +CONFIG_SQUASHFS=m
558 +CONFIG_SQUASHFS_XATTR=y
559 +CONFIG_SQUASHFS_LZO=y
560 +CONFIG_SQUASHFS_XZ=y
561 +CONFIG_NFS_FS=y
562 +CONFIG_NFS_V3=y
563 +CONFIG_NFS_V3_ACL=y
564 +CONFIG_NFS_V4=y
565 +CONFIG_ROOT_NFS=y
566 +CONFIG_NFS_FSCACHE=y
567 +CONFIG_CIFS=m
568 +CONFIG_CIFS_WEAK_PW_HASH=y
569 +CONFIG_CIFS_XATTR=y
570 +CONFIG_CIFS_POSIX=y
571 +CONFIG_9P_FS=m
572 +CONFIG_PARTITION_ADVANCED=y
573 +CONFIG_MAC_PARTITION=y
574 +CONFIG_EFI_PARTITION=y
575 +CONFIG_NLS_DEFAULT="utf8"
576 +CONFIG_NLS_CODEPAGE_437=y
577 +CONFIG_NLS_CODEPAGE_737=m
578 +CONFIG_NLS_CODEPAGE_775=m
579 +CONFIG_NLS_CODEPAGE_850=m
580 +CONFIG_NLS_CODEPAGE_852=m
581 +CONFIG_NLS_CODEPAGE_855=m
582 +CONFIG_NLS_CODEPAGE_857=m
583 +CONFIG_NLS_CODEPAGE_860=m
584 +CONFIG_NLS_CODEPAGE_861=m
585 +CONFIG_NLS_CODEPAGE_862=m
586 +CONFIG_NLS_CODEPAGE_863=m
587 +CONFIG_NLS_CODEPAGE_864=m
588 +CONFIG_NLS_CODEPAGE_865=m
589 +CONFIG_NLS_CODEPAGE_866=m
590 +CONFIG_NLS_CODEPAGE_869=m
591 +CONFIG_NLS_CODEPAGE_936=m
592 +CONFIG_NLS_CODEPAGE_950=m
593 +CONFIG_NLS_CODEPAGE_932=m
594 +CONFIG_NLS_CODEPAGE_949=m
595 +CONFIG_NLS_CODEPAGE_874=m
596 +CONFIG_NLS_ISO8859_8=m
597 +CONFIG_NLS_CODEPAGE_1250=m
598 +CONFIG_NLS_CODEPAGE_1251=m
599 +CONFIG_NLS_ASCII=y
600 +CONFIG_NLS_ISO8859_1=m
601 +CONFIG_NLS_ISO8859_2=m
602 +CONFIG_NLS_ISO8859_3=m
603 +CONFIG_NLS_ISO8859_4=m
604 +CONFIG_NLS_ISO8859_5=m
605 +CONFIG_NLS_ISO8859_6=m
606 +CONFIG_NLS_ISO8859_7=m
607 +CONFIG_NLS_ISO8859_9=m
608 +CONFIG_NLS_ISO8859_13=m
609 +CONFIG_NLS_ISO8859_14=m
610 +CONFIG_NLS_ISO8859_15=m
611 +CONFIG_NLS_KOI8_R=m
612 +CONFIG_NLS_KOI8_U=m
613 +CONFIG_NLS_UTF8=m
614 +# CONFIG_SCHED_DEBUG is not set
615 +# CONFIG_DEBUG_BUGVERBOSE is not set
616 +# CONFIG_FTRACE is not set
617 +# CONFIG_ARM_UNWIND is not set
618 +CONFIG_CRYPTO_AUTHENC=m
619 +CONFIG_CRYPTO_SEQIV=m
620 +CONFIG_CRYPTO_CBC=y
621 +CONFIG_CRYPTO_HMAC=y
622 +CONFIG_CRYPTO_XCBC=m
623 +CONFIG_CRYPTO_MD5=y
624 +CONFIG_CRYPTO_SHA1=y
625 +CONFIG_CRYPTO_SHA256=m
626 +CONFIG_CRYPTO_SHA512=m
627 +CONFIG_CRYPTO_TGR192=m
628 +CONFIG_CRYPTO_WP512=m
629 +CONFIG_CRYPTO_CAST5=m
630 +CONFIG_CRYPTO_DES=y
631 +CONFIG_CRYPTO_DEFLATE=m
632 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
633 +# CONFIG_CRYPTO_HW is not set
634 +CONFIG_CRC_ITU_T=y
635 +CONFIG_LIBCRC32C=y
636 --- /dev/null
637 +++ b/arch/arm/configs/bcmrpi_defconfig
638 @@ -0,0 +1,510 @@
639 +CONFIG_EXPERIMENTAL=y
640 +# CONFIG_LOCALVERSION_AUTO is not set
641 +CONFIG_SYSVIPC=y
642 +CONFIG_POSIX_MQUEUE=y
643 +CONFIG_BSD_PROCESS_ACCT=y
644 +CONFIG_BSD_PROCESS_ACCT_V3=y
645 +CONFIG_FHANDLE=y
646 +CONFIG_AUDIT=y
647 +CONFIG_IKCONFIG=y
648 +CONFIG_IKCONFIG_PROC=y
649 +CONFIG_CGROUP_FREEZER=y
650 +CONFIG_CGROUP_DEVICE=y
651 +CONFIG_CGROUP_CPUACCT=y
652 +CONFIG_RESOURCE_COUNTERS=y
653 +CONFIG_BLK_CGROUP=y
654 +CONFIG_NAMESPACES=y
655 +CONFIG_SCHED_AUTOGROUP=y
656 +CONFIG_EMBEDDED=y
657 +# CONFIG_COMPAT_BRK is not set
658 +CONFIG_SLAB=y
659 +CONFIG_PROFILING=y
660 +CONFIG_OPROFILE=m
661 +CONFIG_KPROBES=y
662 +CONFIG_MODULES=y
663 +CONFIG_MODULE_UNLOAD=y
664 +CONFIG_MODVERSIONS=y
665 +CONFIG_MODULE_SRCVERSION_ALL=y
666 +# CONFIG_BLK_DEV_BSG is not set
667 +CONFIG_BLK_DEV_THROTTLING=y
668 +CONFIG_CFQ_GROUP_IOSCHED=y
669 +CONFIG_ARCH_BCM2708=y
670 +CONFIG_NO_HZ=y
671 +CONFIG_HIGH_RES_TIMERS=y
672 +CONFIG_AEABI=y
673 +CONFIG_SECCOMP=y
674 +CONFIG_CC_STACKPROTECTOR=y
675 +CONFIG_ZBOOT_ROM_TEXT=0x0
676 +CONFIG_ZBOOT_ROM_BSS=0x0
677 +CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait"
678 +CONFIG_KEXEC=y
679 +CONFIG_CPU_IDLE=y
680 +CONFIG_VFP=y
681 +CONFIG_BINFMT_MISC=m
682 +CONFIG_NET=y
683 +CONFIG_PACKET=y
684 +CONFIG_UNIX=y
685 +CONFIG_XFRM_USER=y
686 +CONFIG_NET_KEY=m
687 +CONFIG_INET=y
688 +CONFIG_IP_MULTICAST=y
689 +CONFIG_IP_PNP=y
690 +CONFIG_IP_PNP_DHCP=y
691 +CONFIG_IP_PNP_RARP=y
692 +CONFIG_SYN_COOKIES=y
693 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
694 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
695 +# CONFIG_INET_XFRM_MODE_BEET is not set
696 +# CONFIG_INET_LRO is not set
697 +# CONFIG_INET_DIAG is not set
698 +# CONFIG_IPV6 is not set
699 +CONFIG_NET_PKTGEN=m
700 +CONFIG_IRDA=m
701 +CONFIG_IRLAN=m
702 +CONFIG_IRCOMM=m
703 +CONFIG_IRDA_ULTRA=y
704 +CONFIG_IRDA_CACHE_LAST_LSAP=y
705 +CONFIG_IRDA_FAST_RR=y
706 +CONFIG_IRTTY_SIR=m
707 +CONFIG_KINGSUN_DONGLE=m
708 +CONFIG_KSDAZZLE_DONGLE=m
709 +CONFIG_KS959_DONGLE=m
710 +CONFIG_USB_IRDA=m
711 +CONFIG_SIGMATEL_FIR=m
712 +CONFIG_MCS_FIR=m
713 +CONFIG_BT=m
714 +CONFIG_BT_L2CAP=y
715 +CONFIG_BT_SCO=y
716 +CONFIG_BT_RFCOMM=m
717 +CONFIG_BT_RFCOMM_TTY=y
718 +CONFIG_BT_BNEP=m
719 +CONFIG_BT_BNEP_MC_FILTER=y
720 +CONFIG_BT_BNEP_PROTO_FILTER=y
721 +CONFIG_BT_HIDP=m
722 +CONFIG_BT_HCIBTUSB=m
723 +CONFIG_BT_HCIBCM203X=m
724 +CONFIG_BT_HCIBPA10X=m
725 +CONFIG_BT_HCIBFUSB=m
726 +CONFIG_BT_HCIVHCI=m
727 +CONFIG_BT_MRVL=m
728 +CONFIG_BT_MRVL_SDIO=m
729 +CONFIG_BT_ATH3K=m
730 +CONFIG_CFG80211=m
731 +CONFIG_MAC80211=m
732 +CONFIG_MAC80211_RC_PID=y
733 +CONFIG_MAC80211_MESH=y
734 +CONFIG_WIMAX=m
735 +CONFIG_NET_9P=m
736 +CONFIG_NFC=m
737 +CONFIG_NFC_PN533=m
738 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
739 +CONFIG_BLK_DEV_LOOP=y
740 +CONFIG_BLK_DEV_CRYPTOLOOP=m
741 +CONFIG_BLK_DEV_NBD=m
742 +CONFIG_BLK_DEV_RAM=y
743 +CONFIG_CDROM_PKTCDVD=m
744 +CONFIG_MISC_DEVICES=y
745 +CONFIG_SCSI=y
746 +# CONFIG_SCSI_PROC_FS is not set
747 +CONFIG_BLK_DEV_SD=m
748 +CONFIG_BLK_DEV_SR=m
749 +CONFIG_SCSI_MULTI_LUN=y
750 +# CONFIG_SCSI_LOWLEVEL is not set
751 +CONFIG_MD=y
752 +CONFIG_NETDEVICES=y
753 +CONFIG_TUN=m
754 +CONFIG_PHYLIB=m
755 +CONFIG_MDIO_BITBANG=m
756 +CONFIG_NET_ETHERNET=y
757 +# CONFIG_NETDEV_1000 is not set
758 +# CONFIG_NETDEV_10000 is not set
759 +CONFIG_LIBERTAS_THINFIRM=m
760 +CONFIG_LIBERTAS_THINFIRM_USB=m
761 +CONFIG_AT76C50X_USB=m
762 +CONFIG_USB_ZD1201=m
763 +CONFIG_USB_NET_RNDIS_WLAN=m
764 +CONFIG_RTL8187=m
765 +CONFIG_MAC80211_HWSIM=m
766 +CONFIG_ATH_COMMON=m
767 +CONFIG_ATH9K=m
768 +CONFIG_ATH9K_HTC=m
769 +CONFIG_CARL9170=m
770 +CONFIG_B43=m
771 +CONFIG_B43LEGACY=m
772 +CONFIG_HOSTAP=m
773 +CONFIG_IWM=m
774 +CONFIG_LIBERTAS=m
775 +CONFIG_LIBERTAS_USB=m
776 +CONFIG_LIBERTAS_SDIO=m
777 +CONFIG_P54_COMMON=m
778 +CONFIG_P54_USB=m
779 +CONFIG_RT2X00=m
780 +CONFIG_RT2500USB=m
781 +CONFIG_RT73USB=m
782 +CONFIG_RT2800USB=m
783 +CONFIG_RT2800USB_RT53XX=y
784 +CONFIG_RTL8192CU=m
785 +CONFIG_WL1251=m
786 +CONFIG_WL12XX_MENU=m
787 +CONFIG_ZD1211RW=m
788 +CONFIG_MWIFIEX=m
789 +CONFIG_MWIFIEX_SDIO=m
790 +CONFIG_WIMAX_I2400M_USB=m
791 +CONFIG_USB_CATC=m
792 +CONFIG_USB_KAWETH=m
793 +CONFIG_USB_PEGASUS=m
794 +CONFIG_USB_RTL8150=m
795 +CONFIG_USB_USBNET=y
796 +CONFIG_USB_NET_AX8817X=m
797 +CONFIG_USB_NET_CDCETHER=m
798 +CONFIG_USB_NET_CDC_EEM=m
799 +CONFIG_USB_NET_DM9601=m
800 +CONFIG_USB_NET_SMSC75XX=m
801 +CONFIG_USB_NET_SMSC95XX=y
802 +CONFIG_USB_NET_GL620A=m
803 +CONFIG_USB_NET_NET1080=m
804 +CONFIG_USB_NET_PLUSB=m
805 +CONFIG_USB_NET_MCS7830=m
806 +CONFIG_USB_NET_CDC_SUBSET=m
807 +CONFIG_USB_ALI_M5632=y
808 +CONFIG_USB_AN2720=y
809 +CONFIG_USB_KC2190=y
810 +# CONFIG_USB_NET_ZAURUS is not set
811 +CONFIG_USB_NET_CX82310_ETH=m
812 +CONFIG_USB_NET_KALMIA=m
813 +CONFIG_USB_NET_INT51X1=m
814 +CONFIG_USB_IPHETH=m
815 +CONFIG_USB_SIERRA_NET=m
816 +CONFIG_USB_VL600=m
817 +CONFIG_PPP=m
818 +CONFIG_PPP_ASYNC=m
819 +CONFIG_PPP_SYNC_TTY=m
820 +CONFIG_PPP_DEFLATE=m
821 +CONFIG_PPP_BSDCOMP=m
822 +CONFIG_SLIP=m
823 +CONFIG_SLIP_COMPRESSED=y
824 +CONFIG_NETCONSOLE=m
825 +CONFIG_INPUT_POLLDEV=m
826 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
827 +CONFIG_INPUT_JOYDEV=m
828 +CONFIG_INPUT_EVDEV=m
829 +# CONFIG_INPUT_KEYBOARD is not set
830 +# CONFIG_INPUT_MOUSE is not set
831 +CONFIG_INPUT_MISC=y
832 +CONFIG_INPUT_AD714X=m
833 +CONFIG_INPUT_ATI_REMOTE=m
834 +CONFIG_INPUT_ATI_REMOTE2=m
835 +CONFIG_INPUT_KEYSPAN_REMOTE=m
836 +CONFIG_INPUT_POWERMATE=m
837 +CONFIG_INPUT_YEALINK=m
838 +CONFIG_INPUT_CM109=m
839 +CONFIG_INPUT_UINPUT=m
840 +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
841 +CONFIG_INPUT_ADXL34X=m
842 +CONFIG_INPUT_CMA3000=m
843 +CONFIG_SERIO=m
844 +CONFIG_SERIO_RAW=m
845 +CONFIG_GAMEPORT=m
846 +CONFIG_GAMEPORT_NS558=m
847 +CONFIG_GAMEPORT_L4=m
848 +CONFIG_VT_HW_CONSOLE_BINDING=y
849 +# CONFIG_LEGACY_PTYS is not set
850 +# CONFIG_DEVKMEM is not set
851 +CONFIG_SERIAL_AMBA_PL011=y
852 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
853 +# CONFIG_HW_RANDOM is not set
854 +CONFIG_RAW_DRIVER=y
855 +CONFIG_GPIO_SYSFS=y
856 +# CONFIG_HWMON is not set
857 +CONFIG_WATCHDOG=y
858 +CONFIG_BCM2708_WDT=m
859 +# CONFIG_MFD_SUPPORT is not set
860 +CONFIG_FB=y
861 +CONFIG_FB_BCM2708=y
862 +CONFIG_FRAMEBUFFER_CONSOLE=y
863 +CONFIG_LOGO=y
864 +# CONFIG_LOGO_LINUX_MONO is not set
865 +# CONFIG_LOGO_LINUX_VGA16 is not set
866 +CONFIG_HID_PID=y
867 +CONFIG_USB_HIDDEV=y
868 +CONFIG_HID_A4TECH=m
869 +CONFIG_HID_ACRUX=m
870 +CONFIG_HID_APPLE=m
871 +CONFIG_HID_BELKIN=m
872 +CONFIG_HID_CHERRY=m
873 +CONFIG_HID_CHICONY=m
874 +CONFIG_HID_CYPRESS=m
875 +CONFIG_HID_DRAGONRISE=m
876 +CONFIG_HID_EMS_FF=m
877 +CONFIG_HID_ELECOM=m
878 +CONFIG_HID_EZKEY=m
879 +CONFIG_HID_HOLTEK=m
880 +CONFIG_HID_KEYTOUCH=m
881 +CONFIG_HID_KYE=m
882 +CONFIG_HID_UCLOGIC=m
883 +CONFIG_HID_WALTOP=m
884 +CONFIG_HID_GYRATION=m
885 +CONFIG_HID_TWINHAN=m
886 +CONFIG_HID_KENSINGTON=m
887 +CONFIG_HID_LCPOWER=m
888 +CONFIG_HID_LOGITECH=m
889 +CONFIG_HID_MAGICMOUSE=m
890 +CONFIG_HID_MICROSOFT=m
891 +CONFIG_HID_MONTEREY=m
892 +CONFIG_HID_MULTITOUCH=m
893 +CONFIG_HID_NTRIG=m
894 +CONFIG_HID_ORTEK=m
895 +CONFIG_HID_PANTHERLORD=m
896 +CONFIG_HID_PETALYNX=m
897 +CONFIG_HID_PICOLCD=m
898 +CONFIG_HID_QUANTA=m
899 +CONFIG_HID_ROCCAT=m
900 +CONFIG_HID_SAMSUNG=m
901 +CONFIG_HID_SONY=m
902 +CONFIG_HID_SPEEDLINK=m
903 +CONFIG_HID_SUNPLUS=m
904 +CONFIG_HID_GREENASIA=m
905 +CONFIG_HID_SMARTJOYPLUS=m
906 +CONFIG_HID_TOPSEED=m
907 +CONFIG_HID_THRUSTMASTER=m
908 +CONFIG_HID_WACOM=m
909 +CONFIG_HID_WIIMOTE=m
910 +CONFIG_HID_ZEROPLUS=m
911 +CONFIG_HID_ZYDACRON=m
912 +CONFIG_USB=y
913 +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
914 +CONFIG_USB_MON=m
915 +CONFIG_USB_DWCOTG=y
916 +CONFIG_USB_STORAGE=y
917 +CONFIG_USB_STORAGE_REALTEK=m
918 +CONFIG_USB_STORAGE_DATAFAB=m
919 +CONFIG_USB_STORAGE_FREECOM=m
920 +CONFIG_USB_STORAGE_ISD200=m
921 +CONFIG_USB_STORAGE_USBAT=m
922 +CONFIG_USB_STORAGE_SDDR09=m
923 +CONFIG_USB_STORAGE_SDDR55=m
924 +CONFIG_USB_STORAGE_JUMPSHOT=m
925 +CONFIG_USB_STORAGE_ALAUDA=m
926 +CONFIG_USB_STORAGE_ONETOUCH=m
927 +CONFIG_USB_STORAGE_KARMA=m
928 +CONFIG_USB_STORAGE_CYPRESS_ATACB=m
929 +CONFIG_USB_STORAGE_ENE_UB6250=m
930 +CONFIG_USB_UAS=m
931 +CONFIG_USB_LIBUSUAL=y
932 +CONFIG_USB_MDC800=m
933 +CONFIG_USB_MICROTEK=m
934 +CONFIG_USB_SERIAL=m
935 +CONFIG_USB_SERIAL_GENERIC=y
936 +CONFIG_USB_SERIAL_AIRCABLE=m
937 +CONFIG_USB_SERIAL_ARK3116=m
938 +CONFIG_USB_SERIAL_BELKIN=m
939 +CONFIG_USB_SERIAL_CH341=m
940 +CONFIG_USB_SERIAL_WHITEHEAT=m
941 +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
942 +CONFIG_USB_SERIAL_CP210X=m
943 +CONFIG_USB_SERIAL_CYPRESS_M8=m
944 +CONFIG_USB_SERIAL_EMPEG=m
945 +CONFIG_USB_SERIAL_FTDI_SIO=m
946 +CONFIG_USB_SERIAL_FUNSOFT=m
947 +CONFIG_USB_SERIAL_VISOR=m
948 +CONFIG_USB_SERIAL_IPAQ=m
949 +CONFIG_USB_SERIAL_IR=m
950 +CONFIG_USB_SERIAL_EDGEPORT=m
951 +CONFIG_USB_SERIAL_EDGEPORT_TI=m
952 +CONFIG_USB_SERIAL_GARMIN=m
953 +CONFIG_USB_SERIAL_IPW=m
954 +CONFIG_USB_SERIAL_IUU=m
955 +CONFIG_USB_SERIAL_KEYSPAN_PDA=m
956 +CONFIG_USB_SERIAL_KEYSPAN=m
957 +CONFIG_USB_SERIAL_KLSI=m
958 +CONFIG_USB_SERIAL_KOBIL_SCT=m
959 +CONFIG_USB_SERIAL_MCT_U232=m
960 +CONFIG_USB_SERIAL_MOS7720=m
961 +CONFIG_USB_SERIAL_MOS7840=m
962 +CONFIG_USB_SERIAL_MOTOROLA=m
963 +CONFIG_USB_SERIAL_NAVMAN=m
964 +CONFIG_USB_SERIAL_PL2303=m
965 +CONFIG_USB_SERIAL_OTI6858=m
966 +CONFIG_USB_SERIAL_QCAUX=m
967 +CONFIG_USB_SERIAL_QUALCOMM=m
968 +CONFIG_USB_SERIAL_SPCP8X5=m
969 +CONFIG_USB_SERIAL_HP4X=m
970 +CONFIG_USB_SERIAL_SAFE=m
971 +CONFIG_USB_SERIAL_SIEMENS_MPI=m
972 +CONFIG_USB_SERIAL_SIERRAWIRELESS=m
973 +CONFIG_USB_SERIAL_SYMBOL=m
974 +CONFIG_USB_SERIAL_TI=m
975 +CONFIG_USB_SERIAL_CYBERJACK=m
976 +CONFIG_USB_SERIAL_XIRCOM=m
977 +CONFIG_USB_SERIAL_OPTION=m
978 +CONFIG_USB_SERIAL_OMNINET=m
979 +CONFIG_USB_SERIAL_OPTICON=m
980 +CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m
981 +CONFIG_USB_SERIAL_ZIO=m
982 +CONFIG_USB_SERIAL_SSU100=m
983 +CONFIG_USB_SERIAL_DEBUG=m
984 +CONFIG_USB_EMI62=m
985 +CONFIG_USB_EMI26=m
986 +CONFIG_USB_ADUTUX=m
987 +CONFIG_USB_SEVSEG=m
988 +CONFIG_USB_RIO500=m
989 +CONFIG_USB_LEGOTOWER=m
990 +CONFIG_USB_LCD=m
991 +CONFIG_USB_LED=m
992 +CONFIG_USB_CYPRESS_CY7C63=m
993 +CONFIG_USB_CYTHERM=m
994 +CONFIG_USB_IDMOUSE=m
995 +CONFIG_USB_FTDI_ELAN=m
996 +CONFIG_USB_APPLEDISPLAY=m
997 +CONFIG_USB_LD=m
998 +CONFIG_USB_TRANCEVIBRATOR=m
999 +CONFIG_USB_IOWARRIOR=m
1000 +CONFIG_USB_TEST=m
1001 +CONFIG_USB_ISIGHTFW=m
1002 +CONFIG_USB_YUREX=m
1003 +CONFIG_MMC=y
1004 +CONFIG_MMC_SDHCI=y
1005 +CONFIG_MMC_SDHCI_PLTFM=y
1006 +CONFIG_MMC_SDHCI_BCM2708=y
1007 +CONFIG_MMC_SDHCI_BCM2708_DMA=y
1008 +CONFIG_LEDS_GPIO=y
1009 +CONFIG_LEDS_TRIGGER_TIMER=m
1010 +CONFIG_LEDS_TRIGGER_HEARTBEAT=m
1011 +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
1012 +CONFIG_UIO=m
1013 +CONFIG_UIO_PDRV=m
1014 +CONFIG_UIO_PDRV_GENIRQ=m
1015 +# CONFIG_IOMMU_SUPPORT is not set
1016 +CONFIG_EXT4_FS=y
1017 +CONFIG_EXT4_FS_POSIX_ACL=y
1018 +CONFIG_EXT4_FS_SECURITY=y
1019 +CONFIG_REISERFS_FS=m
1020 +CONFIG_REISERFS_FS_XATTR=y
1021 +CONFIG_REISERFS_FS_POSIX_ACL=y
1022 +CONFIG_REISERFS_FS_SECURITY=y
1023 +CONFIG_JFS_FS=m
1024 +CONFIG_JFS_POSIX_ACL=y
1025 +CONFIG_JFS_SECURITY=y
1026 +CONFIG_JFS_STATISTICS=y
1027 +CONFIG_XFS_FS=m
1028 +CONFIG_XFS_QUOTA=y
1029 +CONFIG_XFS_POSIX_ACL=y
1030 +CONFIG_XFS_RT=y
1031 +CONFIG_GFS2_FS=m
1032 +CONFIG_OCFS2_FS=m
1033 +CONFIG_BTRFS_FS=m
1034 +CONFIG_BTRFS_FS_POSIX_ACL=y
1035 +CONFIG_NILFS2_FS=m
1036 +CONFIG_FANOTIFY=y
1037 +CONFIG_AUTOFS4_FS=y
1038 +CONFIG_FUSE_FS=m
1039 +CONFIG_CUSE=m
1040 +CONFIG_FSCACHE=y
1041 +CONFIG_FSCACHE_STATS=y
1042 +CONFIG_FSCACHE_HISTOGRAM=y
1043 +CONFIG_CACHEFILES=y
1044 +CONFIG_ISO9660_FS=m
1045 +CONFIG_JOLIET=y
1046 +CONFIG_ZISOFS=y
1047 +CONFIG_UDF_FS=m
1048 +CONFIG_MSDOS_FS=y
1049 +CONFIG_VFAT_FS=y
1050 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
1051 +CONFIG_NTFS_FS=m
1052 +CONFIG_TMPFS=y
1053 +CONFIG_TMPFS_POSIX_ACL=y
1054 +CONFIG_CONFIGFS_FS=y
1055 +CONFIG_SQUASHFS=m
1056 +CONFIG_SQUASHFS_XATTR=y
1057 +CONFIG_SQUASHFS_LZO=y
1058 +CONFIG_SQUASHFS_XZ=y
1059 +CONFIG_NFS_FS=y
1060 +CONFIG_NFS_V3=y
1061 +CONFIG_NFS_V3_ACL=y
1062 +CONFIG_NFS_V4=y
1063 +CONFIG_ROOT_NFS=y
1064 +CONFIG_NFS_FSCACHE=y
1065 +CONFIG_CIFS=m
1066 +CONFIG_CIFS_WEAK_PW_HASH=y
1067 +CONFIG_CIFS_XATTR=y
1068 +CONFIG_CIFS_POSIX=y
1069 +CONFIG_9P_FS=m
1070 +CONFIG_9P_FS_POSIX_ACL=y
1071 +CONFIG_PARTITION_ADVANCED=y
1072 +CONFIG_MAC_PARTITION=y
1073 +CONFIG_EFI_PARTITION=y
1074 +CONFIG_NLS_DEFAULT="utf8"
1075 +CONFIG_NLS_CODEPAGE_437=y
1076 +CONFIG_NLS_CODEPAGE_737=m
1077 +CONFIG_NLS_CODEPAGE_775=m
1078 +CONFIG_NLS_CODEPAGE_850=m
1079 +CONFIG_NLS_CODEPAGE_852=m
1080 +CONFIG_NLS_CODEPAGE_855=m
1081 +CONFIG_NLS_CODEPAGE_857=m
1082 +CONFIG_NLS_CODEPAGE_860=m
1083 +CONFIG_NLS_CODEPAGE_861=m
1084 +CONFIG_NLS_CODEPAGE_862=m
1085 +CONFIG_NLS_CODEPAGE_863=m
1086 +CONFIG_NLS_CODEPAGE_864=m
1087 +CONFIG_NLS_CODEPAGE_865=m
1088 +CONFIG_NLS_CODEPAGE_866=m
1089 +CONFIG_NLS_CODEPAGE_869=m
1090 +CONFIG_NLS_CODEPAGE_936=m
1091 +CONFIG_NLS_CODEPAGE_950=m
1092 +CONFIG_NLS_CODEPAGE_932=m
1093 +CONFIG_NLS_CODEPAGE_949=m
1094 +CONFIG_NLS_CODEPAGE_874=m
1095 +CONFIG_NLS_ISO8859_8=m
1096 +CONFIG_NLS_CODEPAGE_1250=m
1097 +CONFIG_NLS_CODEPAGE_1251=m
1098 +CONFIG_NLS_ASCII=y
1099 +CONFIG_NLS_ISO8859_1=m
1100 +CONFIG_NLS_ISO8859_2=m
1101 +CONFIG_NLS_ISO8859_3=m
1102 +CONFIG_NLS_ISO8859_4=m
1103 +CONFIG_NLS_ISO8859_5=m
1104 +CONFIG_NLS_ISO8859_6=m
1105 +CONFIG_NLS_ISO8859_7=m
1106 +CONFIG_NLS_ISO8859_9=m
1107 +CONFIG_NLS_ISO8859_13=m
1108 +CONFIG_NLS_ISO8859_14=m
1109 +CONFIG_NLS_ISO8859_15=m
1110 +CONFIG_NLS_KOI8_R=m
1111 +CONFIG_NLS_KOI8_U=m
1112 +CONFIG_NLS_UTF8=m
1113 +CONFIG_PRINTK_TIME=y
1114 +CONFIG_DETECT_HUNG_TASK=y
1115 +CONFIG_TIMER_STATS=y
1116 +CONFIG_DEBUG_STACK_USAGE=y
1117 +CONFIG_DEBUG_INFO=y
1118 +CONFIG_DEBUG_MEMORY_INIT=y
1119 +CONFIG_BOOT_PRINTK_DELAY=y
1120 +CONFIG_LATENCYTOP=y
1121 +CONFIG_SYSCTL_SYSCALL_CHECK=y
1122 +CONFIG_IRQSOFF_TRACER=y
1123 +CONFIG_SCHED_TRACER=y
1124 +CONFIG_STACK_TRACER=y
1125 +CONFIG_BLK_DEV_IO_TRACE=y
1126 +CONFIG_FUNCTION_PROFILER=y
1127 +CONFIG_KGDB=y
1128 +CONFIG_KGDB_KDB=y
1129 +CONFIG_KDB_KEYBOARD=y
1130 +CONFIG_STRICT_DEVMEM=y
1131 +CONFIG_CRYPTO_AUTHENC=m
1132 +CONFIG_CRYPTO_SEQIV=m
1133 +CONFIG_CRYPTO_CBC=y
1134 +CONFIG_CRYPTO_HMAC=y
1135 +CONFIG_CRYPTO_XCBC=m
1136 +CONFIG_CRYPTO_MD5=y
1137 +CONFIG_CRYPTO_SHA1=y
1138 +CONFIG_CRYPTO_SHA256=m
1139 +CONFIG_CRYPTO_SHA512=m
1140 +CONFIG_CRYPTO_TGR192=m
1141 +CONFIG_CRYPTO_WP512=m
1142 +CONFIG_CRYPTO_CAST5=m
1143 +CONFIG_CRYPTO_DES=y
1144 +CONFIG_CRYPTO_DEFLATE=m
1145 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
1146 +# CONFIG_CRYPTO_HW is not set
1147 +CONFIG_CRC_ITU_T=y
1148 +CONFIG_LIBCRC32C=y
1149 --- /dev/null
1150 +++ b/arch/arm/configs/bcmrpi_emergency_defconfig
1151 @@ -0,0 +1,532 @@
1152 +CONFIG_EXPERIMENTAL=y
1153 +# CONFIG_LOCALVERSION_AUTO is not set
1154 +CONFIG_SYSVIPC=y
1155 +CONFIG_POSIX_MQUEUE=y
1156 +CONFIG_BSD_PROCESS_ACCT=y
1157 +CONFIG_BSD_PROCESS_ACCT_V3=y
1158 +CONFIG_FHANDLE=y
1159 +CONFIG_AUDIT=y
1160 +CONFIG_IKCONFIG=y
1161 +CONFIG_IKCONFIG_PROC=y
1162 +CONFIG_BLK_DEV_INITRD=y
1163 +CONFIG_INITRAMFS_SOURCE="../target_fs"
1164 +CONFIG_CGROUP_FREEZER=y
1165 +CONFIG_CGROUP_DEVICE=y
1166 +CONFIG_CGROUP_CPUACCT=y
1167 +CONFIG_RESOURCE_COUNTERS=y
1168 +CONFIG_BLK_CGROUP=y
1169 +CONFIG_NAMESPACES=y
1170 +CONFIG_SCHED_AUTOGROUP=y
1171 +CONFIG_EMBEDDED=y
1172 +# CONFIG_COMPAT_BRK is not set
1173 +CONFIG_SLAB=y
1174 +CONFIG_PROFILING=y
1175 +CONFIG_OPROFILE=m
1176 +CONFIG_KPROBES=y
1177 +CONFIG_MODULES=y
1178 +CONFIG_MODULE_UNLOAD=y
1179 +CONFIG_MODVERSIONS=y
1180 +CONFIG_MODULE_SRCVERSION_ALL=y
1181 +# CONFIG_BLK_DEV_BSG is not set
1182 +CONFIG_BLK_DEV_THROTTLING=y
1183 +CONFIG_CFQ_GROUP_IOSCHED=y
1184 +CONFIG_ARCH_BCM2708=y
1185 +CONFIG_NO_HZ=y
1186 +CONFIG_HIGH_RES_TIMERS=y
1187 +CONFIG_AEABI=y
1188 +CONFIG_SECCOMP=y
1189 +CONFIG_CC_STACKPROTECTOR=y
1190 +CONFIG_ZBOOT_ROM_TEXT=0x0
1191 +CONFIG_ZBOOT_ROM_BSS=0x0
1192 +CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait"
1193 +CONFIG_KEXEC=y
1194 +CONFIG_CPU_IDLE=y
1195 +CONFIG_VFP=y
1196 +CONFIG_BINFMT_MISC=m
1197 +CONFIG_NET=y
1198 +CONFIG_PACKET=y
1199 +CONFIG_UNIX=y
1200 +CONFIG_XFRM_USER=y
1201 +CONFIG_NET_KEY=m
1202 +CONFIG_INET=y
1203 +CONFIG_IP_MULTICAST=y
1204 +CONFIG_IP_PNP=y
1205 +CONFIG_IP_PNP_DHCP=y
1206 +CONFIG_IP_PNP_RARP=y
1207 +CONFIG_SYN_COOKIES=y
1208 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
1209 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
1210 +# CONFIG_INET_XFRM_MODE_BEET is not set
1211 +# CONFIG_INET_LRO is not set
1212 +# CONFIG_INET_DIAG is not set
1213 +# CONFIG_IPV6 is not set
1214 +CONFIG_NET_PKTGEN=m
1215 +CONFIG_IRDA=m
1216 +CONFIG_IRLAN=m
1217 +CONFIG_IRCOMM=m
1218 +CONFIG_IRDA_ULTRA=y
1219 +CONFIG_IRDA_CACHE_LAST_LSAP=y
1220 +CONFIG_IRDA_FAST_RR=y
1221 +CONFIG_IRTTY_SIR=m
1222 +CONFIG_KINGSUN_DONGLE=m
1223 +CONFIG_KSDAZZLE_DONGLE=m
1224 +CONFIG_KS959_DONGLE=m
1225 +CONFIG_USB_IRDA=m
1226 +CONFIG_SIGMATEL_FIR=m
1227 +CONFIG_MCS_FIR=m
1228 +CONFIG_BT=m
1229 +CONFIG_BT_L2CAP=y
1230 +CONFIG_BT_SCO=y
1231 +CONFIG_BT_RFCOMM=m
1232 +CONFIG_BT_RFCOMM_TTY=y
1233 +CONFIG_BT_BNEP=m
1234 +CONFIG_BT_BNEP_MC_FILTER=y
1235 +CONFIG_BT_BNEP_PROTO_FILTER=y
1236 +CONFIG_BT_HIDP=m
1237 +CONFIG_BT_HCIBTUSB=m
1238 +CONFIG_BT_HCIBCM203X=m
1239 +CONFIG_BT_HCIBPA10X=m
1240 +CONFIG_BT_HCIBFUSB=m
1241 +CONFIG_BT_HCIVHCI=m
1242 +CONFIG_BT_MRVL=m
1243 +CONFIG_BT_MRVL_SDIO=m
1244 +CONFIG_BT_ATH3K=m
1245 +CONFIG_CFG80211=m
1246 +CONFIG_MAC80211=m
1247 +CONFIG_MAC80211_RC_PID=y
1248 +CONFIG_MAC80211_MESH=y
1249 +CONFIG_WIMAX=m
1250 +CONFIG_NET_9P=m
1251 +CONFIG_NFC=m
1252 +CONFIG_NFC_PN533=m
1253 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
1254 +CONFIG_BLK_DEV_LOOP=y
1255 +CONFIG_BLK_DEV_CRYPTOLOOP=m
1256 +CONFIG_BLK_DEV_NBD=m
1257 +CONFIG_BLK_DEV_RAM=y
1258 +CONFIG_CDROM_PKTCDVD=m
1259 +CONFIG_MISC_DEVICES=y
1260 +CONFIG_SCSI=y
1261 +# CONFIG_SCSI_PROC_FS is not set
1262 +CONFIG_BLK_DEV_SD=y
1263 +CONFIG_BLK_DEV_SR=m
1264 +CONFIG_SCSI_MULTI_LUN=y
1265 +# CONFIG_SCSI_LOWLEVEL is not set
1266 +CONFIG_MD=y
1267 +CONFIG_NETDEVICES=y
1268 +CONFIG_TUN=m
1269 +CONFIG_PHYLIB=m
1270 +CONFIG_MDIO_BITBANG=m
1271 +CONFIG_NET_ETHERNET=y
1272 +# CONFIG_NETDEV_1000 is not set
1273 +# CONFIG_NETDEV_10000 is not set
1274 +CONFIG_LIBERTAS_THINFIRM=m
1275 +CONFIG_LIBERTAS_THINFIRM_USB=m
1276 +CONFIG_AT76C50X_USB=m
1277 +CONFIG_USB_ZD1201=m
1278 +CONFIG_USB_NET_RNDIS_WLAN=m
1279 +CONFIG_RTL8187=m
1280 +CONFIG_MAC80211_HWSIM=m
1281 +CONFIG_ATH_COMMON=m
1282 +CONFIG_ATH9K=m
1283 +CONFIG_ATH9K_HTC=m
1284 +CONFIG_CARL9170=m
1285 +CONFIG_B43=m
1286 +CONFIG_B43LEGACY=m
1287 +CONFIG_HOSTAP=m
1288 +CONFIG_IWM=m
1289 +CONFIG_LIBERTAS=m
1290 +CONFIG_LIBERTAS_USB=m
1291 +CONFIG_LIBERTAS_SDIO=m
1292 +CONFIG_P54_COMMON=m
1293 +CONFIG_P54_USB=m
1294 +CONFIG_RT2X00=m
1295 +CONFIG_RT2500USB=m
1296 +CONFIG_RT73USB=m
1297 +CONFIG_RT2800USB=m
1298 +CONFIG_RT2800USB_RT53XX=y
1299 +CONFIG_RTL8192CU=m
1300 +CONFIG_WL1251=m
1301 +CONFIG_WL12XX_MENU=m
1302 +CONFIG_ZD1211RW=m
1303 +CONFIG_MWIFIEX=m
1304 +CONFIG_MWIFIEX_SDIO=m
1305 +CONFIG_WIMAX_I2400M_USB=m
1306 +CONFIG_USB_CATC=m
1307 +CONFIG_USB_KAWETH=m
1308 +CONFIG_USB_PEGASUS=m
1309 +CONFIG_USB_RTL8150=m
1310 +CONFIG_USB_USBNET=y
1311 +CONFIG_USB_NET_AX8817X=m
1312 +CONFIG_USB_NET_CDCETHER=m
1313 +CONFIG_USB_NET_CDC_EEM=m
1314 +CONFIG_USB_NET_DM9601=m
1315 +CONFIG_USB_NET_SMSC75XX=m
1316 +CONFIG_USB_NET_SMSC95XX=y
1317 +CONFIG_USB_NET_GL620A=m
1318 +CONFIG_USB_NET_NET1080=m
1319 +CONFIG_USB_NET_PLUSB=m
1320 +CONFIG_USB_NET_MCS7830=m
1321 +CONFIG_USB_NET_CDC_SUBSET=m
1322 +CONFIG_USB_ALI_M5632=y
1323 +CONFIG_USB_AN2720=y
1324 +CONFIG_USB_KC2190=y
1325 +# CONFIG_USB_NET_ZAURUS is not set
1326 +CONFIG_USB_NET_CX82310_ETH=m
1327 +CONFIG_USB_NET_KALMIA=m
1328 +CONFIG_USB_NET_INT51X1=m
1329 +CONFIG_USB_IPHETH=m
1330 +CONFIG_USB_SIERRA_NET=m
1331 +CONFIG_USB_VL600=m
1332 +CONFIG_PPP=m
1333 +CONFIG_PPP_ASYNC=m
1334 +CONFIG_PPP_SYNC_TTY=m
1335 +CONFIG_PPP_DEFLATE=m
1336 +CONFIG_PPP_BSDCOMP=m
1337 +CONFIG_SLIP=m
1338 +CONFIG_SLIP_COMPRESSED=y
1339 +CONFIG_NETCONSOLE=m
1340 +CONFIG_INPUT_POLLDEV=m
1341 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
1342 +CONFIG_INPUT_JOYDEV=m
1343 +CONFIG_INPUT_EVDEV=m
1344 +# CONFIG_INPUT_KEYBOARD is not set
1345 +# CONFIG_INPUT_MOUSE is not set
1346 +CONFIG_INPUT_MISC=y
1347 +CONFIG_INPUT_AD714X=m
1348 +CONFIG_INPUT_ATI_REMOTE=m
1349 +CONFIG_INPUT_ATI_REMOTE2=m
1350 +CONFIG_INPUT_KEYSPAN_REMOTE=m
1351 +CONFIG_INPUT_POWERMATE=m
1352 +CONFIG_INPUT_YEALINK=m
1353 +CONFIG_INPUT_CM109=m
1354 +CONFIG_INPUT_UINPUT=m
1355 +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
1356 +CONFIG_INPUT_ADXL34X=m
1357 +CONFIG_INPUT_CMA3000=m
1358 +CONFIG_SERIO=m
1359 +CONFIG_SERIO_RAW=m
1360 +CONFIG_GAMEPORT=m
1361 +CONFIG_GAMEPORT_NS558=m
1362 +CONFIG_GAMEPORT_L4=m
1363 +CONFIG_VT_HW_CONSOLE_BINDING=y
1364 +# CONFIG_LEGACY_PTYS is not set
1365 +# CONFIG_DEVKMEM is not set
1366 +CONFIG_SERIAL_AMBA_PL011=y
1367 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
1368 +# CONFIG_HW_RANDOM is not set
1369 +CONFIG_RAW_DRIVER=y
1370 +CONFIG_GPIO_SYSFS=y
1371 +# CONFIG_HWMON is not set
1372 +CONFIG_WATCHDOG=y
1373 +CONFIG_BCM2708_WDT=m
1374 +# CONFIG_MFD_SUPPORT is not set
1375 +CONFIG_FB=y
1376 +CONFIG_FB_BCM2708=y
1377 +CONFIG_FRAMEBUFFER_CONSOLE=y
1378 +CONFIG_LOGO=y
1379 +# CONFIG_LOGO_LINUX_MONO is not set
1380 +# CONFIG_LOGO_LINUX_VGA16 is not set
1381 +CONFIG_SOUND=y
1382 +CONFIG_SND=m
1383 +CONFIG_SND_SEQUENCER=m
1384 +CONFIG_SND_SEQ_DUMMY=m
1385 +CONFIG_SND_MIXER_OSS=m
1386 +CONFIG_SND_PCM_OSS=m
1387 +CONFIG_SND_SEQUENCER_OSS=y
1388 +CONFIG_SND_HRTIMER=m
1389 +CONFIG_SND_DUMMY=m
1390 +CONFIG_SND_ALOOP=m
1391 +CONFIG_SND_VIRMIDI=m
1392 +CONFIG_SND_MTPAV=m
1393 +CONFIG_SND_SERIAL_U16550=m
1394 +CONFIG_SND_MPU401=m
1395 +CONFIG_SND_BCM2835=m
1396 +CONFIG_SND_USB_AUDIO=m
1397 +CONFIG_SND_USB_UA101=m
1398 +CONFIG_SND_USB_CAIAQ=m
1399 +CONFIG_SND_USB_6FIRE=m
1400 +CONFIG_SOUND_PRIME=m
1401 +CONFIG_HID_PID=y
1402 +CONFIG_USB_HIDDEV=y
1403 +CONFIG_HID_A4TECH=m
1404 +CONFIG_HID_ACRUX=m
1405 +CONFIG_HID_APPLE=m
1406 +CONFIG_HID_BELKIN=m
1407 +CONFIG_HID_CHERRY=m
1408 +CONFIG_HID_CHICONY=m
1409 +CONFIG_HID_CYPRESS=m
1410 +CONFIG_HID_DRAGONRISE=m
1411 +CONFIG_HID_EMS_FF=m
1412 +CONFIG_HID_ELECOM=m
1413 +CONFIG_HID_EZKEY=m
1414 +CONFIG_HID_HOLTEK=m
1415 +CONFIG_HID_KEYTOUCH=m
1416 +CONFIG_HID_KYE=m
1417 +CONFIG_HID_UCLOGIC=m
1418 +CONFIG_HID_WALTOP=m
1419 +CONFIG_HID_GYRATION=m
1420 +CONFIG_HID_TWINHAN=m
1421 +CONFIG_HID_KENSINGTON=m
1422 +CONFIG_HID_LCPOWER=m
1423 +CONFIG_HID_LOGITECH=m
1424 +CONFIG_HID_MAGICMOUSE=m
1425 +CONFIG_HID_MICROSOFT=m
1426 +CONFIG_HID_MONTEREY=m
1427 +CONFIG_HID_MULTITOUCH=m
1428 +CONFIG_HID_NTRIG=m
1429 +CONFIG_HID_ORTEK=m
1430 +CONFIG_HID_PANTHERLORD=m
1431 +CONFIG_HID_PETALYNX=m
1432 +CONFIG_HID_PICOLCD=m
1433 +CONFIG_HID_QUANTA=m
1434 +CONFIG_HID_ROCCAT=m
1435 +CONFIG_HID_SAMSUNG=m
1436 +CONFIG_HID_SONY=m
1437 +CONFIG_HID_SPEEDLINK=m
1438 +CONFIG_HID_SUNPLUS=m
1439 +CONFIG_HID_GREENASIA=m
1440 +CONFIG_HID_SMARTJOYPLUS=m
1441 +CONFIG_HID_TOPSEED=m
1442 +CONFIG_HID_THRUSTMASTER=m
1443 +CONFIG_HID_WACOM=m
1444 +CONFIG_HID_WIIMOTE=m
1445 +CONFIG_HID_ZEROPLUS=m
1446 +CONFIG_HID_ZYDACRON=m
1447 +CONFIG_USB=y
1448 +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
1449 +CONFIG_USB_MON=m
1450 +CONFIG_USB_DWCOTG=y
1451 +CONFIG_USB_STORAGE=y
1452 +CONFIG_USB_STORAGE_REALTEK=m
1453 +CONFIG_USB_STORAGE_DATAFAB=m
1454 +CONFIG_USB_STORAGE_FREECOM=m
1455 +CONFIG_USB_STORAGE_ISD200=m
1456 +CONFIG_USB_STORAGE_USBAT=m
1457 +CONFIG_USB_STORAGE_SDDR09=m
1458 +CONFIG_USB_STORAGE_SDDR55=m
1459 +CONFIG_USB_STORAGE_JUMPSHOT=m
1460 +CONFIG_USB_STORAGE_ALAUDA=m
1461 +CONFIG_USB_STORAGE_ONETOUCH=m
1462 +CONFIG_USB_STORAGE_KARMA=m
1463 +CONFIG_USB_STORAGE_CYPRESS_ATACB=m
1464 +CONFIG_USB_STORAGE_ENE_UB6250=m
1465 +CONFIG_USB_UAS=y
1466 +CONFIG_USB_LIBUSUAL=y
1467 +CONFIG_USB_MDC800=m
1468 +CONFIG_USB_MICROTEK=m
1469 +CONFIG_USB_SERIAL=m
1470 +CONFIG_USB_SERIAL_GENERIC=y
1471 +CONFIG_USB_SERIAL_AIRCABLE=m
1472 +CONFIG_USB_SERIAL_ARK3116=m
1473 +CONFIG_USB_SERIAL_BELKIN=m
1474 +CONFIG_USB_SERIAL_CH341=m
1475 +CONFIG_USB_SERIAL_WHITEHEAT=m
1476 +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
1477 +CONFIG_USB_SERIAL_CP210X=m
1478 +CONFIG_USB_SERIAL_CYPRESS_M8=m
1479 +CONFIG_USB_SERIAL_EMPEG=m
1480 +CONFIG_USB_SERIAL_FTDI_SIO=m
1481 +CONFIG_USB_SERIAL_FUNSOFT=m
1482 +CONFIG_USB_SERIAL_VISOR=m
1483 +CONFIG_USB_SERIAL_IPAQ=m
1484 +CONFIG_USB_SERIAL_IR=m
1485 +CONFIG_USB_SERIAL_EDGEPORT=m
1486 +CONFIG_USB_SERIAL_EDGEPORT_TI=m
1487 +CONFIG_USB_SERIAL_GARMIN=m
1488 +CONFIG_USB_SERIAL_IPW=m
1489 +CONFIG_USB_SERIAL_IUU=m
1490 +CONFIG_USB_SERIAL_KEYSPAN_PDA=m
1491 +CONFIG_USB_SERIAL_KEYSPAN=m
1492 +CONFIG_USB_SERIAL_KLSI=m
1493 +CONFIG_USB_SERIAL_KOBIL_SCT=m
1494 +CONFIG_USB_SERIAL_MCT_U232=m
1495 +CONFIG_USB_SERIAL_MOS7720=m
1496 +CONFIG_USB_SERIAL_MOS7840=m
1497 +CONFIG_USB_SERIAL_MOTOROLA=m
1498 +CONFIG_USB_SERIAL_NAVMAN=m
1499 +CONFIG_USB_SERIAL_PL2303=m
1500 +CONFIG_USB_SERIAL_OTI6858=m
1501 +CONFIG_USB_SERIAL_QCAUX=m
1502 +CONFIG_USB_SERIAL_QUALCOMM=m
1503 +CONFIG_USB_SERIAL_SPCP8X5=m
1504 +CONFIG_USB_SERIAL_HP4X=m
1505 +CONFIG_USB_SERIAL_SAFE=m
1506 +CONFIG_USB_SERIAL_SIEMENS_MPI=m
1507 +CONFIG_USB_SERIAL_SIERRAWIRELESS=m
1508 +CONFIG_USB_SERIAL_SYMBOL=m
1509 +CONFIG_USB_SERIAL_TI=m
1510 +CONFIG_USB_SERIAL_CYBERJACK=m
1511 +CONFIG_USB_SERIAL_XIRCOM=m
1512 +CONFIG_USB_SERIAL_OPTION=m
1513 +CONFIG_USB_SERIAL_OMNINET=m
1514 +CONFIG_USB_SERIAL_OPTICON=m
1515 +CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m
1516 +CONFIG_USB_SERIAL_ZIO=m
1517 +CONFIG_USB_SERIAL_SSU100=m
1518 +CONFIG_USB_SERIAL_DEBUG=m
1519 +CONFIG_USB_EMI62=m
1520 +CONFIG_USB_EMI26=m
1521 +CONFIG_USB_ADUTUX=m
1522 +CONFIG_USB_SEVSEG=m
1523 +CONFIG_USB_RIO500=m
1524 +CONFIG_USB_LEGOTOWER=m
1525 +CONFIG_USB_LCD=m
1526 +CONFIG_USB_LED=m
1527 +CONFIG_USB_CYPRESS_CY7C63=m
1528 +CONFIG_USB_CYTHERM=m
1529 +CONFIG_USB_IDMOUSE=m
1530 +CONFIG_USB_FTDI_ELAN=m
1531 +CONFIG_USB_APPLEDISPLAY=m
1532 +CONFIG_USB_LD=m
1533 +CONFIG_USB_TRANCEVIBRATOR=m
1534 +CONFIG_USB_IOWARRIOR=m
1535 +CONFIG_USB_TEST=m
1536 +CONFIG_USB_ISIGHTFW=m
1537 +CONFIG_USB_YUREX=m
1538 +CONFIG_MMC=y
1539 +CONFIG_MMC_SDHCI=y
1540 +CONFIG_MMC_SDHCI_PLTFM=y
1541 +CONFIG_MMC_SDHCI_BCM2708=y
1542 +CONFIG_MMC_SDHCI_BCM2708_DMA=y
1543 +CONFIG_LEDS_GPIO=y
1544 +CONFIG_LEDS_TRIGGER_TIMER=m
1545 +CONFIG_LEDS_TRIGGER_HEARTBEAT=m
1546 +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
1547 +CONFIG_UIO=m
1548 +CONFIG_UIO_PDRV=m
1549 +CONFIG_UIO_PDRV_GENIRQ=m
1550 +# CONFIG_IOMMU_SUPPORT is not set
1551 +CONFIG_EXT4_FS=y
1552 +CONFIG_EXT4_FS_POSIX_ACL=y
1553 +CONFIG_EXT4_FS_SECURITY=y
1554 +CONFIG_REISERFS_FS=m
1555 +CONFIG_REISERFS_FS_XATTR=y
1556 +CONFIG_REISERFS_FS_POSIX_ACL=y
1557 +CONFIG_REISERFS_FS_SECURITY=y
1558 +CONFIG_JFS_FS=m
1559 +CONFIG_JFS_POSIX_ACL=y
1560 +CONFIG_JFS_SECURITY=y
1561 +CONFIG_JFS_STATISTICS=y
1562 +CONFIG_XFS_FS=m
1563 +CONFIG_XFS_QUOTA=y
1564 +CONFIG_XFS_POSIX_ACL=y
1565 +CONFIG_XFS_RT=y
1566 +CONFIG_GFS2_FS=m
1567 +CONFIG_OCFS2_FS=m
1568 +CONFIG_BTRFS_FS=m
1569 +CONFIG_BTRFS_FS_POSIX_ACL=y
1570 +CONFIG_NILFS2_FS=m
1571 +CONFIG_FANOTIFY=y
1572 +CONFIG_AUTOFS4_FS=y
1573 +CONFIG_FUSE_FS=m
1574 +CONFIG_CUSE=m
1575 +CONFIG_FSCACHE=y
1576 +CONFIG_FSCACHE_STATS=y
1577 +CONFIG_FSCACHE_HISTOGRAM=y
1578 +CONFIG_CACHEFILES=y
1579 +CONFIG_ISO9660_FS=m
1580 +CONFIG_JOLIET=y
1581 +CONFIG_ZISOFS=y
1582 +CONFIG_UDF_FS=m
1583 +CONFIG_MSDOS_FS=y
1584 +CONFIG_VFAT_FS=y
1585 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
1586 +CONFIG_NTFS_FS=m
1587 +CONFIG_TMPFS=y
1588 +CONFIG_TMPFS_POSIX_ACL=y
1589 +CONFIG_CONFIGFS_FS=y
1590 +CONFIG_SQUASHFS=m
1591 +CONFIG_SQUASHFS_XATTR=y
1592 +CONFIG_SQUASHFS_LZO=y
1593 +CONFIG_SQUASHFS_XZ=y
1594 +CONFIG_NFS_FS=y
1595 +CONFIG_NFS_V3=y
1596 +CONFIG_NFS_V3_ACL=y
1597 +CONFIG_NFS_V4=y
1598 +CONFIG_ROOT_NFS=y
1599 +CONFIG_NFS_FSCACHE=y
1600 +CONFIG_CIFS=m
1601 +CONFIG_CIFS_WEAK_PW_HASH=y
1602 +CONFIG_CIFS_XATTR=y
1603 +CONFIG_CIFS_POSIX=y
1604 +CONFIG_9P_FS=m
1605 +CONFIG_9P_FS_POSIX_ACL=y
1606 +CONFIG_PARTITION_ADVANCED=y
1607 +CONFIG_MAC_PARTITION=y
1608 +CONFIG_EFI_PARTITION=y
1609 +CONFIG_NLS_DEFAULT="utf8"
1610 +CONFIG_NLS_CODEPAGE_437=y
1611 +CONFIG_NLS_CODEPAGE_737=m
1612 +CONFIG_NLS_CODEPAGE_775=m
1613 +CONFIG_NLS_CODEPAGE_850=m
1614 +CONFIG_NLS_CODEPAGE_852=m
1615 +CONFIG_NLS_CODEPAGE_855=m
1616 +CONFIG_NLS_CODEPAGE_857=m
1617 +CONFIG_NLS_CODEPAGE_860=m
1618 +CONFIG_NLS_CODEPAGE_861=m
1619 +CONFIG_NLS_CODEPAGE_862=m
1620 +CONFIG_NLS_CODEPAGE_863=m
1621 +CONFIG_NLS_CODEPAGE_864=m
1622 +CONFIG_NLS_CODEPAGE_865=m
1623 +CONFIG_NLS_CODEPAGE_866=m
1624 +CONFIG_NLS_CODEPAGE_869=m
1625 +CONFIG_NLS_CODEPAGE_936=m
1626 +CONFIG_NLS_CODEPAGE_950=m
1627 +CONFIG_NLS_CODEPAGE_932=m
1628 +CONFIG_NLS_CODEPAGE_949=m
1629 +CONFIG_NLS_CODEPAGE_874=m
1630 +CONFIG_NLS_ISO8859_8=m
1631 +CONFIG_NLS_CODEPAGE_1250=m
1632 +CONFIG_NLS_CODEPAGE_1251=m
1633 +CONFIG_NLS_ASCII=y
1634 +CONFIG_NLS_ISO8859_1=m
1635 +CONFIG_NLS_ISO8859_2=m
1636 +CONFIG_NLS_ISO8859_3=m
1637 +CONFIG_NLS_ISO8859_4=m
1638 +CONFIG_NLS_ISO8859_5=m
1639 +CONFIG_NLS_ISO8859_6=m
1640 +CONFIG_NLS_ISO8859_7=m
1641 +CONFIG_NLS_ISO8859_9=m
1642 +CONFIG_NLS_ISO8859_13=m
1643 +CONFIG_NLS_ISO8859_14=m
1644 +CONFIG_NLS_ISO8859_15=m
1645 +CONFIG_NLS_KOI8_R=m
1646 +CONFIG_NLS_KOI8_U=m
1647 +CONFIG_NLS_UTF8=m
1648 +CONFIG_PRINTK_TIME=y
1649 +CONFIG_DETECT_HUNG_TASK=y
1650 +CONFIG_TIMER_STATS=y
1651 +CONFIG_DEBUG_STACK_USAGE=y
1652 +CONFIG_DEBUG_INFO=y
1653 +CONFIG_DEBUG_MEMORY_INIT=y
1654 +CONFIG_BOOT_PRINTK_DELAY=y
1655 +CONFIG_LATENCYTOP=y
1656 +CONFIG_SYSCTL_SYSCALL_CHECK=y
1657 +CONFIG_IRQSOFF_TRACER=y
1658 +CONFIG_SCHED_TRACER=y
1659 +CONFIG_STACK_TRACER=y
1660 +CONFIG_BLK_DEV_IO_TRACE=y
1661 +CONFIG_FUNCTION_PROFILER=y
1662 +CONFIG_KGDB=y
1663 +CONFIG_KGDB_KDB=y
1664 +CONFIG_KDB_KEYBOARD=y
1665 +CONFIG_STRICT_DEVMEM=y
1666 +CONFIG_CRYPTO_AUTHENC=m
1667 +CONFIG_CRYPTO_SEQIV=m
1668 +CONFIG_CRYPTO_CBC=y
1669 +CONFIG_CRYPTO_HMAC=y
1670 +CONFIG_CRYPTO_XCBC=m
1671 +CONFIG_CRYPTO_MD5=y
1672 +CONFIG_CRYPTO_SHA1=y
1673 +CONFIG_CRYPTO_SHA256=m
1674 +CONFIG_CRYPTO_SHA512=m
1675 +CONFIG_CRYPTO_TGR192=m
1676 +CONFIG_CRYPTO_WP512=m
1677 +CONFIG_CRYPTO_CAST5=m
1678 +CONFIG_CRYPTO_DES=y
1679 +CONFIG_CRYPTO_DEFLATE=m
1680 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
1681 +# CONFIG_CRYPTO_HW is not set
1682 +CONFIG_CRC_ITU_T=y
1683 +CONFIG_LIBCRC32C=y
1684 --- a/arch/arm/kernel/process.c
1685 +++ b/arch/arm/kernel/process.c
1686 @@ -176,6 +176,16 @@ void arch_cpu_idle(void)
1687 default_idle();
1688 }
1689
1690 +char bcm2708_reboot_mode = 'h';
1691 +
1692 +int __init reboot_setup(char *str)
1693 +{
1694 + bcm2708_reboot_mode = str[0];
1695 + return 1;
1696 +}
1697 +
1698 +__setup("reboot=", reboot_setup);
1699 +
1700 /*
1701 * Called by kexec, immediately prior to machine_kexec().
1702 *
1703 --- /dev/null
1704 +++ b/arch/arm/mach-bcm2708/Kconfig
1705 @@ -0,0 +1,34 @@
1706 +menu "Broadcom BCM2708 Implementations"
1707 + depends on ARCH_BCM2708
1708 +
1709 +config MACH_BCM2708
1710 + bool "Broadcom BCM2708 Development Platform"
1711 + select NEED_MACH_MEMORY_H
1712 + select NEED_MACH_IO_H
1713 + select CPU_V6
1714 + help
1715 + Include support for the Broadcom(R) BCM2708 platform.
1716 +
1717 +config BCM2708_GPIO
1718 + bool "BCM2708 gpio support"
1719 + depends on MACH_BCM2708
1720 + select ARCH_REQUIRE_GPIOLIB
1721 + default y
1722 + help
1723 + Include support for the Broadcom(R) BCM2708 gpio.
1724 +
1725 +config BCM2708_VCMEM
1726 + bool "Videocore Memory"
1727 + depends on MACH_BCM2708
1728 + default y
1729 + help
1730 + Helper for videocore memory access and total size allocation.
1731 +
1732 +config BCM2708_NOL2CACHE
1733 + bool "Videocore L2 cache disable"
1734 + depends on MACH_BCM2708
1735 + default n
1736 + help
1737 + Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt.
1738 +
1739 +endmenu
1740 --- /dev/null
1741 +++ b/arch/arm/mach-bcm2708/Makefile
1742 @@ -0,0 +1,7 @@
1743 +#
1744 +# Makefile for the linux kernel.
1745 +#
1746 +
1747 +obj-$(CONFIG_MACH_BCM2708) += clock.o bcm2708.o armctrl.o vcio.o power.o dma.o
1748 +obj-$(CONFIG_BCM2708_GPIO) += bcm2708_gpio.o
1749 +obj-$(CONFIG_BCM2708_VCMEM) += vc_mem.o
1750 --- /dev/null
1751 +++ b/arch/arm/mach-bcm2708/Makefile.boot
1752 @@ -0,0 +1,3 @@
1753 + zreladdr-y := 0x00008000
1754 +params_phys-y := 0x00000100
1755 +initrd_phys-y := 0x00800000
1756 --- /dev/null
1757 +++ b/arch/arm/mach-bcm2708/armctrl.c
1758 @@ -0,0 +1,208 @@
1759 +/*
1760 + * linux/arch/arm/mach-bcm2708/armctrl.c
1761 + *
1762 + * Copyright (C) 2010 Broadcom
1763 + *
1764 + * This program is free software; you can redistribute it and/or modify
1765 + * it under the terms of the GNU General Public License as published by
1766 + * the Free Software Foundation; either version 2 of the License, or
1767 + * (at your option) any later version.
1768 + *
1769 + * This program is distributed in the hope that it will be useful,
1770 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1771 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1772 + * GNU General Public License for more details.
1773 + *
1774 + * You should have received a copy of the GNU General Public License
1775 + * along with this program; if not, write to the Free Software
1776 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1777 + */
1778 +#include <linux/init.h>
1779 +#include <linux/list.h>
1780 +#include <linux/io.h>
1781 +#include <linux/version.h>
1782 +#include <linux/syscore_ops.h>
1783 +#include <linux/interrupt.h>
1784 +
1785 +#include <asm/mach/irq.h>
1786 +#include <mach/hardware.h>
1787 +#include "armctrl.h"
1788 +
1789 +/* For support of kernels >= 3.0 assume only one VIC for now*/
1790 +static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = {
1791 + INTERRUPT_VC_JPEG,
1792 + INTERRUPT_VC_USB,
1793 + INTERRUPT_VC_3D,
1794 + INTERRUPT_VC_DMA2,
1795 + INTERRUPT_VC_DMA3,
1796 + INTERRUPT_VC_I2C,
1797 + INTERRUPT_VC_SPI,
1798 + INTERRUPT_VC_I2SPCM,
1799 + INTERRUPT_VC_SDIO,
1800 + INTERRUPT_VC_UART,
1801 + INTERRUPT_VC_ARASANSDIO
1802 +};
1803 +
1804 +static void armctrl_mask_irq(struct irq_data *d)
1805 +{
1806 + static const unsigned int disables[4] = {
1807 + ARM_IRQ_DIBL1,
1808 + ARM_IRQ_DIBL2,
1809 + ARM_IRQ_DIBL3,
1810 + 0
1811 + };
1812 +
1813 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
1814 + writel(1 << (data & 0x1f), __io_address(disables[(data >> 5) & 0x3]));
1815 +}
1816 +
1817 +static void armctrl_unmask_irq(struct irq_data *d)
1818 +{
1819 + static const unsigned int enables[4] = {
1820 + ARM_IRQ_ENBL1,
1821 + ARM_IRQ_ENBL2,
1822 + ARM_IRQ_ENBL3,
1823 + 0
1824 + };
1825 +
1826 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
1827 + writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3]));
1828 +}
1829 +
1830 +#if defined(CONFIG_PM)
1831 +
1832 +/* for kernels 3.xx use the new syscore_ops apis but for older kernels use the sys dev class */
1833 +
1834 +/* Static defines
1835 + * struct armctrl_device - VIC PM device (< 3.xx)
1836 + * @sysdev: The system device which is registered. (< 3.xx)
1837 + * @irq: The IRQ number for the base of the VIC.
1838 + * @base: The register base for the VIC.
1839 + * @resume_sources: A bitmask of interrupts for resume.
1840 + * @resume_irqs: The IRQs enabled for resume.
1841 + * @int_select: Save for VIC_INT_SELECT.
1842 + * @int_enable: Save for VIC_INT_ENABLE.
1843 + * @soft_int: Save for VIC_INT_SOFT.
1844 + * @protect: Save for VIC_PROTECT.
1845 + */
1846 +struct armctrl_info {
1847 + void __iomem *base;
1848 + int irq;
1849 + u32 resume_sources;
1850 + u32 resume_irqs;
1851 + u32 int_select;
1852 + u32 int_enable;
1853 + u32 soft_int;
1854 + u32 protect;
1855 +} armctrl;
1856 +
1857 +static int armctrl_suspend(void)
1858 +{
1859 + return 0;
1860 +}
1861 +
1862 +static void armctrl_resume(void)
1863 +{
1864 + return;
1865 +}
1866 +
1867 +/**
1868 + * armctrl_pm_register - Register a VIC for later power management control
1869 + * @base: The base address of the VIC.
1870 + * @irq: The base IRQ for the VIC.
1871 + * @resume_sources: bitmask of interrupts allowed for resume sources.
1872 + *
1873 + * For older kernels (< 3.xx) do -
1874 + * Register the VIC with the system device tree so that it can be notified
1875 + * of suspend and resume requests and ensure that the correct actions are
1876 + * taken to re-instate the settings on resume.
1877 + */
1878 +static void __init armctrl_pm_register(void __iomem * base, unsigned int irq,
1879 + u32 resume_sources)
1880 +{
1881 + armctrl.base = base;
1882 + armctrl.resume_sources = resume_sources;
1883 + armctrl.irq = irq;
1884 +}
1885 +
1886 +static int armctrl_set_wake(struct irq_data *d, unsigned int on)
1887 +{
1888 + unsigned int off = d->irq & 31;
1889 + u32 bit = 1 << off;
1890 +
1891 + if (!(bit & armctrl.resume_sources))
1892 + return -EINVAL;
1893 +
1894 + if (on)
1895 + armctrl.resume_irqs |= bit;
1896 + else
1897 + armctrl.resume_irqs &= ~bit;
1898 +
1899 + return 0;
1900 +}
1901 +
1902 +#else
1903 +static inline void armctrl_pm_register(void __iomem * base, unsigned int irq,
1904 + u32 arg1)
1905 +{
1906 +}
1907 +
1908 +#define armctrl_suspend NULL
1909 +#define armctrl_resume NULL
1910 +#define armctrl_set_wake NULL
1911 +#endif /* CONFIG_PM */
1912 +
1913 +static struct syscore_ops armctrl_syscore_ops = {
1914 + .suspend = armctrl_suspend,
1915 + .resume = armctrl_resume,
1916 +};
1917 +
1918 +/**
1919 + * armctrl_syscore_init - initicall to register VIC pm functions
1920 + *
1921 + * This is called via late_initcall() to register
1922 + * the resources for the VICs due to the early
1923 + * nature of the VIC's registration.
1924 +*/
1925 +static int __init armctrl_syscore_init(void)
1926 +{
1927 + register_syscore_ops(&armctrl_syscore_ops);
1928 + return 0;
1929 +}
1930 +
1931 +late_initcall(armctrl_syscore_init);
1932 +
1933 +static struct irq_chip armctrl_chip = {
1934 + .name = "ARMCTRL",
1935 + .irq_ack = armctrl_mask_irq,
1936 + .irq_mask = armctrl_mask_irq,
1937 + .irq_unmask = armctrl_unmask_irq,
1938 + .irq_set_wake = armctrl_set_wake,
1939 +};
1940 +
1941 +/**
1942 + * armctrl_init - initialise a vectored interrupt controller
1943 + * @base: iomem base address
1944 + * @irq_start: starting interrupt number, must be muliple of 32
1945 + * @armctrl_sources: bitmask of interrupt sources to allow
1946 + * @resume_sources: bitmask of interrupt sources to allow for resume
1947 + */
1948 +int __init armctrl_init(void __iomem * base, unsigned int irq_start,
1949 + u32 armctrl_sources, u32 resume_sources)
1950 +{
1951 + unsigned int irq;
1952 +
1953 + for (irq = 0; irq < NR_IRQS; irq++) {
1954 + unsigned int data = irq;
1955 + if (irq >= INTERRUPT_JPEG && irq <= INTERRUPT_ARASANSDIO)
1956 + data = remap_irqs[irq - INTERRUPT_JPEG];
1957 +
1958 + irq_set_chip(irq, &armctrl_chip);
1959 + irq_set_chip_data(irq, (void *)data);
1960 + irq_set_handler(irq, handle_level_irq);
1961 + set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_DISABLED);
1962 + }
1963 +
1964 + armctrl_pm_register(base, irq_start, resume_sources);
1965 + return 0;
1966 +}
1967 --- /dev/null
1968 +++ b/arch/arm/mach-bcm2708/armctrl.h
1969 @@ -0,0 +1,27 @@
1970 +/*
1971 + * linux/arch/arm/mach-bcm2708/armctrl.h
1972 + *
1973 + * Copyright (C) 2010 Broadcom
1974 + *
1975 + * This program is free software; you can redistribute it and/or modify
1976 + * it under the terms of the GNU General Public License as published by
1977 + * the Free Software Foundation; either version 2 of the License, or
1978 + * (at your option) any later version.
1979 + *
1980 + * This program is distributed in the hope that it will be useful,
1981 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1982 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1983 + * GNU General Public License for more details.
1984 + *
1985 + * You should have received a copy of the GNU General Public License
1986 + * along with this program; if not, write to the Free Software
1987 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1988 + */
1989 +
1990 +#ifndef __BCM2708_ARMCTRL_H
1991 +#define __BCM2708_ARMCTRL_H
1992 +
1993 +extern int __init armctrl_init(void __iomem * base, unsigned int irq_start,
1994 + u32 armctrl_sources, u32 resume_sources);
1995 +
1996 +#endif
1997 --- /dev/null
1998 +++ b/arch/arm/mach-bcm2708/bcm2708.c
1999 @@ -0,0 +1,720 @@
2000 +/*
2001 + * linux/arch/arm/mach-bcm2708/bcm2708.c
2002 + *
2003 + * Copyright (C) 2010 Broadcom
2004 + *
2005 + * This program is free software; you can redistribute it and/or modify
2006 + * it under the terms of the GNU General Public License as published by
2007 + * the Free Software Foundation; either version 2 of the License, or
2008 + * (at your option) any later version.
2009 + *
2010 + * This program is distributed in the hope that it will be useful,
2011 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2012 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2013 + * GNU General Public License for more details.
2014 + *
2015 + * You should have received a copy of the GNU General Public License
2016 + * along with this program; if not, write to the Free Software
2017 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2018 + */
2019 +
2020 +#include <linux/init.h>
2021 +#include <linux/device.h>
2022 +#include <linux/dma-mapping.h>
2023 +#include <linux/serial_8250.h>
2024 +#include <linux/platform_device.h>
2025 +#include <linux/syscore_ops.h>
2026 +#include <linux/interrupt.h>
2027 +#include <linux/amba/bus.h>
2028 +#include <linux/amba/clcd.h>
2029 +#include <linux/clockchips.h>
2030 +#include <linux/cnt32_to_63.h>
2031 +#include <linux/io.h>
2032 +#include <linux/module.h>
2033 +
2034 +#include <linux/version.h>
2035 +#include <linux/clkdev.h>
2036 +#include <asm/system.h>
2037 +#include <mach/hardware.h>
2038 +#include <asm/irq.h>
2039 +#include <linux/leds.h>
2040 +#include <asm/mach-types.h>
2041 +#include <linux/sched_clock.h>
2042 +
2043 +#include <asm/mach/arch.h>
2044 +#include <asm/mach/flash.h>
2045 +#include <asm/mach/irq.h>
2046 +#include <asm/mach/time.h>
2047 +#include <asm/mach/map.h>
2048 +
2049 +#include <mach/timex.h>
2050 +#include <mach/dma.h>
2051 +#include <mach/vcio.h>
2052 +#include <mach/system.h>
2053 +
2054 +#include <linux/delay.h>
2055 +
2056 +#include "bcm2708.h"
2057 +#include "armctrl.h"
2058 +#include "clock.h"
2059 +
2060 +#ifdef CONFIG_BCM_VC_CMA
2061 +#include <linux/broadcom/vc_cma.h>
2062 +#endif
2063 +
2064 +
2065 +/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to
2066 + * give us IO access only to 64Mbytes of physical memory (26 bits). We could
2067 + * represent this window by setting our dmamasks to 26 bits but, in fact
2068 + * we're not going to use addresses outside this range (they're not in real
2069 + * memory) so we don't bother.
2070 + *
2071 + * In the future we might include code to use this IOMMU to remap other
2072 + * physical addresses onto VideoCore memory then the use of 32-bits would be
2073 + * more legitimate.
2074 + */
2075 +#define DMA_MASK_BITS_COMMON 32
2076 +
2077 +/* command line parameters */
2078 +static unsigned boardrev, serial;
2079 +static unsigned uart_clock;
2080 +static unsigned disk_led_gpio = 16;
2081 +static unsigned disk_led_active_low = 1;
2082 +static unsigned reboot_part = 0;
2083 +
2084 +static void __init bcm2708_init_led(void);
2085 +
2086 +void __init bcm2708_init_irq(void)
2087 +{
2088 + armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0);
2089 +}
2090 +
2091 +static struct map_desc bcm2708_io_desc[] __initdata = {
2092 + {
2093 + .virtual = IO_ADDRESS(ARMCTRL_BASE),
2094 + .pfn = __phys_to_pfn(ARMCTRL_BASE),
2095 + .length = SZ_4K,
2096 + .type = MT_DEVICE},
2097 + {
2098 + .virtual = IO_ADDRESS(UART0_BASE),
2099 + .pfn = __phys_to_pfn(UART0_BASE),
2100 + .length = SZ_4K,
2101 + .type = MT_DEVICE},
2102 + {
2103 + .virtual = IO_ADDRESS(UART1_BASE),
2104 + .pfn = __phys_to_pfn(UART1_BASE),
2105 + .length = SZ_4K,
2106 + .type = MT_DEVICE},
2107 + {
2108 + .virtual = IO_ADDRESS(DMA_BASE),
2109 + .pfn = __phys_to_pfn(DMA_BASE),
2110 + .length = SZ_4K,
2111 + .type = MT_DEVICE},
2112 + {
2113 + .virtual = IO_ADDRESS(MCORE_BASE),
2114 + .pfn = __phys_to_pfn(MCORE_BASE),
2115 + .length = SZ_4K,
2116 + .type = MT_DEVICE},
2117 + {
2118 + .virtual = IO_ADDRESS(ST_BASE),
2119 + .pfn = __phys_to_pfn(ST_BASE),
2120 + .length = SZ_4K,
2121 + .type = MT_DEVICE},
2122 + {
2123 + .virtual = IO_ADDRESS(USB_BASE),
2124 + .pfn = __phys_to_pfn(USB_BASE),
2125 + .length = SZ_128K,
2126 + .type = MT_DEVICE},
2127 + {
2128 + .virtual = IO_ADDRESS(PM_BASE),
2129 + .pfn = __phys_to_pfn(PM_BASE),
2130 + .length = SZ_4K,
2131 + .type = MT_DEVICE},
2132 + {
2133 + .virtual = IO_ADDRESS(GPIO_BASE),
2134 + .pfn = __phys_to_pfn(GPIO_BASE),
2135 + .length = SZ_4K,
2136 + .type = MT_DEVICE}
2137 +};
2138 +
2139 +void __init bcm2708_map_io(void)
2140 +{
2141 + iotable_init(bcm2708_io_desc, ARRAY_SIZE(bcm2708_io_desc));
2142 +}
2143 +
2144 +/* The STC is a free running counter that increments at the rate of 1MHz */
2145 +#define STC_FREQ_HZ 1000000
2146 +
2147 +static inline uint32_t timer_read(void)
2148 +{
2149 + /* STC: a free running counter that increments at the rate of 1MHz */
2150 + return readl(__io_address(ST_BASE + 0x04));
2151 +}
2152 +
2153 +static unsigned long bcm2708_read_current_timer(void)
2154 +{
2155 + return timer_read();
2156 +}
2157 +
2158 +static u32 notrace bcm2708_read_sched_clock(void)
2159 +{
2160 + return timer_read();
2161 +}
2162 +
2163 +static cycle_t clksrc_read(struct clocksource *cs)
2164 +{
2165 + return timer_read();
2166 +}
2167 +
2168 +static struct clocksource clocksource_stc = {
2169 + .name = "stc",
2170 + .rating = 300,
2171 + .read = clksrc_read,
2172 + .mask = CLOCKSOURCE_MASK(32),
2173 + .flags = CLOCK_SOURCE_IS_CONTINUOUS,
2174 +};
2175 +
2176 +unsigned long frc_clock_ticks32(void)
2177 +{
2178 + return timer_read();
2179 +}
2180 +
2181 +static void __init bcm2708_clocksource_init(void)
2182 +{
2183 + if (clocksource_register_hz(&clocksource_stc, STC_FREQ_HZ)) {
2184 + printk(KERN_ERR "timer: failed to initialize clock "
2185 + "source %s\n", clocksource_stc.name);
2186 + }
2187 +}
2188 +
2189 +
2190 +/*
2191 + * These are fixed clocks.
2192 + */
2193 +static struct clk ref24_clk = {
2194 + .rate = UART0_CLOCK, /* The UART is clocked at 3MHz via APB_CLK */
2195 +};
2196 +
2197 +static struct clk osc_clk = {
2198 +#ifdef CONFIG_ARCH_BCM2708_CHIPIT
2199 + .rate = 27000000,
2200 +#else
2201 + .rate = 500000000, /* ARM clock is set from the VideoCore booter */
2202 +#endif
2203 +};
2204 +
2205 +/* warning - the USB needs a clock > 34MHz */
2206 +
2207 +#ifdef CONFIG_MMC_BCM2708
2208 +static struct clk sdhost_clk = {
2209 +#ifdef CONFIG_ARCH_BCM2708_CHIPIT
2210 + .rate = 4000000, /* 4MHz */
2211 +#else
2212 + .rate = 250000000, /* 250MHz */
2213 +#endif
2214 +};
2215 +#endif
2216 +
2217 +static struct clk_lookup lookups[] = {
2218 + { /* UART0 */
2219 + .dev_id = "dev:f1",
2220 + .clk = &ref24_clk,
2221 + },
2222 + { /* USB */
2223 + .dev_id = "bcm2708_usb",
2224 + .clk = &osc_clk,
2225 + }
2226 +};
2227 +
2228 +#define UART0_IRQ { IRQ_UART, 0 /*NO_IRQ*/ }
2229 +#define UART0_DMA { 15, 14 }
2230 +
2231 +AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
2232 +
2233 +static struct amba_device *amba_devs[] __initdata = {
2234 + &uart0_device,
2235 +};
2236 +
2237 +static struct resource bcm2708_dmaman_resources[] = {
2238 + {
2239 + .start = DMA_BASE,
2240 + .end = DMA_BASE + SZ_4K - 1,
2241 + .flags = IORESOURCE_MEM,
2242 + }
2243 +};
2244 +
2245 +static struct platform_device bcm2708_dmaman_device = {
2246 + .name = BCM_DMAMAN_DRIVER_NAME,
2247 + .id = 0, /* first bcm2708_dma */
2248 + .resource = bcm2708_dmaman_resources,
2249 + .num_resources = ARRAY_SIZE(bcm2708_dmaman_resources),
2250 +};
2251 +
2252 +static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2253 +
2254 +static struct platform_device bcm2708_fb_device = {
2255 + .name = "bcm2708_fb",
2256 + .id = -1, /* only one bcm2708_fb */
2257 + .resource = NULL,
2258 + .num_resources = 0,
2259 + .dev = {
2260 + .dma_mask = &fb_dmamask,
2261 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
2262 + },
2263 +};
2264 +
2265 +static struct plat_serial8250_port bcm2708_uart1_platform_data[] = {
2266 + {
2267 + .mapbase = UART1_BASE + 0x40,
2268 + .irq = IRQ_AUX,
2269 + .uartclk = 125000000,
2270 + .regshift = 2,
2271 + .iotype = UPIO_MEM,
2272 + .flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_SKIP_TEST,
2273 + .type = PORT_8250,
2274 + },
2275 + {},
2276 +};
2277 +
2278 +static struct platform_device bcm2708_uart1_device = {
2279 + .name = "serial8250",
2280 + .id = PLAT8250_DEV_PLATFORM,
2281 + .dev = {
2282 + .platform_data = bcm2708_uart1_platform_data,
2283 + },
2284 +};
2285 +
2286 +static struct resource bcm2708_usb_resources[] = {
2287 + [0] = {
2288 + .start = USB_BASE,
2289 + .end = USB_BASE + SZ_128K - 1,
2290 + .flags = IORESOURCE_MEM,
2291 + },
2292 + [1] = {
2293 + .start = IRQ_USB,
2294 + .end = IRQ_USB,
2295 + .flags = IORESOURCE_IRQ,
2296 + },
2297 +};
2298 +
2299 +static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2300 +
2301 +static struct platform_device bcm2708_usb_device = {
2302 + .name = "bcm2708_usb",
2303 + .id = -1, /* only one bcm2708_usb */
2304 + .resource = bcm2708_usb_resources,
2305 + .num_resources = ARRAY_SIZE(bcm2708_usb_resources),
2306 + .dev = {
2307 + .dma_mask = &usb_dmamask,
2308 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
2309 + },
2310 +};
2311 +
2312 +static struct resource bcm2708_vcio_resources[] = {
2313 + [0] = { /* mailbox/semaphore/doorbell access */
2314 + .start = MCORE_BASE,
2315 + .end = MCORE_BASE + SZ_4K - 1,
2316 + .flags = IORESOURCE_MEM,
2317 + },
2318 +};
2319 +
2320 +static u64 vcio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2321 +
2322 +static struct platform_device bcm2708_vcio_device = {
2323 + .name = BCM_VCIO_DRIVER_NAME,
2324 + .id = -1, /* only one VideoCore I/O area */
2325 + .resource = bcm2708_vcio_resources,
2326 + .num_resources = ARRAY_SIZE(bcm2708_vcio_resources),
2327 + .dev = {
2328 + .dma_mask = &vcio_dmamask,
2329 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
2330 + },
2331 +};
2332 +
2333 +#ifdef CONFIG_BCM2708_GPIO
2334 +#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio"
2335 +
2336 +static struct resource bcm2708_gpio_resources[] = {
2337 + [0] = { /* general purpose I/O */
2338 + .start = GPIO_BASE,
2339 + .end = GPIO_BASE + SZ_4K - 1,
2340 + .flags = IORESOURCE_MEM,
2341 + },
2342 +};
2343 +
2344 +static u64 gpio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2345 +
2346 +static struct platform_device bcm2708_gpio_device = {
2347 + .name = BCM_GPIO_DRIVER_NAME,
2348 + .id = -1, /* only one VideoCore I/O area */
2349 + .resource = bcm2708_gpio_resources,
2350 + .num_resources = ARRAY_SIZE(bcm2708_gpio_resources),
2351 + .dev = {
2352 + .dma_mask = &gpio_dmamask,
2353 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
2354 + },
2355 +};
2356 +#endif
2357 +
2358 +static struct resource bcm2708_systemtimer_resources[] = {
2359 + [0] = { /* system timer access */
2360 + .start = ST_BASE,
2361 + .end = ST_BASE + SZ_4K - 1,
2362 + .flags = IORESOURCE_MEM,
2363 + },
2364 + {
2365 + .start = IRQ_TIMER3,
2366 + .end = IRQ_TIMER3,
2367 + .flags = IORESOURCE_IRQ,
2368 + }
2369 +
2370 +};
2371 +
2372 +static u64 systemtimer_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2373 +
2374 +static struct platform_device bcm2708_systemtimer_device = {
2375 + .name = "bcm2708_systemtimer",
2376 + .id = -1, /* only one VideoCore I/O area */
2377 + .resource = bcm2708_systemtimer_resources,
2378 + .num_resources = ARRAY_SIZE(bcm2708_systemtimer_resources),
2379 + .dev = {
2380 + .dma_mask = &systemtimer_dmamask,
2381 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
2382 + },
2383 +};
2384 +
2385 +#ifdef CONFIG_MMC_SDHCI_BCM2708 /* Arasan emmc SD */
2386 +static struct resource bcm2708_emmc_resources[] = {
2387 + [0] = {
2388 + .start = EMMC_BASE,
2389 + .end = EMMC_BASE + SZ_256 - 1, /* we only need this area */
2390 + /* the memory map actually makes SZ_4K available */
2391 + .flags = IORESOURCE_MEM,
2392 + },
2393 + [1] = {
2394 + .start = IRQ_ARASANSDIO,
2395 + .end = IRQ_ARASANSDIO,
2396 + .flags = IORESOURCE_IRQ,
2397 + },
2398 +};
2399 +
2400 +static u64 bcm2708_emmc_dmamask = 0xffffffffUL;
2401 +
2402 +struct platform_device bcm2708_emmc_device = {
2403 + .name = "bcm2708_sdhci",
2404 + .id = 0,
2405 + .num_resources = ARRAY_SIZE(bcm2708_emmc_resources),
2406 + .resource = bcm2708_emmc_resources,
2407 + .dev = {
2408 + .dma_mask = &bcm2708_emmc_dmamask,
2409 + .coherent_dma_mask = 0xffffffffUL},
2410 +};
2411 +#endif /* CONFIG_MMC_SDHCI_BCM2708 */
2412 +
2413 +static struct resource bcm2708_powerman_resources[] = {
2414 + [0] = {
2415 + .start = PM_BASE,
2416 + .end = PM_BASE + SZ_256 - 1,
2417 + .flags = IORESOURCE_MEM,
2418 + },
2419 +};
2420 +
2421 +static u64 powerman_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2422 +
2423 +struct platform_device bcm2708_powerman_device = {
2424 + .name = "bcm2708_powerman",
2425 + .id = 0,
2426 + .num_resources = ARRAY_SIZE(bcm2708_powerman_resources),
2427 + .resource = bcm2708_powerman_resources,
2428 + .dev = {
2429 + .dma_mask = &powerman_dmamask,
2430 + .coherent_dma_mask = 0xffffffffUL},
2431 +};
2432 +
2433 +int __init bcm_register_device(struct platform_device *pdev)
2434 +{
2435 + int ret;
2436 +
2437 + ret = platform_device_register(pdev);
2438 + if (ret)
2439 + pr_debug("Unable to register platform device '%s': %d\n",
2440 + pdev->name, ret);
2441 +
2442 + return ret;
2443 +}
2444 +
2445 +int calc_rsts(int partition)
2446 +{
2447 + return PM_PASSWORD |
2448 + ((partition & (1 << 0)) << 0) |
2449 + ((partition & (1 << 1)) << 1) |
2450 + ((partition & (1 << 2)) << 2) |
2451 + ((partition & (1 << 3)) << 3) |
2452 + ((partition & (1 << 4)) << 4) |
2453 + ((partition & (1 << 5)) << 5);
2454 +}
2455 +
2456 +static void bcm2708_restart(enum reboot_mode mode, const char *cmd)
2457 +{
2458 + extern char bcm2708_reboot_mode;
2459 + uint32_t pm_rstc, pm_wdog;
2460 + uint32_t timeout = 10;
2461 + uint32_t pm_rsts = 0;
2462 +
2463 + if(bcm2708_reboot_mode == 'q')
2464 + {
2465 + // NOOBS < 1.3 booting with reboot=q
2466 + pm_rsts = readl(__io_address(PM_RSTS));
2467 + pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRQ_SET;
2468 + }
2469 + else if(bcm2708_reboot_mode == 'p')
2470 + {
2471 + // NOOBS < 1.3 halting
2472 + pm_rsts = readl(__io_address(PM_RSTS));
2473 + pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRH_SET;
2474 + }
2475 + else
2476 + {
2477 + pm_rsts = calc_rsts(reboot_part);
2478 + }
2479 +
2480 + writel(pm_rsts, __io_address(PM_RSTS));
2481 +
2482 + /* Setup watchdog for reset */
2483 + pm_rstc = readl(__io_address(PM_RSTC));
2484 +
2485 + pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0)
2486 + pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET;
2487 +
2488 + writel(pm_wdog, __io_address(PM_WDOG));
2489 + writel(pm_rstc, __io_address(PM_RSTC));
2490 +}
2491 +
2492 +/* We can't really power off, but if we do the normal reset scheme, and indicate to bootcode.bin not to reboot, then most of the chip will be powered off */
2493 +static void bcm2708_power_off(void)
2494 +{
2495 + extern char bcm2708_reboot_mode;
2496 + if(bcm2708_reboot_mode == 'q')
2497 + {
2498 + // NOOBS < v1.3
2499 + bcm2708_restart('p', "");
2500 + }
2501 + else
2502 + {
2503 + /* partition 63 is special code for HALT the bootloader knows not to boot*/
2504 + reboot_part = 63;
2505 + /* continue with normal reset mechanism */
2506 + bcm2708_restart(0, "");
2507 + }
2508 +}
2509 +
2510 +void __init bcm2708_init(void)
2511 +{
2512 + int i;
2513 +
2514 +#if defined(CONFIG_BCM_VC_CMA)
2515 + vc_cma_early_init();
2516 +#endif
2517 + printk("bcm2708.uart_clock = %d\n", uart_clock);
2518 + pm_power_off = bcm2708_power_off;
2519 +
2520 + if (uart_clock)
2521 + lookups[0].clk->rate = uart_clock;
2522 +
2523 + for (i = 0; i < ARRAY_SIZE(lookups); i++)
2524 + clkdev_add(&lookups[i]);
2525 +
2526 + bcm_register_device(&bcm2708_dmaman_device);
2527 + bcm_register_device(&bcm2708_vcio_device);
2528 +#ifdef CONFIG_BCM2708_GPIO
2529 + bcm_register_device(&bcm2708_gpio_device);
2530 +#endif
2531 + bcm_register_device(&bcm2708_systemtimer_device);
2532 + bcm_register_device(&bcm2708_fb_device);
2533 + bcm_register_device(&bcm2708_usb_device);
2534 + bcm_register_device(&bcm2708_uart1_device);
2535 + bcm_register_device(&bcm2708_powerman_device);
2536 +
2537 +#ifdef CONFIG_MMC_SDHCI_BCM2708
2538 + bcm_register_device(&bcm2708_emmc_device);
2539 +#endif
2540 + bcm2708_init_led();
2541 +
2542 + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
2543 + struct amba_device *d = amba_devs[i];
2544 + amba_device_register(d, &iomem_resource);
2545 + }
2546 + system_rev = boardrev;
2547 + system_serial_low = serial;
2548 +}
2549 +
2550 +static void timer_set_mode(enum clock_event_mode mode,
2551 + struct clock_event_device *clk)
2552 +{
2553 + switch (mode) {
2554 + case CLOCK_EVT_MODE_ONESHOT: /* Leave the timer disabled, .set_next_event will enable it */
2555 + case CLOCK_EVT_MODE_SHUTDOWN:
2556 + break;
2557 + case CLOCK_EVT_MODE_PERIODIC:
2558 +
2559 + case CLOCK_EVT_MODE_UNUSED:
2560 + case CLOCK_EVT_MODE_RESUME:
2561 +
2562 + default:
2563 + printk(KERN_ERR "timer_set_mode: unhandled mode:%d\n",
2564 + (int)mode);
2565 + break;
2566 + }
2567 +
2568 +}
2569 +
2570 +static int timer_set_next_event(unsigned long cycles,
2571 + struct clock_event_device *unused)
2572 +{
2573 + unsigned long stc;
2574 + do {
2575 + stc = readl(__io_address(ST_BASE + 0x04));
2576 + /* We could take a FIQ here, which may push ST above STC3 */
2577 + writel(stc + cycles, __io_address(ST_BASE + 0x18));
2578 + } while ((signed long) (readl(__io_address(ST_BASE + 0x04)) - stc)
2579 + >= (signed long) cycles);
2580 + return 0;
2581 +}
2582 +
2583 +static struct clock_event_device timer0_clockevent = {
2584 + .name = "timer0",
2585 + .shift = 32,
2586 + .features = CLOCK_EVT_FEAT_ONESHOT,
2587 + .set_mode = timer_set_mode,
2588 + .set_next_event = timer_set_next_event,
2589 +};
2590 +
2591 +/*
2592 + * IRQ handler for the timer
2593 + */
2594 +static irqreturn_t bcm2708_timer_interrupt(int irq, void *dev_id)
2595 +{
2596 + struct clock_event_device *evt = &timer0_clockevent;
2597 +
2598 + writel(1 << 3, __io_address(ST_BASE + 0x00)); /* stcs clear timer int */
2599 +
2600 + evt->event_handler(evt);
2601 +
2602 + return IRQ_HANDLED;
2603 +}
2604 +
2605 +static struct irqaction bcm2708_timer_irq = {
2606 + .name = "BCM2708 Timer Tick",
2607 + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
2608 + .handler = bcm2708_timer_interrupt,
2609 +};
2610 +
2611 +/*
2612 + * Set up timer interrupt, and return the current time in seconds.
2613 + */
2614 +
2615 +static struct delay_timer bcm2708_delay_timer = {
2616 + .read_current_timer = bcm2708_read_current_timer,
2617 + .freq = STC_FREQ_HZ,
2618 +};
2619 +
2620 +static void __init bcm2708_timer_init(void)
2621 +{
2622 + /* init high res timer */
2623 + bcm2708_clocksource_init();
2624 +
2625 + /*
2626 + * Initialise to a known state (all timers off)
2627 + */
2628 + writel(0, __io_address(ARM_T_CONTROL));
2629 + /*
2630 + * Make irqs happen for the system timer
2631 + */
2632 + setup_irq(IRQ_TIMER3, &bcm2708_timer_irq);
2633 +
2634 + setup_sched_clock(bcm2708_read_sched_clock, 32, STC_FREQ_HZ);
2635 +
2636 + timer0_clockevent.mult =
2637 + div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift);
2638 + timer0_clockevent.max_delta_ns =
2639 + clockevent_delta2ns(0xffffffff, &timer0_clockevent);
2640 + timer0_clockevent.min_delta_ns =
2641 + clockevent_delta2ns(0xf, &timer0_clockevent);
2642 +
2643 + timer0_clockevent.cpumask = cpumask_of(0);
2644 + clockevents_register_device(&timer0_clockevent);
2645 +
2646 + register_current_timer_delay(&bcm2708_delay_timer);
2647 +}
2648 +
2649 +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
2650 +#include <linux/leds.h>
2651 +
2652 +static struct gpio_led bcm2708_leds[] = {
2653 + [0] = {
2654 + .gpio = 16,
2655 + .name = "led0",
2656 + .default_trigger = "mmc0",
2657 + .active_low = 1,
2658 + },
2659 +};
2660 +
2661 +static struct gpio_led_platform_data bcm2708_led_pdata = {
2662 + .num_leds = ARRAY_SIZE(bcm2708_leds),
2663 + .leds = bcm2708_leds,
2664 +};
2665 +
2666 +static struct platform_device bcm2708_led_device = {
2667 + .name = "leds-gpio",
2668 + .id = -1,
2669 + .dev = {
2670 + .platform_data = &bcm2708_led_pdata,
2671 + },
2672 +};
2673 +
2674 +static void __init bcm2708_init_led(void)
2675 +{
2676 + bcm2708_leds[0].gpio = disk_led_gpio;
2677 + bcm2708_leds[0].active_low = disk_led_active_low;
2678 + platform_device_register(&bcm2708_led_device);
2679 +}
2680 +#else
2681 +static inline void bcm2708_init_led(void)
2682 +{
2683 +}
2684 +#endif
2685 +
2686 +void __init bcm2708_init_early(void)
2687 +{
2688 + /*
2689 + * Some devices allocate their coherent buffers from atomic
2690 + * context. Increase size of atomic coherent pool to make sure such
2691 + * the allocations won't fail.
2692 + */
2693 + init_dma_coherent_pool_size(SZ_4M);
2694 +}
2695 +
2696 +static void __init board_reserve(void)
2697 +{
2698 +#if defined(CONFIG_BCM_VC_CMA)
2699 + vc_cma_reserve();
2700 +#endif
2701 +}
2702 +
2703 +MACHINE_START(BCM2708, "BCM2708")
2704 + /* Maintainer: Broadcom Europe Ltd. */
2705 + .map_io = bcm2708_map_io,
2706 + .init_irq = bcm2708_init_irq,
2707 + .init_time = bcm2708_timer_init,
2708 + .init_machine = bcm2708_init,
2709 + .init_early = bcm2708_init_early,
2710 + .reserve = board_reserve,
2711 + .restart = bcm2708_restart,
2712 +MACHINE_END
2713 +
2714 +module_param(boardrev, uint, 0644);
2715 +module_param(serial, uint, 0644);
2716 +module_param(uart_clock, uint, 0644);
2717 +module_param(disk_led_gpio, uint, 0644);
2718 +module_param(disk_led_active_low, uint, 0644);
2719 +module_param(reboot_part, uint, 0644);
2720 --- /dev/null
2721 +++ b/arch/arm/mach-bcm2708/bcm2708.h
2722 @@ -0,0 +1,49 @@
2723 +/*
2724 + * linux/arch/arm/mach-bcm2708/bcm2708.h
2725 + *
2726 + * BCM2708 machine support header
2727 + *
2728 + * Copyright (C) 2010 Broadcom
2729 + *
2730 + * This program is free software; you can redistribute it and/or modify
2731 + * it under the terms of the GNU General Public License as published by
2732 + * the Free Software Foundation; either version 2 of the License, or
2733 + * (at your option) any later version.
2734 + *
2735 + * This program is distributed in the hope that it will be useful,
2736 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2737 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2738 + * GNU General Public License for more details.
2739 + *
2740 + * You should have received a copy of the GNU General Public License
2741 + * along with this program; if not, write to the Free Software
2742 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2743 + */
2744 +
2745 +#ifndef __BCM2708_BCM2708_H
2746 +#define __BCM2708_BCM2708_H
2747 +
2748 +#include <linux/amba/bus.h>
2749 +
2750 +extern void __init bcm2708_init(void);
2751 +extern void __init bcm2708_init_irq(void);
2752 +extern void __init bcm2708_map_io(void);
2753 +extern struct sys_timer bcm2708_timer;
2754 +extern unsigned int mmc_status(struct device *dev);
2755 +
2756 +#define AMBA_DEVICE(name, busid, base, plat) \
2757 +static struct amba_device name##_device = { \
2758 + .dev = { \
2759 + .coherent_dma_mask = ~0, \
2760 + .init_name = busid, \
2761 + .platform_data = plat, \
2762 + }, \
2763 + .res = { \
2764 + .start = base##_BASE, \
2765 + .end = (base##_BASE) + SZ_4K - 1,\
2766 + .flags = IORESOURCE_MEM, \
2767 + }, \
2768 + .irq = base##_IRQ, \
2769 +}
2770 +
2771 +#endif
2772 --- /dev/null
2773 +++ b/arch/arm/mach-bcm2708/bcm2708_gpio.c
2774 @@ -0,0 +1,361 @@
2775 +/*
2776 + * linux/arch/arm/mach-bcm2708/bcm2708_gpio.c
2777 + *
2778 + * Copyright (C) 2010 Broadcom
2779 + *
2780 + * This program is free software; you can redistribute it and/or modify
2781 + * it under the terms of the GNU General Public License version 2 as
2782 + * published by the Free Software Foundation.
2783 + *
2784 + */
2785 +
2786 +#include <linux/spinlock.h>
2787 +#include <linux/module.h>
2788 +#include <linux/list.h>
2789 +#include <linux/io.h>
2790 +#include <linux/irq.h>
2791 +#include <linux/interrupt.h>
2792 +#include <linux/slab.h>
2793 +#include <mach/gpio.h>
2794 +#include <linux/gpio.h>
2795 +#include <linux/platform_device.h>
2796 +#include <mach/platform.h>
2797 +
2798 +#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio"
2799 +#define DRIVER_NAME BCM_GPIO_DRIVER_NAME
2800 +#define BCM_GPIO_USE_IRQ 1
2801 +
2802 +#define GPIOFSEL(x) (0x00+(x)*4)
2803 +#define GPIOSET(x) (0x1c+(x)*4)
2804 +#define GPIOCLR(x) (0x28+(x)*4)
2805 +#define GPIOLEV(x) (0x34+(x)*4)
2806 +#define GPIOEDS(x) (0x40+(x)*4)
2807 +#define GPIOREN(x) (0x4c+(x)*4)
2808 +#define GPIOFEN(x) (0x58+(x)*4)
2809 +#define GPIOHEN(x) (0x64+(x)*4)
2810 +#define GPIOLEN(x) (0x70+(x)*4)
2811 +#define GPIOAREN(x) (0x7c+(x)*4)
2812 +#define GPIOAFEN(x) (0x88+(x)*4)
2813 +#define GPIOUD(x) (0x94+(x)*4)
2814 +#define GPIOUDCLK(x) (0x98+(x)*4)
2815 +
2816 +enum { GPIO_FSEL_INPUT, GPIO_FSEL_OUTPUT,
2817 + GPIO_FSEL_ALT5, GPIO_FSEL_ALT_4,
2818 + GPIO_FSEL_ALT0, GPIO_FSEL_ALT1,
2819 + GPIO_FSEL_ALT2, GPIO_FSEL_ALT3,
2820 +};
2821 +
2822 + /* Each of the two spinlocks protects a different set of hardware
2823 + * regiters and data structurs. This decouples the code of the IRQ from
2824 + * the GPIO code. This also makes the case of a GPIO routine call from
2825 + * the IRQ code simpler.
2826 + */
2827 +static DEFINE_SPINLOCK(lock); /* GPIO registers */
2828 +
2829 +struct bcm2708_gpio {
2830 + struct list_head list;
2831 + void __iomem *base;
2832 + struct gpio_chip gc;
2833 + unsigned long rising;
2834 + unsigned long falling;
2835 + unsigned long high;
2836 + unsigned long low;
2837 +};
2838 +
2839 +static int bcm2708_set_function(struct gpio_chip *gc, unsigned offset,
2840 + int function)
2841 +{
2842 + struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
2843 + unsigned long flags;
2844 + unsigned gpiodir;
2845 + unsigned gpio_bank = offset / 10;
2846 + unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3;
2847 +
2848 +//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set_function %p (%d,%d)\n", gc, offset, function);
2849 + if (offset >= BCM2708_NR_GPIOS)
2850 + return -EINVAL;
2851 +
2852 + spin_lock_irqsave(&lock, flags);
2853 +
2854 + gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank));
2855 + gpiodir &= ~(7 << gpio_field_offset);
2856 + gpiodir |= function << gpio_field_offset;
2857 + writel(gpiodir, gpio->base + GPIOFSEL(gpio_bank));
2858 + spin_unlock_irqrestore(&lock, flags);
2859 + gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank));
2860 +
2861 + return 0;
2862 +}
2863 +
2864 +static int bcm2708_gpio_dir_in(struct gpio_chip *gc, unsigned offset)
2865 +{
2866 + return bcm2708_set_function(gc, offset, GPIO_FSEL_INPUT);
2867 +}
2868 +
2869 +static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
2870 +static int bcm2708_gpio_dir_out(struct gpio_chip *gc, unsigned offset,
2871 + int value)
2872 +{
2873 + int ret;
2874 + ret = bcm2708_set_function(gc, offset, GPIO_FSEL_OUTPUT);
2875 + if (ret >= 0)
2876 + bcm2708_gpio_set(gc, offset, value);
2877 + return ret;
2878 +}
2879 +
2880 +static int bcm2708_gpio_get(struct gpio_chip *gc, unsigned offset)
2881 +{
2882 + struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
2883 + unsigned gpio_bank = offset / 32;
2884 + unsigned gpio_field_offset = (offset - 32 * gpio_bank);
2885 + unsigned lev;
2886 +
2887 + if (offset >= BCM2708_NR_GPIOS)
2888 + return 0;
2889 + lev = readl(gpio->base + GPIOLEV(gpio_bank));
2890 +//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_get %p (%d)=%d\n", gc, offset, 0x1 & (lev>>gpio_field_offset));
2891 + return 0x1 & (lev >> gpio_field_offset);
2892 +}
2893 +
2894 +static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
2895 +{
2896 + struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
2897 + unsigned gpio_bank = offset / 32;
2898 + unsigned gpio_field_offset = (offset - 32 * gpio_bank);
2899 +//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set %p (%d=%d)\n", gc, offset, value);
2900 + if (offset >= BCM2708_NR_GPIOS)
2901 + return;
2902 + if (value)
2903 + writel(1 << gpio_field_offset, gpio->base + GPIOSET(gpio_bank));
2904 + else
2905 + writel(1 << gpio_field_offset, gpio->base + GPIOCLR(gpio_bank));
2906 +}
2907 +
2908 +/*************************************************************************************************************************
2909 + * bcm2708 GPIO IRQ
2910 + */
2911 +
2912 +#if BCM_GPIO_USE_IRQ
2913 +
2914 +static int bcm2708_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
2915 +{
2916 + return gpio_to_irq(gpio);
2917 +}
2918 +
2919 +static int bcm2708_gpio_irq_set_type(struct irq_data *d, unsigned type)
2920 +{
2921 + unsigned irq = d->irq;
2922 + struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
2923 +
2924 + gpio->rising &= ~(1 << irq_to_gpio(irq));
2925 + gpio->falling &= ~(1 << irq_to_gpio(irq));
2926 + gpio->high &= ~(1 << irq_to_gpio(irq));
2927 + gpio->low &= ~(1 << irq_to_gpio(irq));
2928 +
2929 + if (type & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
2930 + return -EINVAL;
2931 +
2932 + if (type & IRQ_TYPE_EDGE_RISING)
2933 + gpio->rising |= (1 << irq_to_gpio(irq));
2934 + if (type & IRQ_TYPE_EDGE_FALLING)
2935 + gpio->falling |= (1 << irq_to_gpio(irq));
2936 + if (type & IRQ_TYPE_LEVEL_HIGH)
2937 + gpio->high |= (1 << irq_to_gpio(irq));
2938 + if (type & IRQ_TYPE_LEVEL_LOW)
2939 + gpio->low |= (1 << irq_to_gpio(irq));
2940 + return 0;
2941 +}
2942 +
2943 +static void bcm2708_gpio_irq_mask(struct irq_data *d)
2944 +{
2945 + unsigned irq = d->irq;
2946 + struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
2947 + unsigned gn = irq_to_gpio(irq);
2948 + unsigned gb = gn / 32;
2949 + unsigned long rising = readl(gpio->base + GPIOREN(gb));
2950 + unsigned long falling = readl(gpio->base + GPIOFEN(gb));
2951 + unsigned long high = readl(gpio->base + GPIOHEN(gb));
2952 + unsigned long low = readl(gpio->base + GPIOLEN(gb));
2953 +
2954 + gn = gn % 32;
2955 +
2956 + writel(rising & ~(1 << gn), gpio->base + GPIOREN(gb));
2957 + writel(falling & ~(1 << gn), gpio->base + GPIOFEN(gb));
2958 + writel(high & ~(1 << gn), gpio->base + GPIOHEN(gb));
2959 + writel(low & ~(1 << gn), gpio->base + GPIOLEN(gb));
2960 +}
2961 +
2962 +static void bcm2708_gpio_irq_unmask(struct irq_data *d)
2963 +{
2964 + unsigned irq = d->irq;
2965 + struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
2966 + unsigned gn = irq_to_gpio(irq);
2967 + unsigned gb = gn / 32;
2968 + unsigned long rising = readl(gpio->base + GPIOREN(gb));
2969 + unsigned long falling = readl(gpio->base + GPIOFEN(gb));
2970 + unsigned long high = readl(gpio->base + GPIOHEN(gb));
2971 + unsigned long low = readl(gpio->base + GPIOLEN(gb));
2972 +
2973 + gn = gn % 32;
2974 +
2975 + writel(1 << gn, gpio->base + GPIOEDS(gb));
2976 +
2977 + if (gpio->rising & (1 << gn)) {
2978 + writel(rising | (1 << gn), gpio->base + GPIOREN(gb));
2979 + } else {
2980 + writel(rising & ~(1 << gn), gpio->base + GPIOREN(gb));
2981 + }
2982 +
2983 + if (gpio->falling & (1 << gn)) {
2984 + writel(falling | (1 << gn), gpio->base + GPIOFEN(gb));
2985 + } else {
2986 + writel(falling & ~(1 << gn), gpio->base + GPIOFEN(gb));
2987 + }
2988 +
2989 + if (gpio->high & (1 << gn)) {
2990 + writel(high | (1 << gn), gpio->base + GPIOHEN(gb));
2991 + } else {
2992 + writel(high & ~(1 << gn), gpio->base + GPIOHEN(gb));
2993 + }
2994 +
2995 + if (gpio->low & (1 << gn)) {
2996 + writel(low | (1 << gn), gpio->base + GPIOLEN(gb));
2997 + } else {
2998 + writel(low & ~(1 << gn), gpio->base + GPIOLEN(gb));
2999 + }
3000 +}
3001 +
3002 +static struct irq_chip bcm2708_irqchip = {
3003 + .name = "GPIO",
3004 + .irq_enable = bcm2708_gpio_irq_unmask,
3005 + .irq_disable = bcm2708_gpio_irq_mask,
3006 + .irq_unmask = bcm2708_gpio_irq_unmask,
3007 + .irq_mask = bcm2708_gpio_irq_mask,
3008 + .irq_set_type = bcm2708_gpio_irq_set_type,
3009 +};
3010 +
3011 +static irqreturn_t bcm2708_gpio_interrupt(int irq, void *dev_id)
3012 +{
3013 + unsigned long edsr;
3014 + unsigned bank;
3015 + int i;
3016 + unsigned gpio;
3017 + for (bank = 0; bank <= 1; bank++) {
3018 + edsr = readl(__io_address(GPIO_BASE) + GPIOEDS(bank));
3019 + for_each_set_bit(i, &edsr, 32) {
3020 + gpio = i + bank * 32;
3021 + generic_handle_irq(gpio_to_irq(gpio));
3022 + }
3023 + writel(0xffffffff, __io_address(GPIO_BASE) + GPIOEDS(bank));
3024 + }
3025 + return IRQ_HANDLED;
3026 +}
3027 +
3028 +static struct irqaction bcm2708_gpio_irq = {
3029 + .name = "BCM2708 GPIO catchall handler",
3030 + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
3031 + .handler = bcm2708_gpio_interrupt,
3032 +};
3033 +
3034 +static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb)
3035 +{
3036 + unsigned irq;
3037 +
3038 + ucb->gc.to_irq = bcm2708_gpio_to_irq;
3039 +
3040 + for (irq = GPIO_IRQ_START; irq < (GPIO_IRQ_START + GPIO_IRQS); irq++) {
3041 + irq_set_chip_data(irq, ucb);
3042 + irq_set_chip(irq, &bcm2708_irqchip);
3043 + set_irq_flags(irq, IRQF_VALID);
3044 + }
3045 + setup_irq(IRQ_GPIO3, &bcm2708_gpio_irq);
3046 +}
3047 +
3048 +#else
3049 +
3050 +static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb)
3051 +{
3052 +}
3053 +
3054 +#endif /* #if BCM_GPIO_USE_IRQ ***************************************************************************************************************** */
3055 +
3056 +static int bcm2708_gpio_probe(struct platform_device *dev)
3057 +{
3058 + struct bcm2708_gpio *ucb;
3059 + struct resource *res;
3060 + int err = 0;
3061 +
3062 + printk(KERN_INFO DRIVER_NAME ": bcm2708_gpio_probe %p\n", dev);
3063 +
3064 + ucb = kzalloc(sizeof(*ucb), GFP_KERNEL);
3065 + if (NULL == ucb) {
3066 + printk(KERN_ERR DRIVER_NAME ": failed to allocate "
3067 + "mailbox memory\n");
3068 + err = -ENOMEM;
3069 + goto err;
3070 + }
3071 +
3072 + res = platform_get_resource(dev, IORESOURCE_MEM, 0);
3073 +
3074 + platform_set_drvdata(dev, ucb);
3075 + ucb->base = __io_address(GPIO_BASE);
3076 +
3077 + ucb->gc.label = "bcm2708_gpio";
3078 + ucb->gc.base = 0;
3079 + ucb->gc.ngpio = BCM2708_NR_GPIOS;
3080 + ucb->gc.owner = THIS_MODULE;
3081 +
3082 + ucb->gc.direction_input = bcm2708_gpio_dir_in;
3083 + ucb->gc.direction_output = bcm2708_gpio_dir_out;
3084 + ucb->gc.get = bcm2708_gpio_get;
3085 + ucb->gc.set = bcm2708_gpio_set;
3086 + ucb->gc.can_sleep = 0;
3087 +
3088 + bcm2708_gpio_irq_init(ucb);
3089 +
3090 + err = gpiochip_add(&ucb->gc);
3091 + if (err)
3092 + goto err;
3093 +
3094 +err:
3095 + return err;
3096 +
3097 +}
3098 +
3099 +static int bcm2708_gpio_remove(struct platform_device *dev)
3100 +{
3101 + int err = 0;
3102 + struct bcm2708_gpio *ucb = platform_get_drvdata(dev);
3103 +
3104 + printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_remove %p\n", dev);
3105 +
3106 + err = gpiochip_remove(&ucb->gc);
3107 +
3108 + platform_set_drvdata(dev, NULL);
3109 + kfree(ucb);
3110 +
3111 + return err;
3112 +}
3113 +
3114 +static struct platform_driver bcm2708_gpio_driver = {
3115 + .probe = bcm2708_gpio_probe,
3116 + .remove = bcm2708_gpio_remove,
3117 + .driver = {
3118 + .name = "bcm2708_gpio"},
3119 +};
3120 +
3121 +static int __init bcm2708_gpio_init(void)
3122 +{
3123 + return platform_driver_register(&bcm2708_gpio_driver);
3124 +}
3125 +
3126 +static void __exit bcm2708_gpio_exit(void)
3127 +{
3128 + platform_driver_unregister(&bcm2708_gpio_driver);
3129 +}
3130 +
3131 +module_init(bcm2708_gpio_init);
3132 +module_exit(bcm2708_gpio_exit);
3133 +
3134 +MODULE_DESCRIPTION("Broadcom BCM2708 GPIO driver");
3135 +MODULE_LICENSE("GPL");
3136 --- /dev/null
3137 +++ b/arch/arm/mach-bcm2708/clock.c
3138 @@ -0,0 +1,61 @@
3139 +/*
3140 + * linux/arch/arm/mach-bcm2708/clock.c
3141 + *
3142 + * Copyright (C) 2010 Broadcom
3143 + *
3144 + * This program is free software; you can redistribute it and/or modify
3145 + * it under the terms of the GNU General Public License as published by
3146 + * the Free Software Foundation; either version 2 of the License, or
3147 + * (at your option) any later version.
3148 + *
3149 + * This program is distributed in the hope that it will be useful,
3150 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3151 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3152 + * GNU General Public License for more details.
3153 + *
3154 + * You should have received a copy of the GNU General Public License
3155 + * along with this program; if not, write to the Free Software
3156 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3157 + */
3158 +#include <linux/module.h>
3159 +#include <linux/kernel.h>
3160 +#include <linux/device.h>
3161 +#include <linux/list.h>
3162 +#include <linux/errno.h>
3163 +#include <linux/err.h>
3164 +#include <linux/string.h>
3165 +#include <linux/clk.h>
3166 +#include <linux/mutex.h>
3167 +
3168 +#include <asm/clkdev.h>
3169 +
3170 +#include "clock.h"
3171 +
3172 +int clk_enable(struct clk *clk)
3173 +{
3174 + return 0;
3175 +}
3176 +EXPORT_SYMBOL(clk_enable);
3177 +
3178 +void clk_disable(struct clk *clk)
3179 +{
3180 +}
3181 +EXPORT_SYMBOL(clk_disable);
3182 +
3183 +unsigned long clk_get_rate(struct clk *clk)
3184 +{
3185 + return clk->rate;
3186 +}
3187 +EXPORT_SYMBOL(clk_get_rate);
3188 +
3189 +long clk_round_rate(struct clk *clk, unsigned long rate)
3190 +{
3191 + return clk->rate;
3192 +}
3193 +EXPORT_SYMBOL(clk_round_rate);
3194 +
3195 +int clk_set_rate(struct clk *clk, unsigned long rate)
3196 +{
3197 + return -EIO;
3198 +}
3199 +EXPORT_SYMBOL(clk_set_rate);
3200 --- /dev/null
3201 +++ b/arch/arm/mach-bcm2708/clock.h
3202 @@ -0,0 +1,24 @@
3203 +/*
3204 + * linux/arch/arm/mach-bcm2708/clock.h
3205 + *
3206 + * Copyright (C) 2010 Broadcom
3207 + *
3208 + * This program is free software; you can redistribute it and/or modify
3209 + * it under the terms of the GNU General Public License as published by
3210 + * the Free Software Foundation; either version 2 of the License, or
3211 + * (at your option) any later version.
3212 + *
3213 + * This program is distributed in the hope that it will be useful,
3214 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3215 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3216 + * GNU General Public License for more details.
3217 + *
3218 + * You should have received a copy of the GNU General Public License
3219 + * along with this program; if not, write to the Free Software
3220 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3221 + */
3222 +struct module;
3223 +
3224 +struct clk {
3225 + unsigned long rate;
3226 +};
3227 --- /dev/null
3228 +++ b/arch/arm/mach-bcm2708/dma.c
3229 @@ -0,0 +1,399 @@
3230 +/*
3231 + * linux/arch/arm/mach-bcm2708/dma.c
3232 + *
3233 + * Copyright (C) 2010 Broadcom
3234 + *
3235 + * This program is free software; you can redistribute it and/or modify
3236 + * it under the terms of the GNU General Public License version 2 as
3237 + * published by the Free Software Foundation.
3238 + */
3239 +
3240 +#include <linux/slab.h>
3241 +#include <linux/device.h>
3242 +#include <linux/platform_device.h>
3243 +#include <linux/module.h>
3244 +#include <linux/scatterlist.h>
3245 +
3246 +#include <mach/dma.h>
3247 +#include <mach/irqs.h>
3248 +
3249 +/*****************************************************************************\
3250 + * *
3251 + * Configuration *
3252 + * *
3253 +\*****************************************************************************/
3254 +
3255 +#define CACHE_LINE_MASK 31
3256 +#define DRIVER_NAME BCM_DMAMAN_DRIVER_NAME
3257 +#define DEFAULT_DMACHAN_BITMAP 0x10 /* channel 4 only */
3258 +
3259 +/* valid only for channels 0 - 14, 15 has its own base address */
3260 +#define BCM2708_DMA_CHAN(n) ((n)<<8) /* base address */
3261 +#define BCM2708_DMA_CHANIO(dma_base, n) \
3262 + ((void __iomem *)((char *)(dma_base)+BCM2708_DMA_CHAN(n)))
3263 +
3264 +
3265 +/*****************************************************************************\
3266 + * *
3267 + * DMA Auxilliary Functions *
3268 + * *
3269 +\*****************************************************************************/
3270 +
3271 +/* A DMA buffer on an arbitrary boundary may separate a cache line into a
3272 + section inside the DMA buffer and another section outside it.
3273 + Even if we flush DMA buffers from the cache there is always the chance that
3274 + during a DMA someone will access the part of a cache line that is outside
3275 + the DMA buffer - which will then bring in unwelcome data.
3276 + Without being able to dictate our own buffer pools we must insist that
3277 + DMA buffers consist of a whole number of cache lines.
3278 +*/
3279 +
3280 +extern int
3281 +bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len)
3282 +{
3283 + int i;
3284 +
3285 + for (i = 0; i < sg_len; i++) {
3286 + if (sg_ptr[i].offset & CACHE_LINE_MASK ||
3287 + sg_ptr[i].length & CACHE_LINE_MASK)
3288 + return 0;
3289 + }
3290 +
3291 + return 1;
3292 +}
3293 +EXPORT_SYMBOL_GPL(bcm_sg_suitable_for_dma);
3294 +
3295 +extern void
3296 +bcm_dma_start(void __iomem *dma_chan_base, dma_addr_t control_block)
3297 +{
3298 + dsb(); /* ARM data synchronization (push) operation */
3299 +
3300 + writel(control_block, dma_chan_base + BCM2708_DMA_ADDR);
3301 + writel(BCM2708_DMA_ACTIVE, dma_chan_base + BCM2708_DMA_CS);
3302 +}
3303 +
3304 +extern void bcm_dma_wait_idle(void __iomem *dma_chan_base)
3305 +{
3306 + dsb();
3307 +
3308 + /* ugly busy wait only option for now */
3309 + while (readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE)
3310 + cpu_relax();
3311 +}
3312 +
3313 +EXPORT_SYMBOL_GPL(bcm_dma_start);
3314 +
3315 +/* Complete an ongoing DMA (assuming its results are to be ignored)
3316 + Does nothing if there is no DMA in progress.
3317 + This routine waits for the current AXI transfer to complete before
3318 + terminating the current DMA. If the current transfer is hung on a DREQ used
3319 + by an uncooperative peripheral the AXI transfer may never complete. In this
3320 + case the routine times out and return a non-zero error code.
3321 + Use of this routine doesn't guarantee that the ongoing or aborted DMA
3322 + does not produce an interrupt.
3323 +*/
3324 +extern int
3325 +bcm_dma_abort(void __iomem *dma_chan_base)
3326 +{
3327 + unsigned long int cs;
3328 + int rc = 0;
3329 +
3330 + cs = readl(dma_chan_base + BCM2708_DMA_CS);
3331 +
3332 + if (BCM2708_DMA_ACTIVE & cs) {
3333 + long int timeout = 10000;
3334 +
3335 + /* write 0 to the active bit - pause the DMA */
3336 + writel(0, dma_chan_base + BCM2708_DMA_CS);
3337 +
3338 + /* wait for any current AXI transfer to complete */
3339 + while (0 != (cs & BCM2708_DMA_ISPAUSED) && --timeout >= 0)
3340 + cs = readl(dma_chan_base + BCM2708_DMA_CS);
3341 +
3342 + if (0 != (cs & BCM2708_DMA_ISPAUSED)) {
3343 + /* we'll un-pause when we set of our next DMA */
3344 + rc = -ETIMEDOUT;
3345 +
3346 + } else if (BCM2708_DMA_ACTIVE & cs) {
3347 + /* terminate the control block chain */
3348 + writel(0, dma_chan_base + BCM2708_DMA_NEXTCB);
3349 +
3350 + /* abort the whole DMA */
3351 + writel(BCM2708_DMA_ABORT | BCM2708_DMA_ACTIVE,
3352 + dma_chan_base + BCM2708_DMA_CS);
3353 + }
3354 + }
3355 +
3356 + return rc;
3357 +}
3358 +EXPORT_SYMBOL_GPL(bcm_dma_abort);
3359 +
3360 +
3361 +/***************************************************************************** \
3362 + * *
3363 + * DMA Manager Device Methods *
3364 + * *
3365 +\*****************************************************************************/
3366 +
3367 +struct vc_dmaman {
3368 + void __iomem *dma_base;
3369 + u32 chan_available; /* bitmap of available channels */
3370 + u32 has_feature[BCM_DMA_FEATURE_COUNT]; /* bitmap of feature presence */
3371 +};
3372 +
3373 +static void vc_dmaman_init(struct vc_dmaman *dmaman, void __iomem *dma_base,
3374 + u32 chans_available)
3375 +{
3376 + dmaman->dma_base = dma_base;
3377 + dmaman->chan_available = chans_available;
3378 + dmaman->has_feature[BCM_DMA_FEATURE_FAST_ORD] = 0x0c; /* chans 2 & 3 */
3379 + dmaman->has_feature[BCM_DMA_FEATURE_BULK_ORD] = 0x01; /* chan 0 */
3380 +}
3381 +
3382 +static int vc_dmaman_chan_alloc(struct vc_dmaman *dmaman,
3383 + unsigned preferred_feature_set)
3384 +{
3385 + u32 chans;
3386 + int feature;
3387 +
3388 + chans = dmaman->chan_available;
3389 + for (feature = 0; feature < BCM_DMA_FEATURE_COUNT; feature++)
3390 + /* select the subset of available channels with the desired
3391 + feature so long as some of the candidate channels have that
3392 + feature */
3393 + if ((preferred_feature_set & (1 << feature)) &&
3394 + (chans & dmaman->has_feature[feature]))
3395 + chans &= dmaman->has_feature[feature];
3396 +
3397 + if (chans) {
3398 + int chan = 0;
3399 + /* return the ordinal of the first channel in the bitmap */
3400 + while (chans != 0 && (chans & 1) == 0) {
3401 + chans >>= 1;
3402 + chan++;
3403 + }
3404 + /* claim the channel */
3405 + dmaman->chan_available &= ~(1 << chan);
3406 + return chan;
3407 + } else
3408 + return -ENOMEM;
3409 +}
3410 +
3411 +static int vc_dmaman_chan_free(struct vc_dmaman *dmaman, int chan)
3412 +{
3413 + if (chan < 0)
3414 + return -EINVAL;
3415 + else if ((1 << chan) & dmaman->chan_available)
3416 + return -EIDRM;
3417 + else {
3418 + dmaman->chan_available |= (1 << chan);
3419 + return 0;
3420 + }
3421 +}
3422 +
3423 +/*****************************************************************************\
3424 + * *
3425 + * DMA IRQs *
3426 + * *
3427 +\*****************************************************************************/
3428 +
3429 +static unsigned char bcm_dma_irqs[] = {
3430 + IRQ_DMA0,
3431 + IRQ_DMA1,
3432 + IRQ_DMA2,
3433 + IRQ_DMA3,
3434 + IRQ_DMA4,
3435 + IRQ_DMA5,
3436 + IRQ_DMA6,
3437 + IRQ_DMA7,
3438 + IRQ_DMA8,
3439 + IRQ_DMA9,
3440 + IRQ_DMA10,
3441 + IRQ_DMA11,
3442 + IRQ_DMA12
3443 +};
3444 +
3445 +
3446 +/***************************************************************************** \
3447 + * *
3448 + * DMA Manager Monitor *
3449 + * *
3450 +\*****************************************************************************/
3451 +
3452 +static struct device *dmaman_dev; /* we assume there's only one! */
3453 +
3454 +extern int bcm_dma_chan_alloc(unsigned preferred_feature_set,
3455 + void __iomem **out_dma_base, int *out_dma_irq)
3456 +{
3457 + if (!dmaman_dev)
3458 + return -ENODEV;
3459 + else {
3460 + struct vc_dmaman *dmaman = dev_get_drvdata(dmaman_dev);
3461 + int rc;
3462 +
3463 + device_lock(dmaman_dev);
3464 + rc = vc_dmaman_chan_alloc(dmaman, preferred_feature_set);
3465 + if (rc >= 0) {
3466 + *out_dma_base = BCM2708_DMA_CHANIO(dmaman->dma_base,
3467 + rc);
3468 + *out_dma_irq = bcm_dma_irqs[rc];
3469 + }
3470 + device_unlock(dmaman_dev);
3471 +
3472 + return rc;
3473 + }
3474 +}
3475 +EXPORT_SYMBOL_GPL(bcm_dma_chan_alloc);
3476 +
3477 +extern int bcm_dma_chan_free(int channel)
3478 +{
3479 + if (dmaman_dev) {
3480 + struct vc_dmaman *dmaman = dev_get_drvdata(dmaman_dev);
3481 + int rc;
3482 +
3483 + device_lock(dmaman_dev);
3484 + rc = vc_dmaman_chan_free(dmaman, channel);
3485 + device_unlock(dmaman_dev);
3486 +
3487 + return rc;
3488 + } else
3489 + return -ENODEV;
3490 +}
3491 +EXPORT_SYMBOL_GPL(bcm_dma_chan_free);
3492 +
3493 +static int dev_dmaman_register(const char *dev_name, struct device *dev)
3494 +{
3495 + int rc = dmaman_dev ? -EINVAL : 0;
3496 + dmaman_dev = dev;
3497 + return rc;
3498 +}
3499 +
3500 +static void dev_dmaman_deregister(const char *dev_name, struct device *dev)
3501 +{
3502 + dmaman_dev = NULL;
3503 +}
3504 +
3505 +/*****************************************************************************\
3506 + * *
3507 + * DMA Device *
3508 + * *
3509 +\*****************************************************************************/
3510 +
3511 +static int dmachans = -1; /* module parameter */
3512 +
3513 +static int bcm_dmaman_probe(struct platform_device *pdev)
3514 +{
3515 + int ret = 0;
3516 + struct vc_dmaman *dmaman;
3517 + struct resource *dma_res = NULL;
3518 + void __iomem *dma_base = NULL;
3519 + int have_dma_region = 0;
3520 +
3521 + dmaman = kzalloc(sizeof(*dmaman), GFP_KERNEL);
3522 + if (NULL == dmaman) {
3523 + printk(KERN_ERR DRIVER_NAME ": failed to allocate "
3524 + "DMA management memory\n");
3525 + ret = -ENOMEM;
3526 + } else {
3527 +
3528 + dma_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3529 + if (dma_res == NULL) {
3530 + printk(KERN_ERR DRIVER_NAME ": failed to obtain memory "
3531 + "resource\n");
3532 + ret = -ENODEV;
3533 + } else if (!request_mem_region(dma_res->start,
3534 + resource_size(dma_res),
3535 + DRIVER_NAME)) {
3536 + dev_err(&pdev->dev, "cannot obtain DMA region\n");
3537 + ret = -EBUSY;
3538 + } else {
3539 + have_dma_region = 1;
3540 + dma_base = ioremap(dma_res->start,
3541 + resource_size(dma_res));
3542 + if (!dma_base) {
3543 + dev_err(&pdev->dev, "cannot map DMA region\n");
3544 + ret = -ENOMEM;
3545 + } else {
3546 + /* use module parameter if one was provided */
3547 + if (dmachans > 0)
3548 + vc_dmaman_init(dmaman, dma_base,
3549 + dmachans);
3550 + else
3551 + vc_dmaman_init(dmaman, dma_base,
3552 + DEFAULT_DMACHAN_BITMAP);
3553 +
3554 + platform_set_drvdata(pdev, dmaman);
3555 + dev_dmaman_register(DRIVER_NAME, &pdev->dev);
3556 +
3557 + printk(KERN_INFO DRIVER_NAME ": DMA manager "
3558 + "at %p\n", dma_base);
3559 + }
3560 + }
3561 + }
3562 + if (ret != 0) {
3563 + if (dma_base)
3564 + iounmap(dma_base);
3565 + if (dma_res && have_dma_region)
3566 + release_mem_region(dma_res->start,
3567 + resource_size(dma_res));
3568 + if (dmaman)
3569 + kfree(dmaman);
3570 + }
3571 + return ret;
3572 +}
3573 +
3574 +static int bcm_dmaman_remove(struct platform_device *pdev)
3575 +{
3576 + struct vc_dmaman *dmaman = platform_get_drvdata(pdev);
3577 +
3578 + platform_set_drvdata(pdev, NULL);
3579 + dev_dmaman_deregister(DRIVER_NAME, &pdev->dev);
3580 + kfree(dmaman);
3581 +
3582 + return 0;
3583 +}
3584 +
3585 +static struct platform_driver bcm_dmaman_driver = {
3586 + .probe = bcm_dmaman_probe,
3587 + .remove = bcm_dmaman_remove,
3588 +
3589 + .driver = {
3590 + .name = DRIVER_NAME,
3591 + .owner = THIS_MODULE,
3592 + },
3593 +};
3594 +
3595 +/*****************************************************************************\
3596 + * *
3597 + * Driver init/exit *
3598 + * *
3599 +\*****************************************************************************/
3600 +
3601 +static int __init bcm_dmaman_drv_init(void)
3602 +{
3603 + int ret;
3604 +
3605 + ret = platform_driver_register(&bcm_dmaman_driver);
3606 + if (ret != 0) {
3607 + printk(KERN_ERR DRIVER_NAME ": failed to register "
3608 + "on platform\n");
3609 + }
3610 +
3611 + return ret;
3612 +}
3613 +
3614 +static void __exit bcm_dmaman_drv_exit(void)
3615 +{
3616 + platform_driver_unregister(&bcm_dmaman_driver);
3617 +}
3618 +
3619 +module_init(bcm_dmaman_drv_init);
3620 +module_exit(bcm_dmaman_drv_exit);
3621 +
3622 +module_param(dmachans, int, 0644);
3623 +
3624 +MODULE_AUTHOR("Gray Girling <grayg@broadcom.com>");
3625 +MODULE_DESCRIPTION("DMA channel manager driver");
3626 +MODULE_LICENSE("GPL");
3627 +
3628 +MODULE_PARM_DESC(dmachans, "Bitmap of DMA channels available to the ARM");
3629 --- /dev/null
3630 +++ b/arch/arm/mach-bcm2708/include/mach/arm_control.h
3631 @@ -0,0 +1,419 @@
3632 +/*
3633 + * linux/arch/arm/mach-bcm2708/arm_control.h
3634 + *
3635 + * Copyright (C) 2010 Broadcom
3636 + *
3637 + * This program is free software; you can redistribute it and/or modify
3638 + * it under the terms of the GNU General Public License as published by
3639 + * the Free Software Foundation; either version 2 of the License, or
3640 + * (at your option) any later version.
3641 + *
3642 + * This program is distributed in the hope that it will be useful,
3643 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3644 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3645 + * GNU General Public License for more details.
3646 + *
3647 + * You should have received a copy of the GNU General Public License
3648 + * along with this program; if not, write to the Free Software
3649 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3650 + */
3651 +
3652 +#ifndef __BCM2708_ARM_CONTROL_H
3653 +#define __BCM2708_ARM_CONTROL_H
3654 +
3655 +/*
3656 + * Definitions and addresses for the ARM CONTROL logic
3657 + * This file is manually generated.
3658 + */
3659 +
3660 +#define ARM_BASE 0x7E00B000
3661 +
3662 +/* Basic configuration */
3663 +#define ARM_CONTROL0 HW_REGISTER_RW(ARM_BASE+0x000)
3664 +#define ARM_C0_SIZ128M 0x00000000
3665 +#define ARM_C0_SIZ256M 0x00000001
3666 +#define ARM_C0_SIZ512M 0x00000002
3667 +#define ARM_C0_SIZ1G 0x00000003
3668 +#define ARM_C0_BRESP0 0x00000000
3669 +#define ARM_C0_BRESP1 0x00000004
3670 +#define ARM_C0_BRESP2 0x00000008
3671 +#define ARM_C0_BOOTHI 0x00000010
3672 +#define ARM_C0_UNUSED05 0x00000020 /* free */
3673 +#define ARM_C0_FULLPERI 0x00000040
3674 +#define ARM_C0_UNUSED78 0x00000180 /* free */
3675 +#define ARM_C0_JTAGMASK 0x00000E00
3676 +#define ARM_C0_JTAGOFF 0x00000000
3677 +#define ARM_C0_JTAGBASH 0x00000800 /* Debug on GPIO off */
3678 +#define ARM_C0_JTAGGPIO 0x00000C00 /* Debug on GPIO on */
3679 +#define ARM_C0_APROTMSK 0x0000F000
3680 +#define ARM_C0_DBG0SYNC 0x00010000 /* VPU0 halt sync */
3681 +#define ARM_C0_DBG1SYNC 0x00020000 /* VPU1 halt sync */
3682 +#define ARM_C0_SWDBGREQ 0x00040000 /* HW debug request */
3683 +#define ARM_C0_PASSHALT 0x00080000 /* ARM halt passed to debugger */
3684 +#define ARM_C0_PRIO_PER 0x00F00000 /* per priority mask */
3685 +#define ARM_C0_PRIO_L2 0x0F000000
3686 +#define ARM_C0_PRIO_UC 0xF0000000
3687 +
3688 +#define ARM_C0_APROTPASS 0x0000A000 /* Translate 1:1 */
3689 +#define ARM_C0_APROTUSER 0x00000000 /* Only user mode */
3690 +#define ARM_C0_APROTSYST 0x0000F000 /* Only system mode */
3691 +
3692 +
3693 +#define ARM_CONTROL1 HW_REGISTER_RW(ARM_BASE+0x440)
3694 +#define ARM_C1_TIMER 0x00000001 /* re-route timer IRQ to VC */
3695 +#define ARM_C1_MAIL 0x00000002 /* re-route Mail IRQ to VC */
3696 +#define ARM_C1_BELL0 0x00000004 /* re-route Doorbell 0 to VC */
3697 +#define ARM_C1_BELL1 0x00000008 /* re-route Doorbell 1 to VC */
3698 +#define ARM_C1_PERSON 0x00000100 /* peripherals on */
3699 +#define ARM_C1_REQSTOP 0x00000200 /* ASYNC bridge request stop */
3700 +
3701 +#define ARM_STATUS HW_REGISTER_RW(ARM_BASE+0x444)
3702 +#define ARM_S_ACKSTOP 0x80000000 /* Bridge stopped */
3703 +#define ARM_S_READPEND 0x000003FF /* pending reads counter */
3704 +#define ARM_S_WRITPEND 0x000FFC00 /* pending writes counter */
3705 +
3706 +#define ARM_ERRHALT HW_REGISTER_RW(ARM_BASE+0x448)
3707 +#define ARM_EH_PERIBURST 0x00000001 /* Burst write seen on peri bus */
3708 +#define ARM_EH_ILLADDRS1 0x00000002 /* Address bits 25-27 error */
3709 +#define ARM_EH_ILLADDRS2 0x00000004 /* Address bits 31-28 error */
3710 +#define ARM_EH_VPU0HALT 0x00000008 /* VPU0 halted & in debug mode */
3711 +#define ARM_EH_VPU1HALT 0x00000010 /* VPU1 halted & in debug mode */
3712 +#define ARM_EH_ARMHALT 0x00000020 /* ARM in halted debug mode */
3713 +
3714 +#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C)
3715 +#define ARM_ID HW_REGISTER_RW(ARM_BASE+0x44C)
3716 +#define ARM_IDVAL 0x364D5241
3717 +
3718 +/* Translation memory */
3719 +#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100)
3720 +/* 32 locations: 0x100.. 0x17F */
3721 +/* 32 spare means we CAN go to 64 pages.... */
3722 +
3723 +
3724 +/* Interrupts */
3725 +#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200) /* Top IRQ bits */
3726 +#define ARM_I0_TIMER 0x00000001 /* timer IRQ */
3727 +#define ARM_I0_MAIL 0x00000002 /* Mail IRQ */
3728 +#define ARM_I0_BELL0 0x00000004 /* Doorbell 0 */
3729 +#define ARM_I0_BELL1 0x00000008 /* Doorbell 1 */
3730 +#define ARM_I0_BANK1 0x00000100 /* Bank1 IRQ */
3731 +#define ARM_I0_BANK2 0x00000200 /* Bank2 IRQ */
3732 +
3733 +#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) /* All bank1 IRQ bits */
3734 +/* todo: all I1_interrupt sources */
3735 +#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) /* All bank2 IRQ bits */
3736 +/* todo: all I2_interrupt sources */
3737 +
3738 +#define ARM_IRQ_FAST HW_REGISTER_RW(ARM_BASE+0x20C) /* FIQ control */
3739 +#define ARM_IF_INDEX 0x0000007F /* FIQ select */
3740 +#define ARM_IF_ENABLE 0x00000080 /* FIQ enable */
3741 +#define ARM_IF_VCMASK 0x0000003F /* FIQ = (index from VC source) */
3742 +#define ARM_IF_TIMER 0x00000040 /* FIQ = ARM timer */
3743 +#define ARM_IF_MAIL 0x00000041 /* FIQ = ARM Mail */
3744 +#define ARM_IF_BELL0 0x00000042 /* FIQ = ARM Doorbell 0 */
3745 +#define ARM_IF_BELL1 0x00000043 /* FIQ = ARM Doorbell 1 */
3746 +#define ARM_IF_VP0HALT 0x00000044 /* FIQ = VPU0 Halt seen */
3747 +#define ARM_IF_VP1HALT 0x00000045 /* FIQ = VPU1 Halt seen */
3748 +#define ARM_IF_ILLEGAL 0x00000046 /* FIQ = Illegal access seen */
3749 +
3750 +#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) /* Bank1 enable bits */
3751 +#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) /* Bank2 enable bits */
3752 +#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) /* ARM irqs enable bits */
3753 +#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) /* Bank1 disable bits */
3754 +#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) /* Bank2 disable bits */
3755 +#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) /* ARM irqs disable bits */
3756 +#define ARM_IE_TIMER 0x00000001 /* Timer IRQ */
3757 +#define ARM_IE_MAIL 0x00000002 /* Mail IRQ */
3758 +#define ARM_IE_BELL0 0x00000004 /* Doorbell 0 */
3759 +#define ARM_IE_BELL1 0x00000008 /* Doorbell 1 */
3760 +#define ARM_IE_VP0HALT 0x00000010 /* VPU0 Halt */
3761 +#define ARM_IE_VP1HALT 0x00000020 /* VPU1 Halt */
3762 +#define ARM_IE_ILLEGAL 0x00000040 /* Illegal access seen */
3763 +
3764 +/* Timer */
3765 +/* For reg. fields see sp804 spec. */
3766 +#define ARM_T_LOAD HW_REGISTER_RW(ARM_BASE+0x400)
3767 +#define ARM_T_VALUE HW_REGISTER_RW(ARM_BASE+0x404)
3768 +#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408)
3769 +#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C)
3770 +#define ARM_T_RAWIRQ HW_REGISTER_RW(ARM_BASE+0x410)
3771 +#define ARM_T_MSKIRQ HW_REGISTER_RW(ARM_BASE+0x414)
3772 +#define ARM_T_RELOAD HW_REGISTER_RW(ARM_BASE+0x418)
3773 +#define ARM_T_PREDIV HW_REGISTER_RW(ARM_BASE+0x41c)
3774 +#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420)
3775 +
3776 +#define TIMER_CTRL_ONESHOT (1 << 0)
3777 +#define TIMER_CTRL_32BIT (1 << 1)
3778 +#define TIMER_CTRL_DIV1 (0 << 2)
3779 +#define TIMER_CTRL_DIV16 (1 << 2)
3780 +#define TIMER_CTRL_DIV256 (2 << 2)
3781 +#define TIMER_CTRL_IE (1 << 5)
3782 +#define TIMER_CTRL_PERIODIC (1 << 6)
3783 +#define TIMER_CTRL_ENABLE (1 << 7)
3784 +#define TIMER_CTRL_DBGHALT (1 << 8)
3785 +#define TIMER_CTRL_ENAFREE (1 << 9)
3786 +#define TIMER_CTRL_FREEDIV_SHIFT 16)
3787 +#define TIMER_CTRL_FREEDIV_MASK 0xff
3788 +
3789 +/* Semaphores, Doorbells, Mailboxes */
3790 +#define ARM_SBM_OWN0 (ARM_BASE+0x800)
3791 +#define ARM_SBM_OWN1 (ARM_BASE+0x900)
3792 +#define ARM_SBM_OWN2 (ARM_BASE+0xA00)
3793 +#define ARM_SBM_OWN3 (ARM_BASE+0xB00)
3794 +
3795 +/* MAILBOXES
3796 + * Register flags are common across all
3797 + * owner registers. See end of this section
3798 + *
3799 + * Semaphores, Doorbells, Mailboxes Owner 0
3800 + *
3801 + */
3802 +
3803 +#define ARM_0_SEMS HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
3804 +#define ARM_0_SEM0 HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
3805 +#define ARM_0_SEM1 HW_REGISTER_RW(ARM_SBM_OWN0+0x04)
3806 +#define ARM_0_SEM2 HW_REGISTER_RW(ARM_SBM_OWN0+0x08)
3807 +#define ARM_0_SEM3 HW_REGISTER_RW(ARM_SBM_OWN0+0x0C)
3808 +#define ARM_0_SEM4 HW_REGISTER_RW(ARM_SBM_OWN0+0x10)
3809 +#define ARM_0_SEM5 HW_REGISTER_RW(ARM_SBM_OWN0+0x14)
3810 +#define ARM_0_SEM6 HW_REGISTER_RW(ARM_SBM_OWN0+0x18)
3811 +#define ARM_0_SEM7 HW_REGISTER_RW(ARM_SBM_OWN0+0x1C)
3812 +#define ARM_0_BELL0 HW_REGISTER_RW(ARM_SBM_OWN0+0x40)
3813 +#define ARM_0_BELL1 HW_REGISTER_RW(ARM_SBM_OWN0+0x44)
3814 +#define ARM_0_BELL2 HW_REGISTER_RW(ARM_SBM_OWN0+0x48)
3815 +#define ARM_0_BELL3 HW_REGISTER_RW(ARM_SBM_OWN0+0x4C)
3816 +/* MAILBOX 0 access in Owner 0 area */
3817 +/* Some addresses should ONLY be used by owner 0 */
3818 +#define ARM_0_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) */
3819 +#define ARM_0_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) Normal read */
3820 +#define ARM_0_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN0+0x90) /* none-pop read */
3821 +#define ARM_0_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN0+0x94) /* Sender read (only LS 2 bits) */
3822 +#define ARM_0_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN0+0x98) /* Status read */
3823 +#define ARM_0_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0x9C) /* Config read/write */
3824 +/* MAILBOX 1 access in Owner 0 area */
3825 +/* Owner 0 should only WRITE to this mailbox */
3826 +#define ARM_0_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) /* .. 0xAC (4 locations) */
3827 +/*#define ARM_0_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) */ /* DO NOT USE THIS !!!!! */
3828 +/*#define ARM_0_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) */ /* DO NOT USE THIS !!!!! */
3829 +/*#define ARM_0_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) */ /* DO NOT USE THIS !!!!! */
3830 +#define ARM_0_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN0+0xB8) /* Status read */
3831 +/*#define ARM_0_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) */ /* DO NOT USE THIS !!!!! */
3832 +/* General SEM, BELL, MAIL config/status */
3833 +#define ARM_0_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE0) /* semaphore clear/debug register */
3834 +#define ARM_0_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE4) /* Doorbells clear/debug register */
3835 +#define ARM_0_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xF8) /* ALL interrupts */
3836 +#define ARM_0_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xFC) /* IRQS pending for owner 0 */
3837 +
3838 +/* Semaphores, Doorbells, Mailboxes Owner 1 */
3839 +#define ARM_1_SEMS HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
3840 +#define ARM_1_SEM0 HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
3841 +#define ARM_1_SEM1 HW_REGISTER_RW(ARM_SBM_OWN1+0x04)
3842 +#define ARM_1_SEM2 HW_REGISTER_RW(ARM_SBM_OWN1+0x08)
3843 +#define ARM_1_SEM3 HW_REGISTER_RW(ARM_SBM_OWN1+0x0C)
3844 +#define ARM_1_SEM4 HW_REGISTER_RW(ARM_SBM_OWN1+0x10)
3845 +#define ARM_1_SEM5 HW_REGISTER_RW(ARM_SBM_OWN1+0x14)
3846 +#define ARM_1_SEM6 HW_REGISTER_RW(ARM_SBM_OWN1+0x18)
3847 +#define ARM_1_SEM7 HW_REGISTER_RW(ARM_SBM_OWN1+0x1C)
3848 +#define ARM_1_BELL0 HW_REGISTER_RW(ARM_SBM_OWN1+0x40)
3849 +#define ARM_1_BELL1 HW_REGISTER_RW(ARM_SBM_OWN1+0x44)
3850 +#define ARM_1_BELL2 HW_REGISTER_RW(ARM_SBM_OWN1+0x48)
3851 +#define ARM_1_BELL3 HW_REGISTER_RW(ARM_SBM_OWN1+0x4C)
3852 +/* MAILBOX 0 access in Owner 0 area */
3853 +/* Owner 1 should only WRITE to this mailbox */
3854 +#define ARM_1_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0x80) /* .. 0x8C (4 locations) */
3855 +/*#define ARM_1_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN1+0x80) */ /* DO NOT USE THIS !!!!! */
3856 +/*#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) */ /* DO NOT USE THIS !!!!! */
3857 +/*#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) */ /* DO NOT USE THIS !!!!! */
3858 +#define ARM_1_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN1+0x98) /* Status read */
3859 +/*#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) */ /* DO NOT USE THIS !!!!! */
3860 +/* MAILBOX 1 access in Owner 0 area */
3861 +#define ARM_1_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) */
3862 +#define ARM_1_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) Normal read */
3863 +#define ARM_1_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN1+0xB0) /* none-pop read */
3864 +#define ARM_1_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN1+0xB4) /* Sender read (only LS 2 bits) */
3865 +#define ARM_1_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN1+0xB8) /* Status read */
3866 +#define ARM_1_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0xBC)
3867 +/* General SEM, BELL, MAIL config/status */
3868 +#define ARM_1_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE0) /* semaphore clear/debug register */
3869 +#define ARM_1_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE4) /* Doorbells clear/debug register */
3870 +#define ARM_1_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xFC) /* IRQS pending for owner 1 */
3871 +#define ARM_1_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xF8) /* ALL interrupts */
3872 +
3873 +/* Semaphores, Doorbells, Mailboxes Owner 2 */
3874 +#define ARM_2_SEMS HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
3875 +#define ARM_2_SEM0 HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
3876 +#define ARM_2_SEM1 HW_REGISTER_RW(ARM_SBM_OWN2+0x04)
3877 +#define ARM_2_SEM2 HW_REGISTER_RW(ARM_SBM_OWN2+0x08)
3878 +#define ARM_2_SEM3 HW_REGISTER_RW(ARM_SBM_OWN2+0x0C)
3879 +#define ARM_2_SEM4 HW_REGISTER_RW(ARM_SBM_OWN2+0x10)
3880 +#define ARM_2_SEM5 HW_REGISTER_RW(ARM_SBM_OWN2+0x14)
3881 +#define ARM_2_SEM6 HW_REGISTER_RW(ARM_SBM_OWN2+0x18)
3882 +#define ARM_2_SEM7 HW_REGISTER_RW(ARM_SBM_OWN2+0x1C)
3883 +#define ARM_2_BELL0 HW_REGISTER_RW(ARM_SBM_OWN2+0x40)
3884 +#define ARM_2_BELL1 HW_REGISTER_RW(ARM_SBM_OWN2+0x44)
3885 +#define ARM_2_BELL2 HW_REGISTER_RW(ARM_SBM_OWN2+0x48)
3886 +#define ARM_2_BELL3 HW_REGISTER_RW(ARM_SBM_OWN2+0x4C)
3887 +/* MAILBOX 0 access in Owner 2 area */
3888 +/* Owner 2 should only WRITE to this mailbox */
3889 +#define ARM_2_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0x80) /* .. 0x8C (4 locations) */
3890 +/*#define ARM_2_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN2+0x80) */ /* DO NOT USE THIS !!!!! */
3891 +/*#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90) */ /* DO NOT USE THIS !!!!! */
3892 +/*#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94) */ /* DO NOT USE THIS !!!!! */
3893 +#define ARM_2_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN2+0x98) /* Status read */
3894 +/*#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C) */ /* DO NOT USE THIS !!!!! */
3895 +/* MAILBOX 1 access in Owner 2 area */
3896 +/* Owner 2 should only WRITE to this mailbox */
3897 +#define ARM_2_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) /* .. 0xAC (4 locations) */
3898 +/*#define ARM_2_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) */ /* DO NOT USE THIS !!!!! */
3899 +/*#define ARM_2_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) */ /* DO NOT USE THIS !!!!! */
3900 +/*#define ARM_2_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) */ /* DO NOT USE THIS !!!!! */
3901 +#define ARM_2_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN2+0xB8) /* Status read */
3902 +/*#define ARM_2_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) */ /* DO NOT USE THIS !!!!! */
3903 +/* General SEM, BELL, MAIL config/status */
3904 +#define ARM_2_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE0) /* semaphore clear/debug register */
3905 +#define ARM_2_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE4) /* Doorbells clear/debug register */
3906 +#define ARM_2_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xFC) /* IRQS pending for owner 2 */
3907 +#define ARM_2_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xF8) /* ALL interrupts */
3908 +
3909 +/* Semaphores, Doorbells, Mailboxes Owner 3 */
3910 +#define ARM_3_SEMS HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
3911 +#define ARM_3_SEM0 HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
3912 +#define ARM_3_SEM1 HW_REGISTER_RW(ARM_SBM_OWN3+0x04)
3913 +#define ARM_3_SEM2 HW_REGISTER_RW(ARM_SBM_OWN3+0x08)
3914 +#define ARM_3_SEM3 HW_REGISTER_RW(ARM_SBM_OWN3+0x0C)
3915 +#define ARM_3_SEM4 HW_REGISTER_RW(ARM_SBM_OWN3+0x10)
3916 +#define ARM_3_SEM5 HW_REGISTER_RW(ARM_SBM_OWN3+0x14)
3917 +#define ARM_3_SEM6 HW_REGISTER_RW(ARM_SBM_OWN3+0x18)
3918 +#define ARM_3_SEM7 HW_REGISTER_RW(ARM_SBM_OWN3+0x1C)
3919 +#define ARM_3_BELL0 HW_REGISTER_RW(ARM_SBM_OWN3+0x40)
3920 +#define ARM_3_BELL1 HW_REGISTER_RW(ARM_SBM_OWN3+0x44)
3921 +#define ARM_3_BELL2 HW_REGISTER_RW(ARM_SBM_OWN3+0x48)
3922 +#define ARM_3_BELL3 HW_REGISTER_RW(ARM_SBM_OWN3+0x4C)
3923 +/* MAILBOX 0 access in Owner 3 area */
3924 +/* Owner 3 should only WRITE to this mailbox */
3925 +#define ARM_3_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0x80) /* .. 0x8C (4 locations) */
3926 +/*#define ARM_3_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN3+0x80) */ /* DO NOT USE THIS !!!!! */
3927 +/*#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90) */ /* DO NOT USE THIS !!!!! */
3928 +/*#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94) */ /* DO NOT USE THIS !!!!! */
3929 +#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98) /* Status read */
3930 +/*#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C) */ /* DO NOT USE THIS !!!!! */
3931 +/* MAILBOX 1 access in Owner 3 area */
3932 +/* Owner 3 should only WRITE to this mailbox */
3933 +#define ARM_3_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) /* .. 0xAC (4 locations) */
3934 +/*#define ARM_3_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) */ /* DO NOT USE THIS !!!!! */
3935 +/*#define ARM_3_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) */ /* DO NOT USE THIS !!!!! */
3936 +/*#define ARM_3_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) */ /* DO NOT USE THIS !!!!! */
3937 +#define ARM_3_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN3+0xB8) /* Status read */
3938 +/*#define ARM_3_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) */ /* DO NOT USE THIS !!!!! */
3939 +/* General SEM, BELL, MAIL config/status */
3940 +#define ARM_3_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE0) /* semaphore clear/debug register */
3941 +#define ARM_3_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE4) /* Doorbells clear/debug register */
3942 +#define ARM_3_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xFC) /* IRQS pending for owner 3 */
3943 +#define ARM_3_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xF8) /* ALL interrupts */
3944 +
3945 +
3946 +
3947 +/* Mailbox flags. Valid for all owners */
3948 +
3949 +/* Mailbox status register (...0x98) */
3950 +#define ARM_MS_FULL 0x80000000
3951 +#define ARM_MS_EMPTY 0x40000000
3952 +#define ARM_MS_LEVEL 0x400000FF /* Max. value depdnds on mailbox depth parameter */
3953 +
3954 +/* MAILBOX config/status register (...0x9C) */
3955 +/* ANY write to this register clears the error bits! */
3956 +#define ARM_MC_IHAVEDATAIRQEN 0x00000001 /* mailbox irq enable: has data */
3957 +#define ARM_MC_IHAVESPACEIRQEN 0x00000002 /* mailbox irq enable: has space */
3958 +#define ARM_MC_OPPISEMPTYIRQEN 0x00000004 /* mailbox irq enable: Opp. is empty */
3959 +#define ARM_MC_MAIL_CLEAR 0x00000008 /* mailbox clear write 1, then 0 */
3960 +#define ARM_MC_IHAVEDATAIRQPEND 0x00000010 /* mailbox irq pending: has space */
3961 +#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 /* mailbox irq pending: Opp. is empty */
3962 +#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 /* mailbox irq pending */
3963 +/* Bit 7 is unused */
3964 +#define ARM_MC_ERRNOOWN 0x00000100 /* error : none owner read from mailbox */
3965 +#define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */
3966 +#define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */
3967 +
3968 +/* Semaphore clear/debug register (...0xE0) */
3969 +#define ARM_SD_OWN0 0x00000003 /* Owner of sem 0 */
3970 +#define ARM_SD_OWN1 0x0000000C /* Owner of sem 1 */
3971 +#define ARM_SD_OWN2 0x00000030 /* Owner of sem 2 */
3972 +#define ARM_SD_OWN3 0x000000C0 /* Owner of sem 3 */
3973 +#define ARM_SD_OWN4 0x00000300 /* Owner of sem 4 */
3974 +#define ARM_SD_OWN5 0x00000C00 /* Owner of sem 5 */
3975 +#define ARM_SD_OWN6 0x00003000 /* Owner of sem 6 */
3976 +#define ARM_SD_OWN7 0x0000C000 /* Owner of sem 7 */
3977 +#define ARM_SD_SEM0 0x00010000 /* Status of sem 0 */
3978 +#define ARM_SD_SEM1 0x00020000 /* Status of sem 1 */
3979 +#define ARM_SD_SEM2 0x00040000 /* Status of sem 2 */
3980 +#define ARM_SD_SEM3 0x00080000 /* Status of sem 3 */
3981 +#define ARM_SD_SEM4 0x00100000 /* Status of sem 4 */
3982 +#define ARM_SD_SEM5 0x00200000 /* Status of sem 5 */
3983 +#define ARM_SD_SEM6 0x00400000 /* Status of sem 6 */
3984 +#define ARM_SD_SEM7 0x00800000 /* Status of sem 7 */
3985 +
3986 +/* Doorbells clear/debug register (...0xE4) */
3987 +#define ARM_BD_OWN0 0x00000003 /* Owner of doorbell 0 */
3988 +#define ARM_BD_OWN1 0x0000000C /* Owner of doorbell 1 */
3989 +#define ARM_BD_OWN2 0x00000030 /* Owner of doorbell 2 */
3990 +#define ARM_BD_OWN3 0x000000C0 /* Owner of doorbell 3 */
3991 +#define ARM_BD_BELL0 0x00000100 /* Status of doorbell 0 */
3992 +#define ARM_BD_BELL1 0x00000200 /* Status of doorbell 1 */
3993 +#define ARM_BD_BELL2 0x00000400 /* Status of doorbell 2 */
3994 +#define ARM_BD_BELL3 0x00000800 /* Status of doorbell 3 */
3995 +
3996 +/* MY IRQS register (...0xF8) */
3997 +#define ARM_MYIRQ_BELL 0x00000001 /* This owner has a doorbell IRQ */
3998 +#define ARM_MYIRQ_MAIL 0x00000002 /* This owner has a mailbox IRQ */
3999 +
4000 +/* ALL IRQS register (...0xF8) */
4001 +#define ARM_AIS_BELL0 0x00000001 /* Doorbell 0 IRQ pending */
4002 +#define ARM_AIS_BELL1 0x00000002 /* Doorbell 1 IRQ pending */
4003 +#define ARM_AIS_BELL2 0x00000004 /* Doorbell 2 IRQ pending */
4004 +#define ARM_AIS_BELL3 0x00000008 /* Doorbell 3 IRQ pending */
4005 +#define ARM_AIS0_HAVEDATA 0x00000010 /* MAIL 0 has data IRQ pending */
4006 +#define ARM_AIS0_HAVESPAC 0x00000020 /* MAIL 0 has space IRQ pending */
4007 +#define ARM_AIS0_OPPEMPTY 0x00000040 /* MAIL 0 opposite is empty IRQ */
4008 +#define ARM_AIS1_HAVEDATA 0x00000080 /* MAIL 1 has data IRQ pending */
4009 +#define ARM_AIS1_HAVESPAC 0x00000100 /* MAIL 1 has space IRQ pending */
4010 +#define ARM_AIS1_OPPEMPTY 0x00000200 /* MAIL 1 opposite is empty IRQ */
4011 +/* Note that bell-0, bell-1 and MAIL0 IRQ go only to the ARM */
4012 +/* Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC */
4013 +/* */
4014 +/* ARM JTAG BASH */
4015 +/* */
4016 +#define AJB_BASE 0x7e2000c0
4017 +
4018 +#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00)
4019 +#define AJB_BITS0 0x000000
4020 +#define AJB_BITS4 0x000004
4021 +#define AJB_BITS8 0x000008
4022 +#define AJB_BITS12 0x00000C
4023 +#define AJB_BITS16 0x000010
4024 +#define AJB_BITS20 0x000014
4025 +#define AJB_BITS24 0x000018
4026 +#define AJB_BITS28 0x00001C
4027 +#define AJB_BITS32 0x000020
4028 +#define AJB_BITS34 0x000022
4029 +#define AJB_OUT_MS 0x000040
4030 +#define AJB_OUT_LS 0x000000
4031 +#define AJB_INV_CLK 0x000080
4032 +#define AJB_D0_RISE 0x000100
4033 +#define AJB_D0_FALL 0x000000
4034 +#define AJB_D1_RISE 0x000200
4035 +#define AJB_D1_FALL 0x000000
4036 +#define AJB_IN_RISE 0x000400
4037 +#define AJB_IN_FALL 0x000000
4038 +#define AJB_ENABLE 0x000800
4039 +#define AJB_HOLD0 0x000000
4040 +#define AJB_HOLD1 0x001000
4041 +#define AJB_HOLD2 0x002000
4042 +#define AJB_HOLD3 0x003000
4043 +#define AJB_RESETN 0x004000
4044 +#define AJB_CLKSHFT 16
4045 +#define AJB_BUSY 0x80000000
4046 +#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04)
4047 +#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08)
4048 +#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c)
4049 +
4050 +#endif
4051 --- /dev/null
4052 +++ b/arch/arm/mach-bcm2708/include/mach/arm_power.h
4053 @@ -0,0 +1,60 @@
4054 +/*
4055 + * linux/arch/arm/mach-bcm2708/include/mach/arm_power.h
4056 + *
4057 + * Copyright (C) 2010 Broadcom
4058 + *
4059 + * This program is free software; you can redistribute it and/or modify
4060 + * it under the terms of the GNU General Public License as published by
4061 + * the Free Software Foundation; either version 2 of the License, or
4062 + * (at your option) any later version.
4063 + *
4064 + * This program is distributed in the hope that it will be useful,
4065 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4066 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4067 + * GNU General Public License for more details.
4068 + *
4069 + * You should have received a copy of the GNU General Public License
4070 + * along with this program; if not, write to the Free Software
4071 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4072 + */
4073 +
4074 +#ifndef _ARM_POWER_H
4075 +#define _ARM_POWER_H
4076 +
4077 +/* Use meaningful names on each side */
4078 +#ifdef __VIDEOCORE__
4079 +#define PREFIX(x) ARM_##x
4080 +#else
4081 +#define PREFIX(x) BCM_##x
4082 +#endif
4083 +
4084 +enum {
4085 + PREFIX(POWER_SDCARD_BIT),
4086 + PREFIX(POWER_UART_BIT),
4087 + PREFIX(POWER_MINIUART_BIT),
4088 + PREFIX(POWER_USB_BIT),
4089 + PREFIX(POWER_I2C0_BIT),
4090 + PREFIX(POWER_I2C1_BIT),
4091 + PREFIX(POWER_I2C2_BIT),
4092 + PREFIX(POWER_SPI_BIT),
4093 + PREFIX(POWER_CCP2TX_BIT),
4094 +
4095 + PREFIX(POWER_MAX)
4096 +};
4097 +
4098 +enum {
4099 + PREFIX(POWER_SDCARD) = (1 << PREFIX(POWER_SDCARD_BIT)),
4100 + PREFIX(POWER_UART) = (1 << PREFIX(POWER_UART_BIT)),
4101 + PREFIX(POWER_MINIUART) = (1 << PREFIX(POWER_MINIUART_BIT)),
4102 + PREFIX(POWER_USB) = (1 << PREFIX(POWER_USB_BIT)),
4103 + PREFIX(POWER_I2C0) = (1 << PREFIX(POWER_I2C0_BIT)),
4104 + PREFIX(POWER_I2C1_MASK) = (1 << PREFIX(POWER_I2C1_BIT)),
4105 + PREFIX(POWER_I2C2_MASK) = (1 << PREFIX(POWER_I2C2_BIT)),
4106 + PREFIX(POWER_SPI_MASK) = (1 << PREFIX(POWER_SPI_BIT)),
4107 + PREFIX(POWER_CCP2TX_MASK) = (1 << PREFIX(POWER_CCP2TX_BIT)),
4108 +
4109 + PREFIX(POWER_MASK) = (1 << PREFIX(POWER_MAX)) - 1,
4110 + PREFIX(POWER_NONE) = 0
4111 +};
4112 +
4113 +#endif
4114 --- /dev/null
4115 +++ b/arch/arm/mach-bcm2708/include/mach/clkdev.h
4116 @@ -0,0 +1,7 @@
4117 +#ifndef __ASM_MACH_CLKDEV_H
4118 +#define __ASM_MACH_CLKDEV_H
4119 +
4120 +#define __clk_get(clk) ({ 1; })
4121 +#define __clk_put(clk) do { } while (0)
4122 +
4123 +#endif
4124 --- /dev/null
4125 +++ b/arch/arm/mach-bcm2708/include/mach/debug-macro.S
4126 @@ -0,0 +1,22 @@
4127 +/* arch/arm/mach-bcm2708/include/mach/debug-macro.S
4128 + *
4129 + * Debugging macro include header
4130 + *
4131 + * Copyright (C) 2010 Broadcom
4132 + * Copyright (C) 1994-1999 Russell King
4133 + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
4134 + *
4135 + * This program is free software; you can redistribute it and/or modify
4136 + * it under the terms of the GNU General Public License version 2 as
4137 + * published by the Free Software Foundation.
4138 + *
4139 +*/
4140 +
4141 +#include <mach/platform.h>
4142 +
4143 + .macro addruart, rp, rv, tmp
4144 + ldr \rp, =UART0_BASE
4145 + ldr \rv, =IO_ADDRESS(UART0_BASE)
4146 + .endm
4147 +
4148 +#include <debug/pl01x.S>
4149 --- /dev/null
4150 +++ b/arch/arm/mach-bcm2708/include/mach/dma.h
4151 @@ -0,0 +1,86 @@
4152 +/*
4153 + * linux/arch/arm/mach-bcm2708/include/mach/dma.h
4154 + *
4155 + * Copyright (C) 2010 Broadcom
4156 + *
4157 + * This program is free software; you can redistribute it and/or modify
4158 + * it under the terms of the GNU General Public License version 2 as
4159 + * published by the Free Software Foundation.
4160 + */
4161 +
4162 +
4163 +#ifndef _MACH_BCM2708_DMA_H
4164 +#define _MACH_BCM2708_DMA_H
4165 +
4166 +#define BCM_DMAMAN_DRIVER_NAME "bcm2708_dma"
4167 +
4168 +/* DMA CS Control and Status bits */
4169 +#define BCM2708_DMA_ACTIVE (1 << 0)
4170 +#define BCM2708_DMA_INT (1 << 2)
4171 +#define BCM2708_DMA_ISPAUSED (1 << 4) /* Pause requested or not active */
4172 +#define BCM2708_DMA_ISHELD (1 << 5) /* Is held by DREQ flow control */
4173 +#define BCM2708_DMA_ERR (1 << 8)
4174 +#define BCM2708_DMA_ABORT (1 << 30) /* stop current CB, go to next, WO */
4175 +#define BCM2708_DMA_RESET (1 << 31) /* WO, self clearing */
4176 +
4177 +/* DMA control block "info" field bits */
4178 +#define BCM2708_DMA_INT_EN (1 << 0)
4179 +#define BCM2708_DMA_TDMODE (1 << 1)
4180 +#define BCM2708_DMA_WAIT_RESP (1 << 3)
4181 +#define BCM2708_DMA_D_INC (1 << 4)
4182 +#define BCM2708_DMA_D_WIDTH (1 << 5)
4183 +#define BCM2708_DMA_D_DREQ (1 << 6)
4184 +#define BCM2708_DMA_S_INC (1 << 8)
4185 +#define BCM2708_DMA_S_WIDTH (1 << 9)
4186 +#define BCM2708_DMA_S_DREQ (1 << 10)
4187 +
4188 +#define BCM2708_DMA_BURST(x) (((x)&0xf) << 12)
4189 +#define BCM2708_DMA_PER_MAP(x) ((x) << 16)
4190 +#define BCM2708_DMA_WAITS(x) (((x)&0x1f) << 21)
4191 +
4192 +#define BCM2708_DMA_DREQ_EMMC 11
4193 +#define BCM2708_DMA_DREQ_SDHOST 13
4194 +
4195 +#define BCM2708_DMA_CS 0x00 /* Control and Status */
4196 +#define BCM2708_DMA_ADDR 0x04
4197 +/* the current control block appears in the following registers - read only */
4198 +#define BCM2708_DMA_INFO 0x08
4199 +#define BCM2708_DMA_NEXTCB 0x1C
4200 +#define BCM2708_DMA_DEBUG 0x20
4201 +
4202 +#define BCM2708_DMA4_CS (BCM2708_DMA_CHAN(4)+BCM2708_DMA_CS)
4203 +#define BCM2708_DMA4_ADDR (BCM2708_DMA_CHAN(4)+BCM2708_DMA_ADDR)
4204 +
4205 +#define BCM2708_DMA_TDMODE_LEN(w, h) ((h) << 16 | (w))
4206 +
4207 +struct bcm2708_dma_cb {
4208 + unsigned long info;
4209 + unsigned long src;
4210 + unsigned long dst;
4211 + unsigned long length;
4212 + unsigned long stride;
4213 + unsigned long next;
4214 + unsigned long pad[2];
4215 +};
4216 +
4217 +extern int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len);
4218 +extern void bcm_dma_start(void __iomem *dma_chan_base,
4219 + dma_addr_t control_block);
4220 +extern void bcm_dma_wait_idle(void __iomem *dma_chan_base);
4221 +extern int /*rc*/ bcm_dma_abort(void __iomem *dma_chan_base);
4222 +
4223 +/* When listing features we can ask for when allocating DMA channels give
4224 + those with higher priority smaller ordinal numbers */
4225 +#define BCM_DMA_FEATURE_FAST_ORD 0
4226 +#define BCM_DMA_FEATURE_BULK_ORD 1
4227 +#define BCM_DMA_FEATURE_FAST (1<<BCM_DMA_FEATURE_FAST_ORD)
4228 +#define BCM_DMA_FEATURE_BULK (1<<BCM_DMA_FEATURE_BULK_ORD)
4229 +#define BCM_DMA_FEATURE_COUNT 2
4230 +
4231 +/* return channel no or -ve error */
4232 +extern int bcm_dma_chan_alloc(unsigned preferred_feature_set,
4233 + void __iomem **out_dma_base, int *out_dma_irq);
4234 +extern int bcm_dma_chan_free(int channel);
4235 +
4236 +
4237 +#endif /* _MACH_BCM2708_DMA_H */
4238 --- /dev/null
4239 +++ b/arch/arm/mach-bcm2708/include/mach/entry-macro.S
4240 @@ -0,0 +1,69 @@
4241 +/*
4242 + * arch/arm/mach-bcm2708/include/mach/entry-macro.S
4243 + *
4244 + * Low-level IRQ helper macros for BCM2708 platforms
4245 + *
4246 + * Copyright (C) 2010 Broadcom
4247 + *
4248 + * This program is free software; you can redistribute it and/or modify
4249 + * it under the terms of the GNU General Public License as published by
4250 + * the Free Software Foundation; either version 2 of the License, or
4251 + * (at your option) any later version.
4252 + *
4253 + * This program is distributed in the hope that it will be useful,
4254 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4255 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4256 + * GNU General Public License for more details.
4257 + *
4258 + * You should have received a copy of the GNU General Public License
4259 + * along with this program; if not, write to the Free Software
4260 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4261 + */
4262 +#include <mach/hardware.h>
4263 +
4264 + .macro disable_fiq
4265 + .endm
4266 +
4267 + .macro get_irqnr_preamble, base, tmp
4268 + ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE)
4269 + .endm
4270 +
4271 + .macro arch_ret_to_user, tmp1, tmp2
4272 + .endm
4273 +
4274 + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
4275 + /* get masked status */
4276 + ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)]
4277 + mov \irqnr, #(ARM_IRQ0_BASE + 31)
4278 + and \tmp, \irqstat, #0x300 @ save bits 8 and 9
4279 + /* clear bits 8 and 9, and test */
4280 + bics \irqstat, \irqstat, #0x300
4281 + bne 1010f
4282 +
4283 + tst \tmp, #0x100
4284 + ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)]
4285 + movne \irqnr, #(ARM_IRQ1_BASE + 31)
4286 + @ Mask out the interrupts also present in PEND0 - see SW-5809
4287 + bicne \irqstat, #((1<<7) | (1<<9) | (1<<10))
4288 + bicne \irqstat, #((1<<18) | (1<<19))
4289 + bne 1010f
4290 +
4291 + tst \tmp, #0x200
4292 + ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)]
4293 + movne \irqnr, #(ARM_IRQ2_BASE + 31)
4294 + @ Mask out the interrupts also present in PEND0 - see SW-5809
4295 + bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25))
4296 + bicne \irqstat, #((1<<30))
4297 + beq 1020f
4298 +
4299 +1010:
4300 + @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
4301 + @ N.B. CLZ is an ARM5 instruction.
4302 + sub \tmp, \irqstat, #1
4303 + eor \irqstat, \irqstat, \tmp
4304 + clz \tmp, \irqstat
4305 + sub \irqnr, \tmp
4306 +
4307 +1020: @ EQ will be set if no irqs pending
4308 +
4309 + .endm
4310 --- /dev/null
4311 +++ b/arch/arm/mach-bcm2708/include/mach/frc.h
4312 @@ -0,0 +1,38 @@
4313 +/*
4314 + * arch/arm/mach-bcm2708/include/mach/timex.h
4315 + *
4316 + * BCM2708 free running counter (timer)
4317 + *
4318 + * Copyright (C) 2010 Broadcom
4319 + *
4320 + * This program is free software; you can redistribute it and/or modify
4321 + * it under the terms of the GNU General Public License as published by
4322 + * the Free Software Foundation; either version 2 of the License, or
4323 + * (at your option) any later version.
4324 + *
4325 + * This program is distributed in the hope that it will be useful,
4326 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4327 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4328 + * GNU General Public License for more details.
4329 + *
4330 + * You should have received a copy of the GNU General Public License
4331 + * along with this program; if not, write to the Free Software
4332 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4333 + */
4334 +
4335 +#ifndef _MACH_FRC_H
4336 +#define _MACH_FRC_H
4337 +
4338 +#define FRC_TICK_RATE (1000000)
4339 +
4340 +/*! Free running counter incrementing at the CLOCK_TICK_RATE
4341 + (slightly faster than frc_clock_ticks63()
4342 + */
4343 +extern unsigned long frc_clock_ticks32(void);
4344 +
4345 +/*! Free running counter incrementing at the CLOCK_TICK_RATE
4346 + * Note - top bit should be ignored (see cnt32_to_63)
4347 + */
4348 +extern unsigned long long frc_clock_ticks63(void);
4349 +
4350 +#endif
4351 --- /dev/null
4352 +++ b/arch/arm/mach-bcm2708/include/mach/gpio.h
4353 @@ -0,0 +1,17 @@
4354 +/*
4355 + * arch/arm/mach-bcm2708/include/mach/gpio.h
4356 + *
4357 + * This file is licensed under the terms of the GNU General Public
4358 + * License version 2. This program is licensed "as is" without any
4359 + * warranty of any kind, whether express or implied.
4360 + */
4361 +
4362 +#ifndef __ASM_ARCH_GPIO_H
4363 +#define __ASM_ARCH_GPIO_H
4364 +
4365 +#define BCM2708_NR_GPIOS 54 // number of gpio lines
4366 +
4367 +#define gpio_to_irq(x) ((x) + GPIO_IRQ_START)
4368 +#define irq_to_gpio(x) ((x) - GPIO_IRQ_START)
4369 +
4370 +#endif
4371 --- /dev/null
4372 +++ b/arch/arm/mach-bcm2708/include/mach/hardware.h
4373 @@ -0,0 +1,28 @@
4374 +/*
4375 + * arch/arm/mach-bcm2708/include/mach/hardware.h
4376 + *
4377 + * This file contains the hardware definitions of the BCM2708 devices.
4378 + *
4379 + * Copyright (C) 2010 Broadcom
4380 + *
4381 + * This program is free software; you can redistribute it and/or modify
4382 + * it under the terms of the GNU General Public License as published by
4383 + * the Free Software Foundation; either version 2 of the License, or
4384 + * (at your option) any later version.
4385 + *
4386 + * This program is distributed in the hope that it will be useful,
4387 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4388 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4389 + * GNU General Public License for more details.
4390 + *
4391 + * You should have received a copy of the GNU General Public License
4392 + * along with this program; if not, write to the Free Software
4393 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4394 + */
4395 +#ifndef __ASM_ARCH_HARDWARE_H
4396 +#define __ASM_ARCH_HARDWARE_H
4397 +
4398 +#include <asm/sizes.h>
4399 +#include <mach/platform.h>
4400 +
4401 +#endif
4402 --- /dev/null
4403 +++ b/arch/arm/mach-bcm2708/include/mach/io.h
4404 @@ -0,0 +1,27 @@
4405 +/*
4406 + * arch/arm/mach-bcm2708/include/mach/io.h
4407 + *
4408 + * Copyright (C) 2003 ARM Limited
4409 + *
4410 + * This program is free software; you can redistribute it and/or modify
4411 + * it under the terms of the GNU General Public License as published by
4412 + * the Free Software Foundation; either version 2 of the License, or
4413 + * (at your option) any later version.
4414 + *
4415 + * This program is distributed in the hope that it will be useful,
4416 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4417 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4418 + * GNU General Public License for more details.
4419 + *
4420 + * You should have received a copy of the GNU General Public License
4421 + * along with this program; if not, write to the Free Software
4422 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4423 + */
4424 +#ifndef __ASM_ARM_ARCH_IO_H
4425 +#define __ASM_ARM_ARCH_IO_H
4426 +
4427 +#define IO_SPACE_LIMIT 0xffffffff
4428 +
4429 +#define __io(a) __typesafe_io(a)
4430 +
4431 +#endif
4432 --- /dev/null
4433 +++ b/arch/arm/mach-bcm2708/include/mach/irqs.h
4434 @@ -0,0 +1,194 @@
4435 +/*
4436 + * arch/arm/mach-bcm2708/include/mach/irqs.h
4437 + *
4438 + * Copyright (C) 2010 Broadcom
4439 + * Copyright (C) 2003 ARM Limited
4440 + * Copyright (C) 2000 Deep Blue Solutions Ltd.
4441 + *
4442 + * This program is free software; you can redistribute it and/or modify
4443 + * it under the terms of the GNU General Public License as published by
4444 + * the Free Software Foundation; either version 2 of the License, or
4445 + * (at your option) any later version.
4446 + *
4447 + * This program is distributed in the hope that it will be useful,
4448 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4449 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4450 + * GNU General Public License for more details.
4451 + *
4452 + * You should have received a copy of the GNU General Public License
4453 + * along with this program; if not, write to the Free Software
4454 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4455 + */
4456 +
4457 +#ifndef _BCM2708_IRQS_H_
4458 +#define _BCM2708_IRQS_H_
4459 +
4460 +#include <mach/platform.h>
4461 +
4462 +/*
4463 + * IRQ interrupts definitions are the same as the INT definitions
4464 + * held within platform.h
4465 + */
4466 +#define IRQ_ARMCTRL_START 0
4467 +#define IRQ_TIMER0 (IRQ_ARMCTRL_START + INTERRUPT_TIMER0)
4468 +#define IRQ_TIMER1 (IRQ_ARMCTRL_START + INTERRUPT_TIMER1)
4469 +#define IRQ_TIMER2 (IRQ_ARMCTRL_START + INTERRUPT_TIMER2)
4470 +#define IRQ_TIMER3 (IRQ_ARMCTRL_START + INTERRUPT_TIMER3)
4471 +#define IRQ_CODEC0 (IRQ_ARMCTRL_START + INTERRUPT_CODEC0)
4472 +#define IRQ_CODEC1 (IRQ_ARMCTRL_START + INTERRUPT_CODEC1)
4473 +#define IRQ_CODEC2 (IRQ_ARMCTRL_START + INTERRUPT_CODEC2)
4474 +#define IRQ_JPEG (IRQ_ARMCTRL_START + INTERRUPT_JPEG)
4475 +#define IRQ_ISP (IRQ_ARMCTRL_START + INTERRUPT_ISP)
4476 +#define IRQ_USB (IRQ_ARMCTRL_START + INTERRUPT_USB)
4477 +#define IRQ_3D (IRQ_ARMCTRL_START + INTERRUPT_3D)
4478 +#define IRQ_TRANSPOSER (IRQ_ARMCTRL_START + INTERRUPT_TRANSPOSER)
4479 +#define IRQ_MULTICORESYNC0 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC0)
4480 +#define IRQ_MULTICORESYNC1 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC1)
4481 +#define IRQ_MULTICORESYNC2 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC2)
4482 +#define IRQ_MULTICORESYNC3 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC3)
4483 +#define IRQ_DMA0 (IRQ_ARMCTRL_START + INTERRUPT_DMA0)
4484 +#define IRQ_DMA1 (IRQ_ARMCTRL_START + INTERRUPT_DMA1)
4485 +#define IRQ_DMA2 (IRQ_ARMCTRL_START + INTERRUPT_DMA2)
4486 +#define IRQ_DMA3 (IRQ_ARMCTRL_START + INTERRUPT_DMA3)
4487 +#define IRQ_DMA4 (IRQ_ARMCTRL_START + INTERRUPT_DMA4)
4488 +#define IRQ_DMA5 (IRQ_ARMCTRL_START + INTERRUPT_DMA5)
4489 +#define IRQ_DMA6 (IRQ_ARMCTRL_START + INTERRUPT_DMA6)
4490 +#define IRQ_DMA7 (IRQ_ARMCTRL_START + INTERRUPT_DMA7)
4491 +#define IRQ_DMA8 (IRQ_ARMCTRL_START + INTERRUPT_DMA8)
4492 +#define IRQ_DMA9 (IRQ_ARMCTRL_START + INTERRUPT_DMA9)
4493 +#define IRQ_DMA10 (IRQ_ARMCTRL_START + INTERRUPT_DMA10)
4494 +#define IRQ_DMA11 (IRQ_ARMCTRL_START + INTERRUPT_DMA11)
4495 +#define IRQ_DMA12 (IRQ_ARMCTRL_START + INTERRUPT_DMA12)
4496 +#define IRQ_AUX (IRQ_ARMCTRL_START + INTERRUPT_AUX)
4497 +#define IRQ_ARM (IRQ_ARMCTRL_START + INTERRUPT_ARM)
4498 +#define IRQ_VPUDMA (IRQ_ARMCTRL_START + INTERRUPT_VPUDMA)
4499 +#define IRQ_HOSTPORT (IRQ_ARMCTRL_START + INTERRUPT_HOSTPORT)
4500 +#define IRQ_VIDEOSCALER (IRQ_ARMCTRL_START + INTERRUPT_VIDEOSCALER)
4501 +#define IRQ_CCP2TX (IRQ_ARMCTRL_START + INTERRUPT_CCP2TX)
4502 +#define IRQ_SDC (IRQ_ARMCTRL_START + INTERRUPT_SDC)
4503 +#define IRQ_DSI0 (IRQ_ARMCTRL_START + INTERRUPT_DSI0)
4504 +#define IRQ_AVE (IRQ_ARMCTRL_START + INTERRUPT_AVE)
4505 +#define IRQ_CAM0 (IRQ_ARMCTRL_START + INTERRUPT_CAM0)
4506 +#define IRQ_CAM1 (IRQ_ARMCTRL_START + INTERRUPT_CAM1)
4507 +#define IRQ_HDMI0 (IRQ_ARMCTRL_START + INTERRUPT_HDMI0)
4508 +#define IRQ_HDMI1 (IRQ_ARMCTRL_START + INTERRUPT_HDMI1)
4509 +#define IRQ_PIXELVALVE1 (IRQ_ARMCTRL_START + INTERRUPT_PIXELVALVE1)
4510 +#define IRQ_I2CSPISLV (IRQ_ARMCTRL_START + INTERRUPT_I2CSPISLV)
4511 +#define IRQ_DSI1 (IRQ_ARMCTRL_START + INTERRUPT_DSI1)
4512 +#define IRQ_PWA0 (IRQ_ARMCTRL_START + INTERRUPT_PWA0)
4513 +#define IRQ_PWA1 (IRQ_ARMCTRL_START + INTERRUPT_PWA1)
4514 +#define IRQ_CPR (IRQ_ARMCTRL_START + INTERRUPT_CPR)
4515 +#define IRQ_SMI (IRQ_ARMCTRL_START + INTERRUPT_SMI)
4516 +#define IRQ_GPIO0 (IRQ_ARMCTRL_START + INTERRUPT_GPIO0)
4517 +#define IRQ_GPIO1 (IRQ_ARMCTRL_START + INTERRUPT_GPIO1)
4518 +#define IRQ_GPIO2 (IRQ_ARMCTRL_START + INTERRUPT_GPIO2)
4519 +#define IRQ_GPIO3 (IRQ_ARMCTRL_START + INTERRUPT_GPIO3)
4520 +#define IRQ_I2C (IRQ_ARMCTRL_START + INTERRUPT_I2C)
4521 +#define IRQ_SPI (IRQ_ARMCTRL_START + INTERRUPT_SPI)
4522 +#define IRQ_I2SPCM (IRQ_ARMCTRL_START + INTERRUPT_I2SPCM)
4523 +#define IRQ_SDIO (IRQ_ARMCTRL_START + INTERRUPT_SDIO)
4524 +#define IRQ_UART (IRQ_ARMCTRL_START + INTERRUPT_UART)
4525 +#define IRQ_SLIMBUS (IRQ_ARMCTRL_START + INTERRUPT_SLIMBUS)
4526 +#define IRQ_VEC (IRQ_ARMCTRL_START + INTERRUPT_VEC)
4527 +#define IRQ_CPG (IRQ_ARMCTRL_START + INTERRUPT_CPG)
4528 +#define IRQ_RNG (IRQ_ARMCTRL_START + INTERRUPT_RNG)
4529 +#define IRQ_ARASANSDIO (IRQ_ARMCTRL_START + INTERRUPT_ARASANSDIO)
4530 +#define IRQ_AVSPMON (IRQ_ARMCTRL_START + INTERRUPT_AVSPMON)
4531 +
4532 +#define IRQ_ARM_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_TIMER)
4533 +#define IRQ_ARM_MAILBOX (IRQ_ARMCTRL_START + INTERRUPT_ARM_MAILBOX)
4534 +#define IRQ_ARM_DOORBELL_0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_0)
4535 +#define IRQ_ARM_DOORBELL_1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_1)
4536 +#define IRQ_VPU0_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU0_HALTED)
4537 +#define IRQ_VPU1_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU1_HALTED)
4538 +#define IRQ_ILLEGAL_TYPE0 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE0)
4539 +#define IRQ_ILLEGAL_TYPE1 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE1)
4540 +#define IRQ_PENDING1 (IRQ_ARMCTRL_START + INTERRUPT_PENDING1)
4541 +#define IRQ_PENDING2 (IRQ_ARMCTRL_START + INTERRUPT_PENDING2)
4542 +
4543 +/*
4544 + * FIQ interrupts definitions are the same as the INT definitions.
4545 + */
4546 +#define FIQ_TIMER0 INT_TIMER0
4547 +#define FIQ_TIMER1 INT_TIMER1
4548 +#define FIQ_TIMER2 INT_TIMER2
4549 +#define FIQ_TIMER3 INT_TIMER3
4550 +#define FIQ_CODEC0 INT_CODEC0
4551 +#define FIQ_CODEC1 INT_CODEC1
4552 +#define FIQ_CODEC2 INT_CODEC2
4553 +#define FIQ_JPEG INT_JPEG
4554 +#define FIQ_ISP INT_ISP
4555 +#define FIQ_USB INT_USB
4556 +#define FIQ_3D INT_3D
4557 +#define FIQ_TRANSPOSER INT_TRANSPOSER
4558 +#define FIQ_MULTICORESYNC0 INT_MULTICORESYNC0
4559 +#define FIQ_MULTICORESYNC1 INT_MULTICORESYNC1
4560 +#define FIQ_MULTICORESYNC2 INT_MULTICORESYNC2
4561 +#define FIQ_MULTICORESYNC3 INT_MULTICORESYNC3
4562 +#define FIQ_DMA0 INT_DMA0
4563 +#define FIQ_DMA1 INT_DMA1
4564 +#define FIQ_DMA2 INT_DMA2
4565 +#define FIQ_DMA3 INT_DMA3
4566 +#define FIQ_DMA4 INT_DMA4
4567 +#define FIQ_DMA5 INT_DMA5
4568 +#define FIQ_DMA6 INT_DMA6
4569 +#define FIQ_DMA7 INT_DMA7
4570 +#define FIQ_DMA8 INT_DMA8
4571 +#define FIQ_DMA9 INT_DMA9
4572 +#define FIQ_DMA10 INT_DMA10
4573 +#define FIQ_DMA11 INT_DMA11
4574 +#define FIQ_DMA12 INT_DMA12
4575 +#define FIQ_AUX INT_AUX
4576 +#define FIQ_ARM INT_ARM
4577 +#define FIQ_VPUDMA INT_VPUDMA
4578 +#define FIQ_HOSTPORT INT_HOSTPORT
4579 +#define FIQ_VIDEOSCALER INT_VIDEOSCALER
4580 +#define FIQ_CCP2TX INT_CCP2TX
4581 +#define FIQ_SDC INT_SDC
4582 +#define FIQ_DSI0 INT_DSI0
4583 +#define FIQ_AVE INT_AVE
4584 +#define FIQ_CAM0 INT_CAM0
4585 +#define FIQ_CAM1 INT_CAM1
4586 +#define FIQ_HDMI0 INT_HDMI0
4587 +#define FIQ_HDMI1 INT_HDMI1
4588 +#define FIQ_PIXELVALVE1 INT_PIXELVALVE1
4589 +#define FIQ_I2CSPISLV INT_I2CSPISLV
4590 +#define FIQ_DSI1 INT_DSI1
4591 +#define FIQ_PWA0 INT_PWA0
4592 +#define FIQ_PWA1 INT_PWA1
4593 +#define FIQ_CPR INT_CPR
4594 +#define FIQ_SMI INT_SMI
4595 +#define FIQ_GPIO0 INT_GPIO0
4596 +#define FIQ_GPIO1 INT_GPIO1
4597 +#define FIQ_GPIO2 INT_GPIO2
4598 +#define FIQ_GPIO3 INT_GPIO3
4599 +#define FIQ_I2C INT_I2C
4600 +#define FIQ_SPI INT_SPI
4601 +#define FIQ_I2SPCM INT_I2SPCM
4602 +#define FIQ_SDIO INT_SDIO
4603 +#define FIQ_UART INT_UART
4604 +#define FIQ_SLIMBUS INT_SLIMBUS
4605 +#define FIQ_VEC INT_VEC
4606 +#define FIQ_CPG INT_CPG
4607 +#define FIQ_RNG INT_RNG
4608 +#define FIQ_ARASANSDIO INT_ARASANSDIO
4609 +#define FIQ_AVSPMON INT_AVSPMON
4610 +
4611 +#define FIQ_ARM_TIMER INT_ARM_TIMER
4612 +#define FIQ_ARM_MAILBOX INT_ARM_MAILBOX
4613 +#define FIQ_ARM_DOORBELL_0 INT_ARM_DOORBELL_0
4614 +#define FIQ_ARM_DOORBELL_1 INT_ARM_DOORBELL_1
4615 +#define FIQ_VPU0_HALTED INT_VPU0_HALTED
4616 +#define FIQ_VPU1_HALTED INT_VPU1_HALTED
4617 +#define FIQ_ILLEGAL_TYPE0 INT_ILLEGAL_TYPE0
4618 +#define FIQ_ILLEGAL_TYPE1 INT_ILLEGAL_TYPE1
4619 +#define FIQ_PENDING1 INT_PENDING1
4620 +#define FIQ_PENDING2 INT_PENDING2
4621 +
4622 +#define HARD_IRQS (64 + 21)
4623 +#define GPIO_IRQ_START (HARD_IRQS)
4624 +#define GPIO_IRQS (32*5)
4625 +#define SPARE_IRQS (64)
4626 +#define NR_IRQS (HARD_IRQS+GPIO_IRQS+SPARE_IRQS)
4627 +
4628 +#endif /* _BCM2708_IRQS_H_ */
4629 --- /dev/null
4630 +++ b/arch/arm/mach-bcm2708/include/mach/memory.h
4631 @@ -0,0 +1,57 @@
4632 +/*
4633 + * arch/arm/mach-bcm2708/include/mach/memory.h
4634 + *
4635 + * Copyright (C) 2010 Broadcom
4636 + *
4637 + * This program is free software; you can redistribute it and/or modify
4638 + * it under the terms of the GNU General Public License as published by
4639 + * the Free Software Foundation; either version 2 of the License, or
4640 + * (at your option) any later version.
4641 + *
4642 + * This program is distributed in the hope that it will be useful,
4643 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4644 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4645 + * GNU General Public License for more details.
4646 + *
4647 + * You should have received a copy of the GNU General Public License
4648 + * along with this program; if not, write to the Free Software
4649 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4650 + */
4651 +#ifndef __ASM_ARCH_MEMORY_H
4652 +#define __ASM_ARCH_MEMORY_H
4653 +
4654 +/* Memory overview:
4655 +
4656 + [ARMcore] <--virtual addr-->
4657 + [ARMmmu] <--physical addr-->
4658 + [GERTmap] <--bus add-->
4659 + [VCperiph]
4660 +
4661 +*/
4662 +
4663 +/*
4664 + * Physical DRAM offset.
4665 + */
4666 +#define PLAT_PHYS_OFFSET UL(0x00000000)
4667 +#define VC_ARMMEM_OFFSET UL(0x00000000) /* offset in VC of ARM memory */
4668 +
4669 +#ifdef CONFIG_BCM2708_NOL2CACHE
4670 + #define _REAL_BUS_OFFSET UL(0xC0000000) /* don't use L1 or L2 caches */
4671 +#else
4672 + #define _REAL_BUS_OFFSET UL(0x40000000) /* use L2 cache */
4673 +#endif
4674 +
4675 +/* We're using the memory at 64M in the VideoCore for Linux - this adjustment
4676 + * will provide the offset into this area as well as setting the bits that
4677 + * stop the L1 and L2 cache from being used
4678 + *
4679 + * WARNING: this only works because the ARM is given memory at a fixed location
4680 + * (ARMMEM_OFFSET)
4681 + */
4682 +#define BUS_OFFSET (VC_ARMMEM_OFFSET + _REAL_BUS_OFFSET)
4683 +#define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET))
4684 +#define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET))
4685 +#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - PLAT_PHYS_OFFSET))
4686 +#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - PLAT_PHYS_OFFSET))
4687 +
4688 +#endif
4689 --- /dev/null
4690 +++ b/arch/arm/mach-bcm2708/include/mach/platform.h
4691 @@ -0,0 +1,220 @@
4692 +/*
4693 + * arch/arm/mach-bcm2708/include/mach/platform.h
4694 + *
4695 + * Copyright (C) 2010 Broadcom
4696 + *
4697 + * This program is free software; you can redistribute it and/or modify
4698 + * it under the terms of the GNU General Public License as published by
4699 + * the Free Software Foundation; either version 2 of the License, or
4700 + * (at your option) any later version.
4701 + *
4702 + * This program is distributed in the hope that it will be useful,
4703 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4704 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4705 + * GNU General Public License for more details.
4706 + *
4707 + * You should have received a copy of the GNU General Public License
4708 + * along with this program; if not, write to the Free Software
4709 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4710 + */
4711 +
4712 +#ifndef _BCM2708_PLATFORM_H
4713 +#define _BCM2708_PLATFORM_H
4714 +
4715 +
4716 +/* macros to get at IO space when running virtually */
4717 +#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
4718 +
4719 +#define __io_address(n) IOMEM(IO_ADDRESS(n))
4720 +
4721 +
4722 +/*
4723 + * SDRAM
4724 + */
4725 +#define BCM2708_SDRAM_BASE 0x00000000
4726 +
4727 +/*
4728 + * Logic expansion modules
4729 + *
4730 + */
4731 +
4732 +
4733 +/* ------------------------------------------------------------------------
4734 + * BCM2708 ARMCTRL Registers
4735 + * ------------------------------------------------------------------------
4736 + */
4737 +
4738 +#define HW_REGISTER_RW(addr) (addr)
4739 +#define HW_REGISTER_RO(addr) (addr)
4740 +
4741 +#include "arm_control.h"
4742 +#undef ARM_BASE
4743 +
4744 +/*
4745 + * Definitions and addresses for the ARM CONTROL logic
4746 + * This file is manually generated.
4747 + */
4748 +
4749 +#define BCM2708_PERI_BASE 0x20000000
4750 +#define ST_BASE (BCM2708_PERI_BASE + 0x3000) /* System Timer */
4751 +#define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */
4752 +#define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */
4753 +#define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */
4754 +#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */
4755 +#define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */
4756 +#define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */
4757 +#define UART1_BASE (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */
4758 +#define EMMC_BASE (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */
4759 +#define SMI_BASE (BCM2708_PERI_BASE + 0x600000) /* SMI */
4760 +#define USB_BASE (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */
4761 +#define MCORE_BASE (BCM2708_PERI_BASE + 0x0000) /* Fake frame buffer device (actually the multicore sync block*/
4762 +
4763 +#define ARMCTRL_BASE (ARM_BASE + 0x000)
4764 +#define ARMCTRL_IC_BASE (ARM_BASE + 0x200) /* ARM interrupt controller */
4765 +#define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */
4766 +#define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */
4767 +
4768 +
4769 +/*
4770 + * Interrupt assignments
4771 + */
4772 +
4773 +#define ARM_IRQ1_BASE 0
4774 +#define INTERRUPT_TIMER0 (ARM_IRQ1_BASE + 0)
4775 +#define INTERRUPT_TIMER1 (ARM_IRQ1_BASE + 1)
4776 +#define INTERRUPT_TIMER2 (ARM_IRQ1_BASE + 2)
4777 +#define INTERRUPT_TIMER3 (ARM_IRQ1_BASE + 3)
4778 +#define INTERRUPT_CODEC0 (ARM_IRQ1_BASE + 4)
4779 +#define INTERRUPT_CODEC1 (ARM_IRQ1_BASE + 5)
4780 +#define INTERRUPT_CODEC2 (ARM_IRQ1_BASE + 6)
4781 +#define INTERRUPT_VC_JPEG (ARM_IRQ1_BASE + 7)
4782 +#define INTERRUPT_ISP (ARM_IRQ1_BASE + 8)
4783 +#define INTERRUPT_VC_USB (ARM_IRQ1_BASE + 9)
4784 +#define INTERRUPT_VC_3D (ARM_IRQ1_BASE + 10)
4785 +#define INTERRUPT_TRANSPOSER (ARM_IRQ1_BASE + 11)
4786 +#define INTERRUPT_MULTICORESYNC0 (ARM_IRQ1_BASE + 12)
4787 +#define INTERRUPT_MULTICORESYNC1 (ARM_IRQ1_BASE + 13)
4788 +#define INTERRUPT_MULTICORESYNC2 (ARM_IRQ1_BASE + 14)
4789 +#define INTERRUPT_MULTICORESYNC3 (ARM_IRQ1_BASE + 15)
4790 +#define INTERRUPT_DMA0 (ARM_IRQ1_BASE + 16)
4791 +#define INTERRUPT_DMA1 (ARM_IRQ1_BASE + 17)
4792 +#define INTERRUPT_VC_DMA2 (ARM_IRQ1_BASE + 18)
4793 +#define INTERRUPT_VC_DMA3 (ARM_IRQ1_BASE + 19)
4794 +#define INTERRUPT_DMA4 (ARM_IRQ1_BASE + 20)
4795 +#define INTERRUPT_DMA5 (ARM_IRQ1_BASE + 21)
4796 +#define INTERRUPT_DMA6 (ARM_IRQ1_BASE + 22)
4797 +#define INTERRUPT_DMA7 (ARM_IRQ1_BASE + 23)
4798 +#define INTERRUPT_DMA8 (ARM_IRQ1_BASE + 24)
4799 +#define INTERRUPT_DMA9 (ARM_IRQ1_BASE + 25)
4800 +#define INTERRUPT_DMA10 (ARM_IRQ1_BASE + 26)
4801 +#define INTERRUPT_DMA11 (ARM_IRQ1_BASE + 27)
4802 +#define INTERRUPT_DMA12 (ARM_IRQ1_BASE + 28)
4803 +#define INTERRUPT_AUX (ARM_IRQ1_BASE + 29)
4804 +#define INTERRUPT_ARM (ARM_IRQ1_BASE + 30)
4805 +#define INTERRUPT_VPUDMA (ARM_IRQ1_BASE + 31)
4806 +
4807 +#define ARM_IRQ2_BASE 32
4808 +#define INTERRUPT_HOSTPORT (ARM_IRQ2_BASE + 0)
4809 +#define INTERRUPT_VIDEOSCALER (ARM_IRQ2_BASE + 1)
4810 +#define INTERRUPT_CCP2TX (ARM_IRQ2_BASE + 2)
4811 +#define INTERRUPT_SDC (ARM_IRQ2_BASE + 3)
4812 +#define INTERRUPT_DSI0 (ARM_IRQ2_BASE + 4)
4813 +#define INTERRUPT_AVE (ARM_IRQ2_BASE + 5)
4814 +#define INTERRUPT_CAM0 (ARM_IRQ2_BASE + 6)
4815 +#define INTERRUPT_CAM1 (ARM_IRQ2_BASE + 7)
4816 +#define INTERRUPT_HDMI0 (ARM_IRQ2_BASE + 8)
4817 +#define INTERRUPT_HDMI1 (ARM_IRQ2_BASE + 9)
4818 +#define INTERRUPT_PIXELVALVE1 (ARM_IRQ2_BASE + 10)
4819 +#define INTERRUPT_I2CSPISLV (ARM_IRQ2_BASE + 11)
4820 +#define INTERRUPT_DSI1 (ARM_IRQ2_BASE + 12)
4821 +#define INTERRUPT_PWA0 (ARM_IRQ2_BASE + 13)
4822 +#define INTERRUPT_PWA1 (ARM_IRQ2_BASE + 14)
4823 +#define INTERRUPT_CPR (ARM_IRQ2_BASE + 15)
4824 +#define INTERRUPT_SMI (ARM_IRQ2_BASE + 16)
4825 +#define INTERRUPT_GPIO0 (ARM_IRQ2_BASE + 17)
4826 +#define INTERRUPT_GPIO1 (ARM_IRQ2_BASE + 18)
4827 +#define INTERRUPT_GPIO2 (ARM_IRQ2_BASE + 19)
4828 +#define INTERRUPT_GPIO3 (ARM_IRQ2_BASE + 20)
4829 +#define INTERRUPT_VC_I2C (ARM_IRQ2_BASE + 21)
4830 +#define INTERRUPT_VC_SPI (ARM_IRQ2_BASE + 22)
4831 +#define INTERRUPT_VC_I2SPCM (ARM_IRQ2_BASE + 23)
4832 +#define INTERRUPT_VC_SDIO (ARM_IRQ2_BASE + 24)
4833 +#define INTERRUPT_VC_UART (ARM_IRQ2_BASE + 25)
4834 +#define INTERRUPT_SLIMBUS (ARM_IRQ2_BASE + 26)
4835 +#define INTERRUPT_VEC (ARM_IRQ2_BASE + 27)
4836 +#define INTERRUPT_CPG (ARM_IRQ2_BASE + 28)
4837 +#define INTERRUPT_RNG (ARM_IRQ2_BASE + 29)
4838 +#define INTERRUPT_VC_ARASANSDIO (ARM_IRQ2_BASE + 30)
4839 +#define INTERRUPT_AVSPMON (ARM_IRQ2_BASE + 31)
4840 +
4841 +#define ARM_IRQ0_BASE 64
4842 +#define INTERRUPT_ARM_TIMER (ARM_IRQ0_BASE + 0)
4843 +#define INTERRUPT_ARM_MAILBOX (ARM_IRQ0_BASE + 1)
4844 +#define INTERRUPT_ARM_DOORBELL_0 (ARM_IRQ0_BASE + 2)
4845 +#define INTERRUPT_ARM_DOORBELL_1 (ARM_IRQ0_BASE + 3)
4846 +#define INTERRUPT_VPU0_HALTED (ARM_IRQ0_BASE + 4)
4847 +#define INTERRUPT_VPU1_HALTED (ARM_IRQ0_BASE + 5)
4848 +#define INTERRUPT_ILLEGAL_TYPE0 (ARM_IRQ0_BASE + 6)
4849 +#define INTERRUPT_ILLEGAL_TYPE1 (ARM_IRQ0_BASE + 7)
4850 +#define INTERRUPT_PENDING1 (ARM_IRQ0_BASE + 8)
4851 +#define INTERRUPT_PENDING2 (ARM_IRQ0_BASE + 9)
4852 +#define INTERRUPT_JPEG (ARM_IRQ0_BASE + 10)
4853 +#define INTERRUPT_USB (ARM_IRQ0_BASE + 11)
4854 +#define INTERRUPT_3D (ARM_IRQ0_BASE + 12)
4855 +#define INTERRUPT_DMA2 (ARM_IRQ0_BASE + 13)
4856 +#define INTERRUPT_DMA3 (ARM_IRQ0_BASE + 14)
4857 +#define INTERRUPT_I2C (ARM_IRQ0_BASE + 15)
4858 +#define INTERRUPT_SPI (ARM_IRQ0_BASE + 16)
4859 +#define INTERRUPT_I2SPCM (ARM_IRQ0_BASE + 17)
4860 +#define INTERRUPT_SDIO (ARM_IRQ0_BASE + 18)
4861 +#define INTERRUPT_UART (ARM_IRQ0_BASE + 19)
4862 +#define INTERRUPT_ARASANSDIO (ARM_IRQ0_BASE + 20)
4863 +
4864 +#define MAXIRQNUM (32 + 32 + 20)
4865 +#define MAXFIQNUM (32 + 32 + 20)
4866 +
4867 +#define MAX_TIMER 2
4868 +#define MAX_PERIOD 699050
4869 +#define TICKS_PER_uSEC 1
4870 +
4871 +/*
4872 + * These are useconds NOT ticks.
4873 + *
4874 + */
4875 +#define mSEC_1 1000
4876 +#define mSEC_5 (mSEC_1 * 5)
4877 +#define mSEC_10 (mSEC_1 * 10)
4878 +#define mSEC_25 (mSEC_1 * 25)
4879 +#define SEC_1 (mSEC_1 * 1000)
4880 +
4881 +/*
4882 + * Watchdog
4883 + */
4884 +#define PM_RSTC (PM_BASE+0x1c)
4885 +#define PM_RSTS (PM_BASE+0x20)
4886 +#define PM_WDOG (PM_BASE+0x24)
4887 +
4888 +#define PM_WDOG_RESET 0000000000
4889 +#define PM_PASSWORD 0x5a000000
4890 +#define PM_WDOG_TIME_SET 0x000fffff
4891 +#define PM_RSTC_WRCFG_CLR 0xffffffcf
4892 +#define PM_RSTC_WRCFG_SET 0x00000030
4893 +#define PM_RSTC_WRCFG_FULL_RESET 0x00000020
4894 +#define PM_RSTC_RESET 0x00000102
4895 +
4896 +#define PM_RSTS_HADPOR_SET 0x00001000
4897 +#define PM_RSTS_HADSRH_SET 0x00000400
4898 +#define PM_RSTS_HADSRF_SET 0x00000200
4899 +#define PM_RSTS_HADSRQ_SET 0x00000100
4900 +#define PM_RSTS_HADWRH_SET 0x00000040
4901 +#define PM_RSTS_HADWRF_SET 0x00000020
4902 +#define PM_RSTS_HADWRQ_SET 0x00000010
4903 +#define PM_RSTS_HADDRH_SET 0x00000004
4904 +#define PM_RSTS_HADDRF_SET 0x00000002
4905 +#define PM_RSTS_HADDRQ_SET 0x00000001
4906 +
4907 +#define UART0_CLOCK 3000000
4908 +
4909 +#endif
4910 +
4911 +/* END */
4912 --- /dev/null
4913 +++ b/arch/arm/mach-bcm2708/include/mach/power.h
4914 @@ -0,0 +1,26 @@
4915 +/*
4916 + * linux/arch/arm/mach-bcm2708/power.h
4917 + *
4918 + * Copyright (C) 2010 Broadcom
4919 + *
4920 + * This program is free software; you can redistribute it and/or modify
4921 + * it under the terms of the GNU General Public License version 2 as
4922 + * published by the Free Software Foundation.
4923 + *
4924 + * This device provides a shared mechanism for controlling the power to
4925 + * VideoCore subsystems.
4926 + */
4927 +
4928 +#ifndef _MACH_BCM2708_POWER_H
4929 +#define _MACH_BCM2708_POWER_H
4930 +
4931 +#include <linux/types.h>
4932 +#include <mach/arm_power.h>
4933 +
4934 +typedef unsigned int BCM_POWER_HANDLE_T;
4935 +
4936 +extern int bcm_power_open(BCM_POWER_HANDLE_T *handle);
4937 +extern int bcm_power_request(BCM_POWER_HANDLE_T handle, uint32_t request);
4938 +extern int bcm_power_close(BCM_POWER_HANDLE_T handle);
4939 +
4940 +#endif
4941 --- /dev/null
4942 +++ b/arch/arm/mach-bcm2708/include/mach/system.h
4943 @@ -0,0 +1,38 @@
4944 +/*
4945 + * arch/arm/mach-bcm2708/include/mach/system.h
4946 + *
4947 + * Copyright (C) 2010 Broadcom
4948 + * Copyright (C) 2003 ARM Limited
4949 + * Copyright (C) 2000 Deep Blue Solutions Ltd
4950 + *
4951 + * This program is free software; you can redistribute it and/or modify
4952 + * it under the terms of the GNU General Public License as published by
4953 + * the Free Software Foundation; either version 2 of the License, or
4954 + * (at your option) any later version.
4955 + *
4956 + * This program is distributed in the hope that it will be useful,
4957 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4958 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4959 + * GNU General Public License for more details.
4960 + *
4961 + * You should have received a copy of the GNU General Public License
4962 + * along with this program; if not, write to the Free Software
4963 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4964 + */
4965 +#ifndef __ASM_ARCH_SYSTEM_H
4966 +#define __ASM_ARCH_SYSTEM_H
4967 +
4968 +#include <linux/io.h>
4969 +#include <mach/hardware.h>
4970 +#include <mach/platform.h>
4971 +
4972 +static inline void arch_idle(void)
4973 +{
4974 + /*
4975 + * This should do all the clock switching
4976 + * and wait for interrupt tricks
4977 + */
4978 + cpu_do_idle();
4979 +}
4980 +
4981 +#endif
4982 --- /dev/null
4983 +++ b/arch/arm/mach-bcm2708/include/mach/timex.h
4984 @@ -0,0 +1,23 @@
4985 +/*
4986 + * arch/arm/mach-bcm2708/include/mach/timex.h
4987 + *
4988 + * BCM2708 sysem clock frequency
4989 + *
4990 + * Copyright (C) 2010 Broadcom
4991 + *
4992 + * This program is free software; you can redistribute it and/or modify
4993 + * it under the terms of the GNU General Public License as published by
4994 + * the Free Software Foundation; either version 2 of the License, or
4995 + * (at your option) any later version.
4996 + *
4997 + * This program is distributed in the hope that it will be useful,
4998 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4999 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5000 + * GNU General Public License for more details.
5001 + *
5002 + * You should have received a copy of the GNU General Public License
5003 + * along with this program; if not, write to the Free Software
5004 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5005 + */
5006 +
5007 +#define CLOCK_TICK_RATE (1000000)
5008 --- /dev/null
5009 +++ b/arch/arm/mach-bcm2708/include/mach/uncompress.h
5010 @@ -0,0 +1,84 @@
5011 +/*
5012 + * arch/arm/mach-bcn2708/include/mach/uncompress.h
5013 + *
5014 + * Copyright (C) 2010 Broadcom
5015 + * Copyright (C) 2003 ARM Limited
5016 + *
5017 + * This program is free software; you can redistribute it and/or modify
5018 + * it under the terms of the GNU General Public License as published by
5019 + * the Free Software Foundation; either version 2 of the License, or
5020 + * (at your option) any later version.
5021 + *
5022 + * This program is distributed in the hope that it will be useful,
5023 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5024 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5025 + * GNU General Public License for more details.
5026 + *
5027 + * You should have received a copy of the GNU General Public License
5028 + * along with this program; if not, write to the Free Software
5029 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5030 + */
5031 +
5032 +#include <linux/io.h>
5033 +#include <linux/amba/serial.h>
5034 +#include <mach/hardware.h>
5035 +
5036 +#define UART_BAUD 115200
5037 +
5038 +#define BCM2708_UART_DR __io(UART0_BASE + UART01x_DR)
5039 +#define BCM2708_UART_FR __io(UART0_BASE + UART01x_FR)
5040 +#define BCM2708_UART_IBRD __io(UART0_BASE + UART011_IBRD)
5041 +#define BCM2708_UART_FBRD __io(UART0_BASE + UART011_FBRD)
5042 +#define BCM2708_UART_LCRH __io(UART0_BASE + UART011_LCRH)
5043 +#define BCM2708_UART_CR __io(UART0_BASE + UART011_CR)
5044 +
5045 +/*
5046 + * This does not append a newline
5047 + */
5048 +static inline void putc(int c)
5049 +{
5050 + while (__raw_readl(BCM2708_UART_FR) & UART01x_FR_TXFF)
5051 + barrier();
5052 +
5053 + __raw_writel(c, BCM2708_UART_DR);
5054 +}
5055 +
5056 +static inline void flush(void)
5057 +{
5058 + int fr;
5059 +
5060 + do {
5061 + fr = __raw_readl(BCM2708_UART_FR);
5062 + barrier();
5063 + } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE);
5064 +}
5065 +
5066 +static inline void arch_decomp_setup(void)
5067 +{
5068 + int temp, div, rem, frac;
5069 +
5070 + temp = 16 * UART_BAUD;
5071 + div = UART0_CLOCK / temp;
5072 + rem = UART0_CLOCK % temp;
5073 + temp = (8 * rem) / UART_BAUD;
5074 + frac = (temp >> 1) + (temp & 1);
5075 +
5076 + /* Make sure the UART is disabled before we start */
5077 + __raw_writel(0, BCM2708_UART_CR);
5078 +
5079 + /* Set the baud rate */
5080 + __raw_writel(div, BCM2708_UART_IBRD);
5081 + __raw_writel(frac, BCM2708_UART_FBRD);
5082 +
5083 + /* Set the UART to 8n1, FIFO enabled */
5084 + __raw_writel(UART01x_LCRH_WLEN_8 | UART01x_LCRH_FEN, BCM2708_UART_LCRH);
5085 +
5086 + /* Enable the UART */
5087 + __raw_writel(UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_RXE,
5088 + BCM2708_UART_CR);
5089 +}
5090 +
5091 +/*
5092 + * nothing to do
5093 + */
5094 +#define arch_decomp_wdog()
5095 --- /dev/null
5096 +++ b/arch/arm/mach-bcm2708/include/mach/vc_mem.h
5097 @@ -0,0 +1,35 @@
5098 +/*****************************************************************************
5099 +* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved.
5100 +*
5101 +* Unless you and Broadcom execute a separate written software license
5102 +* agreement governing use of this software, this software is licensed to you
5103 +* under the terms of the GNU General Public License version 2, available at
5104 +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
5105 +*
5106 +* Notwithstanding the above, under no circumstances may you combine this
5107 +* software in any way with any other Broadcom software provided under a
5108 +* license other than the GPL, without Broadcom's express prior written
5109 +* consent.
5110 +*****************************************************************************/
5111 +
5112 +#if !defined( VC_MEM_H )
5113 +#define VC_MEM_H
5114 +
5115 +#include <linux/ioctl.h>
5116 +
5117 +#define VC_MEM_IOC_MAGIC 'v'
5118 +
5119 +#define VC_MEM_IOC_MEM_PHYS_ADDR _IOR( VC_MEM_IOC_MAGIC, 0, unsigned long )
5120 +#define VC_MEM_IOC_MEM_SIZE _IOR( VC_MEM_IOC_MAGIC, 1, unsigned int )
5121 +#define VC_MEM_IOC_MEM_BASE _IOR( VC_MEM_IOC_MAGIC, 2, unsigned int )
5122 +#define VC_MEM_IOC_MEM_LOAD _IOR( VC_MEM_IOC_MAGIC, 3, unsigned int )
5123 +
5124 +#if defined( __KERNEL__ )
5125 +#define VC_MEM_TO_ARM_ADDR_MASK 0x3FFFFFFF
5126 +
5127 +extern unsigned long mm_vc_mem_phys_addr;
5128 +extern unsigned int mm_vc_mem_size;
5129 +extern int vc_mem_get_current_size( void );
5130 +#endif
5131 +
5132 +#endif /* VC_MEM_H */
5133 --- /dev/null
5134 +++ b/arch/arm/mach-bcm2708/include/mach/vcio.h
5135 @@ -0,0 +1,141 @@
5136 +/*
5137 + * arch/arm/mach-bcm2708/include/mach/vcio.h
5138 + *
5139 + * Copyright (C) 2010 Broadcom
5140 + *
5141 + * This program is free software; you can redistribute it and/or modify
5142 + * it under the terms of the GNU General Public License as published by
5143 + * the Free Software Foundation; either version 2 of the License, or
5144 + * (at your option) any later version.
5145 + *
5146 + * This program is distributed in the hope that it will be useful,
5147 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5148 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5149 + * GNU General Public License for more details.
5150 + *
5151 + * You should have received a copy of the GNU General Public License
5152 + * along with this program; if not, write to the Free Software
5153 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5154 + */
5155 +#ifndef _MACH_BCM2708_VCIO_H
5156 +#define _MACH_BCM2708_VCIO_H
5157 +
5158 +/* Routines to handle I/O via the VideoCore "ARM control" registers
5159 + * (semaphores, doorbells, mailboxes)
5160 + */
5161 +
5162 +#define BCM_VCIO_DRIVER_NAME "bcm2708_vcio"
5163 +
5164 +/* Constants shared with the ARM identifying separate mailbox channels */
5165 +#define MBOX_CHAN_POWER 0 /* for use by the power management interface */
5166 +#define MBOX_CHAN_FB 1 /* for use by the frame buffer */
5167 +#define MBOX_CHAN_VCHIQ 3 /* for use by the VCHIQ interface */
5168 +#define MBOX_CHAN_PROPERTY 8 /* for use by the property channel */
5169 +#define MBOX_CHAN_COUNT 9
5170 +
5171 +/* Mailbox property tags */
5172 +enum {
5173 + VCMSG_PROPERTY_END = 0x00000000,
5174 + VCMSG_GET_FIRMWARE_REVISION = 0x00000001,
5175 + VCMSG_GET_BOARD_MODEL = 0x00010001,
5176 + VCMSG_GET_BOARD_REVISION = 0x00020002,
5177 + VCMSG_GET_BOARD_MAC_ADDRESS = 0x00020003,
5178 + VCMSG_GET_BOARD_SERIAL = 0x00020004,
5179 + VCMSG_GET_ARM_MEMORY = 0x00020005,
5180 + VCMSG_GET_VC_MEMORY = 0x00020006,
5181 + VCMSG_GET_CLOCKS = 0x00020007,
5182 + VCMSG_GET_COMMAND_LINE = 0x00050001,
5183 + VCMSG_GET_DMA_CHANNELS = 0x00060001,
5184 + VCMSG_GET_POWER_STATE = 0x00020001,
5185 + VCMSG_GET_TIMING = 0x00020002,
5186 + VCMSG_SET_POWER_STATE = 0x00028001,
5187 + VCMSG_GET_CLOCK_STATE = 0x00030001,
5188 + VCMSG_SET_CLOCK_STATE = 0x00038001,
5189 + VCMSG_GET_CLOCK_RATE = 0x00030002,
5190 + VCMSG_SET_CLOCK_RATE = 0x00038002,
5191 + VCMSG_GET_VOLTAGE = 0x00030003,
5192 + VCMSG_SET_VOLTAGE = 0x00038003,
5193 + VCMSG_GET_MAX_CLOCK = 0x00030004,
5194 + VCMSG_GET_MAX_VOLTAGE = 0x00030005,
5195 + VCMSG_GET_TEMPERATURE = 0x00030006,
5196 + VCMSG_GET_MIN_CLOCK = 0x00030007,
5197 + VCMSG_GET_MIN_VOLTAGE = 0x00030008,
5198 + VCMSG_GET_TURBO = 0x00030009,
5199 + VCMSG_SET_TURBO = 0x00038009,
5200 + VCMSG_SET_ALLOCATE_BUFFER = 0x00040001,
5201 + VCMSG_SET_RELEASE_BUFFER = 0x00048001,
5202 + VCMSG_SET_BLANK_SCREEN = 0x00040002,
5203 + VCMSG_TST_BLANK_SCREEN = 0x00044002,
5204 + VCMSG_GET_PHYSICAL_WIDTH_HEIGHT = 0x00040003,
5205 + VCMSG_TST_PHYSICAL_WIDTH_HEIGHT = 0x00044003,
5206 + VCMSG_SET_PHYSICAL_WIDTH_HEIGHT = 0x00048003,
5207 + VCMSG_GET_VIRTUAL_WIDTH_HEIGHT = 0x00040004,
5208 + VCMSG_TST_VIRTUAL_WIDTH_HEIGHT = 0x00044004,
5209 + VCMSG_SET_VIRTUAL_WIDTH_HEIGHT = 0x00048004,
5210 + VCMSG_GET_DEPTH = 0x00040005,
5211 + VCMSG_TST_DEPTH = 0x00044005,
5212 + VCMSG_SET_DEPTH = 0x00048005,
5213 + VCMSG_GET_PIXEL_ORDER = 0x00040006,
5214 + VCMSG_TST_PIXEL_ORDER = 0x00044006,
5215 + VCMSG_SET_PIXEL_ORDER = 0x00048006,
5216 + VCMSG_GET_ALPHA_MODE = 0x00040007,
5217 + VCMSG_TST_ALPHA_MODE = 0x00044007,
5218 + VCMSG_SET_ALPHA_MODE = 0x00048007,
5219 + VCMSG_GET_PITCH = 0x00040008,
5220 + VCMSG_TST_PITCH = 0x00044008,
5221 + VCMSG_SET_PITCH = 0x00048008,
5222 + VCMSG_GET_VIRTUAL_OFFSET = 0x00040009,
5223 + VCMSG_TST_VIRTUAL_OFFSET = 0x00044009,
5224 + VCMSG_SET_VIRTUAL_OFFSET = 0x00048009,
5225 + VCMSG_GET_OVERSCAN = 0x0004000a,
5226 + VCMSG_TST_OVERSCAN = 0x0004400a,
5227 + VCMSG_SET_OVERSCAN = 0x0004800a,
5228 + VCMSG_GET_PALETTE = 0x0004000b,
5229 + VCMSG_TST_PALETTE = 0x0004400b,
5230 + VCMSG_SET_PALETTE = 0x0004800b,
5231 + VCMSG_GET_LAYER = 0x0004000c,
5232 + VCMSG_TST_LAYER = 0x0004400c,
5233 + VCMSG_SET_LAYER = 0x0004800c,
5234 + VCMSG_GET_TRANSFORM = 0x0004000d,
5235 + VCMSG_TST_TRANSFORM = 0x0004400d,
5236 + VCMSG_SET_TRANSFORM = 0x0004800d,
5237 +};
5238 +
5239 +extern int /*rc*/ bcm_mailbox_read(unsigned chan, uint32_t *data28);
5240 +extern int /*rc*/ bcm_mailbox_write(unsigned chan, uint32_t data28);
5241 +extern int /*rc*/ bcm_mailbox_property(void *data, int size);
5242 +
5243 +#include <linux/ioctl.h>
5244 +
5245 +/*
5246 + * The major device number. We can't rely on dynamic
5247 + * registration any more, because ioctls need to know
5248 + * it.
5249 + */
5250 +#define MAJOR_NUM 100
5251 +
5252 +/*
5253 + * Set the message of the device driver
5254 + */
5255 +#define IOCTL_MBOX_PROPERTY _IOWR(MAJOR_NUM, 0, char *)
5256 +/*
5257 + * _IOWR means that we're creating an ioctl command
5258 + * number for passing information from a user process
5259 + * to the kernel module and from the kernel module to user process
5260 + *
5261 + * The first arguments, MAJOR_NUM, is the major device
5262 + * number we're using.
5263 + *
5264 + * The second argument is the number of the command
5265 + * (there could be several with different meanings).
5266 + *
5267 + * The third argument is the type we want to get from
5268 + * the process to the kernel.
5269 + */
5270 +
5271 +/*
5272 + * The name of the device file
5273 + */
5274 +#define DEVICE_FILE_NAME "char_dev"
5275 +
5276 +#endif
5277 --- /dev/null
5278 +++ b/arch/arm/mach-bcm2708/include/mach/vmalloc.h
5279 @@ -0,0 +1,20 @@
5280 +/*
5281 + * arch/arm/mach-bcm2708/include/mach/vmalloc.h
5282 + *
5283 + * Copyright (C) 2010 Broadcom
5284 + *
5285 + * This program is free software; you can redistribute it and/or modify
5286 + * it under the terms of the GNU General Public License as published by
5287 + * the Free Software Foundation; either version 2 of the License, or
5288 + * (at your option) any later version.
5289 + *
5290 + * This program is distributed in the hope that it will be useful,
5291 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5292 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5293 + * GNU General Public License for more details.
5294 + *
5295 + * You should have received a copy of the GNU General Public License
5296 + * along with this program; if not, write to the Free Software
5297 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5298 + */
5299 +#define VMALLOC_END (0xe8000000)
5300 --- /dev/null
5301 +++ b/arch/arm/mach-bcm2708/power.c
5302 @@ -0,0 +1,194 @@
5303 +/*
5304 + * linux/arch/arm/mach-bcm2708/power.c
5305 + *
5306 + * Copyright (C) 2010 Broadcom
5307 + *
5308 + * This program is free software; you can redistribute it and/or modify
5309 + * it under the terms of the GNU General Public License version 2 as
5310 + * published by the Free Software Foundation.
5311 + *
5312 + * This device provides a shared mechanism for controlling the power to
5313 + * VideoCore subsystems.
5314 + */
5315 +
5316 +#include <linux/module.h>
5317 +#include <linux/semaphore.h>
5318 +#include <linux/bug.h>
5319 +#include <mach/power.h>
5320 +#include <mach/vcio.h>
5321 +#include <mach/arm_power.h>
5322 +
5323 +#define DRIVER_NAME "bcm2708_power"
5324 +
5325 +#define BCM_POWER_MAXCLIENTS 4
5326 +#define BCM_POWER_NOCLIENT (1<<31)
5327 +
5328 +/* Some drivers expect there devices to be permanently powered */
5329 +#define BCM_POWER_ALWAYS_ON (BCM_POWER_USB)
5330 +
5331 +#if 1
5332 +#define DPRINTK printk
5333 +#else
5334 +#define DPRINTK if (0) printk
5335 +#endif
5336 +
5337 +struct state_struct {
5338 + uint32_t global_request;
5339 + uint32_t client_request[BCM_POWER_MAXCLIENTS];
5340 + struct semaphore client_mutex;
5341 + struct semaphore mutex;
5342 +} g_state;
5343 +
5344 +int bcm_power_open(BCM_POWER_HANDLE_T *handle)
5345 +{
5346 + BCM_POWER_HANDLE_T i;
5347 + int ret = -EBUSY;
5348 +
5349 + down(&g_state.client_mutex);
5350 +
5351 + for (i = 0; i < BCM_POWER_MAXCLIENTS; i++) {
5352 + if (g_state.client_request[i] == BCM_POWER_NOCLIENT) {
5353 + g_state.client_request[i] = BCM_POWER_NONE;
5354 + *handle = i;
5355 + ret = 0;
5356 + break;
5357 + }
5358 + }
5359 +
5360 + up(&g_state.client_mutex);
5361 +
5362 + DPRINTK("bcm_power_open() -> %d\n", *handle);
5363 +
5364 + return ret;
5365 +}
5366 +EXPORT_SYMBOL_GPL(bcm_power_open);
5367 +
5368 +int bcm_power_request(BCM_POWER_HANDLE_T handle, uint32_t request)
5369 +{
5370 + int rc = 0;
5371 +
5372 + DPRINTK("bcm_power_request(%d, %x)\n", handle, request);
5373 +
5374 + if ((handle < BCM_POWER_MAXCLIENTS) &&
5375 + (g_state.client_request[handle] != BCM_POWER_NOCLIENT)) {
5376 + if (down_interruptible(&g_state.mutex) != 0) {
5377 + DPRINTK("bcm_power_request -> interrupted\n");
5378 + return -EINTR;
5379 + }
5380 +
5381 + if (request != g_state.client_request[handle]) {
5382 + uint32_t others_request = 0;
5383 + uint32_t global_request;
5384 + BCM_POWER_HANDLE_T i;
5385 +
5386 + for (i = 0; i < BCM_POWER_MAXCLIENTS; i++) {
5387 + if (i != handle)
5388 + others_request |=
5389 + g_state.client_request[i];
5390 + }
5391 + others_request &= ~BCM_POWER_NOCLIENT;
5392 +
5393 + global_request = request | others_request;
5394 + if (global_request != g_state.global_request) {
5395 + uint32_t actual;
5396 +
5397 + /* Send a request to VideoCore */
5398 + bcm_mailbox_write(MBOX_CHAN_POWER,
5399 + global_request << 4);
5400 +
5401 + /* Wait for a response during power-up */
5402 + if (global_request & ~g_state.global_request) {
5403 + rc = bcm_mailbox_read(MBOX_CHAN_POWER,
5404 + &actual);
5405 + DPRINTK
5406 + ("bcm_mailbox_read -> %08x, %d\n",
5407 + actual, rc);
5408 + actual >>= 4;
5409 + } else {
5410 + rc = 0;
5411 + actual = global_request;
5412 + }
5413 +
5414 + if (rc == 0) {
5415 + if (actual != global_request) {
5416 + printk(KERN_ERR
5417 + "%s: prev global %x, new global %x, actual %x, request %x, others_request %x\n",
5418 + __func__,
5419 + g_state.global_request,
5420 + global_request, actual, request, others_request);
5421 + /* A failure */
5422 + BUG_ON((others_request & actual)
5423 + != others_request);
5424 + request &= actual;
5425 + rc = -EIO;
5426 + }
5427 +
5428 + g_state.global_request = actual;
5429 + g_state.client_request[handle] =
5430 + request;
5431 + }
5432 + }
5433 + }
5434 + up(&g_state.mutex);
5435 + } else {
5436 + rc = -EINVAL;
5437 + }
5438 + DPRINTK("bcm_power_request -> %d\n", rc);
5439 + return rc;
5440 +}
5441 +EXPORT_SYMBOL_GPL(bcm_power_request);
5442 +
5443 +int bcm_power_close(BCM_POWER_HANDLE_T handle)
5444 +{
5445 + int rc;
5446 +
5447 + DPRINTK("bcm_power_close(%d)\n", handle);
5448 +
5449 + rc = bcm_power_request(handle, BCM_POWER_NONE);
5450 + if (rc == 0)
5451 + g_state.client_request[handle] = BCM_POWER_NOCLIENT;
5452 +
5453 + return rc;
5454 +}
5455 +EXPORT_SYMBOL_GPL(bcm_power_close);
5456 +
5457 +static int __init bcm_power_init(void)
5458 +{
5459 +#if defined(BCM_POWER_ALWAYS_ON)
5460 + BCM_POWER_HANDLE_T always_on_handle;
5461 +#endif
5462 + int rc = 0;
5463 + int i;
5464 +
5465 + printk(KERN_INFO "bcm_power: Broadcom power driver\n");
5466 + bcm_mailbox_write(MBOX_CHAN_POWER, 0);
5467 +
5468 + for (i = 0; i < BCM_POWER_MAXCLIENTS; i++)
5469 + g_state.client_request[i] = BCM_POWER_NOCLIENT;
5470 +
5471 + sema_init(&g_state.client_mutex, 1);
5472 + sema_init(&g_state.mutex, 1);
5473 +
5474 + g_state.global_request = 0;
5475 +
5476 +#if defined(BCM_POWER_ALWAYS_ON)
5477 + if (BCM_POWER_ALWAYS_ON) {
5478 + bcm_power_open(&always_on_handle);
5479 + bcm_power_request(always_on_handle, BCM_POWER_ALWAYS_ON);
5480 + }
5481 +#endif
5482 +
5483 + return rc;
5484 +}
5485 +
5486 +static void __exit bcm_power_exit(void)
5487 +{
5488 + bcm_mailbox_write(MBOX_CHAN_POWER, 0);
5489 +}
5490 +
5491 +arch_initcall(bcm_power_init); /* Initialize early */
5492 +module_exit(bcm_power_exit);
5493 +
5494 +MODULE_AUTHOR("Phil Elwell");
5495 +MODULE_DESCRIPTION("Interface to BCM2708 power management");
5496 +MODULE_LICENSE("GPL");
5497 --- /dev/null
5498 +++ b/arch/arm/mach-bcm2708/vc_mem.c
5499 @@ -0,0 +1,432 @@
5500 +/*****************************************************************************
5501 +* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved.
5502 +*
5503 +* Unless you and Broadcom execute a separate written software license
5504 +* agreement governing use of this software, this software is licensed to you
5505 +* under the terms of the GNU General Public License version 2, available at
5506 +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
5507 +*
5508 +* Notwithstanding the above, under no circumstances may you combine this
5509 +* software in any way with any other Broadcom software provided under a
5510 +* license other than the GPL, without Broadcom's express prior written
5511 +* consent.
5512 +*****************************************************************************/
5513 +
5514 +#include <linux/kernel.h>
5515 +#include <linux/module.h>
5516 +#include <linux/fs.h>
5517 +#include <linux/device.h>
5518 +#include <linux/cdev.h>
5519 +#include <linux/mm.h>
5520 +#include <linux/slab.h>
5521 +#include <linux/debugfs.h>
5522 +#include <asm/uaccess.h>
5523 +#include <linux/dma-mapping.h>
5524 +
5525 +#ifdef CONFIG_ARCH_KONA
5526 +#include <chal/chal_ipc.h>
5527 +#elif CONFIG_ARCH_BCM2708
5528 +#else
5529 +#include <csp/chal_ipc.h>
5530 +#endif
5531 +
5532 +#include "mach/vc_mem.h"
5533 +#include <mach/vcio.h>
5534 +
5535 +#define DRIVER_NAME "vc-mem"
5536 +
5537 +// Device (/dev) related variables
5538 +static dev_t vc_mem_devnum = 0;
5539 +static struct class *vc_mem_class = NULL;
5540 +static struct cdev vc_mem_cdev;
5541 +static int vc_mem_inited = 0;
5542 +
5543 +#ifdef CONFIG_DEBUG_FS
5544 +static struct dentry *vc_mem_debugfs_entry;
5545 +#endif
5546 +
5547 +/*
5548 + * Videocore memory addresses and size
5549 + *
5550 + * Drivers that wish to know the videocore memory addresses and sizes should
5551 + * use these variables instead of the MM_IO_BASE and MM_ADDR_IO defines in
5552 + * headers. This allows the other drivers to not be tied down to a a certain
5553 + * address/size at compile time.
5554 + *
5555 + * In the future, the goal is to have the videocore memory virtual address and
5556 + * size be calculated at boot time rather than at compile time. The decision of
5557 + * where the videocore memory resides and its size would be in the hands of the
5558 + * bootloader (and/or kernel). When that happens, the values of these variables
5559 + * would be calculated and assigned in the init function.
5560 + */
5561 +// in the 2835 VC in mapped above ARM, but ARM has full access to VC space
5562 +unsigned long mm_vc_mem_phys_addr = 0x00000000;
5563 +unsigned int mm_vc_mem_size = 0;
5564 +unsigned int mm_vc_mem_base = 0;
5565 +
5566 +EXPORT_SYMBOL(mm_vc_mem_phys_addr);
5567 +EXPORT_SYMBOL(mm_vc_mem_size);
5568 +EXPORT_SYMBOL(mm_vc_mem_base);
5569 +
5570 +static uint phys_addr = 0;
5571 +static uint mem_size = 0;
5572 +static uint mem_base = 0;
5573 +
5574 +
5575 +/****************************************************************************
5576 +*
5577 +* vc_mem_open
5578 +*
5579 +***************************************************************************/
5580 +
5581 +static int
5582 +vc_mem_open(struct inode *inode, struct file *file)
5583 +{
5584 + (void) inode;
5585 + (void) file;
5586 +
5587 + pr_debug("%s: called file = 0x%p\n", __func__, file);
5588 +
5589 + return 0;
5590 +}
5591 +
5592 +/****************************************************************************
5593 +*
5594 +* vc_mem_release
5595 +*
5596 +***************************************************************************/
5597 +
5598 +static int
5599 +vc_mem_release(struct inode *inode, struct file *file)
5600 +{
5601 + (void) inode;
5602 + (void) file;
5603 +
5604 + pr_debug("%s: called file = 0x%p\n", __func__, file);
5605 +
5606 + return 0;
5607 +}
5608 +
5609 +/****************************************************************************
5610 +*
5611 +* vc_mem_get_size
5612 +*
5613 +***************************************************************************/
5614 +
5615 +static void
5616 +vc_mem_get_size(void)
5617 +{
5618 +}
5619 +
5620 +/****************************************************************************
5621 +*
5622 +* vc_mem_get_base
5623 +*
5624 +***************************************************************************/
5625 +
5626 +static void
5627 +vc_mem_get_base(void)
5628 +{
5629 +}
5630 +
5631 +/****************************************************************************
5632 +*
5633 +* vc_mem_get_current_size
5634 +*
5635 +***************************************************************************/
5636 +
5637 +int
5638 +vc_mem_get_current_size(void)
5639 +{
5640 + return mm_vc_mem_size;
5641 +}
5642 +
5643 +EXPORT_SYMBOL_GPL(vc_mem_get_current_size);
5644 +
5645 +/****************************************************************************
5646 +*
5647 +* vc_mem_ioctl
5648 +*
5649 +***************************************************************************/
5650 +
5651 +static long
5652 +vc_mem_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
5653 +{
5654 + int rc = 0;
5655 +
5656 + (void) cmd;
5657 + (void) arg;
5658 +
5659 + pr_debug("%s: called file = 0x%p\n", __func__, file);
5660 +
5661 + switch (cmd) {
5662 + case VC_MEM_IOC_MEM_PHYS_ADDR:
5663 + {
5664 + pr_debug("%s: VC_MEM_IOC_MEM_PHYS_ADDR=0x%p\n",
5665 + __func__, (void *) mm_vc_mem_phys_addr);
5666 +
5667 + if (copy_to_user((void *) arg, &mm_vc_mem_phys_addr,
5668 + sizeof (mm_vc_mem_phys_addr)) != 0) {
5669 + rc = -EFAULT;
5670 + }
5671 + break;
5672 + }
5673 + case VC_MEM_IOC_MEM_SIZE:
5674 + {
5675 + // Get the videocore memory size first
5676 + vc_mem_get_size();
5677 +
5678 + pr_debug("%s: VC_MEM_IOC_MEM_SIZE=%u\n", __func__,
5679 + mm_vc_mem_size);
5680 +
5681 + if (copy_to_user((void *) arg, &mm_vc_mem_size,
5682 + sizeof (mm_vc_mem_size)) != 0) {
5683 + rc = -EFAULT;
5684 + }
5685 + break;
5686 + }
5687 + case VC_MEM_IOC_MEM_BASE:
5688 + {
5689 + // Get the videocore memory base
5690 + vc_mem_get_base();
5691 +
5692 + pr_debug("%s: VC_MEM_IOC_MEM_BASE=%u\n", __func__,
5693 + mm_vc_mem_base);
5694 +
5695 + if (copy_to_user((void *) arg, &mm_vc_mem_base,
5696 + sizeof (mm_vc_mem_base)) != 0) {
5697 + rc = -EFAULT;
5698 + }
5699 + break;
5700 + }
5701 + case VC_MEM_IOC_MEM_LOAD:
5702 + {
5703 + // Get the videocore memory base
5704 + vc_mem_get_base();
5705 +
5706 + pr_debug("%s: VC_MEM_IOC_MEM_LOAD=%u\n", __func__,
5707 + mm_vc_mem_base);
5708 +
5709 + if (copy_to_user((void *) arg, &mm_vc_mem_base,
5710 + sizeof (mm_vc_mem_base)) != 0) {
5711 + rc = -EFAULT;
5712 + }
5713 + break;
5714 + }
5715 + default:
5716 + {
5717 + return -ENOTTY;
5718 + }
5719 + }
5720 + pr_debug("%s: file = 0x%p returning %d\n", __func__, file, rc);
5721 +
5722 + return rc;
5723 +}
5724 +
5725 +/****************************************************************************
5726 +*
5727 +* vc_mem_mmap
5728 +*
5729 +***************************************************************************/
5730 +
5731 +static int
5732 +vc_mem_mmap(struct file *filp, struct vm_area_struct *vma)
5733 +{
5734 + int rc = 0;
5735 + unsigned long length = vma->vm_end - vma->vm_start;
5736 + unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
5737 +
5738 + pr_debug("%s: vm_start = 0x%08lx vm_end = 0x%08lx vm_pgoff = 0x%08lx\n",
5739 + __func__, (long) vma->vm_start, (long) vma->vm_end,
5740 + (long) vma->vm_pgoff);
5741 +
5742 + if (offset + length > mm_vc_mem_size) {
5743 + pr_err("%s: length %ld is too big\n", __func__, length);
5744 + return -EINVAL;
5745 + }
5746 + // Do not cache the memory map
5747 + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
5748 +
5749 + rc = remap_pfn_range(vma, vma->vm_start,
5750 + (mm_vc_mem_phys_addr >> PAGE_SHIFT) +
5751 + vma->vm_pgoff, length, vma->vm_page_prot);
5752 + if (rc != 0) {
5753 + pr_err("%s: remap_pfn_range failed (rc=%d)\n", __func__, rc);
5754 + }
5755 +
5756 + return rc;
5757 +}
5758 +
5759 +/****************************************************************************
5760 +*
5761 +* File Operations for the driver.
5762 +*
5763 +***************************************************************************/
5764 +
5765 +static const struct file_operations vc_mem_fops = {
5766 + .owner = THIS_MODULE,
5767 + .open = vc_mem_open,
5768 + .release = vc_mem_release,
5769 + .unlocked_ioctl = vc_mem_ioctl,
5770 + .mmap = vc_mem_mmap,
5771 +};
5772 +
5773 +#ifdef CONFIG_DEBUG_FS
5774 +static void vc_mem_debugfs_deinit(void)
5775 +{
5776 + debugfs_remove_recursive(vc_mem_debugfs_entry);
5777 + vc_mem_debugfs_entry = NULL;
5778 +}
5779 +
5780 +
5781 +static int vc_mem_debugfs_init(
5782 + struct device *dev)
5783 +{
5784 + vc_mem_debugfs_entry = debugfs_create_dir(DRIVER_NAME, NULL);
5785 + if (!vc_mem_debugfs_entry) {
5786 + dev_warn(dev, "could not create debugfs entry\n");
5787 + return -EFAULT;
5788 + }
5789 +
5790 + if (!debugfs_create_x32("vc_mem_phys_addr",
5791 + 0444,
5792 + vc_mem_debugfs_entry,
5793 + (u32 *)&mm_vc_mem_phys_addr)) {
5794 + dev_warn(dev, "%s:could not create vc_mem_phys entry\n",
5795 + __func__);
5796 + goto fail;
5797 + }
5798 +
5799 + if (!debugfs_create_x32("vc_mem_size",
5800 + 0444,
5801 + vc_mem_debugfs_entry,
5802 + (u32 *)&mm_vc_mem_size)) {
5803 + dev_warn(dev, "%s:could not create vc_mem_size entry\n",
5804 + __func__);
5805 + goto fail;
5806 + }
5807 +
5808 + if (!debugfs_create_x32("vc_mem_base",
5809 + 0444,
5810 + vc_mem_debugfs_entry,
5811 + (u32 *)&mm_vc_mem_base)) {
5812 + dev_warn(dev, "%s:could not create vc_mem_base entry\n",
5813 + __func__);
5814 + goto fail;
5815 + }
5816 +
5817 + return 0;
5818 +
5819 +fail:
5820 + vc_mem_debugfs_deinit();
5821 + return -EFAULT;
5822 +}
5823 +
5824 +#endif /* CONFIG_DEBUG_FS */
5825 +
5826 +
5827 +/****************************************************************************
5828 +*
5829 +* vc_mem_init
5830 +*
5831 +***************************************************************************/
5832 +
5833 +static int __init
5834 +vc_mem_init(void)
5835 +{
5836 + int rc = -EFAULT;
5837 + struct device *dev;
5838 +
5839 + pr_debug("%s: called\n", __func__);
5840 +
5841 + mm_vc_mem_phys_addr = phys_addr;
5842 + mm_vc_mem_size = mem_size;
5843 + mm_vc_mem_base = mem_base;
5844 +
5845 + vc_mem_get_size();
5846 +
5847 + pr_info("vc-mem: phys_addr:0x%08lx mem_base=0x%08x mem_size:0x%08x(%u MiB)\n",
5848 + mm_vc_mem_phys_addr, mm_vc_mem_base, mm_vc_mem_size, mm_vc_mem_size / (1024 * 1024));
5849 +
5850 + if ((rc = alloc_chrdev_region(&vc_mem_devnum, 0, 1, DRIVER_NAME)) < 0) {
5851 + pr_err("%s: alloc_chrdev_region failed (rc=%d)\n",
5852 + __func__, rc);
5853 + goto out_err;
5854 + }
5855 +
5856 + cdev_init(&vc_mem_cdev, &vc_mem_fops);
5857 + if ((rc = cdev_add(&vc_mem_cdev, vc_mem_devnum, 1)) != 0) {
5858 + pr_err("%s: cdev_add failed (rc=%d)\n", __func__, rc);
5859 + goto out_unregister;
5860 + }
5861 +
5862 + vc_mem_class = class_create(THIS_MODULE, DRIVER_NAME);
5863 + if (IS_ERR(vc_mem_class)) {
5864 + rc = PTR_ERR(vc_mem_class);
5865 + pr_err("%s: class_create failed (rc=%d)\n", __func__, rc);
5866 + goto out_cdev_del;
5867 + }
5868 +
5869 + dev = device_create(vc_mem_class, NULL, vc_mem_devnum, NULL,
5870 + DRIVER_NAME);
5871 + if (IS_ERR(dev)) {
5872 + rc = PTR_ERR(dev);
5873 + pr_err("%s: device_create failed (rc=%d)\n", __func__, rc);
5874 + goto out_class_destroy;
5875 + }
5876 +
5877 +#ifdef CONFIG_DEBUG_FS
5878 + /* don't fail if the debug entries cannot be created */
5879 + vc_mem_debugfs_init(dev);
5880 +#endif
5881 +
5882 + vc_mem_inited = 1;
5883 + return 0;
5884 +
5885 + device_destroy(vc_mem_class, vc_mem_devnum);
5886 +
5887 + out_class_destroy:
5888 + class_destroy(vc_mem_class);
5889 + vc_mem_class = NULL;
5890 +
5891 + out_cdev_del:
5892 + cdev_del(&vc_mem_cdev);
5893 +
5894 + out_unregister:
5895 + unregister_chrdev_region(vc_mem_devnum, 1);
5896 +
5897 + out_err:
5898 + return -1;
5899 +}
5900 +
5901 +/****************************************************************************
5902 +*
5903 +* vc_mem_exit
5904 +*
5905 +***************************************************************************/
5906 +
5907 +static void __exit
5908 +vc_mem_exit(void)
5909 +{
5910 + pr_debug("%s: called\n", __func__);
5911 +
5912 + if (vc_mem_inited) {
5913 +#if CONFIG_DEBUG_FS
5914 + vc_mem_debugfs_deinit();
5915 +#endif
5916 + device_destroy(vc_mem_class, vc_mem_devnum);
5917 + class_destroy(vc_mem_class);
5918 + cdev_del(&vc_mem_cdev);
5919 + unregister_chrdev_region(vc_mem_devnum, 1);
5920 + }
5921 +}
5922 +
5923 +module_init(vc_mem_init);
5924 +module_exit(vc_mem_exit);
5925 +MODULE_LICENSE("GPL");
5926 +MODULE_AUTHOR("Broadcom Corporation");
5927 +
5928 +module_param(phys_addr, uint, 0644);
5929 +module_param(mem_size, uint, 0644);
5930 +module_param(mem_base, uint, 0644);
5931 +
5932 --- /dev/null
5933 +++ b/arch/arm/mach-bcm2708/vcio.c
5934 @@ -0,0 +1,474 @@
5935 +/*
5936 + * linux/arch/arm/mach-bcm2708/vcio.c
5937 + *
5938 + * Copyright (C) 2010 Broadcom
5939 + *
5940 + * This program is free software; you can redistribute it and/or modify
5941 + * it under the terms of the GNU General Public License version 2 as
5942 + * published by the Free Software Foundation.
5943 + *
5944 + * This device provides a shared mechanism for writing to the mailboxes,
5945 + * semaphores, doorbells etc. that are shared between the ARM and the
5946 + * VideoCore processor
5947 + */
5948 +
5949 +#if defined(CONFIG_SERIAL_BCM_MBOX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
5950 +#define SUPPORT_SYSRQ
5951 +#endif
5952 +
5953 +#include <linux/module.h>
5954 +#include <linux/console.h>
5955 +#include <linux/serial_core.h>
5956 +#include <linux/serial.h>
5957 +#include <linux/errno.h>
5958 +#include <linux/device.h>
5959 +#include <linux/init.h>
5960 +#include <linux/mm.h>
5961 +#include <linux/dma-mapping.h>
5962 +#include <linux/platform_device.h>
5963 +#include <linux/sysrq.h>
5964 +#include <linux/delay.h>
5965 +#include <linux/slab.h>
5966 +#include <linux/interrupt.h>
5967 +#include <linux/irq.h>
5968 +
5969 +#include <linux/io.h>
5970 +
5971 +#include <mach/vcio.h>
5972 +#include <mach/platform.h>
5973 +
5974 +#include <asm/uaccess.h>
5975 +
5976 +
5977 +#define DRIVER_NAME BCM_VCIO_DRIVER_NAME
5978 +
5979 +/* ----------------------------------------------------------------------
5980 + * Mailbox
5981 + * -------------------------------------------------------------------- */
5982 +
5983 +/* offsets from a mail box base address */
5984 +#define MAIL_WRT 0x00 /* write - and next 4 words */
5985 +#define MAIL_RD 0x00 /* read - and next 4 words */
5986 +#define MAIL_POL 0x10 /* read without popping the fifo */
5987 +#define MAIL_SND 0x14 /* sender ID (bottom two bits) */
5988 +#define MAIL_STA 0x18 /* status */
5989 +#define MAIL_CNF 0x1C /* configuration */
5990 +
5991 +#define MBOX_MSG(chan, data28) (((data28) & ~0xf) | ((chan) & 0xf))
5992 +#define MBOX_MSG_LSB(chan, data28) (((data28) << 4) | ((chan) & 0xf))
5993 +#define MBOX_CHAN(msg) ((msg) & 0xf)
5994 +#define MBOX_DATA28(msg) ((msg) & ~0xf)
5995 +#define MBOX_DATA28_LSB(msg) (((uint32_t)msg) >> 4)
5996 +
5997 +#define MBOX_MAGIC 0xd0d0c0de
5998 +
5999 +struct vc_mailbox {
6000 + struct device *dev; /* parent device */
6001 + void __iomem *status;
6002 + void __iomem *config;
6003 + void __iomem *read;
6004 + void __iomem *write;
6005 + uint32_t msg[MBOX_CHAN_COUNT];
6006 + struct semaphore sema[MBOX_CHAN_COUNT];
6007 + uint32_t magic;
6008 +};
6009 +
6010 +static void mbox_init(struct vc_mailbox *mbox_out, struct device *dev,
6011 + uint32_t addr_mbox)
6012 +{
6013 + int i;
6014 +
6015 + mbox_out->dev = dev;
6016 + mbox_out->status = __io_address(addr_mbox + MAIL_STA);
6017 + mbox_out->config = __io_address(addr_mbox + MAIL_CNF);
6018 + mbox_out->read = __io_address(addr_mbox + MAIL_RD);
6019 + /* Write to the other mailbox */
6020 + mbox_out->write =
6021 + __io_address((addr_mbox ^ ARM_0_MAIL0_WRT ^ ARM_0_MAIL1_WRT) +
6022 + MAIL_WRT);
6023 +
6024 + for (i = 0; i < MBOX_CHAN_COUNT; i++) {
6025 + mbox_out->msg[i] = 0;
6026 + sema_init(&mbox_out->sema[i], 0);
6027 + }
6028 +
6029 + /* Enable the interrupt on data reception */
6030 + writel(ARM_MC_IHAVEDATAIRQEN, mbox_out->config);
6031 +
6032 + mbox_out->magic = MBOX_MAGIC;
6033 +}
6034 +
6035 +static int mbox_write(struct vc_mailbox *mbox, unsigned chan, uint32_t data28)
6036 +{
6037 + int rc;
6038 +
6039 + if (mbox->magic != MBOX_MAGIC)
6040 + rc = -EINVAL;
6041 + else {
6042 + /* wait for the mailbox FIFO to have some space in it */
6043 + while (0 != (readl(mbox->status) & ARM_MS_FULL))
6044 + cpu_relax();
6045 +
6046 + writel(MBOX_MSG(chan, data28), mbox->write);
6047 + rc = 0;
6048 + }
6049 + return rc;
6050 +}
6051 +
6052 +static int mbox_read(struct vc_mailbox *mbox, unsigned chan, uint32_t *data28)
6053 +{
6054 + int rc;
6055 +
6056 + if (mbox->magic != MBOX_MAGIC)
6057 + rc = -EINVAL;
6058 + else {
6059 + down(&mbox->sema[chan]);
6060 + *data28 = MBOX_DATA28(mbox->msg[chan]);
6061 + mbox->msg[chan] = 0;
6062 + rc = 0;
6063 + }
6064 + return rc;
6065 +}
6066 +
6067 +static irqreturn_t mbox_irq(int irq, void *dev_id)
6068 +{
6069 + /* wait for the mailbox FIFO to have some data in it */
6070 + struct vc_mailbox *mbox = (struct vc_mailbox *) dev_id;
6071 + int status = readl(mbox->status);
6072 + int ret = IRQ_NONE;
6073 +
6074 + while (!(status & ARM_MS_EMPTY)) {
6075 + uint32_t msg = readl(mbox->read);
6076 + int chan = MBOX_CHAN(msg);
6077 + if (chan < MBOX_CHAN_COUNT) {
6078 + if (mbox->msg[chan]) {
6079 + /* Overflow */
6080 + printk(KERN_ERR DRIVER_NAME
6081 + ": mbox chan %d overflow - drop %08x\n",
6082 + chan, msg);
6083 + } else {
6084 + mbox->msg[chan] = (msg | 0xf);
6085 + up(&mbox->sema[chan]);
6086 + }
6087 + } else {
6088 + printk(KERN_ERR DRIVER_NAME
6089 + ": invalid channel selector (msg %08x)\n", msg);
6090 + }
6091 + ret = IRQ_HANDLED;
6092 + status = readl(mbox->status);
6093 + }
6094 + return ret;
6095 +}
6096 +
6097 +static struct irqaction mbox_irqaction = {
6098 + .name = "ARM Mailbox IRQ",
6099 + .flags = IRQF_DISABLED | IRQF_IRQPOLL,
6100 + .handler = mbox_irq,
6101 +};
6102 +
6103 +/* ----------------------------------------------------------------------
6104 + * Mailbox Methods
6105 + * -------------------------------------------------------------------- */
6106 +
6107 +static struct device *mbox_dev; /* we assume there's only one! */
6108 +
6109 +static int dev_mbox_write(struct device *dev, unsigned chan, uint32_t data28)
6110 +{
6111 + int rc;
6112 +
6113 + struct vc_mailbox *mailbox = dev_get_drvdata(dev);
6114 + device_lock(dev);
6115 + rc = mbox_write(mailbox, chan, data28);
6116 + device_unlock(dev);
6117 +
6118 + return rc;
6119 +}
6120 +
6121 +static int dev_mbox_read(struct device *dev, unsigned chan, uint32_t *data28)
6122 +{
6123 + int rc;
6124 +
6125 + struct vc_mailbox *mailbox = dev_get_drvdata(dev);
6126 + device_lock(dev);
6127 + rc = mbox_read(mailbox, chan, data28);
6128 + device_unlock(dev);
6129 +
6130 + return rc;
6131 +}
6132 +
6133 +extern int bcm_mailbox_write(unsigned chan, uint32_t data28)
6134 +{
6135 + if (mbox_dev)
6136 + return dev_mbox_write(mbox_dev, chan, data28);
6137 + else
6138 + return -ENODEV;
6139 +}
6140 +EXPORT_SYMBOL_GPL(bcm_mailbox_write);
6141 +
6142 +extern int bcm_mailbox_read(unsigned chan, uint32_t *data28)
6143 +{
6144 + if (mbox_dev)
6145 + return dev_mbox_read(mbox_dev, chan, data28);
6146 + else
6147 + return -ENODEV;
6148 +}
6149 +EXPORT_SYMBOL_GPL(bcm_mailbox_read);
6150 +
6151 +static void dev_mbox_register(const char *dev_name, struct device *dev)
6152 +{
6153 + mbox_dev = dev;
6154 +}
6155 +
6156 +static int mbox_copy_from_user(void *dst, const void *src, int size)
6157 +{
6158 + if ( (uint32_t)src < TASK_SIZE)
6159 + {
6160 + return copy_from_user(dst, src, size);
6161 + }
6162 + else
6163 + {
6164 + memcpy( dst, src, size );
6165 + return 0;
6166 + }
6167 +}
6168 +
6169 +static int mbox_copy_to_user(void *dst, const void *src, int size)
6170 +{
6171 + if ( (uint32_t)dst < TASK_SIZE)
6172 + {
6173 + return copy_to_user(dst, src, size);
6174 + }
6175 + else
6176 + {
6177 + memcpy( dst, src, size );
6178 + return 0;
6179 + }
6180 +}
6181 +
6182 +static DEFINE_MUTEX(mailbox_lock);
6183 +extern int bcm_mailbox_property(void *data, int size)
6184 +{
6185 + uint32_t success;
6186 + dma_addr_t mem_bus; /* the memory address accessed from videocore */
6187 + void *mem_kern; /* the memory address accessed from driver */
6188 + int s = 0;
6189 +
6190 + mutex_lock(&mailbox_lock);
6191 + /* allocate some memory for the messages communicating with GPU */
6192 + mem_kern = dma_alloc_coherent(NULL, PAGE_ALIGN(size), &mem_bus, GFP_ATOMIC);
6193 + if (mem_kern) {
6194 + /* create the message */
6195 + mbox_copy_from_user(mem_kern, data, size);
6196 +
6197 + /* send the message */
6198 + wmb();
6199 + s = bcm_mailbox_write(MBOX_CHAN_PROPERTY, (uint32_t)mem_bus);
6200 + if (s == 0) {
6201 + s = bcm_mailbox_read(MBOX_CHAN_PROPERTY, &success);
6202 + }
6203 + if (s == 0) {
6204 + /* copy the response */
6205 + rmb();
6206 + mbox_copy_to_user(data, mem_kern, size);
6207 + }
6208 + dma_free_coherent(NULL, PAGE_ALIGN(size), mem_kern, mem_bus);
6209 + } else {
6210 + s = -ENOMEM;
6211 + }
6212 + if (s != 0)
6213 + printk(KERN_ERR DRIVER_NAME ": %s failed (%d)\n", __func__, s);
6214 +
6215 + mutex_unlock(&mailbox_lock);
6216 + return s;
6217 +}
6218 +EXPORT_SYMBOL_GPL(bcm_mailbox_property);
6219 +
6220 +/* ----------------------------------------------------------------------
6221 + * Platform Device for Mailbox
6222 + * -------------------------------------------------------------------- */
6223 +
6224 +/*
6225 + * Is the device open right now? Used to prevent
6226 + * concurent access into the same device
6227 + */
6228 +static int Device_Open = 0;
6229 +
6230 +/*
6231 + * This is called whenever a process attempts to open the device file
6232 + */
6233 +static int device_open(struct inode *inode, struct file *file)
6234 +{
6235 + /*
6236 + * We don't want to talk to two processes at the same time
6237 + */
6238 + if (Device_Open)
6239 + return -EBUSY;
6240 +
6241 + Device_Open++;
6242 + /*
6243 + * Initialize the message
6244 + */
6245 + try_module_get(THIS_MODULE);
6246 + return 0;
6247 +}
6248 +
6249 +static int device_release(struct inode *inode, struct file *file)
6250 +{
6251 + /*
6252 + * We're now ready for our next caller
6253 + */
6254 + Device_Open--;
6255 +
6256 + module_put(THIS_MODULE);
6257 + return 0;
6258 +}
6259 +
6260 +/*
6261 + * This function is called whenever a process tries to do an ioctl on our
6262 + * device file. We get two extra parameters (additional to the inode and file
6263 + * structures, which all device functions get): the number of the ioctl called
6264 + * and the parameter given to the ioctl function.
6265 + *
6266 + * If the ioctl is write or read/write (meaning output is returned to the
6267 + * calling process), the ioctl call returns the output of this function.
6268 + *
6269 + */
6270 +static long device_ioctl(struct file *file, /* see include/linux/fs.h */
6271 + unsigned int ioctl_num, /* number and param for ioctl */
6272 + unsigned long ioctl_param)
6273 +{
6274 + unsigned size;
6275 + /*
6276 + * Switch according to the ioctl called
6277 + */
6278 + switch (ioctl_num) {
6279 + case IOCTL_MBOX_PROPERTY:
6280 + /*
6281 + * Receive a pointer to a message (in user space) and set that
6282 + * to be the device's message. Get the parameter given to
6283 + * ioctl by the process.
6284 + */
6285 + mbox_copy_from_user(&size, (void *)ioctl_param, sizeof size);
6286 + return bcm_mailbox_property((void *)ioctl_param, size);
6287 + break;
6288 + default:
6289 + printk(KERN_ERR DRIVER_NAME "unknown ioctl: %d\n", ioctl_num);
6290 + return -EINVAL;
6291 + }
6292 +
6293 + return 0;
6294 +}
6295 +
6296 +/* Module Declarations */
6297 +
6298 +/*
6299 + * This structure will hold the functions to be called
6300 + * when a process does something to the device we
6301 + * created. Since a pointer to this structure is kept in
6302 + * the devices table, it can't be local to
6303 + * init_module. NULL is for unimplemented functios.
6304 + */
6305 +struct file_operations fops = {
6306 + .unlocked_ioctl = device_ioctl,
6307 + .open = device_open,
6308 + .release = device_release, /* a.k.a. close */
6309 +};
6310 +
6311 +static int bcm_vcio_probe(struct platform_device *pdev)
6312 +{
6313 + int ret = 0;
6314 + struct vc_mailbox *mailbox;
6315 +
6316 + mailbox = kzalloc(sizeof(*mailbox), GFP_KERNEL);
6317 + if (NULL == mailbox) {
6318 + printk(KERN_ERR DRIVER_NAME ": failed to allocate "
6319 + "mailbox memory\n");
6320 + ret = -ENOMEM;
6321 + } else {
6322 + struct resource *res;
6323 +
6324 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
6325 + if (res == NULL) {
6326 + printk(KERN_ERR DRIVER_NAME ": failed to obtain memory "
6327 + "resource\n");
6328 + ret = -ENODEV;
6329 + kfree(mailbox);
6330 + } else {
6331 + /* should be based on the registers from res really */
6332 + mbox_init(mailbox, &pdev->dev, ARM_0_MAIL0_RD);
6333 +
6334 + platform_set_drvdata(pdev, mailbox);
6335 + dev_mbox_register(DRIVER_NAME, &pdev->dev);
6336 +
6337 + mbox_irqaction.dev_id = mailbox;
6338 + setup_irq(IRQ_ARM_MAILBOX, &mbox_irqaction);
6339 + printk(KERN_INFO DRIVER_NAME ": mailbox at %p\n",
6340 + __io_address(ARM_0_MAIL0_RD));
6341 + }
6342 + }
6343 +
6344 + if (ret == 0) {
6345 + /*
6346 + * Register the character device
6347 + */
6348 + ret = register_chrdev(MAJOR_NUM, DEVICE_FILE_NAME, &fops);
6349 +
6350 + /*
6351 + * Negative values signify an error
6352 + */
6353 + if (ret < 0) {
6354 + printk(KERN_ERR DRIVER_NAME
6355 + "Failed registering the character device %d\n", ret);
6356 + return ret;
6357 + }
6358 + }
6359 + return ret;
6360 +}
6361 +
6362 +static int bcm_vcio_remove(struct platform_device *pdev)
6363 +{
6364 + struct vc_mailbox *mailbox = platform_get_drvdata(pdev);
6365 +
6366 + platform_set_drvdata(pdev, NULL);
6367 + kfree(mailbox);
6368 +
6369 + return 0;
6370 +}
6371 +
6372 +static struct platform_driver bcm_mbox_driver = {
6373 + .probe = bcm_vcio_probe,
6374 + .remove = bcm_vcio_remove,
6375 +
6376 + .driver = {
6377 + .name = DRIVER_NAME,
6378 + .owner = THIS_MODULE,
6379 + },
6380 +};
6381 +
6382 +static int __init bcm_mbox_init(void)
6383 +{
6384 + int ret;
6385 +
6386 + printk(KERN_INFO "mailbox: Broadcom VideoCore Mailbox driver\n");
6387 +
6388 + ret = platform_driver_register(&bcm_mbox_driver);
6389 + if (ret != 0) {
6390 + printk(KERN_ERR DRIVER_NAME ": failed to register "
6391 + "on platform\n");
6392 + }
6393 +
6394 + return ret;
6395 +}
6396 +
6397 +static void __exit bcm_mbox_exit(void)
6398 +{
6399 + platform_driver_unregister(&bcm_mbox_driver);
6400 +}
6401 +
6402 +arch_initcall(bcm_mbox_init); /* Initialize early */
6403 +module_exit(bcm_mbox_exit);
6404 +
6405 +MODULE_AUTHOR("Gray Girling");
6406 +MODULE_DESCRIPTION("ARM I/O to VideoCore processor");
6407 +MODULE_LICENSE("GPL");
6408 +MODULE_ALIAS("platform:bcm-mbox");
6409 --- a/arch/arm/mm/Kconfig
6410 +++ b/arch/arm/mm/Kconfig
6411 @@ -358,7 +358,7 @@ config CPU_PJ4B
6412
6413 # ARMv6
6414 config CPU_V6
6415 - bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
6416 + bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || MACH_BCM2708
6417 select CPU_32v6
6418 select CPU_ABRT_EV6
6419 select CPU_CACHE_V6
6420 --- a/arch/arm/mm/proc-v6.S
6421 +++ b/arch/arm/mm/proc-v6.S
6422 @@ -73,10 +73,19 @@ ENDPROC(cpu_v6_reset)
6423 *
6424 * IRQs are already disabled.
6425 */
6426 +
6427 +/* See jira SW-5991 for details of this workaround */
6428 ENTRY(cpu_v6_do_idle)
6429 - mov r1, #0
6430 - mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
6431 - mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
6432 + .align 5
6433 + mov r1, #2
6434 +1: subs r1, #1
6435 + nop
6436 + mcreq p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
6437 + mcreq p15, 0, r1, c7, c0, 4 @ wait for interrupt
6438 + nop
6439 + nop
6440 + nop
6441 + bne 1b
6442 mov pc, lr
6443
6444 ENTRY(cpu_v6_dcache_clean_area)
6445 --- a/arch/arm/tools/mach-types
6446 +++ b/arch/arm/tools/mach-types
6447 @@ -522,6 +522,7 @@ torbreck MACH_TORBRECK TORBRECK 3090
6448 prima2_evb MACH_PRIMA2_EVB PRIMA2_EVB 3103
6449 paz00 MACH_PAZ00 PAZ00 3128
6450 acmenetusfoxg20 MACH_ACMENETUSFOXG20 ACMENETUSFOXG20 3129
6451 +bcm2708 MACH_BCM2708 BCM2708 3138
6452 ag5evm MACH_AG5EVM AG5EVM 3189
6453 ics_if_voip MACH_ICS_IF_VOIP ICS_IF_VOIP 3206
6454 wlf_cragg_6410 MACH_WLF_CRAGG_6410 WLF_CRAGG_6410 3207
6455 --- a/drivers/mmc/host/Kconfig
6456 +++ b/drivers/mmc/host/Kconfig
6457 @@ -272,6 +272,27 @@ config MMC_SDHCI_BCM_KONA
6458
6459 If you have a controller with this interface, say Y or M here.
6460
6461 +config MMC_SDHCI_BCM2708
6462 + tristate "SDHCI support on BCM2708"
6463 + depends on MMC_SDHCI && MACH_BCM2708
6464 + select MMC_SDHCI_IO_ACCESSORS
6465 + help
6466 + This selects the Secure Digital Host Controller Interface (SDHCI)
6467 + often referrered to as the eMMC block.
6468 +
6469 + If you have a controller with this interface, say Y or M here.
6470 +
6471 + If unsure, say N.
6472 +
6473 +config MMC_SDHCI_BCM2708_DMA
6474 + bool "DMA support on BCM2708 Arasan controller"
6475 + depends on MMC_SDHCI_BCM2708
6476 + help
6477 + Enable DMA support on the Arasan SDHCI controller in Broadcom 2708
6478 + based chips.
6479 +
6480 + If unsure, say N.
6481 +
6482 config MMC_SDHCI_BCM2835
6483 tristate "SDHCI platform support for the BCM2835 SD/MMC Controller"
6484 depends on ARCH_BCM2835
6485 --- a/drivers/mmc/host/Makefile
6486 +++ b/drivers/mmc/host/Makefile
6487 @@ -16,6 +16,7 @@ obj-$(CONFIG_MMC_SDHCI_PXAV2) += sdhci-p
6488 obj-$(CONFIG_MMC_SDHCI_S3C) += sdhci-s3c.o
6489 obj-$(CONFIG_MMC_SDHCI_SIRF) += sdhci-sirf.o
6490 obj-$(CONFIG_MMC_SDHCI_SPEAR) += sdhci-spear.o
6491 +obj-$(CONFIG_MMC_SDHCI_BCM2708) += sdhci-bcm2708.o
6492 obj-$(CONFIG_MMC_WBSD) += wbsd.o
6493 obj-$(CONFIG_MMC_AU1X) += au1xmmc.o
6494 obj-$(CONFIG_MMC_OMAP) += omap.o
6495 --- /dev/null
6496 +++ b/drivers/mmc/host/sdhci-bcm2708.c
6497 @@ -0,0 +1,1424 @@
6498 +/*
6499 + * sdhci-bcm2708.c Support for SDHCI device on BCM2708
6500 + * Copyright (c) 2010 Broadcom
6501 + *
6502 + * This program is free software; you can redistribute it and/or modify
6503 + * it under the terms of the GNU General Public License version 2 as
6504 + * published by the Free Software Foundation.
6505 + *
6506 + * This program is distributed in the hope that it will be useful,
6507 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6508 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6509 + * GNU General Public License for more details.
6510 + *
6511 + * You should have received a copy of the GNU General Public License
6512 + * along with this program; if not, write to the Free Software
6513 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
6514 + */
6515 +
6516 +/* Supports:
6517 + * SDHCI platform device - Arasan SD controller in BCM2708
6518 + *
6519 + * Inspired by sdhci-pci.c, by Pierre Ossman
6520 + */
6521 +
6522 +#include <linux/delay.h>
6523 +#include <linux/highmem.h>
6524 +#include <linux/platform_device.h>
6525 +#include <linux/module.h>
6526 +#include <linux/mmc/mmc.h>
6527 +#include <linux/mmc/host.h>
6528 +#include <linux/mmc/sd.h>
6529 +
6530 +#include <linux/io.h>
6531 +#include <linux/dma-mapping.h>
6532 +#include <mach/dma.h>
6533 +
6534 +#include "sdhci.h"
6535 +
6536 +/*****************************************************************************\
6537 + * *
6538 + * Configuration *
6539 + * *
6540 +\*****************************************************************************/
6541 +
6542 +#define DRIVER_NAME "bcm2708_sdhci"
6543 +
6544 +/* for the time being insist on DMA mode - PIO seems not to work */
6545 +#ifndef CONFIG_MMC_SDHCI_BCM2708_DMA
6546 +#warning Non-DMA (PIO) version of this driver currently unavailable
6547 +#endif
6548 +#undef CONFIG_MMC_SDHCI_BCM2708_DMA
6549 +#define CONFIG_MMC_SDHCI_BCM2708_DMA y
6550 +
6551 +#define USE_SYNC_AFTER_DMA
6552 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
6553 +/* #define CHECK_DMA_USE */
6554 +#endif
6555 +//#define LOG_REGISTERS
6556 +
6557 +#define USE_SCHED_TIME
6558 +#define USE_SPACED_WRITES_2CLK 1 /* space consecutive register writes */
6559 +#define USE_SOFTWARE_TIMEOUTS 1 /* not hardware timeouts */
6560 +#define SOFTWARE_ERASE_TIMEOUT_SEC 30
6561 +
6562 +#define SDHCI_BCM_DMA_CHAN 4 /* this default is normally overriden */
6563 +#define SDHCI_BCM_DMA_WAITS 0 /* delays slowing DMA transfers: 0-31 */
6564 +/* We are worried that SD card DMA use may be blocking the AXI bus for others */
6565 +
6566 +/*! TODO: obtain these from the physical address */
6567 +#define DMA_SDHCI_BASE 0x7e300000 /* EMMC register block on Videocore */
6568 +#define DMA_SDHCI_BUFFER (DMA_SDHCI_BASE + SDHCI_BUFFER)
6569 +
6570 +#define BCM2708_SDHCI_SLEEP_TIMEOUT 1000 /* msecs */
6571 +
6572 +/* Mhz clock that the EMMC core is running at. Should match the platform clockman settings */
6573 +#define BCM2708_EMMC_CLOCK_FREQ 80000000
6574 +
6575 +/*****************************************************************************\
6576 + * *
6577 + * Debug *
6578 + * *
6579 +\*****************************************************************************/
6580 +
6581 +
6582 +
6583 +#define DBG(f, x...) \
6584 + pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
6585 +// printk(KERN_INFO DRIVER_NAME " [%s()]: " f, __func__,## x)//GRAYG
6586 +
6587 +
6588 +/*****************************************************************************\
6589 + * *
6590 + * High Precision Time *
6591 + * *
6592 +\*****************************************************************************/
6593 +
6594 +#ifdef USE_SCHED_TIME
6595 +
6596 +#include <mach/frc.h>
6597 +
6598 +typedef unsigned long hptime_t;
6599 +
6600 +#define FMT_HPT "lu"
6601 +
6602 +static inline hptime_t hptime(void)
6603 +{
6604 + return frc_clock_ticks32();
6605 +}
6606 +
6607 +#define HPTIME_CLK_NS 1000ul
6608 +
6609 +#else
6610 +
6611 +typedef unsigned long hptime_t;
6612 +
6613 +#define FMT_HPT "lu"
6614 +
6615 +static inline hptime_t hptime(void)
6616 +{
6617 + return jiffies;
6618 +}
6619 +
6620 +#define HPTIME_CLK_NS (1000000000ul/HZ)
6621 +
6622 +#endif
6623 +
6624 +static inline unsigned long int since_ns(hptime_t t)
6625 +{
6626 + return (unsigned long)((hptime() - t) * HPTIME_CLK_NS);
6627 +}
6628 +
6629 +#if 0
6630 +static void hptime_test(void)
6631 +{
6632 + hptime_t now;
6633 + hptime_t later;
6634 +
6635 + now = hptime();
6636 + msleep(10);
6637 + later = hptime();
6638 +
6639 + printk(KERN_INFO DRIVER_NAME": 10ms = %"FMT_HPT" clks "
6640 + "(from %"FMT_HPT" to %"FMT_HPT") = %luns\n",
6641 + later-now, now, later,
6642 + (unsigned long)(HPTIME_CLK_NS * (later - now)));
6643 +
6644 + now = hptime();
6645 + msleep(1000);
6646 + later = hptime();
6647 +
6648 + printk(KERN_INFO DRIVER_NAME": 1s = %"FMT_HPT" clks "
6649 + "(from %"FMT_HPT" to %"FMT_HPT") = %luns\n",
6650 + later-now, now, later,
6651 + (unsigned long)(HPTIME_CLK_NS * (later - now)));
6652 +}
6653 +#endif
6654 +
6655 +/*****************************************************************************\
6656 + * *
6657 + * SDHCI core callbacks *
6658 + * *
6659 +\*****************************************************************************/
6660 +
6661 +
6662 +#ifdef CHECK_DMA_USE
6663 +/*#define CHECK_DMA_REG_USE*/
6664 +#endif
6665 +
6666 +#ifdef CHECK_DMA_REG_USE
6667 +/* we don't expect anything to be using these registers during a
6668 + DMA (except the IRQ status) - so check */
6669 +static void check_dma_reg_use(struct sdhci_host *host, int reg);
6670 +#else
6671 +#define check_dma_reg_use(host, reg)
6672 +#endif
6673 +
6674 +
6675 +static inline u32 sdhci_bcm2708_raw_readl(struct sdhci_host *host, int reg)
6676 +{
6677 + return readl(host->ioaddr + reg);
6678 +}
6679 +
6680 +u32 sdhci_bcm2708_readl(struct sdhci_host *host, int reg)
6681 +{
6682 + u32 l = sdhci_bcm2708_raw_readl(host, reg);
6683 +
6684 +#ifdef LOG_REGISTERS
6685 + printk(KERN_ERR "%s: readl from 0x%02x, value 0x%08x\n",
6686 + mmc_hostname(host->mmc), reg, l);
6687 +#endif
6688 + check_dma_reg_use(host, reg);
6689 +
6690 + return l;
6691 +}
6692 +
6693 +u16 sdhci_bcm2708_readw(struct sdhci_host *host, int reg)
6694 +{
6695 + u32 l = sdhci_bcm2708_raw_readl(host, reg & ~3);
6696 + u32 w = l >> (reg << 3 & 0x18) & 0xffff;
6697 +
6698 +#ifdef LOG_REGISTERS
6699 + printk(KERN_ERR "%s: readw from 0x%02x, value 0x%04x\n",
6700 + mmc_hostname(host->mmc), reg, w);
6701 +#endif
6702 + check_dma_reg_use(host, reg);
6703 +
6704 + return (u16)w;
6705 +}
6706 +
6707 +u8 sdhci_bcm2708_readb(struct sdhci_host *host, int reg)
6708 +{
6709 + u32 l = sdhci_bcm2708_raw_readl(host, reg & ~3);
6710 + u32 b = l >> (reg << 3 & 0x18) & 0xff;
6711 +
6712 +#ifdef LOG_REGISTERS
6713 + printk(KERN_ERR "%s: readb from 0x%02x, value 0x%02x\n",
6714 + mmc_hostname(host->mmc), reg, b);
6715 +#endif
6716 + check_dma_reg_use(host, reg);
6717 +
6718 + return (u8)b;
6719 +}
6720 +
6721 +
6722 +static void sdhci_bcm2708_raw_writel(struct sdhci_host *host, u32 val, int reg)
6723 +{
6724 + u32 ier;
6725 +
6726 +#if USE_SPACED_WRITES_2CLK
6727 + static bool timeout_disabled = false;
6728 + unsigned int ns_2clk = 0;
6729 +
6730 + /* The Arasan has a bugette whereby it may lose the content of
6731 + * successive writes to registers that are within two SD-card clock
6732 + * cycles of each other (a clock domain crossing problem).
6733 + * It seems, however, that the data register does not have this problem.
6734 + * (Which is just as well - otherwise we'd have to nobble the DMA engine
6735 + * too)
6736 + */
6737 + if (reg != SDHCI_BUFFER && host->clock != 0) {
6738 + /* host->clock is the clock freq in Hz */
6739 + static hptime_t last_write_hpt;
6740 + hptime_t now = hptime();
6741 + ns_2clk = 2000000000/host->clock;
6742 +
6743 + if (now == last_write_hpt || now == last_write_hpt+1) {
6744 + /* we can't guarantee any significant time has
6745 + * passed - we'll have to wait anyway ! */
6746 + udelay((ns_2clk+1000-1)/1000);
6747 + } else
6748 + {
6749 + /* we must have waited at least this many ns: */
6750 + unsigned int ns_wait = HPTIME_CLK_NS *
6751 + (last_write_hpt - now - 1);
6752 + if (ns_wait < ns_2clk)
6753 + udelay((ns_2clk-ns_wait+500)/1000);
6754 + }
6755 + last_write_hpt = now;
6756 + }
6757 +#if USE_SOFTWARE_TIMEOUTS
6758 + /* The Arasan is clocked for timeouts using the SD clock which is too
6759 + * fast for ERASE commands and causes issues. So we disable timeouts
6760 + * for ERASE */
6761 + if (host->cmd != NULL && host->cmd->opcode == MMC_ERASE &&
6762 + reg == (SDHCI_COMMAND & ~3)) {
6763 + mod_timer(&host->timer,
6764 + jiffies + SOFTWARE_ERASE_TIMEOUT_SEC * HZ);
6765 + ier = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE);
6766 + ier &= ~SDHCI_INT_DATA_TIMEOUT;
6767 + writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE);
6768 + timeout_disabled = true;
6769 + udelay((ns_2clk+1000-1)/1000);
6770 + } else if (timeout_disabled) {
6771 + ier = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE);
6772 + ier |= SDHCI_INT_DATA_TIMEOUT;
6773 + writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE);
6774 + timeout_disabled = false;
6775 + udelay((ns_2clk+1000-1)/1000);
6776 + }
6777 +#endif
6778 + writel(val, host->ioaddr + reg);
6779 +#else
6780 + void __iomem * regaddr = host->ioaddr + reg;
6781 +
6782 + writel(val, regaddr);
6783 +
6784 + if (reg != SDHCI_BUFFER && reg != SDHCI_INT_STATUS && host->clock != 0)
6785 + {
6786 + int timeout = 100000;
6787 + while (val != readl(regaddr) && --timeout > 0)
6788 + continue;
6789 +
6790 + if (timeout <= 0)
6791 + printk(KERN_ERR "%s: writing 0x%X to reg 0x%X "
6792 + "always gives 0x%X\n",
6793 + mmc_hostname(host->mmc),
6794 + val, reg, readl(regaddr));
6795 + BUG_ON(timeout <= 0);
6796 + }
6797 +#endif
6798 +}
6799 +
6800 +
6801 +void sdhci_bcm2708_writel(struct sdhci_host *host, u32 val, int reg)
6802 +{
6803 +#ifdef LOG_REGISTERS
6804 + printk(KERN_ERR "%s: writel to 0x%02x, value 0x%08x\n",
6805 + mmc_hostname(host->mmc), reg, val);
6806 +#endif
6807 + check_dma_reg_use(host, reg);
6808 +
6809 + sdhci_bcm2708_raw_writel(host, val, reg);
6810 +}
6811 +
6812 +void sdhci_bcm2708_writew(struct sdhci_host *host, u16 val, int reg)
6813 +{
6814 + static u32 shadow = 0;
6815 +
6816 + u32 p = reg == SDHCI_COMMAND ? shadow :
6817 + sdhci_bcm2708_raw_readl(host, reg & ~3);
6818 + u32 s = reg << 3 & 0x18;
6819 + u32 l = val << s;
6820 + u32 m = 0xffff << s;
6821 +
6822 +#ifdef LOG_REGISTERS
6823 + printk(KERN_ERR "%s: writew to 0x%02x, value 0x%04x\n",
6824 + mmc_hostname(host->mmc), reg, val);
6825 +#endif
6826 +
6827 + if (reg == SDHCI_TRANSFER_MODE)
6828 + shadow = (p & ~m) | l;
6829 + else {
6830 + check_dma_reg_use(host, reg);
6831 + sdhci_bcm2708_raw_writel(host, (p & ~m) | l, reg & ~3);
6832 + }
6833 +}
6834 +
6835 +void sdhci_bcm2708_writeb(struct sdhci_host *host, u8 val, int reg)
6836 +{
6837 + u32 p = sdhci_bcm2708_raw_readl(host, reg & ~3);
6838 + u32 s = reg << 3 & 0x18;
6839 + u32 l = val << s;
6840 + u32 m = 0xff << s;
6841 +
6842 +#ifdef LOG_REGISTERS
6843 + printk(KERN_ERR "%s: writeb to 0x%02x, value 0x%02x\n",
6844 + mmc_hostname(host->mmc), reg, val);
6845 +#endif
6846 +
6847 + check_dma_reg_use(host, reg);
6848 + sdhci_bcm2708_raw_writel(host, (p & ~m) | l, reg & ~3);
6849 +}
6850 +
6851 +static unsigned int sdhci_bcm2708_get_max_clock(struct sdhci_host *host)
6852 +{
6853 + return 20000000; // this value is in Hz (20MHz)
6854 +}
6855 +
6856 +static unsigned int sdhci_bcm2708_get_timeout_clock(struct sdhci_host *host)
6857 +{
6858 + if(host->clock)
6859 + return (host->clock / 1000); // this value is in kHz (100MHz)
6860 + else
6861 + return (sdhci_bcm2708_get_max_clock(host) / 1000);
6862 +}
6863 +
6864 +static void sdhci_bcm2708_set_clock(struct sdhci_host *host, unsigned int clock)
6865 +{
6866 + int div = 0;
6867 + u16 clk = 0;
6868 + unsigned long timeout;
6869 +
6870 + if (clock == host->clock)
6871 + return;
6872 +
6873 + sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
6874 +
6875 + if (clock == 0)
6876 + goto out;
6877 +
6878 + if (BCM2708_EMMC_CLOCK_FREQ <= clock)
6879 + div = 1;
6880 + else {
6881 + for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
6882 + if ((BCM2708_EMMC_CLOCK_FREQ / div) <= clock)
6883 + break;
6884 + }
6885 + }
6886 +
6887 + DBG( "desired SD clock: %d, actual: %d\n",
6888 + clock, BCM2708_EMMC_CLOCK_FREQ / div);
6889 +
6890 + clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
6891 + clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
6892 + << SDHCI_DIVIDER_HI_SHIFT;
6893 + clk |= SDHCI_CLOCK_INT_EN;
6894 +
6895 + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
6896 +
6897 + timeout = 20;
6898 + while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
6899 + & SDHCI_CLOCK_INT_STABLE)) {
6900 + if (timeout == 0) {
6901 + printk(KERN_ERR "%s: Internal clock never "
6902 + "stabilised.\n", mmc_hostname(host->mmc));
6903 + return;
6904 + }
6905 + timeout--;
6906 + mdelay(1);
6907 + }
6908 +
6909 + clk |= SDHCI_CLOCK_CARD_EN;
6910 + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
6911 +out:
6912 + host->clock = clock;
6913 + }
6914 +
6915 +/*****************************************************************************\
6916 + * *
6917 + * DMA Operation *
6918 + * *
6919 +\*****************************************************************************/
6920 +
6921 +struct sdhci_bcm2708_priv {
6922 + int dma_chan;
6923 + int dma_irq;
6924 + void __iomem *dma_chan_base;
6925 + struct bcm2708_dma_cb *cb_base; /* DMA control blocks */
6926 + dma_addr_t cb_handle;
6927 + /* tracking scatter gather progress */
6928 + unsigned sg_ix; /* scatter gather list index */
6929 + unsigned sg_done; /* bytes in current sg_ix done */
6930 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
6931 + unsigned char dma_wanted; /* DMA transfer requested */
6932 + unsigned char dma_waits; /* wait states in DMAs */
6933 +#ifdef CHECK_DMA_USE
6934 + unsigned char dmas_pending; /* no of unfinished DMAs */
6935 + hptime_t when_started;
6936 + hptime_t when_reset;
6937 + hptime_t when_stopped;
6938 +#endif
6939 +#endif
6940 + /* signalling the end of a transfer */
6941 + void (*complete)(struct sdhci_host *);
6942 +};
6943 +
6944 +#define SDHCI_HOST_PRIV(host) \
6945 + (struct sdhci_bcm2708_priv *)((struct sdhci_host *)(host)+1)
6946 +
6947 +
6948 +
6949 +#ifdef CHECK_DMA_REG_USE
6950 +static void check_dma_reg_use(struct sdhci_host *host, int reg)
6951 +{
6952 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
6953 + if (host_priv->dma_wanted && reg != SDHCI_INT_STATUS) {
6954 + printk(KERN_INFO"%s: accessing register 0x%x during DMA\n",
6955 + mmc_hostname(host->mmc), reg);
6956 + }
6957 +}
6958 +#endif
6959 +
6960 +
6961 +
6962 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
6963 +
6964 +static void sdhci_clear_set_irqgen(struct sdhci_host *host, u32 clear, u32 set)
6965 +{
6966 + u32 ier;
6967 +
6968 + ier = sdhci_bcm2708_raw_readl(host, SDHCI_SIGNAL_ENABLE);
6969 + ier &= ~clear;
6970 + ier |= set;
6971 + /* change which requests generate IRQs - makes no difference to
6972 + the content of SDHCI_INT_STATUS, or the need to acknowledge IRQs */
6973 + sdhci_bcm2708_raw_writel(host, ier, SDHCI_SIGNAL_ENABLE);
6974 +}
6975 +
6976 +static void sdhci_signal_irqs(struct sdhci_host *host, u32 irqs)
6977 +{
6978 + sdhci_clear_set_irqgen(host, 0, irqs);
6979 +}
6980 +
6981 +static void sdhci_unsignal_irqs(struct sdhci_host *host, u32 irqs)
6982 +{
6983 + sdhci_clear_set_irqgen(host, irqs, 0);
6984 +}
6985 +
6986 +
6987 +
6988 +static void schci_bcm2708_cb_read(struct sdhci_bcm2708_priv *host,
6989 + int ix,
6990 + dma_addr_t dma_addr, unsigned len,
6991 + int /*bool*/ is_last)
6992 +{
6993 + struct bcm2708_dma_cb *cb = &host->cb_base[ix];
6994 + unsigned char dmawaits = host->dma_waits;
6995 +
6996 + cb->info = BCM2708_DMA_PER_MAP(BCM2708_DMA_DREQ_EMMC) |
6997 + BCM2708_DMA_WAITS(dmawaits) |
6998 + BCM2708_DMA_S_DREQ |
6999 + BCM2708_DMA_D_WIDTH |
7000 + BCM2708_DMA_D_INC;
7001 + cb->src = DMA_SDHCI_BUFFER; /* DATA register DMA address */
7002 + cb->dst = dma_addr;
7003 + cb->length = len;
7004 + cb->stride = 0;
7005 +
7006 + if (is_last) {
7007 + cb->info |= BCM2708_DMA_INT_EN |
7008 + BCM2708_DMA_WAIT_RESP;
7009 + cb->next = 0;
7010 + } else
7011 + cb->next = host->cb_handle +
7012 + (ix+1)*sizeof(struct bcm2708_dma_cb);
7013 +
7014 + cb->pad[0] = 0;
7015 + cb->pad[1] = 0;
7016 +}
7017 +
7018 +static void schci_bcm2708_cb_write(struct sdhci_bcm2708_priv *host,
7019 + int ix,
7020 + dma_addr_t dma_addr, unsigned len,
7021 + int /*bool*/ is_last)
7022 +{
7023 + struct bcm2708_dma_cb *cb = &host->cb_base[ix];
7024 + unsigned char dmawaits = host->dma_waits;
7025 +
7026 + /* We can make arbitrarily large writes as long as we specify DREQ to
7027 + pace the delivery of bytes to the Arasan hardware */
7028 + cb->info = BCM2708_DMA_PER_MAP(BCM2708_DMA_DREQ_EMMC) |
7029 + BCM2708_DMA_WAITS(dmawaits) |
7030 + BCM2708_DMA_D_DREQ |
7031 + BCM2708_DMA_S_WIDTH |
7032 + BCM2708_DMA_S_INC;
7033 + cb->src = dma_addr;
7034 + cb->dst = DMA_SDHCI_BUFFER; /* DATA register DMA address */
7035 + cb->length = len;
7036 + cb->stride = 0;
7037 +
7038 + if (is_last) {
7039 + cb->info |= BCM2708_DMA_INT_EN |
7040 + BCM2708_DMA_WAIT_RESP;
7041 + cb->next = 0;
7042 + } else
7043 + cb->next = host->cb_handle +
7044 + (ix+1)*sizeof(struct bcm2708_dma_cb);
7045 +
7046 + cb->pad[0] = 0;
7047 + cb->pad[1] = 0;
7048 +}
7049 +
7050 +
7051 +static void schci_bcm2708_dma_go(struct sdhci_host *host)
7052 +{
7053 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7054 + void __iomem *dma_chan_base = host_priv->dma_chan_base;
7055 +
7056 + BUG_ON(host_priv->dma_wanted);
7057 +#ifdef CHECK_DMA_USE
7058 + if (host_priv->dma_wanted)
7059 + printk(KERN_ERR "%s: DMA already in progress - "
7060 + "now %"FMT_HPT", last started %lu "
7061 + "reset %lu stopped %lu\n",
7062 + mmc_hostname(host->mmc),
7063 + hptime(), since_ns(host_priv->when_started),
7064 + since_ns(host_priv->when_reset),
7065 + since_ns(host_priv->when_stopped));
7066 + else if (host_priv->dmas_pending > 0)
7067 + printk(KERN_INFO "%s: note - new DMA when %d reset DMAs "
7068 + "already in progress - "
7069 + "now %"FMT_HPT", started %lu reset %lu stopped %lu\n",
7070 + mmc_hostname(host->mmc),
7071 + host_priv->dmas_pending,
7072 + hptime(), since_ns(host_priv->when_started),
7073 + since_ns(host_priv->when_reset),
7074 + since_ns(host_priv->when_stopped));
7075 + host_priv->dmas_pending += 1;
7076 + host_priv->when_started = hptime();
7077 +#endif
7078 + host_priv->dma_wanted = 1;
7079 + DBG("PDMA go - base %p handle %08X\n", dma_chan_base,
7080 + host_priv->cb_handle);
7081 + bcm_dma_start(dma_chan_base, host_priv->cb_handle);
7082 +}
7083 +
7084 +
7085 +static void
7086 +sdhci_platdma_read(struct sdhci_host *host, dma_addr_t dma_addr, size_t len)
7087 +{
7088 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7089 +
7090 + DBG("PDMA to read %d bytes\n", len);
7091 + host_priv->sg_done += len;
7092 + schci_bcm2708_cb_read(host_priv, 0, dma_addr, len, 1/*TRUE*/);
7093 + schci_bcm2708_dma_go(host);
7094 +}
7095 +
7096 +
7097 +static void
7098 +sdhci_platdma_write(struct sdhci_host *host, dma_addr_t dma_addr, size_t len)
7099 +{
7100 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7101 +
7102 + DBG("PDMA to write %d bytes\n", len);
7103 + //BUG_ON(0 != (len & 0x1ff));
7104 +
7105 + host_priv->sg_done += len;
7106 + schci_bcm2708_cb_write(host_priv, 0, dma_addr, len, 1/*TRUE*/);
7107 + schci_bcm2708_dma_go(host);
7108 +}
7109 +
7110 +/*! space is avaiable to receive into or data is available to write
7111 + Platform DMA exported function
7112 +*/
7113 +void
7114 +sdhci_bcm2708_platdma_avail(struct sdhci_host *host, unsigned int *ref_intmask,
7115 + void(*completion_callback)(struct sdhci_host *host))
7116 +{
7117 + struct mmc_data *data = host->data;
7118 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7119 + int sg_ix;
7120 + size_t bytes;
7121 + dma_addr_t addr;
7122 +
7123 + BUG_ON(NULL == data);
7124 + BUG_ON(0 == data->blksz);
7125 +
7126 + host_priv->complete = completion_callback;
7127 +
7128 + sg_ix = host_priv->sg_ix;
7129 + BUG_ON(sg_ix >= data->sg_len);
7130 +
7131 + /* we can DMA blocks larger than blksz - it may hang the DMA
7132 + channel but we are its only user */
7133 + bytes = sg_dma_len(&data->sg[sg_ix]) - host_priv->sg_done;
7134 + addr = sg_dma_address(&data->sg[sg_ix]) + host_priv->sg_done;
7135 +
7136 + if (bytes > 0) {
7137 + /* We're going to poll for read/write available state until
7138 + we finish this DMA
7139 + */
7140 +
7141 + if (data->flags & MMC_DATA_READ) {
7142 + if (*ref_intmask & SDHCI_INT_DATA_AVAIL) {
7143 + sdhci_unsignal_irqs(host, SDHCI_INT_DATA_AVAIL |
7144 + SDHCI_INT_SPACE_AVAIL);
7145 + sdhci_platdma_read(host, addr, bytes);
7146 + }
7147 + } else {
7148 + if (*ref_intmask & SDHCI_INT_SPACE_AVAIL) {
7149 + sdhci_unsignal_irqs(host, SDHCI_INT_DATA_AVAIL |
7150 + SDHCI_INT_SPACE_AVAIL);
7151 + sdhci_platdma_write(host, addr, bytes);
7152 + }
7153 + }
7154 + }
7155 + /* else:
7156 + we have run out of bytes that need transferring (e.g. we may be in
7157 + the middle of the last DMA transfer), or
7158 + it is also possible that we've been called when another IRQ is
7159 + signalled, even though we've turned off signalling of our own IRQ */
7160 +
7161 + *ref_intmask &= ~SDHCI_INT_DATA_END;
7162 + /* don't let the main sdhci driver act on this .. we'll deal with it
7163 + when we respond to the DMA - if one is currently in progress */
7164 +}
7165 +
7166 +/* is it possible to DMA the given mmc_data structure?
7167 + Platform DMA exported function
7168 +*/
7169 +int /*bool*/
7170 +sdhci_bcm2708_platdma_dmaable(struct sdhci_host *host, struct mmc_data *data)
7171 +{
7172 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7173 + int ok = bcm_sg_suitable_for_dma(data->sg, data->sg_len);
7174 +
7175 + if (!ok)
7176 + DBG("Reverting to PIO - bad cache alignment\n");
7177 +
7178 + else {
7179 + host_priv->sg_ix = 0; /* first SG index */
7180 + host_priv->sg_done = 0; /* no bytes done */
7181 + }
7182 +
7183 + return ok;
7184 +}
7185 +
7186 +#include <mach/arm_control.h> //GRAYG
7187 +/*! the current SD transacton has been abandonned
7188 + We need to tidy up if we were in the middle of a DMA
7189 + Platform DMA exported function
7190 +*/
7191 +void
7192 +sdhci_bcm2708_platdma_reset(struct sdhci_host *host, struct mmc_data *data)
7193 +{
7194 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7195 + unsigned long flags;
7196 +
7197 + BUG_ON(NULL == host);
7198 +
7199 + spin_lock_irqsave(&host->lock, flags);
7200 +
7201 + if (host_priv->dma_wanted) {
7202 + if (NULL == data) {
7203 + printk(KERN_ERR "%s: ongoing DMA reset - no data!\n",
7204 + mmc_hostname(host->mmc));
7205 + BUG_ON(NULL == data);
7206 + } else {
7207 + struct scatterlist *sg;
7208 + int sg_len;
7209 + int sg_todo;
7210 + int rc;
7211 + unsigned long cs;
7212 +
7213 + sg = data->sg;
7214 + sg_len = data->sg_len;
7215 + sg_todo = sg_dma_len(&sg[host_priv->sg_ix]);
7216 +
7217 + cs = readl(host_priv->dma_chan_base + BCM2708_DMA_CS);
7218 +
7219 + if (!(BCM2708_DMA_ACTIVE & cs))
7220 + printk(KERN_INFO "%s: missed completion of "
7221 + "cmd %d DMA (%d/%d [%d]/[%d]) - "
7222 + "ignoring it\n",
7223 + mmc_hostname(host->mmc),
7224 + host->last_cmdop,
7225 + host_priv->sg_done, sg_todo,
7226 + host_priv->sg_ix+1, sg_len);
7227 + else
7228 + printk(KERN_INFO "%s: resetting ongoing cmd %d"
7229 + "DMA before %d/%d [%d]/[%d] complete\n",
7230 + mmc_hostname(host->mmc),
7231 + host->last_cmdop,
7232 + host_priv->sg_done, sg_todo,
7233 + host_priv->sg_ix+1, sg_len);
7234 +#ifdef CHECK_DMA_USE
7235 + printk(KERN_INFO "%s: now %"FMT_HPT" started %lu "
7236 + "last reset %lu last stopped %lu\n",
7237 + mmc_hostname(host->mmc),
7238 + hptime(), since_ns(host_priv->when_started),
7239 + since_ns(host_priv->when_reset),
7240 + since_ns(host_priv->when_stopped));
7241 + { unsigned long info, debug;
7242 + void __iomem *base;
7243 + unsigned long pend0, pend1, pend2;
7244 +
7245 + base = host_priv->dma_chan_base;
7246 + cs = readl(base + BCM2708_DMA_CS);
7247 + info = readl(base + BCM2708_DMA_INFO);
7248 + debug = readl(base + BCM2708_DMA_DEBUG);
7249 + printk(KERN_INFO "%s: DMA%d CS=%08lX TI=%08lX "
7250 + "DEBUG=%08lX\n",
7251 + mmc_hostname(host->mmc),
7252 + host_priv->dma_chan,
7253 + cs, info, debug);
7254 + pend0 = readl(__io_address(ARM_IRQ_PEND0));
7255 + pend1 = readl(__io_address(ARM_IRQ_PEND1));
7256 + pend2 = readl(__io_address(ARM_IRQ_PEND2));
7257 +
7258 + printk(KERN_INFO "%s: PEND0=%08lX "
7259 + "PEND1=%08lX PEND2=%08lX\n",
7260 + mmc_hostname(host->mmc),
7261 + pend0, pend1, pend2);
7262 +
7263 + //gintsts = readl(__io_address(GINTSTS));
7264 + //gintmsk = readl(__io_address(GINTMSK));
7265 + //printk(KERN_INFO "%s: USB GINTSTS=%08lX"
7266 + // "GINTMSK=%08lX\n",
7267 + // mmc_hostname(host->mmc), gintsts, gintmsk);
7268 + }
7269 +#endif
7270 + rc = bcm_dma_abort(host_priv->dma_chan_base);
7271 + BUG_ON(rc != 0);
7272 + }
7273 + host_priv->dma_wanted = 0;
7274 +#ifdef CHECK_DMA_USE
7275 + host_priv->when_reset = hptime();
7276 +#endif
7277 + }
7278 +
7279 + spin_unlock_irqrestore(&host->lock, flags);
7280 +}
7281 +
7282 +
7283 +static void sdhci_bcm2708_dma_complete_irq(struct sdhci_host *host,
7284 + u32 dma_cs)
7285 +{
7286 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7287 + struct mmc_data *data;
7288 + struct scatterlist *sg;
7289 + int sg_len;
7290 + int sg_ix;
7291 + int sg_todo;
7292 + unsigned long flags;
7293 +
7294 + BUG_ON(NULL == host);
7295 +
7296 + spin_lock_irqsave(&host->lock, flags);
7297 + data = host->data;
7298 +
7299 +#ifdef CHECK_DMA_USE
7300 + if (host_priv->dmas_pending <= 0)
7301 + DBG("on completion no DMA in progress - "
7302 + "now %"FMT_HPT" started %lu reset %lu stopped %lu\n",
7303 + hptime(), since_ns(host_priv->when_started),
7304 + since_ns(host_priv->when_reset),
7305 + since_ns(host_priv->when_stopped));
7306 + else if (host_priv->dmas_pending > 1)
7307 + DBG("still %d DMA in progress after completion - "
7308 + "now %"FMT_HPT" started %lu reset %lu stopped %lu\n",
7309 + host_priv->dmas_pending - 1,
7310 + hptime(), since_ns(host_priv->when_started),
7311 + since_ns(host_priv->when_reset),
7312 + since_ns(host_priv->when_stopped));
7313 + BUG_ON(host_priv->dmas_pending <= 0);
7314 + host_priv->dmas_pending -= 1;
7315 + host_priv->when_stopped = hptime();
7316 +#endif
7317 + host_priv->dma_wanted = 0;
7318 +
7319 + if (NULL == data) {
7320 + DBG("PDMA unused completion - status 0x%X\n", dma_cs);
7321 + spin_unlock_irqrestore(&host->lock, flags);
7322 + return;
7323 + }
7324 + sg = data->sg;
7325 + sg_len = data->sg_len;
7326 + sg_todo = sg_dma_len(&sg[host_priv->sg_ix]);
7327 +
7328 + DBG("PDMA complete %d/%d [%d]/[%d]..\n",
7329 + host_priv->sg_done, sg_todo,
7330 + host_priv->sg_ix+1, sg_len);
7331 +
7332 + BUG_ON(host_priv->sg_done > sg_todo);
7333 +
7334 + if (host_priv->sg_done >= sg_todo) {
7335 + host_priv->sg_ix++;
7336 + host_priv->sg_done = 0;
7337 + }
7338 +
7339 + sg_ix = host_priv->sg_ix;
7340 + if (sg_ix < sg_len) {
7341 + u32 irq_mask;
7342 + /* Set off next DMA if we've got the capacity */
7343 +
7344 + if (data->flags & MMC_DATA_READ)
7345 + irq_mask = SDHCI_INT_DATA_AVAIL;
7346 + else
7347 + irq_mask = SDHCI_INT_SPACE_AVAIL;
7348 +
7349 + /* We have to use the interrupt status register on the BCM2708
7350 + rather than the SDHCI_PRESENT_STATE register because latency
7351 + in the glue logic means that the information retrieved from
7352 + the latter is not always up-to-date w.r.t the DMA engine -
7353 + it may not indicate that a read or a write is ready yet */
7354 + if (sdhci_bcm2708_raw_readl(host, SDHCI_INT_STATUS) &
7355 + irq_mask) {
7356 + size_t bytes = sg_dma_len(&sg[sg_ix]) -
7357 + host_priv->sg_done;
7358 + dma_addr_t addr = sg_dma_address(&data->sg[sg_ix]) +
7359 + host_priv->sg_done;
7360 +
7361 + /* acknowledge interrupt */
7362 + sdhci_bcm2708_raw_writel(host, irq_mask,
7363 + SDHCI_INT_STATUS);
7364 +
7365 + BUG_ON(0 == bytes);
7366 +
7367 + if (data->flags & MMC_DATA_READ)
7368 + sdhci_platdma_read(host, addr, bytes);
7369 + else
7370 + sdhci_platdma_write(host, addr, bytes);
7371 + } else {
7372 + DBG("PDMA - wait avail\n");
7373 + /* may generate an IRQ if already present */
7374 + sdhci_signal_irqs(host, SDHCI_INT_DATA_AVAIL |
7375 + SDHCI_INT_SPACE_AVAIL);
7376 + }
7377 + } else {
7378 +#ifdef USE_SYNC_AFTER_DMA
7379 + /* On the Arasan controller the stop command (which will be
7380 + scheduled after this completes) does not seem to work
7381 + properly if we allow it to be issued when we are
7382 + transferring data to/from the SD card.
7383 + We get CRC and DEND errors unless we wait for
7384 + the SD controller to finish reading/writing to the card. */
7385 + u32 state_mask;
7386 + int timeout=1000000;
7387 + hptime_t now = hptime();
7388 +
7389 + DBG("PDMA over - sync card\n");
7390 + if (data->flags & MMC_DATA_READ)
7391 + state_mask = SDHCI_DOING_READ;
7392 + else
7393 + state_mask = SDHCI_DOING_WRITE;
7394 +
7395 + while (0 != (sdhci_bcm2708_raw_readl(host,
7396 + SDHCI_PRESENT_STATE) &
7397 + state_mask) && --timeout > 0)
7398 + continue;
7399 +
7400 + if (1000000-timeout > 4000) /*ave. is about 3250*/
7401 + DBG("%s: note - long %s sync %luns - "
7402 + "%d its.\n",
7403 + mmc_hostname(host->mmc),
7404 + data->flags & MMC_DATA_READ? "read": "write",
7405 + since_ns(now), 1000000-timeout);
7406 + if (timeout <= 0)
7407 + printk(KERN_ERR"%s: final %s to SD card still "
7408 + "running\n",
7409 + mmc_hostname(host->mmc),
7410 + data->flags & MMC_DATA_READ? "read": "write");
7411 +#endif
7412 + if (host_priv->complete) {
7413 + (*host_priv->complete)(host);
7414 + DBG("PDMA %s complete\n",
7415 + data->flags & MMC_DATA_READ?"read":"write");
7416 + sdhci_signal_irqs(host, SDHCI_INT_DATA_AVAIL |
7417 + SDHCI_INT_SPACE_AVAIL);
7418 + }
7419 + }
7420 + spin_unlock_irqrestore(&host->lock, flags);
7421 +}
7422 +
7423 +static irqreturn_t sdhci_bcm2708_dma_irq(int irq, void *dev_id)
7424 +{
7425 + irqreturn_t result = IRQ_NONE;
7426 + struct sdhci_host *host = dev_id;
7427 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7428 + u32 dma_cs; /* control and status register */
7429 + unsigned long flags;
7430 +
7431 + BUG_ON(NULL == dev_id);
7432 + BUG_ON(NULL == host_priv->dma_chan_base);
7433 +
7434 + spin_lock_irqsave(&host->lock, flags);
7435 +
7436 + dma_cs = readl(host_priv->dma_chan_base + BCM2708_DMA_CS);
7437 +
7438 + if (dma_cs & BCM2708_DMA_ERR) {
7439 + unsigned long debug;
7440 + debug = readl(host_priv->dma_chan_base +
7441 + BCM2708_DMA_DEBUG);
7442 + printk(KERN_ERR "%s: DMA error - CS %lX DEBUG %lX\n",
7443 + mmc_hostname(host->mmc), (unsigned long)dma_cs,
7444 + (unsigned long)debug);
7445 + /* reset error */
7446 + writel(debug, host_priv->dma_chan_base +
7447 + BCM2708_DMA_DEBUG);
7448 + }
7449 + if (dma_cs & BCM2708_DMA_INT) {
7450 + /* acknowledge interrupt */
7451 + writel(BCM2708_DMA_INT,
7452 + host_priv->dma_chan_base + BCM2708_DMA_CS);
7453 +
7454 + dsb(); /* ARM data synchronization (push) operation */
7455 +
7456 + if (!host_priv->dma_wanted) {
7457 + /* ignore this interrupt - it was reset */
7458 + printk(KERN_INFO "%s: DMA IRQ %X ignored - "
7459 + "results were reset\n",
7460 + mmc_hostname(host->mmc), dma_cs);
7461 +#ifdef CHECK_DMA_USE
7462 + printk(KERN_INFO "%s: now %"FMT_HPT
7463 + " started %lu reset %lu stopped %lu\n",
7464 + mmc_hostname(host->mmc), hptime(),
7465 + since_ns(host_priv->when_started),
7466 + since_ns(host_priv->when_reset),
7467 + since_ns(host_priv->when_stopped));
7468 + host_priv->dmas_pending--;
7469 +#endif
7470 + } else
7471 + sdhci_bcm2708_dma_complete_irq(host, dma_cs);
7472 +
7473 + result = IRQ_HANDLED;
7474 + }
7475 +
7476 + spin_unlock_irqrestore(&host->lock, flags);
7477 +
7478 + return result;
7479 +}
7480 +#endif /* CONFIG_MMC_SDHCI_BCM2708_DMA */
7481 +
7482 +
7483 +/***************************************************************************** \
7484 + * *
7485 + * Device Attributes *
7486 + * *
7487 +\*****************************************************************************/
7488 +
7489 +
7490 +/**
7491 + * Show the DMA-using status
7492 + */
7493 +static ssize_t attr_dma_show(struct device *_dev,
7494 + struct device_attribute *attr, char *buf)
7495 +{
7496 + struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev);
7497 +
7498 + if (host) {
7499 + int use_dma = (host->flags & SDHCI_USE_PLATDMA? 1:0);
7500 + return sprintf(buf, "%d\n", use_dma);
7501 + } else
7502 + return -EINVAL;
7503 +}
7504 +
7505 +/**
7506 + * Set the DMA-using status
7507 + */
7508 +static ssize_t attr_dma_store(struct device *_dev,
7509 + struct device_attribute *attr,
7510 + const char *buf, size_t count)
7511 +{
7512 + struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev);
7513 +
7514 + if (host) {
7515 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7516 + int on = simple_strtol(buf, NULL, 0);
7517 + if (on) {
7518 + host->flags |= SDHCI_USE_PLATDMA;
7519 + printk(KERN_INFO "%s: DMA enabled\n",
7520 + mmc_hostname(host->mmc));
7521 + } else {
7522 + host->flags &= ~(SDHCI_USE_PLATDMA | SDHCI_REQ_USE_DMA);
7523 + printk(KERN_INFO "%s: DMA disabled\n",
7524 + mmc_hostname(host->mmc));
7525 + }
7526 +#endif
7527 + return count;
7528 + } else
7529 + return -EINVAL;
7530 +}
7531 +
7532 +static DEVICE_ATTR(use_dma, S_IRUGO | S_IWUGO, attr_dma_show, attr_dma_store);
7533 +
7534 +
7535 +/**
7536 + * Show the DMA wait states used
7537 + */
7538 +static ssize_t attr_dmawait_show(struct device *_dev,
7539 + struct device_attribute *attr, char *buf)
7540 +{
7541 + struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev);
7542 +
7543 + if (host) {
7544 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7545 + int dmawait = host_priv->dma_waits;
7546 + return sprintf(buf, "%d\n", dmawait);
7547 + } else
7548 + return -EINVAL;
7549 +}
7550 +
7551 +/**
7552 + * Set the DMA wait state used
7553 + */
7554 +static ssize_t attr_dmawait_store(struct device *_dev,
7555 + struct device_attribute *attr,
7556 + const char *buf, size_t count)
7557 +{
7558 + struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev);
7559 +
7560 + if (host) {
7561 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7562 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7563 + int dma_waits = simple_strtol(buf, NULL, 0);
7564 + if (dma_waits >= 0 && dma_waits < 32)
7565 + host_priv->dma_waits = dma_waits;
7566 + else
7567 + printk(KERN_ERR "%s: illegal dma_waits value - %d",
7568 + mmc_hostname(host->mmc), dma_waits);
7569 +#endif
7570 + return count;
7571 + } else
7572 + return -EINVAL;
7573 +}
7574 +
7575 +static DEVICE_ATTR(dma_wait, S_IRUGO | S_IWUGO,
7576 + attr_dmawait_show, attr_dmawait_store);
7577 +
7578 +
7579 +/**
7580 + * Show the DMA-using status
7581 + */
7582 +static ssize_t attr_status_show(struct device *_dev,
7583 + struct device_attribute *attr, char *buf)
7584 +{
7585 + struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev);
7586 +
7587 + if (host) {
7588 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7589 + return sprintf(buf,
7590 + "present: yes\n"
7591 + "power: %s\n"
7592 + "clock: %u Hz\n"
7593 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7594 + "dma: %s (%d waits)\n",
7595 +#else
7596 + "dma: unconfigured\n",
7597 +#endif
7598 + "always on",
7599 + host->clock
7600 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7601 + , (host->flags & SDHCI_USE_PLATDMA)? "on": "off"
7602 + , host_priv->dma_waits
7603 +#endif
7604 + );
7605 + } else
7606 + return -EINVAL;
7607 +}
7608 +
7609 +static DEVICE_ATTR(status, S_IRUGO, attr_status_show, NULL);
7610 +
7611 +/***************************************************************************** \
7612 + * *
7613 + * Power Management *
7614 + * *
7615 +\*****************************************************************************/
7616 +
7617 +
7618 +#ifdef CONFIG_PM
7619 +static int sdhci_bcm2708_suspend(struct platform_device *dev, pm_message_t state)
7620 +{
7621 + struct sdhci_host *host = (struct sdhci_host *)
7622 + platform_get_drvdata(dev);
7623 + int ret = 0;
7624 +
7625 + if (host->mmc) {
7626 + ret = mmc_suspend_host(host->mmc);
7627 + }
7628 +
7629 + return ret;
7630 +}
7631 +
7632 +static int sdhci_bcm2708_resume(struct platform_device *dev)
7633 +{
7634 + struct sdhci_host *host = (struct sdhci_host *)
7635 + platform_get_drvdata(dev);
7636 + int ret = 0;
7637 +
7638 + if (host->mmc) {
7639 + ret = mmc_resume_host(host->mmc);
7640 + }
7641 +
7642 + return ret;
7643 +}
7644 +#endif
7645 +
7646 +
7647 +/*****************************************************************************\
7648 + * *
7649 + * Device quirk functions. Implemented as local ops because the flags *
7650 + * field is out of space with newer kernels. This implementation can be *
7651 + * back ported to older kernels as well. *
7652 +\****************************************************************************/
7653 +static unsigned int sdhci_bcm2708_quirk_extra_ints(struct sdhci_host *host)
7654 +{
7655 + return 1;
7656 +}
7657 +
7658 +static unsigned int sdhci_bcm2708_quirk_spurious_crc(struct sdhci_host *host)
7659 +{
7660 + return 1;
7661 +}
7662 +
7663 +static unsigned int sdhci_bcm2708_quirk_voltage_broken(struct sdhci_host *host)
7664 +{
7665 + return 1;
7666 +}
7667 +
7668 +static unsigned int sdhci_bcm2708_uhs_broken(struct sdhci_host *host)
7669 +{
7670 + return 1;
7671 +}
7672 +
7673 +/***************************************************************************** \
7674 + * *
7675 + * Device ops *
7676 + * *
7677 +\*****************************************************************************/
7678 +
7679 +static struct sdhci_ops sdhci_bcm2708_ops = {
7680 +#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
7681 + .read_l = sdhci_bcm2708_readl,
7682 + .read_w = sdhci_bcm2708_readw,
7683 + .read_b = sdhci_bcm2708_readb,
7684 + .write_l = sdhci_bcm2708_writel,
7685 + .write_w = sdhci_bcm2708_writew,
7686 + .write_b = sdhci_bcm2708_writeb,
7687 +#else
7688 +#error The BCM2708 SDHCI driver needs CONFIG_MMC_SDHCI_IO_ACCESSORS to be set
7689 +#endif
7690 + //.enable_dma = NULL,
7691 + .set_clock = sdhci_bcm2708_set_clock,
7692 + .get_max_clock = sdhci_bcm2708_get_max_clock,
7693 + //.get_min_clock = NULL,
7694 + .get_timeout_clock = sdhci_bcm2708_get_timeout_clock,
7695 +
7696 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7697 + // Platform DMA operations
7698 + .pdma_able = sdhci_bcm2708_platdma_dmaable,
7699 + .pdma_avail = sdhci_bcm2708_platdma_avail,
7700 + .pdma_reset = sdhci_bcm2708_platdma_reset,
7701 +#endif
7702 + .extra_ints = sdhci_bcm2708_quirk_extra_ints,
7703 + .spurious_crc_acmd51 = sdhci_bcm2708_quirk_spurious_crc,
7704 + .voltage_broken = sdhci_bcm2708_quirk_voltage_broken,
7705 + .uhs_broken = sdhci_bcm2708_uhs_broken,
7706 +};
7707 +
7708 +/*****************************************************************************\
7709 + * *
7710 + * Device probing/removal *
7711 + * *
7712 +\*****************************************************************************/
7713 +
7714 +static int sdhci_bcm2708_probe(struct platform_device *pdev)
7715 +{
7716 + struct sdhci_host *host;
7717 + struct resource *iomem;
7718 + struct sdhci_bcm2708_priv *host_priv;
7719 + int ret;
7720 +
7721 + BUG_ON(pdev == NULL);
7722 +
7723 + iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7724 + if (!iomem) {
7725 + ret = -ENOMEM;
7726 + goto err;
7727 + }
7728 +
7729 + if (resource_size(iomem) != 0x100)
7730 + dev_err(&pdev->dev, "Invalid iomem size. You may "
7731 + "experience problems.\n");
7732 +
7733 + if (pdev->dev.parent)
7734 + host = sdhci_alloc_host(pdev->dev.parent,
7735 + sizeof(struct sdhci_bcm2708_priv));
7736 + else
7737 + host = sdhci_alloc_host(&pdev->dev,
7738 + sizeof(struct sdhci_bcm2708_priv));
7739 +
7740 + if (IS_ERR(host)) {
7741 + ret = PTR_ERR(host);
7742 + goto err;
7743 + }
7744 +
7745 + host->hw_name = "BCM2708_Arasan";
7746 + host->ops = &sdhci_bcm2708_ops;
7747 + host->irq = platform_get_irq(pdev, 0);
7748 +
7749 + host->quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
7750 + SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
7751 + SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
7752 + SDHCI_QUIRK_NONSTANDARD_CLOCK;
7753 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7754 + host->flags = SDHCI_USE_PLATDMA;
7755 +#endif
7756 +
7757 + if (!request_mem_region(iomem->start, resource_size(iomem),
7758 + mmc_hostname(host->mmc))) {
7759 + dev_err(&pdev->dev, "cannot request region\n");
7760 + ret = -EBUSY;
7761 + goto err_request;
7762 + }
7763 +
7764 + host->ioaddr = ioremap(iomem->start, resource_size(iomem));
7765 + if (!host->ioaddr) {
7766 + dev_err(&pdev->dev, "failed to remap registers\n");
7767 + ret = -ENOMEM;
7768 + goto err_remap;
7769 + }
7770 +
7771 + host_priv = SDHCI_HOST_PRIV(host);
7772 +
7773 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7774 + host_priv->dma_wanted = 0;
7775 +#ifdef CHECK_DMA_USE
7776 + host_priv->dmas_pending = 0;
7777 + host_priv->when_started = 0;
7778 + host_priv->when_reset = 0;
7779 + host_priv->when_stopped = 0;
7780 +#endif
7781 + host_priv->sg_ix = 0;
7782 + host_priv->sg_done = 0;
7783 + host_priv->complete = NULL;
7784 + host_priv->dma_waits = SDHCI_BCM_DMA_WAITS;
7785 +
7786 + host_priv->cb_base = dma_alloc_writecombine(&pdev->dev, SZ_4K,
7787 + &host_priv->cb_handle,
7788 + GFP_KERNEL);
7789 + if (!host_priv->cb_base) {
7790 + dev_err(&pdev->dev, "cannot allocate DMA CBs\n");
7791 + ret = -ENOMEM;
7792 + goto err_alloc_cb;
7793 + }
7794 +
7795 + ret = bcm_dma_chan_alloc(BCM_DMA_FEATURE_FAST,
7796 + &host_priv->dma_chan_base,
7797 + &host_priv->dma_irq);
7798 + if (ret < 0) {
7799 + dev_err(&pdev->dev, "couldn't allocate a DMA channel\n");
7800 + goto err_add_dma;
7801 + }
7802 + host_priv->dma_chan = ret;
7803 +
7804 + ret = request_irq(host_priv->dma_irq, sdhci_bcm2708_dma_irq,
7805 + IRQF_SHARED, DRIVER_NAME " (dma)", host);
7806 + if (ret) {
7807 + dev_err(&pdev->dev, "cannot set DMA IRQ\n");
7808 + goto err_add_dma_irq;
7809 + }
7810 + DBG("DMA CBs %p handle %08X DMA%d %p DMA IRQ %d\n",
7811 + host_priv->cb_base, (unsigned)host_priv->cb_handle,
7812 + host_priv->dma_chan, host_priv->dma_chan_base,
7813 + host_priv->dma_irq);
7814 +
7815 + host->mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
7816 +#endif
7817 +
7818 + ret = sdhci_add_host(host);
7819 + if (ret)
7820 + goto err_add_host;
7821 +
7822 + platform_set_drvdata(pdev, host);
7823 + ret = device_create_file(&pdev->dev, &dev_attr_use_dma);
7824 + ret = device_create_file(&pdev->dev, &dev_attr_dma_wait);
7825 + ret = device_create_file(&pdev->dev, &dev_attr_status);
7826 +
7827 + printk(KERN_INFO "%s: BCM2708 SDHC host at 0x%08llx DMA %d IRQ %d\n",
7828 + mmc_hostname(host->mmc), (unsigned long long)iomem->start,
7829 + host_priv->dma_chan, host_priv->dma_irq);
7830 +
7831 + return 0;
7832 +
7833 +err_add_host:
7834 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7835 + free_irq(host_priv->dma_irq, host);
7836 +err_add_dma_irq:
7837 + bcm_dma_chan_free(host_priv->dma_chan);
7838 +err_add_dma:
7839 + dma_free_writecombine(&pdev->dev, SZ_4K, host_priv->cb_base,
7840 + host_priv->cb_handle);
7841 +err_alloc_cb:
7842 +#endif
7843 + iounmap(host->ioaddr);
7844 +err_remap:
7845 + release_mem_region(iomem->start, resource_size(iomem));
7846 +err_request:
7847 + sdhci_free_host(host);
7848 +err:
7849 + dev_err(&pdev->dev, "probe failed, err %d\n", ret);
7850 + return ret;
7851 +}
7852 +
7853 +static int sdhci_bcm2708_remove(struct platform_device *pdev)
7854 +{
7855 + struct sdhci_host *host = platform_get_drvdata(pdev);
7856 + struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7857 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7858 + int dead;
7859 + u32 scratch;
7860 +
7861 + dead = 0;
7862 + scratch = sdhci_bcm2708_readl(host, SDHCI_INT_STATUS);
7863 + if (scratch == (u32)-1)
7864 + dead = 1;
7865 +
7866 + device_remove_file(&pdev->dev, &dev_attr_status);
7867 + device_remove_file(&pdev->dev, &dev_attr_dma_wait);
7868 + device_remove_file(&pdev->dev, &dev_attr_use_dma);
7869 +
7870 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7871 + free_irq(host_priv->dma_irq, host);
7872 + dma_free_writecombine(&pdev->dev, SZ_4K, host_priv->cb_base,
7873 + host_priv->cb_handle);
7874 +#endif
7875 + sdhci_remove_host(host, dead);
7876 + iounmap(host->ioaddr);
7877 + release_mem_region(iomem->start, resource_size(iomem));
7878 + sdhci_free_host(host);
7879 + platform_set_drvdata(pdev, NULL);
7880 +
7881 + return 0;
7882 +}
7883 +
7884 +static struct platform_driver sdhci_bcm2708_driver = {
7885 + .driver = {
7886 + .name = DRIVER_NAME,
7887 + .owner = THIS_MODULE,
7888 + },
7889 + .probe = sdhci_bcm2708_probe,
7890 + .remove = sdhci_bcm2708_remove,
7891 +
7892 +#ifdef CONFIG_PM
7893 + .suspend = sdhci_bcm2708_suspend,
7894 + .resume = sdhci_bcm2708_resume,
7895 +#endif
7896 +
7897 +};
7898 +
7899 +/*****************************************************************************\
7900 + * *
7901 + * Driver init/exit *
7902 + * *
7903 +\*****************************************************************************/
7904 +
7905 +static int __init sdhci_drv_init(void)
7906 +{
7907 + return platform_driver_register(&sdhci_bcm2708_driver);
7908 +}
7909 +
7910 +static void __exit sdhci_drv_exit(void)
7911 +{
7912 + platform_driver_unregister(&sdhci_bcm2708_driver);
7913 +}
7914 +
7915 +module_init(sdhci_drv_init);
7916 +module_exit(sdhci_drv_exit);
7917 +
7918 +MODULE_DESCRIPTION("Secure Digital Host Controller Interface platform driver");
7919 +MODULE_AUTHOR("Broadcom <info@broadcom.com>");
7920 +MODULE_LICENSE("GPL v2");
7921 +MODULE_ALIAS("platform:"DRIVER_NAME);
7922 --- a/drivers/mmc/host/sdhci.c
7923 +++ b/drivers/mmc/host/sdhci.c
7924 @@ -28,6 +28,7 @@
7925 #include <linux/mmc/mmc.h>
7926 #include <linux/mmc/host.h>
7927 #include <linux/mmc/card.h>
7928 +#include <linux/mmc/sd.h>
7929 #include <linux/mmc/slot-gpio.h>
7930
7931 #include "sdhci.h"
7932 @@ -326,7 +327,7 @@ static void sdhci_read_block_pio(struct
7933 u32 uninitialized_var(scratch);
7934 u8 *buf;
7935
7936 - DBG("PIO reading\n");
7937 + DBG("PIO reading %db\n", host->data->blksz);
7938
7939 blksize = host->data->blksz;
7940 chunk = 0;
7941 @@ -371,7 +372,7 @@ static void sdhci_write_block_pio(struct
7942 u32 scratch;
7943 u8 *buf;
7944
7945 - DBG("PIO writing\n");
7946 + DBG("PIO writing %db\n", host->data->blksz);
7947
7948 blksize = host->data->blksz;
7949 chunk = 0;
7950 @@ -410,19 +411,28 @@ static void sdhci_write_block_pio(struct
7951 local_irq_restore(flags);
7952 }
7953
7954 -static void sdhci_transfer_pio(struct sdhci_host *host)
7955 +static void sdhci_transfer_pio(struct sdhci_host *host, u32 intstate)
7956 {
7957 u32 mask;
7958 + u32 state = 0;
7959 + u32 intmask;
7960 + int available;
7961
7962 BUG_ON(!host->data);
7963
7964 if (host->blocks == 0)
7965 return;
7966
7967 - if (host->data->flags & MMC_DATA_READ)
7968 + if (host->data->flags & MMC_DATA_READ) {
7969 mask = SDHCI_DATA_AVAILABLE;
7970 - else
7971 + intmask = SDHCI_INT_DATA_AVAIL;
7972 + } else {
7973 mask = SDHCI_SPACE_AVAILABLE;
7974 + intmask = SDHCI_INT_SPACE_AVAIL;
7975 + }
7976 +
7977 + /* initially we can see whether we can procede using intstate */
7978 + available = (intstate & intmask);
7979
7980 /*
7981 * Some controllers (JMicron JMB38x) mess up the buffer bits
7982 @@ -433,7 +443,7 @@ static void sdhci_transfer_pio(struct sd
7983 (host->data->blocks == 1))
7984 mask = ~0;
7985
7986 - while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7987 + while (available) {
7988 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
7989 udelay(100);
7990
7991 @@ -445,9 +455,11 @@ static void sdhci_transfer_pio(struct sd
7992 host->blocks--;
7993 if (host->blocks == 0)
7994 break;
7995 + state = sdhci_readl(host, SDHCI_PRESENT_STATE);
7996 + available = state & mask;
7997 }
7998
7999 - DBG("PIO transfer complete.\n");
8000 + DBG("PIO transfer complete - %d blocks left.\n", host->blocks);
8001 }
8002
8003 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
8004 @@ -720,7 +732,9 @@ static void sdhci_set_transfer_irqs(stru
8005 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
8006 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
8007
8008 - if (host->flags & SDHCI_REQ_USE_DMA)
8009 + /* platform DMA will begin on receipt of PIO irqs */
8010 + if ((host->flags & SDHCI_REQ_USE_DMA) &&
8011 + !(host->flags & SDHCI_USE_PLATDMA))
8012 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
8013 else
8014 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
8015 @@ -752,44 +766,25 @@ static void sdhci_prepare_data(struct sd
8016 host->data_early = 0;
8017 host->data->bytes_xfered = 0;
8018
8019 - if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
8020 + if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA | SDHCI_USE_PLATDMA))
8021 host->flags |= SDHCI_REQ_USE_DMA;
8022
8023 /*
8024 * FIXME: This doesn't account for merging when mapping the
8025 * scatterlist.
8026 */
8027 - if (host->flags & SDHCI_REQ_USE_DMA) {
8028 - int broken, i;
8029 - struct scatterlist *sg;
8030 -
8031 - broken = 0;
8032 - if (host->flags & SDHCI_USE_ADMA) {
8033 - if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
8034 - broken = 1;
8035 - } else {
8036 - if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
8037 - broken = 1;
8038 - }
8039 -
8040 - if (unlikely(broken)) {
8041 - for_each_sg(data->sg, sg, data->sg_len, i) {
8042 - if (sg->length & 0x3) {
8043 - DBG("Reverting to PIO because of "
8044 - "transfer size (%d)\n",
8045 - sg->length);
8046 - host->flags &= ~SDHCI_REQ_USE_DMA;
8047 - break;
8048 - }
8049 - }
8050 - }
8051 - }
8052
8053 /*
8054 * The assumption here being that alignment is the same after
8055 * translation to device address space.
8056 */
8057 - if (host->flags & SDHCI_REQ_USE_DMA) {
8058 + if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_PLATDMA)) ==
8059 + (SDHCI_REQ_USE_DMA | SDHCI_USE_PLATDMA)) {
8060 +
8061 + if (! sdhci_platdma_dmaable(host, data))
8062 + host->flags &= ~SDHCI_REQ_USE_DMA;
8063 +
8064 + } else if (host->flags & SDHCI_REQ_USE_DMA) {
8065 int broken, i;
8066 struct scatterlist *sg;
8067
8068 @@ -848,7 +843,8 @@ static void sdhci_prepare_data(struct sd
8069 */
8070 WARN_ON(1);
8071 host->flags &= ~SDHCI_REQ_USE_DMA;
8072 - } else {
8073 + } else
8074 + if (!(host->flags & SDHCI_USE_PLATDMA)) {
8075 WARN_ON(sg_cnt != 1);
8076 sdhci_writel(host, sg_dma_address(data->sg),
8077 SDHCI_DMA_ADDRESS);
8078 @@ -864,11 +860,13 @@ static void sdhci_prepare_data(struct sd
8079 if (host->version >= SDHCI_SPEC_200) {
8080 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
8081 ctrl &= ~SDHCI_CTRL_DMA_MASK;
8082 + if (! (host->flags & SDHCI_USE_PLATDMA)) {
8083 if ((host->flags & SDHCI_REQ_USE_DMA) &&
8084 (host->flags & SDHCI_USE_ADMA))
8085 ctrl |= SDHCI_CTRL_ADMA32;
8086 else
8087 ctrl |= SDHCI_CTRL_SDMA;
8088 + }
8089 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
8090 }
8091
8092 @@ -925,7 +923,8 @@ static void sdhci_set_transfer_mode(stru
8093
8094 if (data->flags & MMC_DATA_READ)
8095 mode |= SDHCI_TRNS_READ;
8096 - if (host->flags & SDHCI_REQ_USE_DMA)
8097 + if ((host->flags & SDHCI_REQ_USE_DMA) &&
8098 + !(host->flags & SDHCI_USE_PLATDMA))
8099 mode |= SDHCI_TRNS_DMA;
8100
8101 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
8102 @@ -941,13 +940,16 @@ static void sdhci_finish_data(struct sdh
8103 host->data = NULL;
8104
8105 if (host->flags & SDHCI_REQ_USE_DMA) {
8106 - if (host->flags & SDHCI_USE_ADMA)
8107 - sdhci_adma_table_post(host, data);
8108 - else {
8109 + /* we may have to abandon an ongoing platform DMA */
8110 + if (host->flags & SDHCI_USE_PLATDMA)
8111 + sdhci_platdma_reset(host, data);
8112 +
8113 + if (host->flags & (SDHCI_USE_PLATDMA | SDHCI_USE_SDMA)) {
8114 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
8115 data->sg_len, (data->flags & MMC_DATA_READ) ?
8116 DMA_FROM_DEVICE : DMA_TO_DEVICE);
8117 - }
8118 + } else if (host->flags & SDHCI_USE_ADMA)
8119 + sdhci_adma_table_post(host, data);
8120 }
8121
8122 /*
8123 @@ -1000,6 +1002,12 @@ void sdhci_send_command(struct sdhci_hos
8124 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
8125 mask |= SDHCI_DATA_INHIBIT;
8126
8127 + if(host->ops->missing_status && (cmd->opcode == MMC_SEND_STATUS)) {
8128 + timeout = 5000; // Really obscenely large delay to send the status, due to bug in controller
8129 + // which might cause the STATUS command to get stuck when a data operation is in flow
8130 + mask |= SDHCI_DATA_INHIBIT;
8131 + }
8132 +
8133 /* We shouldn't wait for data inihibit for stop commands, even
8134 though they might use busy signaling */
8135 if (host->mrq->data && (cmd == host->mrq->data->stop))
8136 @@ -1017,6 +1025,8 @@ void sdhci_send_command(struct sdhci_hos
8137 timeout--;
8138 mdelay(1);
8139 }
8140 + DBG("send cmd %d - wait 0x%X irq 0x%x\n", cmd->opcode, mask,
8141 + sdhci_readl(host, SDHCI_INT_STATUS));
8142
8143 timeout = jiffies;
8144 if (!cmd->data && cmd->cmd_timeout_ms > 9000)
8145 @@ -1026,6 +1036,10 @@ void sdhci_send_command(struct sdhci_hos
8146 mod_timer(&host->timer, timeout);
8147
8148 host->cmd = cmd;
8149 + if (host->last_cmdop == MMC_APP_CMD)
8150 + host->last_cmdop = -cmd->opcode;
8151 + else
8152 + host->last_cmdop = cmd->opcode;
8153
8154 sdhci_prepare_data(host, cmd);
8155
8156 @@ -1505,7 +1519,7 @@ static void sdhci_do_set_ios(struct sdhc
8157 else
8158 ctrl &= ~SDHCI_CTRL_HISPD;
8159
8160 - if (host->version >= SDHCI_SPEC_300) {
8161 + if (host->version >= SDHCI_SPEC_300 && !(host->ops->uhs_broken)) {
8162 u16 clk, ctrl_2;
8163
8164 /* In case of UHS-I modes, set High Speed Enable */
8165 @@ -2204,7 +2218,7 @@ static void sdhci_timeout_timer(unsigned
8166
8167 if (host->mrq) {
8168 pr_err("%s: Timeout waiting for hardware "
8169 - "interrupt.\n", mmc_hostname(host->mmc));
8170 + "interrupt - cmd%d.\n", mmc_hostname(host->mmc), host->last_cmdop);
8171 sdhci_dumpregs(host);
8172
8173 if (host->data) {
8174 @@ -2249,10 +2263,13 @@ static void sdhci_cmd_irq(struct sdhci_h
8175 BUG_ON(intmask == 0);
8176
8177 if (!host->cmd) {
8178 + if (!(host->ops->extra_ints)) {
8179 pr_err("%s: Got command interrupt 0x%08x even "
8180 "though no command operation was in progress.\n",
8181 mmc_hostname(host->mmc), (unsigned)intmask);
8182 sdhci_dumpregs(host);
8183 + } else
8184 + DBG("cmd irq 0x%08x cmd complete\n", (unsigned)intmask);
8185 return;
8186 }
8187
8188 @@ -2322,6 +2339,19 @@ static void sdhci_show_adma_error(struct
8189 static void sdhci_show_adma_error(struct sdhci_host *host) { }
8190 #endif
8191
8192 +static void sdhci_data_end(struct sdhci_host *host)
8193 +{
8194 + if (host->cmd) {
8195 + /*
8196 + * Data managed to finish before the
8197 + * command completed. Make sure we do
8198 + * things in the proper order.
8199 + */
8200 + host->data_early = 1;
8201 + } else
8202 + sdhci_finish_data(host);
8203 +}
8204 +
8205 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
8206 {
8207 u32 command;
8208 @@ -2351,23 +2381,39 @@ static void sdhci_data_irq(struct sdhci_
8209 }
8210 }
8211
8212 + if (!(host->ops->extra_ints)) {
8213 pr_err("%s: Got data interrupt 0x%08x even "
8214 "though no data operation was in progress.\n",
8215 mmc_hostname(host->mmc), (unsigned)intmask);
8216 sdhci_dumpregs(host);
8217 + } else
8218 + DBG("data irq 0x%08x but no data\n", (unsigned)intmask);
8219
8220 return;
8221 }
8222
8223 if (intmask & SDHCI_INT_DATA_TIMEOUT)
8224 host->data->error = -ETIMEDOUT;
8225 - else if (intmask & SDHCI_INT_DATA_END_BIT)
8226 + else if (intmask & SDHCI_INT_DATA_END_BIT) {
8227 + DBG("end error in cmd %d\n", host->last_cmdop);
8228 + if (host->ops->spurious_crc_acmd51 &&
8229 + host->last_cmdop == -SD_APP_SEND_SCR) {
8230 + DBG("ignoring spurious data_end_bit error\n");
8231 + intmask = SDHCI_INT_DATA_AVAIL|SDHCI_INT_DATA_END;
8232 + } else
8233 host->data->error = -EILSEQ;
8234 - else if ((intmask & SDHCI_INT_DATA_CRC) &&
8235 + } else if ((intmask & SDHCI_INT_DATA_CRC) &&
8236 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
8237 - != MMC_BUS_TEST_R)
8238 + != MMC_BUS_TEST_R) {
8239 + DBG("crc error in cmd %d\n", host->last_cmdop);
8240 + if (host->ops->spurious_crc_acmd51 &&
8241 + host->last_cmdop == -SD_APP_SEND_SCR) {
8242 + DBG("ignoring spurious data_crc_bit error\n");
8243 + intmask = SDHCI_INT_DATA_AVAIL|SDHCI_INT_DATA_END;
8244 + } else {
8245 host->data->error = -EILSEQ;
8246 - else if (intmask & SDHCI_INT_ADMA_ERROR) {
8247 + }
8248 + } else if (intmask & SDHCI_INT_ADMA_ERROR) {
8249 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
8250 sdhci_show_adma_error(host);
8251 host->data->error = -EIO;
8252 @@ -2375,11 +2421,18 @@ static void sdhci_data_irq(struct sdhci_
8253 host->ops->adma_workaround(host, intmask);
8254 }
8255
8256 - if (host->data->error)
8257 + if (host->data->error) {
8258 + DBG("finish request early on error %d\n", host->data->error);
8259 sdhci_finish_data(host);
8260 - else {
8261 - if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
8262 - sdhci_transfer_pio(host);
8263 + } else {
8264 + if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) {
8265 + if (host->flags & SDHCI_REQ_USE_DMA) {
8266 + /* possible only in PLATDMA mode */
8267 + sdhci_platdma_avail(host, &intmask,
8268 + &sdhci_data_end);
8269 + } else
8270 + sdhci_transfer_pio(host, intmask);
8271 + }
8272
8273 /*
8274 * We currently don't do anything fancy with DMA
8275 @@ -2408,18 +2461,8 @@ static void sdhci_data_irq(struct sdhci_
8276 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
8277 }
8278
8279 - if (intmask & SDHCI_INT_DATA_END) {
8280 - if (host->cmd) {
8281 - /*
8282 - * Data managed to finish before the
8283 - * command completed. Make sure we do
8284 - * things in the proper order.
8285 - */
8286 - host->data_early = 1;
8287 - } else {
8288 - sdhci_finish_data(host);
8289 - }
8290 - }
8291 + if (intmask & SDHCI_INT_DATA_END)
8292 + sdhci_data_end(host);
8293 }
8294 }
8295
8296 @@ -2475,6 +2518,22 @@ again:
8297 tasklet_schedule(&host->card_tasklet);
8298 }
8299
8300 + if (intmask & SDHCI_INT_ERROR_MASK & ~SDHCI_INT_ERROR)
8301 + DBG("controller reports error 0x%x -"
8302 + "%s%s%s%s%s%s%s%s%s%s",
8303 + intmask,
8304 + intmask & SDHCI_INT_TIMEOUT? " timeout": "",
8305 + intmask & SDHCI_INT_CRC ? " crc": "",
8306 + intmask & SDHCI_INT_END_BIT? " endbit": "",
8307 + intmask & SDHCI_INT_INDEX? " index": "",
8308 + intmask & SDHCI_INT_DATA_TIMEOUT? " data_timeout": "",
8309 + intmask & SDHCI_INT_DATA_CRC? " data_crc": "",
8310 + intmask & SDHCI_INT_DATA_END_BIT? " data_endbit": "",
8311 + intmask & SDHCI_INT_BUS_POWER? " buspower": "",
8312 + intmask & SDHCI_INT_ACMD12ERR? " acmd12": "",
8313 + intmask & SDHCI_INT_ADMA_ERROR? " adma": ""
8314 + );
8315 +
8316 if (intmask & SDHCI_INT_CMD_MASK) {
8317 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
8318 SDHCI_INT_STATUS);
8319 @@ -2489,7 +2548,13 @@ again:
8320
8321 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
8322
8323 - intmask &= ~SDHCI_INT_ERROR;
8324 + if (intmask & SDHCI_INT_ERROR_MASK) {
8325 + /* collect any uncovered errors */
8326 + sdhci_writel(host, intmask & SDHCI_INT_ERROR_MASK,
8327 + SDHCI_INT_STATUS);
8328 + }
8329 +
8330 + intmask &= ~SDHCI_INT_ERROR_MASK;
8331
8332 if (intmask & SDHCI_INT_BUS_POWER) {
8333 pr_err("%s: Card is consuming too much power!\n",
8334 @@ -2602,7 +2667,8 @@ int sdhci_resume_host(struct sdhci_host
8335 {
8336 int ret = 0;
8337
8338 - if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
8339 + if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA |
8340 + SDHCI_USE_PLATDMA)) {
8341 if (host->ops->enable_dma)
8342 host->ops->enable_dma(host);
8343 }
8344 @@ -2833,14 +2899,16 @@ int sdhci_add_host(struct sdhci_host *ho
8345 host->flags &= ~SDHCI_USE_ADMA;
8346 }
8347
8348 - if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
8349 + if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA |
8350 + SDHCI_USE_PLATDMA)) {
8351 if (host->ops->enable_dma) {
8352 if (host->ops->enable_dma(host)) {
8353 pr_warning("%s: No suitable DMA "
8354 "available. Falling back to PIO.\n",
8355 mmc_hostname(mmc));
8356 host->flags &=
8357 - ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
8358 + ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA |
8359 + SDHCI_USE_PLATDMA);
8360 }
8361 }
8362 }
8363 @@ -3266,6 +3334,7 @@ int sdhci_add_host(struct sdhci_host *ho
8364
8365 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
8366 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
8367 + (host->flags & SDHCI_USE_PLATDMA) ? "platform's DMA" :
8368 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
8369 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
8370
8371 --- a/drivers/mmc/host/sdhci.h
8372 +++ b/drivers/mmc/host/sdhci.h
8373 @@ -290,6 +290,20 @@ struct sdhci_ops {
8374 void (*platform_reset_exit)(struct sdhci_host *host, u8 mask);
8375 int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode);
8376 int (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
8377 +
8378 + int (*pdma_able)(struct sdhci_host *host,
8379 + struct mmc_data *data);
8380 + void (*pdma_avail)(struct sdhci_host *host,
8381 + unsigned int *ref_intmask,
8382 + void(*complete)(struct sdhci_host *));
8383 + void (*pdma_reset)(struct sdhci_host *host,
8384 + struct mmc_data *data);
8385 + unsigned int (*extra_ints)(struct sdhci_host *host);
8386 + unsigned int (*spurious_crc_acmd51)(struct sdhci_host *host);
8387 + unsigned int (*voltage_broken)(struct sdhci_host *host);
8388 + unsigned int (*uhs_broken)(struct sdhci_host *host);
8389 + unsigned int (*missing_status)(struct sdhci_host *host);
8390 +
8391 void (*hw_reset)(struct sdhci_host *host);
8392 void (*platform_suspend)(struct sdhci_host *host);
8393 void (*platform_resume)(struct sdhci_host *host);
8394 @@ -403,6 +417,29 @@ extern int sdhci_resume_host(struct sdhc
8395 extern void sdhci_enable_irq_wakeups(struct sdhci_host *host);
8396 #endif
8397
8398 +static inline int /*bool*/
8399 +sdhci_platdma_dmaable(struct sdhci_host *host, struct mmc_data *data)
8400 +{
8401 + if (host->ops->pdma_able)
8402 + return host->ops->pdma_able(host, data);
8403 + else
8404 + return 1;
8405 +}
8406 +static inline void
8407 +sdhci_platdma_avail(struct sdhci_host *host, unsigned int *ref_intmask,
8408 + void(*completion_callback)(struct sdhci_host *))
8409 +{
8410 + if (host->ops->pdma_avail)
8411 + host->ops->pdma_avail(host, ref_intmask, completion_callback);
8412 +}
8413 +
8414 +static inline void
8415 +sdhci_platdma_reset(struct sdhci_host *host, struct mmc_data *data)
8416 +{
8417 + if (host->ops->pdma_reset)
8418 + host->ops->pdma_reset(host, data);
8419 +}
8420 +
8421 #ifdef CONFIG_PM_RUNTIME
8422 extern int sdhci_runtime_suspend_host(struct sdhci_host *host);
8423 extern int sdhci_runtime_resume_host(struct sdhci_host *host);
8424 --- a/drivers/tty/serial/amba-pl011.c
8425 +++ b/drivers/tty/serial/amba-pl011.c
8426 @@ -84,7 +84,7 @@ struct vendor_data {
8427
8428 static unsigned int get_fifosize_arm(struct amba_device *dev)
8429 {
8430 - return amba_rev(dev) < 3 ? 16 : 32;
8431 + return 16; //TODO: fix: amba_rev(dev) < 3 ? 16 : 32;
8432 }
8433
8434 static struct vendor_data vendor_arm = {
8435 --- a/include/linux/mmc/sdhci.h
8436 +++ b/include/linux/mmc/sdhci.h
8437 @@ -133,6 +133,7 @@ struct sdhci_host {
8438 #define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */
8439 #define SDHCI_SDR104_NEEDS_TUNING (1<<10) /* SDR104/HS200 needs tuning */
8440 #define SDHCI_USING_RETUNING_TIMER (1<<11) /* Host is using a retuning timer for the card */
8441 +#define SDHCI_USE_PLATDMA (1<<12) /* Host uses 3rd party DMA */
8442
8443 unsigned int version; /* SDHCI spec. version */
8444
8445 @@ -148,6 +149,7 @@ struct sdhci_host {
8446
8447 struct mmc_request *mrq; /* Current request */
8448 struct mmc_command *cmd; /* Current command */
8449 + int last_cmdop; /* Opcode of last cmd sent */
8450 struct mmc_data *data; /* Current data request */
8451 unsigned int data_early:1; /* Data finished before cmd */
8452
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