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kernel: refresh patches
[openwrt/openwrt.git] / target / linux / brcm2708 / patches-3.14 / 0017-Add-Chris-Boot-s-i2c-and-spi-drivers.patch
1 From cb4edee665f3f37f21ea84b76404d3ef0ff97515 Mon Sep 17 00:00:00 2001
2 From: popcornmix <popcornmix@gmail.com>
3 Date: Mon, 4 Nov 2013 18:56:10 +0000
4 Subject: [PATCH 17/54] Add Chris Boot's i2c and spi drivers.
5
6 i2c-bcm2708: fixed baudrate
7
8 Fixed issue where the wrong CDIV value was set for baudrates below 3815 Hz (for 250MHz bus clock).
9 In that case the computed CDIV value was more than 0xffff. However the CDIV register width is only 16 bits.
10 This resulted in incorrect setting of CDIV and higher baudrate than intended.
11 Example: 3500Hz -> CDIV=0x11704 -> CDIV(16bit)=0x1704 -> 42430Hz
12 After correction: 3500Hz -> CDIV=0x11704 -> CDIV(16bit)=0xffff -> 3815Hz
13 The correct baudrate is shown in the log after the cdiv > 0xffff correction.
14 ---
15 arch/arm/configs/bcmrpi_cutdown_defconfig | 9 +
16 arch/arm/configs/bcmrpi_defconfig | 6 +
17 arch/arm/mach-bcm2708/Kconfig | 7 +
18 arch/arm/mach-bcm2708/bcm2708.c | 104 ++++-
19 arch/arm/mach-bcm2708/include/mach/platform.h | 3 +
20 drivers/i2c/busses/Kconfig | 19 +
21 drivers/i2c/busses/Makefile | 1 +
22 drivers/i2c/busses/i2c-bcm2708.c | 419 +++++++++++++++++
23 drivers/spi/Kconfig | 8 +
24 drivers/spi/Makefile | 1 +
25 drivers/spi/spi-bcm2708.c | 626 ++++++++++++++++++++++++++
26 11 files changed, 1201 insertions(+), 2 deletions(-)
27 create mode 100644 drivers/i2c/busses/i2c-bcm2708.c
28 create mode 100644 drivers/spi/spi-bcm2708.c
29
30 --- a/arch/arm/configs/bcmrpi_cutdown_defconfig
31 +++ b/arch/arm/configs/bcmrpi_cutdown_defconfig
32 @@ -492,3 +492,12 @@ CONFIG_CRYPTO_DEFLATE=m
33 # CONFIG_CRYPTO_HW is not set
34 CONFIG_CRC_ITU_T=y
35 CONFIG_LIBCRC32C=y
36 +CONFIG_I2C=y
37 +CONFIG_I2C_BOARDINFO=y
38 +CONFIG_I2C_COMPAT=y
39 +CONFIG_I2C_CHARDEV=m
40 +CONFIG_I2C_HELPER_AUTO=y
41 +CONFIG_I2C_BCM2708=m
42 +CONFIG_SPI=y
43 +CONFIG_SPI_MASTER=y
44 +CONFIG_SPI_BCM2708=m
45 --- a/arch/arm/configs/bcmrpi_defconfig
46 +++ b/arch/arm/configs/bcmrpi_defconfig
47 @@ -214,6 +214,12 @@ CONFIG_SERIAL_AMBA_PL011=y
48 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
49 # CONFIG_HW_RANDOM is not set
50 CONFIG_RAW_DRIVER=y
51 +CONFIG_I2C=y
52 +CONFIG_I2C_CHARDEV=m
53 +CONFIG_I2C_BCM2708=m
54 +CONFIG_SPI=y
55 +CONFIG_SPI_BCM2708=m
56 +CONFIG_SPI_SPIDEV=m
57 CONFIG_GPIO_SYSFS=y
58 # CONFIG_HWMON is not set
59 CONFIG_WATCHDOG=y
60 --- a/arch/arm/mach-bcm2708/Kconfig
61 +++ b/arch/arm/mach-bcm2708/Kconfig
62 @@ -31,4 +31,11 @@ config BCM2708_NOL2CACHE
63 help
64 Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt.
65
66 +config BCM2708_SPIDEV
67 + bool "Bind spidev to SPI0 master"
68 + depends on MACH_BCM2708
69 + depends on SPI
70 + default y
71 + help
72 + Binds spidev driver to the SPI0 master
73 endmenu
74 --- a/arch/arm/mach-bcm2708/bcm2708.c
75 +++ b/arch/arm/mach-bcm2708/bcm2708.c
76 @@ -31,6 +31,7 @@
77 #include <linux/cnt32_to_63.h>
78 #include <linux/io.h>
79 #include <linux/module.h>
80 +#include <linux/spi/spi.h>
81
82 #include <linux/version.h>
83 #include <linux/clkdev.h>
84 @@ -205,7 +206,6 @@ static struct clk osc_clk = {
85
86 /* warning - the USB needs a clock > 34MHz */
87
88 -#ifdef CONFIG_MMC_BCM2708
89 static struct clk sdhost_clk = {
90 #ifdef CONFIG_ARCH_BCM2708_CHIPIT
91 .rate = 4000000, /* 4MHz */
92 @@ -213,7 +213,6 @@ static struct clk sdhost_clk = {
93 .rate = 250000000, /* 250MHz */
94 #endif
95 };
96 -#endif
97
98 static struct clk_lookup lookups[] = {
99 { /* UART0 */
100 @@ -223,6 +222,15 @@ static struct clk_lookup lookups[] = {
101 { /* USB */
102 .dev_id = "bcm2708_usb",
103 .clk = &osc_clk,
104 + }, { /* SPI */
105 + .dev_id = "bcm2708_spi.0",
106 + .clk = &sdhost_clk,
107 + }, { /* BSC0 */
108 + .dev_id = "bcm2708_i2c.0",
109 + .clk = &sdhost_clk,
110 + }, { /* BSC1 */
111 + .dev_id = "bcm2708_i2c.1",
112 + .clk = &sdhost_clk,
113 }
114 };
115
116 @@ -483,6 +491,89 @@ static struct platform_device bcm2708_al
117 },
118 };
119
120 +static struct resource bcm2708_spi_resources[] = {
121 + {
122 + .start = SPI0_BASE,
123 + .end = SPI0_BASE + SZ_256 - 1,
124 + .flags = IORESOURCE_MEM,
125 + }, {
126 + .start = IRQ_SPI,
127 + .end = IRQ_SPI,
128 + .flags = IORESOURCE_IRQ,
129 + }
130 +};
131 +
132 +
133 +static u64 bcm2708_spi_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
134 +static struct platform_device bcm2708_spi_device = {
135 + .name = "bcm2708_spi",
136 + .id = 0,
137 + .num_resources = ARRAY_SIZE(bcm2708_spi_resources),
138 + .resource = bcm2708_spi_resources,
139 + .dev = {
140 + .dma_mask = &bcm2708_spi_dmamask,
141 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON)},
142 +};
143 +
144 +#ifdef CONFIG_BCM2708_SPIDEV
145 +static struct spi_board_info bcm2708_spi_devices[] = {
146 +#ifdef CONFIG_SPI_SPIDEV
147 + {
148 + .modalias = "spidev",
149 + .max_speed_hz = 500000,
150 + .bus_num = 0,
151 + .chip_select = 0,
152 + .mode = SPI_MODE_0,
153 + }, {
154 + .modalias = "spidev",
155 + .max_speed_hz = 500000,
156 + .bus_num = 0,
157 + .chip_select = 1,
158 + .mode = SPI_MODE_0,
159 + }
160 +#endif
161 +};
162 +#endif
163 +
164 +static struct resource bcm2708_bsc0_resources[] = {
165 + {
166 + .start = BSC0_BASE,
167 + .end = BSC0_BASE + SZ_256 - 1,
168 + .flags = IORESOURCE_MEM,
169 + }, {
170 + .start = INTERRUPT_I2C,
171 + .end = INTERRUPT_I2C,
172 + .flags = IORESOURCE_IRQ,
173 + }
174 +};
175 +
176 +static struct platform_device bcm2708_bsc0_device = {
177 + .name = "bcm2708_i2c",
178 + .id = 0,
179 + .num_resources = ARRAY_SIZE(bcm2708_bsc0_resources),
180 + .resource = bcm2708_bsc0_resources,
181 +};
182 +
183 +
184 +static struct resource bcm2708_bsc1_resources[] = {
185 + {
186 + .start = BSC1_BASE,
187 + .end = BSC1_BASE + SZ_256 - 1,
188 + .flags = IORESOURCE_MEM,
189 + }, {
190 + .start = INTERRUPT_I2C,
191 + .end = INTERRUPT_I2C,
192 + .flags = IORESOURCE_IRQ,
193 + }
194 +};
195 +
196 +static struct platform_device bcm2708_bsc1_device = {
197 + .name = "bcm2708_i2c",
198 + .id = 1,
199 + .num_resources = ARRAY_SIZE(bcm2708_bsc1_resources),
200 + .resource = bcm2708_bsc1_resources,
201 +};
202 +
203 static struct platform_device bcm2835_hwmon_device = {
204 .name = "bcm2835_hwmon",
205 };
206 @@ -602,6 +693,10 @@ void __init bcm2708_init(void)
207 for (i = 0; i < ARRAY_SIZE(bcm2708_alsa_devices); i++)
208 bcm_register_device(&bcm2708_alsa_devices[i]);
209
210 + bcm_register_device(&bcm2708_spi_device);
211 + bcm_register_device(&bcm2708_bsc0_device);
212 + bcm_register_device(&bcm2708_bsc1_device);
213 +
214 bcm_register_device(&bcm2835_hwmon_device);
215 bcm_register_device(&bcm2835_thermal_device);
216
217 @@ -611,6 +706,11 @@ void __init bcm2708_init(void)
218 }
219 system_rev = boardrev;
220 system_serial_low = serial;
221 +
222 +#ifdef CONFIG_BCM2708_SPIDEV
223 + spi_register_board_info(bcm2708_spi_devices,
224 + ARRAY_SIZE(bcm2708_spi_devices));
225 +#endif
226 }
227
228 static void timer_set_mode(enum clock_event_mode mode,
229 --- a/arch/arm/mach-bcm2708/include/mach/platform.h
230 +++ b/arch/arm/mach-bcm2708/include/mach/platform.h
231 @@ -64,9 +64,12 @@
232 #define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */
233 #define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */
234 #define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */
235 +#define SPI0_BASE (BCM2708_PERI_BASE + 0x204000) /* SPI0 */
236 +#define BSC0_BASE (BCM2708_PERI_BASE + 0x205000) /* BSC0 I2C/TWI */
237 #define UART1_BASE (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */
238 #define EMMC_BASE (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */
239 #define SMI_BASE (BCM2708_PERI_BASE + 0x600000) /* SMI */
240 +#define BSC1_BASE (BCM2708_PERI_BASE + 0x804000) /* BSC1 I2C/TWI */
241 #define USB_BASE (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */
242 #define MCORE_BASE (BCM2708_PERI_BASE + 0x0000) /* Fake frame buffer device (actually the multicore sync block*/
243
244 --- a/drivers/i2c/busses/Kconfig
245 +++ b/drivers/i2c/busses/Kconfig
246 @@ -348,6 +348,25 @@ config I2C_BCM2835
247 This support is also available as a module. If so, the module
248 will be called i2c-bcm2835.
249
250 +config I2C_BCM2708
251 + tristate "BCM2708 BSC"
252 + depends on MACH_BCM2708
253 + help
254 + Enabling this option will add BSC (Broadcom Serial Controller)
255 + support for the BCM2708. BSC is a Broadcom proprietary bus compatible
256 + with I2C/TWI/SMBus.
257 +
258 +config I2C_BCM2708_BAUDRATE
259 + prompt "BCM2708 I2C baudrate"
260 + depends on I2C_BCM2708
261 + int
262 + default 100000
263 + help
264 + Set the I2C baudrate. This will alter the default value. A
265 + different baudrate can be set by using a module parameter as well. If
266 + no parameter is provided when loading, this is the value that will be
267 + used.
268 +
269 config I2C_BCM_KONA
270 tristate "BCM Kona I2C adapter"
271 depends on ARCH_BCM_MOBILE
272 --- a/drivers/i2c/busses/Makefile
273 +++ b/drivers/i2c/busses/Makefile
274 @@ -32,6 +32,7 @@ obj-$(CONFIG_I2C_POWERMAC) += i2c-powerm
275 obj-$(CONFIG_I2C_AT91) += i2c-at91.o
276 obj-$(CONFIG_I2C_AU1550) += i2c-au1550.o
277 obj-$(CONFIG_I2C_BCM2835) += i2c-bcm2835.o
278 +obj-$(CONFIG_I2C_BCM2708) += i2c-bcm2708.o
279 obj-$(CONFIG_I2C_BLACKFIN_TWI) += i2c-bfin-twi.o
280 obj-$(CONFIG_I2C_CBUS_GPIO) += i2c-cbus-gpio.o
281 obj-$(CONFIG_I2C_CPM) += i2c-cpm.o
282 --- /dev/null
283 +++ b/drivers/i2c/busses/i2c-bcm2708.c
284 @@ -0,0 +1,419 @@
285 +/*
286 + * Driver for Broadcom BCM2708 BSC Controllers
287 + *
288 + * Copyright (C) 2012 Chris Boot & Frank Buss
289 + *
290 + * This driver is inspired by:
291 + * i2c-ocores.c, by Peter Korsgaard <jacmet@sunsite.dk>
292 + *
293 + * This program is free software; you can redistribute it and/or modify
294 + * it under the terms of the GNU General Public License as published by
295 + * the Free Software Foundation; either version 2 of the License, or
296 + * (at your option) any later version.
297 + *
298 + * This program is distributed in the hope that it will be useful,
299 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
300 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
301 + * GNU General Public License for more details.
302 + *
303 + * You should have received a copy of the GNU General Public License
304 + * along with this program; if not, write to the Free Software
305 + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
306 + */
307 +
308 +#include <linux/kernel.h>
309 +#include <linux/module.h>
310 +#include <linux/spinlock.h>
311 +#include <linux/clk.h>
312 +#include <linux/err.h>
313 +#include <linux/platform_device.h>
314 +#include <linux/io.h>
315 +#include <linux/slab.h>
316 +#include <linux/i2c.h>
317 +#include <linux/interrupt.h>
318 +#include <linux/sched.h>
319 +#include <linux/wait.h>
320 +
321 +/* BSC register offsets */
322 +#define BSC_C 0x00
323 +#define BSC_S 0x04
324 +#define BSC_DLEN 0x08
325 +#define BSC_A 0x0c
326 +#define BSC_FIFO 0x10
327 +#define BSC_DIV 0x14
328 +#define BSC_DEL 0x18
329 +#define BSC_CLKT 0x1c
330 +
331 +/* Bitfields in BSC_C */
332 +#define BSC_C_I2CEN 0x00008000
333 +#define BSC_C_INTR 0x00000400
334 +#define BSC_C_INTT 0x00000200
335 +#define BSC_C_INTD 0x00000100
336 +#define BSC_C_ST 0x00000080
337 +#define BSC_C_CLEAR_1 0x00000020
338 +#define BSC_C_CLEAR_2 0x00000010
339 +#define BSC_C_READ 0x00000001
340 +
341 +/* Bitfields in BSC_S */
342 +#define BSC_S_CLKT 0x00000200
343 +#define BSC_S_ERR 0x00000100
344 +#define BSC_S_RXF 0x00000080
345 +#define BSC_S_TXE 0x00000040
346 +#define BSC_S_RXD 0x00000020
347 +#define BSC_S_TXD 0x00000010
348 +#define BSC_S_RXR 0x00000008
349 +#define BSC_S_TXW 0x00000004
350 +#define BSC_S_DONE 0x00000002
351 +#define BSC_S_TA 0x00000001
352 +
353 +#define I2C_TIMEOUT_MS 150
354 +
355 +#define DRV_NAME "bcm2708_i2c"
356 +
357 +static unsigned int baudrate = CONFIG_I2C_BCM2708_BAUDRATE;
358 +module_param(baudrate, uint, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP);
359 +MODULE_PARM_DESC(baudrate, "The I2C baudrate");
360 +
361 +
362 +struct bcm2708_i2c {
363 + struct i2c_adapter adapter;
364 +
365 + spinlock_t lock;
366 + void __iomem *base;
367 + int irq;
368 + struct clk *clk;
369 +
370 + struct completion done;
371 +
372 + struct i2c_msg *msg;
373 + int pos;
374 + int nmsgs;
375 + bool error;
376 +};
377 +
378 +/*
379 + * This function sets the ALT mode on the I2C pins so that we can use them with
380 + * the BSC hardware.
381 + *
382 + * FIXME: This is a hack. Use pinmux / pinctrl.
383 + */
384 +static void bcm2708_i2c_init_pinmode(int id)
385 +{
386 +#define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3))
387 +#define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3))
388 +
389 + int pin;
390 + u32 *gpio = ioremap(0x20200000, SZ_16K);
391 +
392 + BUG_ON(id != 0 && id != 1);
393 + /* BSC0 is on GPIO 0 & 1, BSC1 is on GPIO 2 & 3 */
394 + for (pin = id*2+0; pin <= id*2+1; pin++) {
395 +printk("bcm2708_i2c_init_pinmode(%d,%d)\n", id, pin);
396 + INP_GPIO(pin); /* set mode to GPIO input first */
397 + SET_GPIO_ALT(pin, 0); /* set mode to ALT 0 */
398 + }
399 +
400 + iounmap(gpio);
401 +
402 +#undef INP_GPIO
403 +#undef SET_GPIO_ALT
404 +}
405 +
406 +static inline u32 bcm2708_rd(struct bcm2708_i2c *bi, unsigned reg)
407 +{
408 + return readl(bi->base + reg);
409 +}
410 +
411 +static inline void bcm2708_wr(struct bcm2708_i2c *bi, unsigned reg, u32 val)
412 +{
413 + writel(val, bi->base + reg);
414 +}
415 +
416 +static inline void bcm2708_bsc_reset(struct bcm2708_i2c *bi)
417 +{
418 + bcm2708_wr(bi, BSC_C, 0);
419 + bcm2708_wr(bi, BSC_S, BSC_S_CLKT | BSC_S_ERR | BSC_S_DONE);
420 +}
421 +
422 +static inline void bcm2708_bsc_fifo_drain(struct bcm2708_i2c *bi)
423 +{
424 + while ((bcm2708_rd(bi, BSC_S) & BSC_S_RXD) && (bi->pos < bi->msg->len))
425 + bi->msg->buf[bi->pos++] = bcm2708_rd(bi, BSC_FIFO);
426 +}
427 +
428 +static inline void bcm2708_bsc_fifo_fill(struct bcm2708_i2c *bi)
429 +{
430 + while ((bcm2708_rd(bi, BSC_S) & BSC_S_TXD) && (bi->pos < bi->msg->len))
431 + bcm2708_wr(bi, BSC_FIFO, bi->msg->buf[bi->pos++]);
432 +}
433 +
434 +static inline void bcm2708_bsc_setup(struct bcm2708_i2c *bi)
435 +{
436 + unsigned long bus_hz;
437 + u32 cdiv;
438 + u32 c = BSC_C_I2CEN | BSC_C_INTD | BSC_C_ST | BSC_C_CLEAR_1;
439 +
440 + bus_hz = clk_get_rate(bi->clk);
441 + cdiv = bus_hz / baudrate;
442 + if (cdiv > 0xffff)
443 + cdiv = 0xffff;
444 +
445 + if (bi->msg->flags & I2C_M_RD)
446 + c |= BSC_C_INTR | BSC_C_READ;
447 + else
448 + c |= BSC_C_INTT;
449 +
450 + bcm2708_wr(bi, BSC_DIV, cdiv);
451 + bcm2708_wr(bi, BSC_A, bi->msg->addr);
452 + bcm2708_wr(bi, BSC_DLEN, bi->msg->len);
453 + bcm2708_wr(bi, BSC_C, c);
454 +}
455 +
456 +static irqreturn_t bcm2708_i2c_interrupt(int irq, void *dev_id)
457 +{
458 + struct bcm2708_i2c *bi = dev_id;
459 + bool handled = true;
460 + u32 s;
461 +
462 + spin_lock(&bi->lock);
463 +
464 + /* we may see camera interrupts on the "other" I2C channel
465 + Just return if we've not sent anything */
466 + if (!bi->nmsgs || !bi->msg )
467 + goto early_exit;
468 +
469 + s = bcm2708_rd(bi, BSC_S);
470 +
471 + if (s & (BSC_S_CLKT | BSC_S_ERR)) {
472 + bcm2708_bsc_reset(bi);
473 + bi->error = true;
474 +
475 + /* wake up our bh */
476 + complete(&bi->done);
477 + } else if (s & BSC_S_DONE) {
478 + bi->nmsgs--;
479 +
480 + if (bi->msg->flags & I2C_M_RD)
481 + bcm2708_bsc_fifo_drain(bi);
482 +
483 + bcm2708_bsc_reset(bi);
484 +
485 + if (bi->nmsgs) {
486 + /* advance to next message */
487 + bi->msg++;
488 + bi->pos = 0;
489 + bcm2708_bsc_setup(bi);
490 + } else {
491 + /* wake up our bh */
492 + complete(&bi->done);
493 + }
494 + } else if (s & BSC_S_TXW) {
495 + bcm2708_bsc_fifo_fill(bi);
496 + } else if (s & BSC_S_RXR) {
497 + bcm2708_bsc_fifo_drain(bi);
498 + } else {
499 + handled = false;
500 + }
501 +
502 +early_exit:
503 + spin_unlock(&bi->lock);
504 +
505 + return handled ? IRQ_HANDLED : IRQ_NONE;
506 +}
507 +
508 +static int bcm2708_i2c_master_xfer(struct i2c_adapter *adap,
509 + struct i2c_msg *msgs, int num)
510 +{
511 + struct bcm2708_i2c *bi = adap->algo_data;
512 + unsigned long flags;
513 + int ret;
514 +
515 + spin_lock_irqsave(&bi->lock, flags);
516 +
517 + reinit_completion(&bi->done);
518 + bi->msg = msgs;
519 + bi->pos = 0;
520 + bi->nmsgs = num;
521 + bi->error = false;
522 +
523 + spin_unlock_irqrestore(&bi->lock, flags);
524 +
525 + bcm2708_bsc_setup(bi);
526 +
527 + ret = wait_for_completion_timeout(&bi->done,
528 + msecs_to_jiffies(I2C_TIMEOUT_MS));
529 + if (ret == 0) {
530 + dev_err(&adap->dev, "transfer timed out\n");
531 + spin_lock_irqsave(&bi->lock, flags);
532 + bcm2708_bsc_reset(bi);
533 + spin_unlock_irqrestore(&bi->lock, flags);
534 + return -ETIMEDOUT;
535 + }
536 +
537 + return bi->error ? -EIO : num;
538 +}
539 +
540 +static u32 bcm2708_i2c_functionality(struct i2c_adapter *adap)
541 +{
542 + return I2C_FUNC_I2C | /*I2C_FUNC_10BIT_ADDR |*/ I2C_FUNC_SMBUS_EMUL;
543 +}
544 +
545 +static struct i2c_algorithm bcm2708_i2c_algorithm = {
546 + .master_xfer = bcm2708_i2c_master_xfer,
547 + .functionality = bcm2708_i2c_functionality,
548 +};
549 +
550 +static int bcm2708_i2c_probe(struct platform_device *pdev)
551 +{
552 + struct resource *regs;
553 + int irq, err = -ENOMEM;
554 + struct clk *clk;
555 + struct bcm2708_i2c *bi;
556 + struct i2c_adapter *adap;
557 + unsigned long bus_hz;
558 + u32 cdiv;
559 +
560 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
561 + if (!regs) {
562 + dev_err(&pdev->dev, "could not get IO memory\n");
563 + return -ENXIO;
564 + }
565 +
566 + irq = platform_get_irq(pdev, 0);
567 + if (irq < 0) {
568 + dev_err(&pdev->dev, "could not get IRQ\n");
569 + return irq;
570 + }
571 +
572 + clk = clk_get(&pdev->dev, NULL);
573 + if (IS_ERR(clk)) {
574 + dev_err(&pdev->dev, "could not find clk: %ld\n", PTR_ERR(clk));
575 + return PTR_ERR(clk);
576 + }
577 +
578 + bcm2708_i2c_init_pinmode(pdev->id);
579 +
580 + bi = kzalloc(sizeof(*bi), GFP_KERNEL);
581 + if (!bi)
582 + goto out_clk_put;
583 +
584 + platform_set_drvdata(pdev, bi);
585 +
586 + adap = &bi->adapter;
587 + adap->class = I2C_CLASS_HWMON | I2C_CLASS_DDC;
588 + adap->algo = &bcm2708_i2c_algorithm;
589 + adap->algo_data = bi;
590 + adap->dev.parent = &pdev->dev;
591 + adap->nr = pdev->id;
592 + strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));
593 +
594 + switch (pdev->id) {
595 + case 0:
596 + adap->class = I2C_CLASS_HWMON;
597 + break;
598 + case 1:
599 + adap->class = I2C_CLASS_DDC;
600 + break;
601 + default:
602 + dev_err(&pdev->dev, "can only bind to BSC 0 or 1\n");
603 + err = -ENXIO;
604 + goto out_free_bi;
605 + }
606 +
607 + spin_lock_init(&bi->lock);
608 + init_completion(&bi->done);
609 +
610 + bi->base = ioremap(regs->start, resource_size(regs));
611 + if (!bi->base) {
612 + dev_err(&pdev->dev, "could not remap memory\n");
613 + goto out_free_bi;
614 + }
615 +
616 + bi->irq = irq;
617 + bi->clk = clk;
618 +
619 + err = request_irq(irq, bcm2708_i2c_interrupt, IRQF_SHARED,
620 + dev_name(&pdev->dev), bi);
621 + if (err) {
622 + dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
623 + goto out_iounmap;
624 + }
625 +
626 + bcm2708_bsc_reset(bi);
627 +
628 + err = i2c_add_numbered_adapter(adap);
629 + if (err < 0) {
630 + dev_err(&pdev->dev, "could not add I2C adapter: %d\n", err);
631 + goto out_free_irq;
632 + }
633 +
634 + bus_hz = clk_get_rate(bi->clk);
635 + cdiv = bus_hz / baudrate;
636 + if (cdiv > 0xffff) {
637 + cdiv = 0xffff;
638 + baudrate = bus_hz / cdiv;
639 + }
640 +
641 + dev_info(&pdev->dev, "BSC%d Controller at 0x%08lx (irq %d) (baudrate %d)\n",
642 + pdev->id, (unsigned long)regs->start, irq, baudrate);
643 +
644 + return 0;
645 +
646 +out_free_irq:
647 + free_irq(bi->irq, bi);
648 +out_iounmap:
649 + iounmap(bi->base);
650 +out_free_bi:
651 + kfree(bi);
652 +out_clk_put:
653 + clk_put(clk);
654 + return err;
655 +}
656 +
657 +static int bcm2708_i2c_remove(struct platform_device *pdev)
658 +{
659 + struct bcm2708_i2c *bi = platform_get_drvdata(pdev);
660 +
661 + platform_set_drvdata(pdev, NULL);
662 +
663 + i2c_del_adapter(&bi->adapter);
664 + free_irq(bi->irq, bi);
665 + iounmap(bi->base);
666 + clk_disable(bi->clk);
667 + clk_put(bi->clk);
668 + kfree(bi);
669 +
670 + return 0;
671 +}
672 +
673 +static struct platform_driver bcm2708_i2c_driver = {
674 + .driver = {
675 + .name = DRV_NAME,
676 + .owner = THIS_MODULE,
677 + },
678 + .probe = bcm2708_i2c_probe,
679 + .remove = bcm2708_i2c_remove,
680 +};
681 +
682 +// module_platform_driver(bcm2708_i2c_driver);
683 +
684 +
685 +static int __init bcm2708_i2c_init(void)
686 +{
687 + return platform_driver_register(&bcm2708_i2c_driver);
688 +}
689 +
690 +static void __exit bcm2708_i2c_exit(void)
691 +{
692 + platform_driver_unregister(&bcm2708_i2c_driver);
693 +}
694 +
695 +module_init(bcm2708_i2c_init);
696 +module_exit(bcm2708_i2c_exit);
697 +
698 +
699 +
700 +MODULE_DESCRIPTION("BSC controller driver for Broadcom BCM2708");
701 +MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
702 +MODULE_LICENSE("GPL v2");
703 +MODULE_ALIAS("platform:" DRV_NAME);
704 --- a/drivers/spi/Kconfig
705 +++ b/drivers/spi/Kconfig
706 @@ -85,6 +85,14 @@ config SPI_BCM2835
707 is for the regular SPI controller. Slave mode operation is not also
708 not supported.
709
710 +config SPI_BCM2708
711 + tristate "BCM2708 SPI controller driver (SPI0)"
712 + depends on MACH_BCM2708
713 + help
714 + This selects a driver for the Broadcom BCM2708 SPI master (SPI0). This
715 + driver is not compatible with the "Universal SPI Master" or the SPI slave
716 + device.
717 +
718 config SPI_BFIN5XX
719 tristate "SPI controller driver for ADI Blackfin5xx"
720 depends on BLACKFIN && !BF60x
721 --- a/drivers/spi/Makefile
722 +++ b/drivers/spi/Makefile
723 @@ -19,6 +19,7 @@ obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63x
724 obj-$(CONFIG_SPI_BCM63XX_HSSPI) += spi-bcm63xx-hsspi.o
725 obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o
726 obj-$(CONFIG_SPI_BFIN_V3) += spi-bfin-v3.o
727 +obj-$(CONFIG_SPI_BCM2708) += spi-bcm2708.o
728 obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o
729 obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o
730 obj-$(CONFIG_SPI_BUTTERFLY) += spi-butterfly.o
731 --- /dev/null
732 +++ b/drivers/spi/spi-bcm2708.c
733 @@ -0,0 +1,626 @@
734 +/*
735 + * Driver for Broadcom BCM2708 SPI Controllers
736 + *
737 + * Copyright (C) 2012 Chris Boot
738 + *
739 + * This driver is inspired by:
740 + * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
741 + * spi-atmel.c, Copyright (C) 2006 Atmel Corporation
742 + *
743 + * This program is free software; you can redistribute it and/or modify
744 + * it under the terms of the GNU General Public License as published by
745 + * the Free Software Foundation; either version 2 of the License, or
746 + * (at your option) any later version.
747 + *
748 + * This program is distributed in the hope that it will be useful,
749 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
750 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
751 + * GNU General Public License for more details.
752 + *
753 + * You should have received a copy of the GNU General Public License
754 + * along with this program; if not, write to the Free Software
755 + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
756 + */
757 +
758 +#include <linux/kernel.h>
759 +#include <linux/module.h>
760 +#include <linux/spinlock.h>
761 +#include <linux/clk.h>
762 +#include <linux/err.h>
763 +#include <linux/platform_device.h>
764 +#include <linux/io.h>
765 +#include <linux/spi/spi.h>
766 +#include <linux/interrupt.h>
767 +#include <linux/delay.h>
768 +#include <linux/log2.h>
769 +#include <linux/sched.h>
770 +#include <linux/wait.h>
771 +
772 +/* SPI register offsets */
773 +#define SPI_CS 0x00
774 +#define SPI_FIFO 0x04
775 +#define SPI_CLK 0x08
776 +#define SPI_DLEN 0x0c
777 +#define SPI_LTOH 0x10
778 +#define SPI_DC 0x14
779 +
780 +/* Bitfields in CS */
781 +#define SPI_CS_LEN_LONG 0x02000000
782 +#define SPI_CS_DMA_LEN 0x01000000
783 +#define SPI_CS_CSPOL2 0x00800000
784 +#define SPI_CS_CSPOL1 0x00400000
785 +#define SPI_CS_CSPOL0 0x00200000
786 +#define SPI_CS_RXF 0x00100000
787 +#define SPI_CS_RXR 0x00080000
788 +#define SPI_CS_TXD 0x00040000
789 +#define SPI_CS_RXD 0x00020000
790 +#define SPI_CS_DONE 0x00010000
791 +#define SPI_CS_LEN 0x00002000
792 +#define SPI_CS_REN 0x00001000
793 +#define SPI_CS_ADCS 0x00000800
794 +#define SPI_CS_INTR 0x00000400
795 +#define SPI_CS_INTD 0x00000200
796 +#define SPI_CS_DMAEN 0x00000100
797 +#define SPI_CS_TA 0x00000080
798 +#define SPI_CS_CSPOL 0x00000040
799 +#define SPI_CS_CLEAR_RX 0x00000020
800 +#define SPI_CS_CLEAR_TX 0x00000010
801 +#define SPI_CS_CPOL 0x00000008
802 +#define SPI_CS_CPHA 0x00000004
803 +#define SPI_CS_CS_10 0x00000002
804 +#define SPI_CS_CS_01 0x00000001
805 +
806 +#define SPI_TIMEOUT_MS 150
807 +
808 +#define DRV_NAME "bcm2708_spi"
809 +
810 +struct bcm2708_spi {
811 + spinlock_t lock;
812 + void __iomem *base;
813 + int irq;
814 + struct clk *clk;
815 + bool stopping;
816 +
817 + struct list_head queue;
818 + struct workqueue_struct *workq;
819 + struct work_struct work;
820 + struct completion done;
821 +
822 + const u8 *tx_buf;
823 + u8 *rx_buf;
824 + int len;
825 +};
826 +
827 +struct bcm2708_spi_state {
828 + u32 cs;
829 + u16 cdiv;
830 +};
831 +
832 +/*
833 + * This function sets the ALT mode on the SPI pins so that we can use them with
834 + * the SPI hardware.
835 + *
836 + * FIXME: This is a hack. Use pinmux / pinctrl.
837 + */
838 +static void bcm2708_init_pinmode(void)
839 +{
840 +#define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3))
841 +#define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3))
842 +
843 + int pin;
844 + u32 *gpio = ioremap(0x20200000, SZ_16K);
845 +
846 + /* SPI is on GPIO 7..11 */
847 + for (pin = 7; pin <= 11; pin++) {
848 + INP_GPIO(pin); /* set mode to GPIO input first */
849 + SET_GPIO_ALT(pin, 0); /* set mode to ALT 0 */
850 + }
851 +
852 + iounmap(gpio);
853 +
854 +#undef INP_GPIO
855 +#undef SET_GPIO_ALT
856 +}
857 +
858 +static inline u32 bcm2708_rd(struct bcm2708_spi *bs, unsigned reg)
859 +{
860 + return readl(bs->base + reg);
861 +}
862 +
863 +static inline void bcm2708_wr(struct bcm2708_spi *bs, unsigned reg, u32 val)
864 +{
865 + writel(val, bs->base + reg);
866 +}
867 +
868 +static inline void bcm2708_rd_fifo(struct bcm2708_spi *bs, int len)
869 +{
870 + u8 byte;
871 +
872 + while (len--) {
873 + byte = bcm2708_rd(bs, SPI_FIFO);
874 + if (bs->rx_buf)
875 + *bs->rx_buf++ = byte;
876 + }
877 +}
878 +
879 +static inline void bcm2708_wr_fifo(struct bcm2708_spi *bs, int len)
880 +{
881 + u8 byte;
882 + u16 val;
883 +
884 + if (len > bs->len)
885 + len = bs->len;
886 +
887 + if (unlikely(bcm2708_rd(bs, SPI_CS) & SPI_CS_LEN)) {
888 + /* LoSSI mode */
889 + if (unlikely(len % 2)) {
890 + printk(KERN_ERR"bcm2708_wr_fifo: length must be even, skipping.\n");
891 + bs->len = 0;
892 + return;
893 + }
894 + while (len) {
895 + if (bs->tx_buf) {
896 + val = *(const u16 *)bs->tx_buf;
897 + bs->tx_buf += 2;
898 + } else
899 + val = 0;
900 + bcm2708_wr(bs, SPI_FIFO, val);
901 + bs->len -= 2;
902 + len -= 2;
903 + }
904 + return;
905 + }
906 +
907 + while (len--) {
908 + byte = bs->tx_buf ? *bs->tx_buf++ : 0;
909 + bcm2708_wr(bs, SPI_FIFO, byte);
910 + bs->len--;
911 + }
912 +}
913 +
914 +static irqreturn_t bcm2708_spi_interrupt(int irq, void *dev_id)
915 +{
916 + struct spi_master *master = dev_id;
917 + struct bcm2708_spi *bs = spi_master_get_devdata(master);
918 + u32 cs;
919 +
920 + spin_lock(&bs->lock);
921 +
922 + cs = bcm2708_rd(bs, SPI_CS);
923 +
924 + if (cs & SPI_CS_DONE) {
925 + if (bs->len) { /* first interrupt in a transfer */
926 + /* fill the TX fifo with up to 16 bytes */
927 + bcm2708_wr_fifo(bs, 16);
928 + } else { /* transfer complete */
929 + /* disable interrupts */
930 + cs &= ~(SPI_CS_INTR | SPI_CS_INTD);
931 + bcm2708_wr(bs, SPI_CS, cs);
932 +
933 + /* drain RX FIFO */
934 + while (cs & SPI_CS_RXD) {
935 + bcm2708_rd_fifo(bs, 1);
936 + cs = bcm2708_rd(bs, SPI_CS);
937 + }
938 +
939 + /* wake up our bh */
940 + complete(&bs->done);
941 + }
942 + } else if (cs & SPI_CS_RXR) {
943 + /* read 12 bytes of data */
944 + bcm2708_rd_fifo(bs, 12);
945 +
946 + /* write up to 12 bytes */
947 + bcm2708_wr_fifo(bs, 12);
948 + }
949 +
950 + spin_unlock(&bs->lock);
951 +
952 + return IRQ_HANDLED;
953 +}
954 +
955 +static int bcm2708_setup_state(struct spi_master *master,
956 + struct device *dev, struct bcm2708_spi_state *state,
957 + u32 hz, u8 csel, u8 mode, u8 bpw)
958 +{
959 + struct bcm2708_spi *bs = spi_master_get_devdata(master);
960 + int cdiv;
961 + unsigned long bus_hz;
962 + u32 cs = 0;
963 +
964 + bus_hz = clk_get_rate(bs->clk);
965 +
966 + if (hz >= bus_hz) {
967 + cdiv = 2; /* bus_hz / 2 is as fast as we can go */
968 + } else if (hz) {
969 + cdiv = DIV_ROUND_UP(bus_hz, hz);
970 +
971 + /* CDIV must be a power of 2, so round up */
972 + cdiv = roundup_pow_of_two(cdiv);
973 +
974 + if (cdiv > 65536) {
975 + dev_dbg(dev,
976 + "setup: %d Hz too slow, cdiv %u; min %ld Hz\n",
977 + hz, cdiv, bus_hz / 65536);
978 + return -EINVAL;
979 + } else if (cdiv == 65536) {
980 + cdiv = 0;
981 + } else if (cdiv == 1) {
982 + cdiv = 2; /* 1 gets rounded down to 0; == 65536 */
983 + }
984 + } else {
985 + cdiv = 0;
986 + }
987 +
988 + switch (bpw) {
989 + case 8:
990 + break;
991 + case 9:
992 + /* Reading in LoSSI mode is a special case. See 'BCM2835 ARM Peripherals' datasheet */
993 + cs |= SPI_CS_LEN;
994 + break;
995 + default:
996 + dev_dbg(dev, "setup: invalid bits_per_word %u (must be 8 or 9)\n",
997 + bpw);
998 + return -EINVAL;
999 + }
1000 +
1001 + if (mode & SPI_CPOL)
1002 + cs |= SPI_CS_CPOL;
1003 + if (mode & SPI_CPHA)
1004 + cs |= SPI_CS_CPHA;
1005 +
1006 + if (!(mode & SPI_NO_CS)) {
1007 + if (mode & SPI_CS_HIGH) {
1008 + cs |= SPI_CS_CSPOL;
1009 + cs |= SPI_CS_CSPOL0 << csel;
1010 + }
1011 +
1012 + cs |= csel;
1013 + } else {
1014 + cs |= SPI_CS_CS_10 | SPI_CS_CS_01;
1015 + }
1016 +
1017 + if (state) {
1018 + state->cs = cs;
1019 + state->cdiv = cdiv;
1020 + dev_dbg(dev, "setup: want %d Hz; "
1021 + "bus_hz=%lu / cdiv=%u == %lu Hz; "
1022 + "mode %u: cs 0x%08X\n",
1023 + hz, bus_hz, cdiv, bus_hz/cdiv, mode, cs);
1024 + }
1025 +
1026 + return 0;
1027 +}
1028 +
1029 +static int bcm2708_process_transfer(struct bcm2708_spi *bs,
1030 + struct spi_message *msg, struct spi_transfer *xfer)
1031 +{
1032 + struct spi_device *spi = msg->spi;
1033 + struct bcm2708_spi_state state, *stp;
1034 + int ret;
1035 + u32 cs;
1036 +
1037 + if (bs->stopping)
1038 + return -ESHUTDOWN;
1039 +
1040 + if (xfer->bits_per_word || xfer->speed_hz) {
1041 + ret = bcm2708_setup_state(spi->master, &spi->dev, &state,
1042 + xfer->speed_hz ? xfer->speed_hz : spi->max_speed_hz,
1043 + spi->chip_select, spi->mode,
1044 + xfer->bits_per_word ? xfer->bits_per_word :
1045 + spi->bits_per_word);
1046 + if (ret)
1047 + return ret;
1048 +
1049 + stp = &state;
1050 + } else {
1051 + stp = spi->controller_state;
1052 + }
1053 +
1054 + reinit_completion(&bs->done);
1055 + bs->tx_buf = xfer->tx_buf;
1056 + bs->rx_buf = xfer->rx_buf;
1057 + bs->len = xfer->len;
1058 +
1059 + cs = stp->cs | SPI_CS_INTR | SPI_CS_INTD | SPI_CS_TA;
1060 +
1061 + bcm2708_wr(bs, SPI_CLK, stp->cdiv);
1062 + bcm2708_wr(bs, SPI_CS, cs);
1063 +
1064 + ret = wait_for_completion_timeout(&bs->done,
1065 + msecs_to_jiffies(SPI_TIMEOUT_MS));
1066 + if (ret == 0) {
1067 + dev_err(&spi->dev, "transfer timed out\n");
1068 + return -ETIMEDOUT;
1069 + }
1070 +
1071 + if (xfer->delay_usecs)
1072 + udelay(xfer->delay_usecs);
1073 +
1074 + if (list_is_last(&xfer->transfer_list, &msg->transfers) ||
1075 + xfer->cs_change) {
1076 + /* clear TA and interrupt flags */
1077 + bcm2708_wr(bs, SPI_CS, stp->cs);
1078 + }
1079 +
1080 + msg->actual_length += (xfer->len - bs->len);
1081 +
1082 + return 0;
1083 +}
1084 +
1085 +static void bcm2708_work(struct work_struct *work)
1086 +{
1087 + struct bcm2708_spi *bs = container_of(work, struct bcm2708_spi, work);
1088 + unsigned long flags;
1089 + struct spi_message *msg;
1090 + struct spi_transfer *xfer;
1091 + int status = 0;
1092 +
1093 + spin_lock_irqsave(&bs->lock, flags);
1094 + while (!list_empty(&bs->queue)) {
1095 + msg = list_first_entry(&bs->queue, struct spi_message, queue);
1096 + list_del_init(&msg->queue);
1097 + spin_unlock_irqrestore(&bs->lock, flags);
1098 +
1099 + list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1100 + status = bcm2708_process_transfer(bs, msg, xfer);
1101 + if (status)
1102 + break;
1103 + }
1104 +
1105 + msg->status = status;
1106 + msg->complete(msg->context);
1107 +
1108 + spin_lock_irqsave(&bs->lock, flags);
1109 + }
1110 + spin_unlock_irqrestore(&bs->lock, flags);
1111 +}
1112 +
1113 +static int bcm2708_spi_setup(struct spi_device *spi)
1114 +{
1115 + struct bcm2708_spi *bs = spi_master_get_devdata(spi->master);
1116 + struct bcm2708_spi_state *state;
1117 + int ret;
1118 +
1119 + if (bs->stopping)
1120 + return -ESHUTDOWN;
1121 +
1122 + if (!(spi->mode & SPI_NO_CS) &&
1123 + (spi->chip_select > spi->master->num_chipselect)) {
1124 + dev_dbg(&spi->dev,
1125 + "setup: invalid chipselect %u (%u defined)\n",
1126 + spi->chip_select, spi->master->num_chipselect);
1127 + return -EINVAL;
1128 + }
1129 +
1130 + state = spi->controller_state;
1131 + if (!state) {
1132 + state = kzalloc(sizeof(*state), GFP_KERNEL);
1133 + if (!state)
1134 + return -ENOMEM;
1135 +
1136 + spi->controller_state = state;
1137 + }
1138 +
1139 + ret = bcm2708_setup_state(spi->master, &spi->dev, state,
1140 + spi->max_speed_hz, spi->chip_select, spi->mode,
1141 + spi->bits_per_word);
1142 + if (ret < 0) {
1143 + kfree(state);
1144 + spi->controller_state = NULL;
1145 + return ret;
1146 + }
1147 +
1148 + dev_dbg(&spi->dev,
1149 + "setup: cd %d: %d Hz, bpw %u, mode 0x%x -> CS=%08x CDIV=%04x\n",
1150 + spi->chip_select, spi->max_speed_hz, spi->bits_per_word,
1151 + spi->mode, state->cs, state->cdiv);
1152 +
1153 + return 0;
1154 +}
1155 +
1156 +static int bcm2708_spi_transfer(struct spi_device *spi, struct spi_message *msg)
1157 +{
1158 + struct bcm2708_spi *bs = spi_master_get_devdata(spi->master);
1159 + struct spi_transfer *xfer;
1160 + int ret;
1161 + unsigned long flags;
1162 +
1163 + if (unlikely(list_empty(&msg->transfers)))
1164 + return -EINVAL;
1165 +
1166 + if (bs->stopping)
1167 + return -ESHUTDOWN;
1168 +
1169 + list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1170 + if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
1171 + dev_dbg(&spi->dev, "missing rx or tx buf\n");
1172 + return -EINVAL;
1173 + }
1174 +
1175 + if (!xfer->bits_per_word || xfer->speed_hz)
1176 + continue;
1177 +
1178 + ret = bcm2708_setup_state(spi->master, &spi->dev, NULL,
1179 + xfer->speed_hz ? xfer->speed_hz : spi->max_speed_hz,
1180 + spi->chip_select, spi->mode,
1181 + xfer->bits_per_word ? xfer->bits_per_word :
1182 + spi->bits_per_word);
1183 + if (ret)
1184 + return ret;
1185 + }
1186 +
1187 + msg->status = -EINPROGRESS;
1188 + msg->actual_length = 0;
1189 +
1190 + spin_lock_irqsave(&bs->lock, flags);
1191 + list_add_tail(&msg->queue, &bs->queue);
1192 + queue_work(bs->workq, &bs->work);
1193 + spin_unlock_irqrestore(&bs->lock, flags);
1194 +
1195 + return 0;
1196 +}
1197 +
1198 +static void bcm2708_spi_cleanup(struct spi_device *spi)
1199 +{
1200 + if (spi->controller_state) {
1201 + kfree(spi->controller_state);
1202 + spi->controller_state = NULL;
1203 + }
1204 +}
1205 +
1206 +static int bcm2708_spi_probe(struct platform_device *pdev)
1207 +{
1208 + struct resource *regs;
1209 + int irq, err = -ENOMEM;
1210 + struct clk *clk;
1211 + struct spi_master *master;
1212 + struct bcm2708_spi *bs;
1213 +
1214 + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1215 + if (!regs) {
1216 + dev_err(&pdev->dev, "could not get IO memory\n");
1217 + return -ENXIO;
1218 + }
1219 +
1220 + irq = platform_get_irq(pdev, 0);
1221 + if (irq < 0) {
1222 + dev_err(&pdev->dev, "could not get IRQ\n");
1223 + return irq;
1224 + }
1225 +
1226 + clk = clk_get(&pdev->dev, NULL);
1227 + if (IS_ERR(clk)) {
1228 + dev_err(&pdev->dev, "could not find clk: %ld\n", PTR_ERR(clk));
1229 + return PTR_ERR(clk);
1230 + }
1231 +
1232 + bcm2708_init_pinmode();
1233 +
1234 + master = spi_alloc_master(&pdev->dev, sizeof(*bs));
1235 + if (!master) {
1236 + dev_err(&pdev->dev, "spi_alloc_master() failed\n");
1237 + goto out_clk_put;
1238 + }
1239 +
1240 + /* the spi->mode bits understood by this driver: */
1241 + master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_NO_CS;
1242 +
1243 + master->bus_num = pdev->id;
1244 + master->num_chipselect = 3;
1245 + master->setup = bcm2708_spi_setup;
1246 + master->transfer = bcm2708_spi_transfer;
1247 + master->cleanup = bcm2708_spi_cleanup;
1248 + platform_set_drvdata(pdev, master);
1249 +
1250 + bs = spi_master_get_devdata(master);
1251 +
1252 + spin_lock_init(&bs->lock);
1253 + INIT_LIST_HEAD(&bs->queue);
1254 + init_completion(&bs->done);
1255 + INIT_WORK(&bs->work, bcm2708_work);
1256 +
1257 + bs->base = ioremap(regs->start, resource_size(regs));
1258 + if (!bs->base) {
1259 + dev_err(&pdev->dev, "could not remap memory\n");
1260 + goto out_master_put;
1261 + }
1262 +
1263 + bs->workq = create_singlethread_workqueue(dev_name(&pdev->dev));
1264 + if (!bs->workq) {
1265 + dev_err(&pdev->dev, "could not create workqueue\n");
1266 + goto out_iounmap;
1267 + }
1268 +
1269 + bs->irq = irq;
1270 + bs->clk = clk;
1271 + bs->stopping = false;
1272 +
1273 + err = request_irq(irq, bcm2708_spi_interrupt, 0, dev_name(&pdev->dev),
1274 + master);
1275 + if (err) {
1276 + dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
1277 + goto out_workqueue;
1278 + }
1279 +
1280 + /* initialise the hardware */
1281 + clk_enable(clk);
1282 + bcm2708_wr(bs, SPI_CS, SPI_CS_REN | SPI_CS_CLEAR_RX | SPI_CS_CLEAR_TX);
1283 +
1284 + err = spi_register_master(master);
1285 + if (err) {
1286 + dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
1287 + goto out_free_irq;
1288 + }
1289 +
1290 + dev_info(&pdev->dev, "SPI Controller at 0x%08lx (irq %d)\n",
1291 + (unsigned long)regs->start, irq);
1292 +
1293 + return 0;
1294 +
1295 +out_free_irq:
1296 + free_irq(bs->irq, master);
1297 +out_workqueue:
1298 + destroy_workqueue(bs->workq);
1299 +out_iounmap:
1300 + iounmap(bs->base);
1301 +out_master_put:
1302 + spi_master_put(master);
1303 +out_clk_put:
1304 + clk_put(clk);
1305 + return err;
1306 +}
1307 +
1308 +static int bcm2708_spi_remove(struct platform_device *pdev)
1309 +{
1310 + struct spi_master *master = platform_get_drvdata(pdev);
1311 + struct bcm2708_spi *bs = spi_master_get_devdata(master);
1312 +
1313 + /* reset the hardware and block queue progress */
1314 + spin_lock_irq(&bs->lock);
1315 + bs->stopping = true;
1316 + bcm2708_wr(bs, SPI_CS, SPI_CS_CLEAR_RX | SPI_CS_CLEAR_TX);
1317 + spin_unlock_irq(&bs->lock);
1318 +
1319 + flush_work_sync(&bs->work);
1320 +
1321 + clk_disable(bs->clk);
1322 + clk_put(bs->clk);
1323 + free_irq(bs->irq, master);
1324 + iounmap(bs->base);
1325 +
1326 + spi_unregister_master(master);
1327 +
1328 + return 0;
1329 +}
1330 +
1331 +static struct platform_driver bcm2708_spi_driver = {
1332 + .driver = {
1333 + .name = DRV_NAME,
1334 + .owner = THIS_MODULE,
1335 + },
1336 + .probe = bcm2708_spi_probe,
1337 + .remove = bcm2708_spi_remove,
1338 +};
1339 +
1340 +
1341 +static int __init bcm2708_spi_init(void)
1342 +{
1343 + return platform_driver_probe(&bcm2708_spi_driver, bcm2708_spi_probe);
1344 +}
1345 +module_init(bcm2708_spi_init);
1346 +
1347 +static void __exit bcm2708_spi_exit(void)
1348 +{
1349 + platform_driver_unregister(&bcm2708_spi_driver);
1350 +}
1351 +module_exit(bcm2708_spi_exit);
1352 +
1353 +
1354 +//module_platform_driver(bcm2708_spi_driver);
1355 +
1356 +MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2708");
1357 +MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
1358 +MODULE_LICENSE("GPL v2");
1359 +MODULE_ALIAS("platform:" DRV_NAME);
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