target/linux/brcm2708/patches-3.14/0033-dmaengine-Add-support-for-BCM2708.patch

   1 From 568b7292b8e7e1fe3d852db8b463d989d06b5adf Mon Sep 17 00:00:00 2001
   2 From: Florian Meier <florian.meier@koalo.de>
   3 Date: Fri, 22 Nov 2013 14:22:53 +0100
   4 Subject: [PATCH 33/54] dmaengine: Add support for BCM2708
   5
   6 Add support for DMA controller of BCM2708 as used in the Raspberry Pi.
   7 Currently it only supports cyclic DMA.
   8
   9 Signed-off-by: Florian Meier <florian.meier@koalo.de>
  10 ---
  11  drivers/dma/Kconfig             |   6 +
  12  drivers/dma/Makefile            |   1 +
  13  drivers/dma/bcm2708-dmaengine.c | 588 ++++++++++++++++++++++++++++++++++++++++
  14  3 files changed, 595 insertions(+)
  15  create mode 100644 drivers/dma/bcm2708-dmaengine.c
  16
  17 diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
  18 index 605b016..edd5842 100644
  19 --- a/drivers/dma/Kconfig
  20 +++ b/drivers/dma/Kconfig
  21 @@ -312,6 +312,12 @@ config DMA_BCM2835
  22         select DMA_ENGINE
  23         select DMA_VIRTUAL_CHANNELS
  24
  25 +config DMA_BCM2708
  26 +       tristate "BCM2708 DMA engine support"
  27 +       depends on MACH_BCM2708
  28 +       select DMA_ENGINE
  29 +       select DMA_VIRTUAL_CHANNELS
  30 +
  31  config TI_CPPI41
  32         tristate "AM33xx CPPI41 DMA support"
  33         depends on ARCH_OMAP
  34 diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
  35 index a029d0f4..f4d9516 100644
  36 --- a/drivers/dma/Makefile
  37 +++ b/drivers/dma/Makefile
  38 @@ -39,6 +39,7 @@ obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o
  39  obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o
  40  obj-$(CONFIG_DMA_OMAP) += omap-dma.o
  41  obj-$(CONFIG_DMA_BCM2835) += bcm2835-dma.o
  42 +obj-$(CONFIG_DMA_BCM2708) += bcm2708-dmaengine.o
  43  obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o
  44  obj-$(CONFIG_DMA_JZ4740) += dma-jz4740.o
  45  obj-$(CONFIG_TI_CPPI41) += cppi41.o
  46 diff --git a/drivers/dma/bcm2708-dmaengine.c b/drivers/dma/bcm2708-dmaengine.c
  47 new file mode 100644
  48 index 0000000..b244293
  49 --- /dev/null
  50 +++ b/drivers/dma/bcm2708-dmaengine.c
  51 @@ -0,0 +1,588 @@
  52 +/*
  53 + * BCM2708 DMA engine support
  54 + *
  55 + * This driver only supports cyclic DMA transfers
  56 + * as needed for the I2S module.
  57 + *
  58 + * Author:      Florian Meier <florian.meier@koalo.de>
  59 + *              Copyright 2013
  60 + *
  61 + * Based on
  62 + *     OMAP DMAengine support by Russell King
  63 + *
  64 + *     BCM2708 DMA Driver
  65 + *     Copyright (C) 2010 Broadcom
  66 + *
  67 + *     Raspberry Pi PCM I2S ALSA Driver
  68 + *     Copyright (c) by Phil Poole 2013
  69 + *
  70 + *     MARVELL MMP Peripheral DMA Driver
  71 + *     Copyright 2012 Marvell International Ltd.
  72 + *
  73 + * This program is free software; you can redistribute it and/or modify
  74 + * it under the terms of the GNU General Public License as published by
  75 + * the Free Software Foundation; either version 2 of the License, or
  76 + * (at your option) any later version.
  77 + *
  78 + * This program is distributed in the hope that it will be useful,
  79 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  80 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  81 + * GNU General Public License for more details.
  82 + */
  83 +#include <linux/dmaengine.h>
  84 +#include <linux/dma-mapping.h>
  85 +#include <linux/err.h>
  86 +#include <linux/init.h>
  87 +#include <linux/interrupt.h>
  88 +#include <linux/list.h>
  89 +#include <linux/module.h>
  90 +#include <linux/platform_device.h>
  91 +#include <linux/slab.h>
  92 +#include <linux/io.h>
  93 +#include <linux/spinlock.h>
  94 +#include <linux/irq.h>
  95 +
  96 +#include "virt-dma.h"
  97 +
  98 +#include <mach/dma.h>
  99 +#include <mach/irqs.h>
 100 +
 101 +struct bcm2708_dmadev {
 102 +       struct dma_device ddev;
 103 +       spinlock_t lock;
 104 +       void __iomem *base;
 105 +       struct device_dma_parameters dma_parms;
 106 +};
 107 +
 108 +struct bcm2708_chan {
 109 +       struct virt_dma_chan vc;
 110 +       struct list_head node;
 111 +
 112 +       struct dma_slave_config cfg;
 113 +       bool cyclic;
 114 +
 115 +       int ch;
 116 +       struct bcm2708_desc *desc;
 117 +
 118 +       void __iomem *chan_base;
 119 +       int irq_number;
 120 +};
 121 +
 122 +struct bcm2708_desc {
 123 +       struct virt_dma_desc vd;
 124 +       enum dma_transfer_direction dir;
 125 +
 126 +       unsigned int control_block_size;
 127 +       struct bcm2708_dma_cb *control_block_base;
 128 +       dma_addr_t control_block_base_phys;
 129 +
 130 +       unsigned frames;
 131 +       size_t size;
 132 +};
 133 +
 134 +#define BCM2708_DMA_DATA_TYPE_S8       1
 135 +#define BCM2708_DMA_DATA_TYPE_S16      2
 136 +#define BCM2708_DMA_DATA_TYPE_S32      4
 137 +#define BCM2708_DMA_DATA_TYPE_S128     16
 138 +
 139 +static inline struct bcm2708_dmadev *to_bcm2708_dma_dev(struct dma_device *d)
 140 +{
 141 +       return container_of(d, struct bcm2708_dmadev, ddev);
 142 +}
 143 +
 144 +static inline struct bcm2708_chan *to_bcm2708_dma_chan(struct dma_chan *c)
 145 +{
 146 +       return container_of(c, struct bcm2708_chan, vc.chan);
 147 +}
 148 +
 149 +static inline struct bcm2708_desc *to_bcm2708_dma_desc(
 150 +               struct dma_async_tx_descriptor *t)
 151 +{
 152 +       return container_of(t, struct bcm2708_desc, vd.tx);
 153 +}
 154 +
 155 +static void bcm2708_dma_desc_free(struct virt_dma_desc *vd)
 156 +{
 157 +       struct bcm2708_desc *desc = container_of(vd, struct bcm2708_desc, vd);
 158 +       dma_free_coherent(desc->vd.tx.chan->device->dev,
 159 +                       desc->control_block_size,
 160 +                       desc->control_block_base,
 161 +                       desc->control_block_base_phys);
 162 +       kfree(desc);
 163 +}
 164 +
 165 +static void bcm2708_dma_start_desc(struct bcm2708_chan *c)
 166 +{
 167 +       struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
 168 +       struct bcm2708_desc *d;
 169 +
 170 +       if (!vd) {
 171 +               c->desc = NULL;
 172 +               return;
 173 +       }
 174 +
 175 +       list_del(&vd->node);
 176 +
 177 +       c->desc = d = to_bcm2708_dma_desc(&vd->tx);
 178 +
 179 +       bcm_dma_start(c->chan_base, d->control_block_base_phys);
 180 +}
 181 +
 182 +static irqreturn_t bcm2708_dma_callback(int irq, void *data)
 183 +{
 184 +       struct bcm2708_chan *c = data;
 185 +       struct bcm2708_desc *d;
 186 +       unsigned long flags;
 187 +
 188 +       spin_lock_irqsave(&c->vc.lock, flags);
 189 +
 190 +       /* Acknowledge interrupt */
 191 +       writel(BCM2708_DMA_INT, c->chan_base + BCM2708_DMA_CS);
 192 +
 193 +       d = c->desc;
 194 +
 195 +       if (d) {
 196 +               /* TODO Only works for cyclic DMA */
 197 +               vchan_cyclic_callback(&d->vd);
 198 +       }
 199 +
 200 +       /* Keep the DMA engine running */
 201 +       dsb(); /* ARM synchronization barrier */
 202 +       writel(BCM2708_DMA_ACTIVE, c->chan_base + BCM2708_DMA_CS);
 203 +
 204 +       spin_unlock_irqrestore(&c->vc.lock, flags);
 205 +
 206 +       return IRQ_HANDLED;
 207 +}
 208 +
 209 +static int bcm2708_dma_alloc_chan_resources(struct dma_chan *chan)
 210 +{
 211 +       struct bcm2708_chan *c = to_bcm2708_dma_chan(chan);
 212 +
 213 +       return request_irq(c->irq_number,
 214 +                       bcm2708_dma_callback, 0, "DMA IRQ", c);
 215 +}
 216 +
 217 +static void bcm2708_dma_free_chan_resources(struct dma_chan *chan)
 218 +{
 219 +       struct bcm2708_chan *c = to_bcm2708_dma_chan(chan);
 220 +
 221 +       vchan_free_chan_resources(&c->vc);
 222 +       free_irq(c->irq_number, c);
 223 +
 224 +       dev_dbg(c->vc.chan.device->dev, "Freeing DMA channel %u\n", c->ch);
 225 +}
 226 +
 227 +static size_t bcm2708_dma_desc_size(struct bcm2708_desc *d)
 228 +{
 229 +       return d->size;
 230 +}
 231 +
 232 +static size_t bcm2708_dma_desc_size_pos(struct bcm2708_desc *d, dma_addr_t addr)
 233 +{
 234 +       unsigned i;
 235 +       size_t size;
 236 +
 237 +       for (size = i = 0; i < d->frames; i++) {
 238 +               struct bcm2708_dma_cb *control_block =
 239 +                       &d->control_block_base[i];
 240 +               size_t this_size = control_block->length;
 241 +               dma_addr_t dma;
 242 +
 243 +               if (d->dir == DMA_DEV_TO_MEM)
 244 +                       dma = control_block->dst;
 245 +               else
 246 +                       dma = control_block->src;
 247 +
 248 +               if (size)
 249 +                       size += this_size;
 250 +               else if (addr >= dma && addr < dma + this_size)
 251 +                       size += dma + this_size - addr;
 252 +       }
 253 +
 254 +       return size;
 255 +}
 256 +
 257 +static enum dma_status bcm2708_dma_tx_status(struct dma_chan *chan,
 258 +       dma_cookie_t cookie, struct dma_tx_state *txstate)
 259 +{
 260 +       struct bcm2708_chan *c = to_bcm2708_dma_chan(chan);
 261 +       struct virt_dma_desc *vd;
 262 +       enum dma_status ret;
 263 +       unsigned long flags;
 264 +
 265 +       ret = dma_cookie_status(chan, cookie, txstate);
 266 +       if (ret == DMA_COMPLETE || !txstate)
 267 +               return ret;
 268 +
 269 +       spin_lock_irqsave(&c->vc.lock, flags);
 270 +       vd = vchan_find_desc(&c->vc, cookie);
 271 +       if (vd) {
 272 +               txstate->residue =
 273 +                       bcm2708_dma_desc_size(to_bcm2708_dma_desc(&vd->tx));
 274 +       } else if (c->desc && c->desc->vd.tx.cookie == cookie) {
 275 +               struct bcm2708_desc *d = c->desc;
 276 +               dma_addr_t pos;
 277 +
 278 +               if (d->dir == DMA_MEM_TO_DEV)
 279 +                       pos = readl(c->chan_base + BCM2708_DMA_SOURCE_AD);
 280 +               else if (d->dir == DMA_DEV_TO_MEM)
 281 +                       pos = readl(c->chan_base + BCM2708_DMA_DEST_AD);
 282 +               else
 283 +                       pos = 0;
 284 +
 285 +               txstate->residue = bcm2708_dma_desc_size_pos(d, pos);
 286 +       } else {
 287 +               txstate->residue = 0;
 288 +       }
 289 +
 290 +       spin_unlock_irqrestore(&c->vc.lock, flags);
 291 +
 292 +       return ret;
 293 +}
 294 +
 295 +static void bcm2708_dma_issue_pending(struct dma_chan *chan)
 296 +{
 297 +       struct bcm2708_chan *c = to_bcm2708_dma_chan(chan);
 298 +       unsigned long flags;
 299 +
 300 +       c->cyclic = true; /* Nothing else is implemented */
 301 +
 302 +       spin_lock_irqsave(&c->vc.lock, flags);
 303 +       if (vchan_issue_pending(&c->vc) && !c->desc)
 304 +               bcm2708_dma_start_desc(c);
 305 +
 306 +       spin_unlock_irqrestore(&c->vc.lock, flags);
 307 +}
 308 +
 309 +static struct dma_async_tx_descriptor *bcm2708_dma_prep_dma_cyclic(
 310 +       struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
 311 +       size_t period_len, enum dma_transfer_direction direction,
 312 +       unsigned long flags, void *context)
 313 +{
 314 +       struct bcm2708_chan *c = to_bcm2708_dma_chan(chan);
 315 +       enum dma_slave_buswidth dev_width;
 316 +       struct bcm2708_desc *d;
 317 +       dma_addr_t dev_addr;
 318 +       unsigned es, sync_type;
 319 +       unsigned frame;
 320 +
 321 +       /* Grab configuration */
 322 +       if (direction == DMA_DEV_TO_MEM) {
 323 +               dev_addr = c->cfg.src_addr;
 324 +               dev_width = c->cfg.src_addr_width;
 325 +               sync_type = BCM2708_DMA_S_DREQ;
 326 +       } else if (direction == DMA_MEM_TO_DEV) {
 327 +               dev_addr = c->cfg.dst_addr;
 328 +               dev_width = c->cfg.dst_addr_width;
 329 +               sync_type = BCM2708_DMA_D_DREQ;
 330 +       } else {
 331 +               dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
 332 +               return NULL;
 333 +       }
 334 +
 335 +       /* Bus width translates to the element size (ES) */
 336 +       switch (dev_width) {
 337 +       case DMA_SLAVE_BUSWIDTH_4_BYTES:
 338 +               es = BCM2708_DMA_DATA_TYPE_S32;
 339 +               break;
 340 +       default:
 341 +               return NULL;
 342 +       }
 343 +
 344 +       /* Now allocate and setup the descriptor. */
 345 +       d = kzalloc(sizeof(*d), GFP_NOWAIT);
 346 +       if (!d)
 347 +               return NULL;
 348 +
 349 +       d->dir = direction;
 350 +       d->frames = buf_len / period_len;
 351 +
 352 +       /* Allocate memory for control blocks */
 353 +       d->control_block_size = d->frames * sizeof(struct bcm2708_dma_cb);
 354 +       d->control_block_base = dma_zalloc_coherent(chan->device->dev,
 355 +                       d->control_block_size, &d->control_block_base_phys,
 356 +                       GFP_NOWAIT);
 357 +
 358 +       if (!d->control_block_base) {
 359 +               kfree(d);
 360 +               return NULL;
 361 +       }
 362 +
 363 +       /*
 364 +        * Iterate over all frames, create a control block
 365 +        * for each frame and link them together.
 366 +        */
 367 +       for (frame = 0; frame < d->frames; frame++) {
 368 +               struct bcm2708_dma_cb *control_block =
 369 +                       &d->control_block_base[frame];
 370 +
 371 +               /* Setup adresses */
 372 +               if (d->dir == DMA_DEV_TO_MEM) {
 373 +                       control_block->info = BCM2708_DMA_D_INC;
 374 +                       control_block->src = dev_addr;
 375 +                       control_block->dst = buf_addr + frame * period_len;
 376 +               } else {
 377 +                       control_block->info = BCM2708_DMA_S_INC;
 378 +                       control_block->src = buf_addr + frame * period_len;
 379 +                       control_block->dst = dev_addr;
 380 +               }
 381 +
 382 +               /* Enable interrupt */
 383 +               control_block->info |= BCM2708_DMA_INT_EN;
 384 +
 385 +               /* Setup synchronization */
 386 +               if (sync_type != 0)
 387 +                       control_block->info |= sync_type;
 388 +
 389 +               /* Setup DREQ channel */
 390 +               if (c->cfg.slave_id != 0)
 391 +                       control_block->info |=
 392 +                               BCM2708_DMA_PER_MAP(c->cfg.slave_id);
 393 +
 394 +               /* Length of a frame */
 395 +               control_block->length = period_len;
 396 +               d->size += control_block->length;
 397 +
 398 +               /*
 399 +                * Next block is the next frame.
 400 +                * This DMA engine driver currently only supports cyclic DMA.
 401 +                * Therefore, wrap around at number of frames.
 402 +                */
 403 +               control_block->next = d->control_block_base_phys +
 404 +                       sizeof(struct bcm2708_dma_cb)
 405 +                       * ((frame + 1) % d->frames);
 406 +       }
 407 +
 408 +       return vchan_tx_prep(&c->vc, &d->vd, flags);
 409 +}
 410 +
 411 +static int bcm2708_dma_slave_config(struct bcm2708_chan *c,
 412 +               struct dma_slave_config *cfg)
 413 +{
 414 +       if ((cfg->direction == DMA_DEV_TO_MEM &&
 415 +            cfg->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
 416 +           (cfg->direction == DMA_MEM_TO_DEV &&
 417 +            cfg->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
 418 +           !is_slave_direction(cfg->direction)) {
 419 +               return -EINVAL;
 420 +       }
 421 +
 422 +       c->cfg = *cfg;
 423 +
 424 +       return 0;
 425 +}
 426 +
 427 +static int bcm2708_dma_terminate_all(struct bcm2708_chan *c)
 428 +{
 429 +       struct bcm2708_dmadev *d = to_bcm2708_dma_dev(c->vc.chan.device);
 430 +       unsigned long flags;
 431 +       int timeout = 10000;
 432 +       LIST_HEAD(head);
 433 +
 434 +       spin_lock_irqsave(&c->vc.lock, flags);
 435 +
 436 +       /* Prevent this channel being scheduled */
 437 +       spin_lock(&d->lock);
 438 +       list_del_init(&c->node);
 439 +       spin_unlock(&d->lock);
 440 +
 441 +       /*
 442 +        * Stop DMA activity: we assume the callback will not be called
 443 +        * after bcm_dma_abort() returns (even if it does, it will see
 444 +        * c->desc is NULL and exit.)
 445 +        */
 446 +       if (c->desc) {
 447 +               c->desc = NULL;
 448 +               bcm_dma_abort(c->chan_base);
 449 +
 450 +               /* Wait for stopping */
 451 +               while (timeout > 0) {
 452 +                       timeout--;
 453 +                       if (!(readl(c->chan_base + BCM2708_DMA_CS) &
 454 +                                               BCM2708_DMA_ACTIVE))
 455 +                               break;
 456 +
 457 +                       cpu_relax();
 458 +               }
 459 +
 460 +               if (timeout <= 0)
 461 +                       dev_err(d->ddev.dev, "DMA transfer could not be terminated\n");
 462 +       }
 463 +
 464 +       vchan_get_all_descriptors(&c->vc, &head);
 465 +       spin_unlock_irqrestore(&c->vc.lock, flags);
 466 +       vchan_dma_desc_free_list(&c->vc, &head);
 467 +
 468 +       return 0;
 469 +}
 470 +
 471 +static int bcm2708_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 472 +       unsigned long arg)
 473 +{
 474 +       struct bcm2708_chan *c = to_bcm2708_dma_chan(chan);
 475 +
 476 +       switch (cmd) {
 477 +       case DMA_SLAVE_CONFIG:
 478 +               return bcm2708_dma_slave_config(c,
 479 +                               (struct dma_slave_config *)arg);
 480 +
 481 +       case DMA_TERMINATE_ALL:
 482 +               return bcm2708_dma_terminate_all(c);
 483 +
 484 +       default:
 485 +               return -ENXIO;
 486 +       }
 487 +}
 488 +
 489 +static int bcm2708_dma_chan_init(struct bcm2708_dmadev *d, void __iomem* chan_base,
 490 +                                                                       int chan_id, int irq)
 491 +{
 492 +       struct bcm2708_chan *c;
 493 +
 494 +       c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL);
 495 +       if (!c)
 496 +               return -ENOMEM;
 497 +
 498 +       c->vc.desc_free = bcm2708_dma_desc_free;
 499 +       vchan_init(&c->vc, &d->ddev);
 500 +       INIT_LIST_HEAD(&c->node);
 501 +
 502 +       d->ddev.chancnt++;
 503 +
 504 +       c->chan_base = chan_base;
 505 +       c->ch = chan_id;
 506 +       c->irq_number = irq;
 507 +
 508 +       return 0;
 509 +}
 510 +
 511 +static void bcm2708_dma_free(struct bcm2708_dmadev *od)
 512 +{
 513 +       while (!list_empty(&od->ddev.channels)) {
 514 +               struct bcm2708_chan *c = list_first_entry(&od->ddev.channels,
 515 +                       struct bcm2708_chan, vc.chan.device_node);
 516 +
 517 +               list_del(&c->vc.chan.device_node);
 518 +               tasklet_kill(&c->vc.task);
 519 +       }
 520 +}
 521 +
 522 +static int bcm2708_dma_probe(struct platform_device *pdev)
 523 +{
 524 +       struct bcm2708_dmadev *od;
 525 +       int rc, i;
 526 +
 527 +       if (!pdev->dev.dma_mask)
 528 +               pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
 529 +
 530 +       rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
 531 +       if (rc)
 532 +               return rc;
 533 +       dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
 534 +
 535 +       od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
 536 +       if (!od)
 537 +               return -ENOMEM;
 538 +
 539 +       pdev->dev.dma_parms = &od->dma_parms;
 540 +       dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF);
 541 +
 542 +       dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
 543 +       dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
 544 +       od->ddev.device_alloc_chan_resources = bcm2708_dma_alloc_chan_resources;
 545 +       od->ddev.device_free_chan_resources = bcm2708_dma_free_chan_resources;
 546 +       od->ddev.device_tx_status = bcm2708_dma_tx_status;
 547 +       od->ddev.device_issue_pending = bcm2708_dma_issue_pending;
 548 +       od->ddev.device_prep_dma_cyclic = bcm2708_dma_prep_dma_cyclic;
 549 +       od->ddev.device_control = bcm2708_dma_control;
 550 +       od->ddev.dev = &pdev->dev;
 551 +       INIT_LIST_HEAD(&od->ddev.channels);
 552 +       spin_lock_init(&od->lock);
 553 +
 554 +       platform_set_drvdata(pdev, od);
 555 +
 556 +       for (i = 0; i < 16; i++) {
 557 +               void __iomem* chan_base;
 558 +               int chan_id, irq;
 559 +
 560 +               chan_id = bcm_dma_chan_alloc(BCM_DMA_FEATURE_FAST,
 561 +                       &chan_base,
 562 +                       &irq);
 563 +
 564 +               if (chan_id < 0)
 565 +                       break;
 566 +
 567 +               rc = bcm2708_dma_chan_init(od, chan_base, chan_id, irq);
 568 +               if (rc) {
 569 +                       bcm2708_dma_free(od);
 570 +                       return rc;
 571 +               }
 572 +       }
 573 +
 574 +       rc = dma_async_device_register(&od->ddev);
 575 +       if (rc) {
 576 +               dev_err(&pdev->dev,
 577 +                       "Failed to register slave DMA engine device: %d\n", rc);
 578 +               bcm2708_dma_free(od);
 579 +               return rc;
 580 +       }
 581 +
 582 +       dev_dbg(&pdev->dev, "Load BCM2708 DMA engine driver\n");
 583 +
 584 +       return rc;
 585 +}
 586 +
 587 +static int bcm2708_dma_remove(struct platform_device *pdev)
 588 +{
 589 +       struct bcm2708_dmadev *od = platform_get_drvdata(pdev);
 590 +
 591 +       dma_async_device_unregister(&od->ddev);
 592 +       bcm2708_dma_free(od);
 593 +
 594 +       return 0;
 595 +}
 596 +
 597 +static struct platform_driver bcm2708_dma_driver = {
 598 +       .probe  = bcm2708_dma_probe,
 599 +       .remove = bcm2708_dma_remove,
 600 +       .driver = {
 601 +               .name = "bcm2708-dmaengine",
 602 +               .owner = THIS_MODULE,
 603 +       },
 604 +};
 605 +
 606 +static struct platform_device *pdev;
 607 +
 608 +static const struct platform_device_info bcm2708_dma_dev_info = {
 609 +       .name = "bcm2708-dmaengine",
 610 +       .id = -1,
 611 +};
 612 +
 613 +static int bcm2708_dma_init(void)
 614 +{
 615 +       int rc = platform_driver_register(&bcm2708_dma_driver);
 616 +
 617 +       if (rc == 0) {
 618 +               pdev = platform_device_register_full(&bcm2708_dma_dev_info);
 619 +               if (IS_ERR(pdev)) {
 620 +                       platform_driver_unregister(&bcm2708_dma_driver);
 621 +                       rc = PTR_ERR(pdev);
 622 +               }
 623 +       }
 624 +
 625 +       return rc;
 626 +}
 627 +subsys_initcall(bcm2708_dma_init);
 628 +
 629 +static void __exit bcm2708_dma_exit(void)
 630 +{
 631 +       platform_device_unregister(pdev);
 632 +       platform_driver_unregister(&bcm2708_dma_driver);
 633 +}
 634 +module_exit(bcm2708_dma_exit);
 635 +
 636 +MODULE_ALIAS("platform:bcm2708-dma");
 637 +MODULE_DESCRIPTION("BCM2708 DMA engine driver");
 638 +MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
 639 +MODULE_LICENSE("GPL v2");
 640 --
 641 1.9.1
 642