target/linux/brcm2708/patches-3.14/0034-ASoC-Add-support-for-BCM2708.patch

   1 From 8b7d5e646f5b71b22894623419202c9e8c739b2a Mon Sep 17 00:00:00 2001
   2 From: Florian Meier <florian.meier@koalo.de>
   3 Date: Fri, 22 Nov 2013 14:33:38 +0100
   4 Subject: [PATCH 34/54] ASoC: Add support for BCM2708
   5
   6 This driver adds support for digital audio (I2S)
   7 for the BCM2708 SoC that is used by the
   8 Raspberry Pi. External audio codecs can be
   9 connected to the Raspberry Pi via P5 header.
  10
  11 It relies on cyclic DMA engine support for BCM2708.
  12
  13 Signed-off-by: Florian Meier <florian.meier@koalo.de>
  14 ---
  15  sound/soc/bcm/Kconfig       |  11 +
  16  sound/soc/bcm/Makefile      |   4 +
  17  sound/soc/bcm/bcm2708-i2s.c | 940 ++++++++++++++++++++++++++++++++++++++++++++
  18  3 files changed, 955 insertions(+)
  19  create mode 100644 sound/soc/bcm/bcm2708-i2s.c
  20
  21 --- a/sound/soc/bcm/Kconfig
  22 +++ b/sound/soc/bcm/Kconfig
  23 @@ -7,3 +7,14 @@ config SND_BCM2835_SOC_I2S
  24           Say Y or M if you want to add support for codecs attached to
  25           the BCM2835 I2S interface. You will also need
  26           to select the audio interfaces to support below.
  27 +
  28 +config SND_BCM2708_SOC_I2S
  29 +       tristate "SoC Audio support for the Broadcom BCM2708 I2S module"
  30 +       depends on MACH_BCM2708
  31 +       select REGMAP_MMIO
  32 +       select SND_SOC_DMAENGINE_PCM
  33 +       select SND_SOC_GENERIC_DMAENGINE_PCM
  34 +       help
  35 +         Say Y or M if you want to add support for codecs attached to
  36 +         the BCM2708 I2S interface. You will also need
  37 +         to select the audio interfaces to support below.
  38 --- a/sound/soc/bcm/Makefile
  39 +++ b/sound/soc/bcm/Makefile
  40 @@ -3,3 +3,7 @@ snd-soc-bcm2835-i2s-objs := bcm2835-i2s.
  41
  42  obj-$(CONFIG_SND_BCM2835_SOC_I2S) += snd-soc-bcm2835-i2s.o
  43
  44 +# BCM2708 Platform Support
  45 +snd-soc-bcm2708-i2s-objs := bcm2708-i2s.o
  46 +
  47 +obj-$(CONFIG_SND_BCM2708_SOC_I2S) += snd-soc-bcm2708-i2s.o
  48 --- /dev/null
  49 +++ b/sound/soc/bcm/bcm2708-i2s.c
  50 @@ -0,0 +1,940 @@
  51 +/*
  52 + * ALSA SoC I2S Audio Layer for Broadcom BCM2708 SoC
  53 + *
  54 + * Author:     Florian Meier <florian.meier@koalo.de>
  55 + *             Copyright 2013
  56 + *
  57 + * Based on
  58 + *     Raspberry Pi PCM I2S ALSA Driver
  59 + *     Copyright (c) by Phil Poole 2013
  60 + *
  61 + *     ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
  62 + *      Vladimir Barinov, <vbarinov@embeddedalley.com>
  63 + *     Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com>
  64 + *
  65 + *     OMAP ALSA SoC DAI driver using McBSP port
  66 + *     Copyright (C) 2008 Nokia Corporation
  67 + *     Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
  68 + *              Peter Ujfalusi <peter.ujfalusi@ti.com>
  69 + *
  70 + *     Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
  71 + *     Author: Timur Tabi <timur@freescale.com>
  72 + *     Copyright 2007-2010 Freescale Semiconductor, Inc.
  73 + *
  74 + * This program is free software; you can redistribute it and/or
  75 + * modify it under the terms of the GNU General Public License
  76 + * version 2 as published by the Free Software Foundation.
  77 + *
  78 + * This program is distributed in the hope that it will be useful, but
  79 + * WITHOUT ANY WARRANTY; without even the implied warranty of
  80 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  81 + * General Public License for more details.
  82 + */
  83 +
  84 +#include <linux/init.h>
  85 +#include <linux/module.h>
  86 +#include <linux/device.h>
  87 +#include <linux/slab.h>
  88 +#include <linux/delay.h>
  89 +#include <linux/io.h>
  90 +#include <linux/clk.h>
  91 +
  92 +#include <sound/core.h>
  93 +#include <sound/pcm.h>
  94 +#include <sound/pcm_params.h>
  95 +#include <sound/initval.h>
  96 +#include <sound/soc.h>
  97 +#include <sound/dmaengine_pcm.h>
  98 +
  99 +/* Clock registers */
 100 +#define BCM2708_CLK_PCMCTL_REG  0x00
 101 +#define BCM2708_CLK_PCMDIV_REG  0x04
 102 +
 103 +/* Clock register settings */
 104 +#define BCM2708_CLK_PASSWD             (0x5a000000)
 105 +#define BCM2708_CLK_PASSWD_MASK        (0xff000000)
 106 +#define BCM2708_CLK_MASH(v)            ((v) << 9)
 107 +#define BCM2708_CLK_FLIP               BIT(8)
 108 +#define BCM2708_CLK_BUSY               BIT(7)
 109 +#define BCM2708_CLK_KILL               BIT(5)
 110 +#define BCM2708_CLK_ENAB               BIT(4)
 111 +#define BCM2708_CLK_SRC(v)             (v)
 112 +
 113 +#define BCM2708_CLK_SHIFT              (12)
 114 +#define BCM2708_CLK_DIVI(v)            ((v) << BCM2708_CLK_SHIFT)
 115 +#define BCM2708_CLK_DIVF(v)            (v)
 116 +#define BCM2708_CLK_DIVF_MASK          (0xFFF)
 117 +
 118 +enum {
 119 +       BCM2708_CLK_MASH_0 = 0,
 120 +       BCM2708_CLK_MASH_1,
 121 +       BCM2708_CLK_MASH_2,
 122 +       BCM2708_CLK_MASH_3,
 123 +};
 124 +
 125 +enum {
 126 +       BCM2708_CLK_SRC_GND = 0,
 127 +       BCM2708_CLK_SRC_OSC,
 128 +       BCM2708_CLK_SRC_DBG0,
 129 +       BCM2708_CLK_SRC_DBG1,
 130 +       BCM2708_CLK_SRC_PLLA,
 131 +       BCM2708_CLK_SRC_PLLC,
 132 +       BCM2708_CLK_SRC_PLLD,
 133 +       BCM2708_CLK_SRC_HDMI,
 134 +};
 135 +
 136 +/* Most clocks are not useable (freq = 0) */
 137 +static const unsigned int bcm2708_clk_freq[BCM2708_CLK_SRC_HDMI+1] = {
 138 +       [BCM2708_CLK_SRC_GND]           = 0,
 139 +       [BCM2708_CLK_SRC_OSC]           = 19200000,
 140 +       [BCM2708_CLK_SRC_DBG0]          = 0,
 141 +       [BCM2708_CLK_SRC_DBG1]          = 0,
 142 +       [BCM2708_CLK_SRC_PLLA]          = 0,
 143 +       [BCM2708_CLK_SRC_PLLC]          = 0,
 144 +       [BCM2708_CLK_SRC_PLLD]          = 500000000,
 145 +       [BCM2708_CLK_SRC_HDMI]          = 0,
 146 +};
 147 +
 148 +/* I2S registers */
 149 +#define BCM2708_I2S_CS_A_REG           0x00
 150 +#define BCM2708_I2S_FIFO_A_REG         0x04
 151 +#define BCM2708_I2S_MODE_A_REG         0x08
 152 +#define BCM2708_I2S_RXC_A_REG          0x0c
 153 +#define BCM2708_I2S_TXC_A_REG          0x10
 154 +#define BCM2708_I2S_DREQ_A_REG         0x14
 155 +#define BCM2708_I2S_INTEN_A_REG        0x18
 156 +#define BCM2708_I2S_INTSTC_A_REG       0x1c
 157 +#define BCM2708_I2S_GRAY_REG           0x20
 158 +
 159 +/* I2S register settings */
 160 +#define BCM2708_I2S_STBY               BIT(25)
 161 +#define BCM2708_I2S_SYNC               BIT(24)
 162 +#define BCM2708_I2S_RXSEX              BIT(23)
 163 +#define BCM2708_I2S_RXF                BIT(22)
 164 +#define BCM2708_I2S_TXE                BIT(21)
 165 +#define BCM2708_I2S_RXD                BIT(20)
 166 +#define BCM2708_I2S_TXD                BIT(19)
 167 +#define BCM2708_I2S_RXR                BIT(18)
 168 +#define BCM2708_I2S_TXW                BIT(17)
 169 +#define BCM2708_I2S_CS_RXERR           BIT(16)
 170 +#define BCM2708_I2S_CS_TXERR           BIT(15)
 171 +#define BCM2708_I2S_RXSYNC             BIT(14)
 172 +#define BCM2708_I2S_TXSYNC             BIT(13)
 173 +#define BCM2708_I2S_DMAEN              BIT(9)
 174 +#define BCM2708_I2S_RXTHR(v)           ((v) << 7)
 175 +#define BCM2708_I2S_TXTHR(v)           ((v) << 5)
 176 +#define BCM2708_I2S_RXCLR              BIT(4)
 177 +#define BCM2708_I2S_TXCLR              BIT(3)
 178 +#define BCM2708_I2S_TXON               BIT(2)
 179 +#define BCM2708_I2S_RXON               BIT(1)
 180 +#define BCM2708_I2S_EN                 (1)
 181 +
 182 +#define BCM2708_I2S_CLKDIS             BIT(28)
 183 +#define BCM2708_I2S_PDMN               BIT(27)
 184 +#define BCM2708_I2S_PDME               BIT(26)
 185 +#define BCM2708_I2S_FRXP               BIT(25)
 186 +#define BCM2708_I2S_FTXP               BIT(24)
 187 +#define BCM2708_I2S_CLKM               BIT(23)
 188 +#define BCM2708_I2S_CLKI               BIT(22)
 189 +#define BCM2708_I2S_FSM                BIT(21)
 190 +#define BCM2708_I2S_FSI                BIT(20)
 191 +#define BCM2708_I2S_FLEN(v)            ((v) << 10)
 192 +#define BCM2708_I2S_FSLEN(v)           (v)
 193 +
 194 +#define BCM2708_I2S_CHWEX              BIT(15)
 195 +#define BCM2708_I2S_CHEN               BIT(14)
 196 +#define BCM2708_I2S_CHPOS(v)           ((v) << 4)
 197 +#define BCM2708_I2S_CHWID(v)           (v)
 198 +#define BCM2708_I2S_CH1(v)             ((v) << 16)
 199 +#define BCM2708_I2S_CH2(v)             (v)
 200 +
 201 +#define BCM2708_I2S_TX_PANIC(v)        ((v) << 24)
 202 +#define BCM2708_I2S_RX_PANIC(v)        ((v) << 16)
 203 +#define BCM2708_I2S_TX(v)              ((v) << 8)
 204 +#define BCM2708_I2S_RX(v)              (v)
 205 +
 206 +#define BCM2708_I2S_INT_RXERR          BIT(3)
 207 +#define BCM2708_I2S_INT_TXERR          BIT(2)
 208 +#define BCM2708_I2S_INT_RXR            BIT(1)
 209 +#define BCM2708_I2S_INT_TXW            BIT(0)
 210 +
 211 +/* I2S DMA interface */
 212 +#define BCM2708_I2S_FIFO_PHYSICAL_ADDR 0x7E203004
 213 +#define BCM2708_DMA_DREQ_PCM_TX                2
 214 +#define BCM2708_DMA_DREQ_PCM_RX                3
 215 +
 216 +/* General device struct */
 217 +struct bcm2708_i2s_dev {
 218 +       struct device                           *dev;
 219 +       struct snd_dmaengine_dai_dma_data       dma_data[2];
 220 +       unsigned int                            fmt;
 221 +       unsigned int                            bclk_ratio;
 222 +
 223 +       struct regmap *i2s_regmap;
 224 +       struct regmap *clk_regmap;
 225 +};
 226 +
 227 +static void bcm2708_i2s_start_clock(struct bcm2708_i2s_dev *dev)
 228 +{
 229 +       /* Start the clock if in master mode */
 230 +       unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
 231 +
 232 +       switch (master) {
 233 +       case SND_SOC_DAIFMT_CBS_CFS:
 234 +       case SND_SOC_DAIFMT_CBS_CFM:
 235 +               regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG,
 236 +                       BCM2708_CLK_PASSWD_MASK | BCM2708_CLK_ENAB,
 237 +                       BCM2708_CLK_PASSWD | BCM2708_CLK_ENAB);
 238 +               break;
 239 +       default:
 240 +               break;
 241 +       }
 242 +}
 243 +
 244 +static void bcm2708_i2s_stop_clock(struct bcm2708_i2s_dev *dev)
 245 +{
 246 +       uint32_t clkreg;
 247 +       int timeout = 1000;
 248 +
 249 +       /* Stop clock */
 250 +       regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG,
 251 +                       BCM2708_CLK_PASSWD_MASK | BCM2708_CLK_ENAB,
 252 +                       BCM2708_CLK_PASSWD);
 253 +
 254 +       /* Wait for the BUSY flag going down */
 255 +       while (--timeout) {
 256 +               regmap_read(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, &clkreg);
 257 +               if (!(clkreg & BCM2708_CLK_BUSY))
 258 +                       break;
 259 +       }
 260 +
 261 +       if (!timeout) {
 262 +               /* KILL the clock */
 263 +               dev_err(dev->dev, "I2S clock didn't stop. Kill the clock!\n");
 264 +               regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG,
 265 +                       BCM2708_CLK_KILL | BCM2708_CLK_PASSWD_MASK,
 266 +                       BCM2708_CLK_KILL | BCM2708_CLK_PASSWD);
 267 +       }
 268 +}
 269 +
 270 +static void bcm2708_i2s_clear_fifos(struct bcm2708_i2s_dev *dev,
 271 +                                   bool tx, bool rx)
 272 +{
 273 +       int timeout = 1000;
 274 +       uint32_t syncval;
 275 +       uint32_t csreg;
 276 +       uint32_t i2s_active_state;
 277 +       uint32_t clkreg;
 278 +       uint32_t clk_active_state;
 279 +       uint32_t off;
 280 +       uint32_t clr;
 281 +
 282 +       off =  tx ? BCM2708_I2S_TXON : 0;
 283 +       off |= rx ? BCM2708_I2S_RXON : 0;
 284 +
 285 +       clr =  tx ? BCM2708_I2S_TXCLR : 0;
 286 +       clr |= rx ? BCM2708_I2S_RXCLR : 0;
 287 +
 288 +       /* Backup the current state */
 289 +       regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &csreg);
 290 +       i2s_active_state = csreg & (BCM2708_I2S_RXON | BCM2708_I2S_TXON);
 291 +
 292 +       regmap_read(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, &clkreg);
 293 +       clk_active_state = clkreg & BCM2708_CLK_ENAB;
 294 +
 295 +       /* Start clock if not running */
 296 +       if (!clk_active_state) {
 297 +               regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG,
 298 +                       BCM2708_CLK_PASSWD_MASK | BCM2708_CLK_ENAB,
 299 +                       BCM2708_CLK_PASSWD | BCM2708_CLK_ENAB);
 300 +       }
 301 +
 302 +       /* Stop I2S module */
 303 +       regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, off, 0);
 304 +
 305 +       /*
 306 +        * Clear the FIFOs
 307 +        * Requires at least 2 PCM clock cycles to take effect
 308 +        */
 309 +       regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, clr, clr);
 310 +
 311 +       /* Wait for 2 PCM clock cycles */
 312 +
 313 +       /*
 314 +        * Toggle the SYNC flag. After 2 PCM clock cycles it can be read back
 315 +        * FIXME: This does not seem to work for slave mode!
 316 +        */
 317 +       regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &syncval);
 318 +       syncval &= BCM2708_I2S_SYNC;
 319 +
 320 +       regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
 321 +                       BCM2708_I2S_SYNC, ~syncval);
 322 +
 323 +       /* Wait for the SYNC flag changing it's state */
 324 +       while (--timeout) {
 325 +               regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &csreg);
 326 +               if ((csreg & BCM2708_I2S_SYNC) != syncval)
 327 +                       break;
 328 +       }
 329 +
 330 +       if (!timeout)
 331 +               dev_err(dev->dev, "I2S SYNC error!\n");
 332 +
 333 +       /* Stop clock if it was not running before */
 334 +       if (!clk_active_state)
 335 +               bcm2708_i2s_stop_clock(dev);
 336 +
 337 +       /* Restore I2S state */
 338 +       regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
 339 +                       BCM2708_I2S_RXON | BCM2708_I2S_TXON, i2s_active_state);
 340 +}
 341 +
 342 +static int bcm2708_i2s_set_dai_fmt(struct snd_soc_dai *dai,
 343 +                                     unsigned int fmt)
 344 +{
 345 +       struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 346 +       dev->fmt = fmt;
 347 +       return 0;
 348 +}
 349 +
 350 +static int bcm2708_i2s_set_dai_bclk_ratio(struct snd_soc_dai *dai,
 351 +                                     unsigned int ratio)
 352 +{
 353 +       struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 354 +       dev->bclk_ratio = ratio;
 355 +       return 0;
 356 +}
 357 +
 358 +static int bcm2708_i2s_hw_params(struct snd_pcm_substream *substream,
 359 +                                struct snd_pcm_hw_params *params,
 360 +                                struct snd_soc_dai *dai)
 361 +{
 362 +       struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 363 +
 364 +       unsigned int sampling_rate = params_rate(params);
 365 +       unsigned int data_length, data_delay, bclk_ratio;
 366 +       unsigned int ch1pos, ch2pos, mode, format;
 367 +       unsigned int mash = BCM2708_CLK_MASH_1;
 368 +       unsigned int divi, divf, target_frequency;
 369 +       int clk_src = -1;
 370 +       unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
 371 +       bool bit_master =       (master == SND_SOC_DAIFMT_CBS_CFS
 372 +                                       || master == SND_SOC_DAIFMT_CBS_CFM);
 373 +
 374 +       bool frame_master =     (master == SND_SOC_DAIFMT_CBS_CFS
 375 +                                       || master == SND_SOC_DAIFMT_CBM_CFS);
 376 +       uint32_t csreg;
 377 +
 378 +       /*
 379 +        * If a stream is already enabled,
 380 +        * the registers are already set properly.
 381 +        */
 382 +       regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &csreg);
 383 +
 384 +       if (csreg & (BCM2708_I2S_TXON | BCM2708_I2S_RXON))
 385 +               return 0;
 386 +
 387 +       /*
 388 +        * Adjust the data length according to the format.
 389 +        * We prefill the half frame length with an integer
 390 +        * divider of 2400 as explained at the clock settings.
 391 +        * Maybe it is overwritten there, if the Integer mode
 392 +        * does not apply.
 393 +        */
 394 +       switch (params_format(params)) {
 395 +       case SNDRV_PCM_FORMAT_S16_LE:
 396 +               data_length = 16;
 397 +               bclk_ratio = 40;
 398 +               break;
 399 +       case SNDRV_PCM_FORMAT_S32_LE:
 400 +               data_length = 32;
 401 +               bclk_ratio = 80;
 402 +               break;
 403 +       default:
 404 +               return -EINVAL;
 405 +       }
 406 +
 407 +       /* If bclk_ratio already set, use that one. */
 408 +       if (dev->bclk_ratio)
 409 +               bclk_ratio = dev->bclk_ratio;
 410 +
 411 +       /*
 412 +        * Clock Settings
 413 +        *
 414 +        * The target frequency of the bit clock is
 415 +        *      sampling rate * frame length
 416 +        *
 417 +        * Integer mode:
 418 +        * Sampling rates that are multiples of 8000 kHz
 419 +        * can be driven by the oscillator of 19.2 MHz
 420 +        * with an integer divider as long as the frame length
 421 +        * is an integer divider of 19200000/8000=2400 as set up above.
 422 +        * This is no longer possible if the sampling rate
 423 +        * is too high (e.g. 192 kHz), because the oscillator is too slow.
 424 +        *
 425 +        * MASH mode:
 426 +        * For all other sampling rates, it is not possible to
 427 +        * have an integer divider. Approximate the clock
 428 +        * with the MASH module that induces a slight frequency
 429 +        * variance. To minimize that it is best to have the fastest
 430 +        * clock here. That is PLLD with 500 MHz.
 431 +        */
 432 +       target_frequency = sampling_rate * bclk_ratio;
 433 +       clk_src = BCM2708_CLK_SRC_OSC;
 434 +       mash = BCM2708_CLK_MASH_0;
 435 +
 436 +       if (bcm2708_clk_freq[clk_src] % target_frequency == 0
 437 +                       && bit_master && frame_master) {
 438 +               divi = bcm2708_clk_freq[clk_src] / target_frequency;
 439 +               divf = 0;
 440 +       } else {
 441 +               uint64_t dividend;
 442 +
 443 +               if (!dev->bclk_ratio) {
 444 +                       /*
 445 +                        * Overwrite bclk_ratio, because the
 446 +                        * above trick is not needed or can
 447 +                        * not be used.
 448 +                        */
 449 +                       bclk_ratio = 2 * data_length;
 450 +               }
 451 +
 452 +               target_frequency = sampling_rate * bclk_ratio;
 453 +
 454 +               clk_src = BCM2708_CLK_SRC_PLLD;
 455 +               mash = BCM2708_CLK_MASH_1;
 456 +
 457 +               dividend = bcm2708_clk_freq[clk_src];
 458 +               dividend <<= BCM2708_CLK_SHIFT;
 459 +               do_div(dividend, target_frequency);
 460 +               divi = dividend >> BCM2708_CLK_SHIFT;
 461 +               divf = dividend & BCM2708_CLK_DIVF_MASK;
 462 +       }
 463 +
 464 +       /* Set clock divider */
 465 +       regmap_write(dev->clk_regmap, BCM2708_CLK_PCMDIV_REG, BCM2708_CLK_PASSWD
 466 +                       | BCM2708_CLK_DIVI(divi)
 467 +                       | BCM2708_CLK_DIVF(divf));
 468 +
 469 +       /* Setup clock, but don't start it yet */
 470 +       regmap_write(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, BCM2708_CLK_PASSWD
 471 +                       | BCM2708_CLK_MASH(mash)
 472 +                       | BCM2708_CLK_SRC(clk_src));
 473 +
 474 +       /* Setup the frame format */
 475 +       format = BCM2708_I2S_CHEN;
 476 +
 477 +       if (data_length > 24)
 478 +               format |= BCM2708_I2S_CHWEX;
 479 +
 480 +       format |= BCM2708_I2S_CHWID((data_length-8)&0xf);
 481 +
 482 +       switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 483 +       case SND_SOC_DAIFMT_I2S:
 484 +               data_delay = 1;
 485 +               break;
 486 +       default:
 487 +               /*
 488 +                * TODO
 489 +                * Others are possible but are not implemented at the moment.
 490 +                */
 491 +               dev_err(dev->dev, "%s:bad format\n", __func__);
 492 +               return -EINVAL;
 493 +       }
 494 +
 495 +       ch1pos = data_delay;
 496 +       ch2pos = bclk_ratio / 2 + data_delay;
 497 +
 498 +       switch (params_channels(params)) {
 499 +       case 2:
 500 +               format = BCM2708_I2S_CH1(format) | BCM2708_I2S_CH2(format);
 501 +               format |= BCM2708_I2S_CH1(BCM2708_I2S_CHPOS(ch1pos));
 502 +               format |= BCM2708_I2S_CH2(BCM2708_I2S_CHPOS(ch2pos));
 503 +               break;
 504 +       default:
 505 +               return -EINVAL;
 506 +       }
 507 +
 508 +       /*
 509 +        * Set format for both streams.
 510 +        * We cannot set another frame length
 511 +        * (and therefore word length) anyway,
 512 +        * so the format will be the same.
 513 +        */
 514 +       regmap_write(dev->i2s_regmap, BCM2708_I2S_RXC_A_REG, format);
 515 +       regmap_write(dev->i2s_regmap, BCM2708_I2S_TXC_A_REG, format);
 516 +
 517 +       /* Setup the I2S mode */
 518 +       mode = 0;
 519 +
 520 +       if (data_length <= 16) {
 521 +               /*
 522 +                * Use frame packed mode (2 channels per 32 bit word)
 523 +                * We cannot set another frame length in the second stream
 524 +                * (and therefore word length) anyway,
 525 +                * so the format will be the same.
 526 +                */
 527 +               mode |= BCM2708_I2S_FTXP | BCM2708_I2S_FRXP;
 528 +       }
 529 +
 530 +       mode |= BCM2708_I2S_FLEN(bclk_ratio - 1);
 531 +       mode |= BCM2708_I2S_FSLEN(bclk_ratio / 2);
 532 +
 533 +       /* Master or slave? */
 534 +       switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 535 +       case SND_SOC_DAIFMT_CBS_CFS:
 536 +               /* CPU is master */
 537 +               break;
 538 +       case SND_SOC_DAIFMT_CBM_CFS:
 539 +               /*
 540 +                * CODEC is bit clock master
 541 +                * CPU is frame master
 542 +                */
 543 +               mode |= BCM2708_I2S_CLKM;
 544 +               break;
 545 +       case SND_SOC_DAIFMT_CBS_CFM:
 546 +               /*
 547 +                * CODEC is frame master
 548 +                * CPU is bit clock master
 549 +                */
 550 +               mode |= BCM2708_I2S_FSM;
 551 +               break;
 552 +       case SND_SOC_DAIFMT_CBM_CFM:
 553 +               /* CODEC is master */
 554 +               mode |= BCM2708_I2S_CLKM;
 555 +               mode |= BCM2708_I2S_FSM;
 556 +               break;
 557 +       default:
 558 +               dev_err(dev->dev, "%s:bad master\n", __func__);
 559 +               return -EINVAL;
 560 +       }
 561 +
 562 +       /*
 563 +        * Invert clocks?
 564 +        *
 565 +        * The BCM approach seems to be inverted to the classical I2S approach.
 566 +        */
 567 +       switch (dev->fmt & SND_SOC_DAIFMT_INV_MASK) {
 568 +       case SND_SOC_DAIFMT_NB_NF:
 569 +               /* None. Therefore, both for BCM */
 570 +               mode |= BCM2708_I2S_CLKI;
 571 +               mode |= BCM2708_I2S_FSI;
 572 +               break;
 573 +       case SND_SOC_DAIFMT_IB_IF:
 574 +               /* Both. Therefore, none for BCM */
 575 +               break;
 576 +       case SND_SOC_DAIFMT_NB_IF:
 577 +               /*
 578 +                * Invert only frame sync. Therefore,
 579 +                * invert only bit clock for BCM
 580 +                */
 581 +               mode |= BCM2708_I2S_CLKI;
 582 +               break;
 583 +       case SND_SOC_DAIFMT_IB_NF:
 584 +               /*
 585 +                * Invert only bit clock. Therefore,
 586 +                * invert only frame sync for BCM
 587 +                */
 588 +               mode |= BCM2708_I2S_FSI;
 589 +               break;
 590 +       default:
 591 +               return -EINVAL;
 592 +       }
 593 +
 594 +       regmap_write(dev->i2s_regmap, BCM2708_I2S_MODE_A_REG, mode);
 595 +
 596 +       /* Setup the DMA parameters */
 597 +       regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
 598 +                       BCM2708_I2S_RXTHR(1)
 599 +                       | BCM2708_I2S_TXTHR(1)
 600 +                       | BCM2708_I2S_DMAEN, 0xffffffff);
 601 +
 602 +       regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_DREQ_A_REG,
 603 +                         BCM2708_I2S_TX_PANIC(0x10)
 604 +                       | BCM2708_I2S_RX_PANIC(0x30)
 605 +                       | BCM2708_I2S_TX(0x30)
 606 +                       | BCM2708_I2S_RX(0x20), 0xffffffff);
 607 +
 608 +       /* Clear FIFOs */
 609 +       bcm2708_i2s_clear_fifos(dev, true, true);
 610 +
 611 +       return 0;
 612 +}
 613 +
 614 +static int bcm2708_i2s_prepare(struct snd_pcm_substream *substream,
 615 +               struct snd_soc_dai *dai)
 616 +{
 617 +       struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 618 +       uint32_t cs_reg;
 619 +
 620 +       bcm2708_i2s_start_clock(dev);
 621 +
 622 +       /*
 623 +        * Clear both FIFOs if the one that should be started
 624 +        * is not empty at the moment. This should only happen
 625 +        * after overrun. Otherwise, hw_params would have cleared
 626 +        * the FIFO.
 627 +        */
 628 +       regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &cs_reg);
 629 +
 630 +       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK
 631 +                       && !(cs_reg & BCM2708_I2S_TXE))
 632 +               bcm2708_i2s_clear_fifos(dev, true, false);
 633 +       else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE
 634 +                       && (cs_reg & BCM2708_I2S_RXD))
 635 +               bcm2708_i2s_clear_fifos(dev, false, true);
 636 +
 637 +       return 0;
 638 +}
 639 +
 640 +static void bcm2708_i2s_stop(struct bcm2708_i2s_dev *dev,
 641 +               struct snd_pcm_substream *substream,
 642 +               struct snd_soc_dai *dai)
 643 +{
 644 +       uint32_t mask;
 645 +
 646 +       if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 647 +               mask = BCM2708_I2S_RXON;
 648 +       else
 649 +               mask = BCM2708_I2S_TXON;
 650 +
 651 +       regmap_update_bits(dev->i2s_regmap,
 652 +                       BCM2708_I2S_CS_A_REG, mask, 0);
 653 +
 654 +       /* Stop also the clock when not SND_SOC_DAIFMT_CONT */
 655 +       if (!dai->active && !(dev->fmt & SND_SOC_DAIFMT_CONT))
 656 +               bcm2708_i2s_stop_clock(dev);
 657 +}
 658 +
 659 +static int bcm2708_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 660 +                              struct snd_soc_dai *dai)
 661 +{
 662 +       struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 663 +       uint32_t mask;
 664 +
 665 +       switch (cmd) {
 666 +       case SNDRV_PCM_TRIGGER_START:
 667 +       case SNDRV_PCM_TRIGGER_RESUME:
 668 +       case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 669 +               bcm2708_i2s_start_clock(dev);
 670 +
 671 +               if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 672 +                       mask = BCM2708_I2S_RXON;
 673 +               else
 674 +                       mask = BCM2708_I2S_TXON;
 675 +
 676 +               regmap_update_bits(dev->i2s_regmap,
 677 +                               BCM2708_I2S_CS_A_REG, mask, mask);
 678 +               break;
 679 +
 680 +       case SNDRV_PCM_TRIGGER_STOP:
 681 +       case SNDRV_PCM_TRIGGER_SUSPEND:
 682 +       case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 683 +               bcm2708_i2s_stop(dev, substream, dai);
 684 +               break;
 685 +       default:
 686 +               return -EINVAL;
 687 +       }
 688 +
 689 +       return 0;
 690 +}
 691 +
 692 +static int bcm2708_i2s_startup(struct snd_pcm_substream *substream,
 693 +                              struct snd_soc_dai *dai)
 694 +{
 695 +       struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 696 +
 697 +       if (dai->active)
 698 +               return 0;
 699 +
 700 +       /* Should this still be running stop it */
 701 +       bcm2708_i2s_stop_clock(dev);
 702 +
 703 +       /* Enable PCM block */
 704 +       regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
 705 +                       BCM2708_I2S_EN, BCM2708_I2S_EN);
 706 +
 707 +       /*
 708 +        * Disable STBY.
 709 +        * Requires at least 4 PCM clock cycles to take effect.
 710 +        */
 711 +       regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
 712 +                       BCM2708_I2S_STBY, BCM2708_I2S_STBY);
 713 +
 714 +       return 0;
 715 +}
 716 +
 717 +static void bcm2708_i2s_shutdown(struct snd_pcm_substream *substream,
 718 +               struct snd_soc_dai *dai)
 719 +{
 720 +       struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 721 +
 722 +       bcm2708_i2s_stop(dev, substream, dai);
 723 +
 724 +       /* If both streams are stopped, disable module and clock */
 725 +       if (dai->active)
 726 +               return;
 727 +
 728 +       /* Disable the module */
 729 +       regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
 730 +                       BCM2708_I2S_EN, 0);
 731 +
 732 +       /*
 733 +        * Stopping clock is necessary, because stop does
 734 +        * not stop the clock when SND_SOC_DAIFMT_CONT
 735 +        */
 736 +       bcm2708_i2s_stop_clock(dev);
 737 +}
 738 +
 739 +static const struct snd_soc_dai_ops bcm2708_i2s_dai_ops = {
 740 +       .startup        = bcm2708_i2s_startup,
 741 +       .shutdown       = bcm2708_i2s_shutdown,
 742 +       .prepare        = bcm2708_i2s_prepare,
 743 +       .trigger        = bcm2708_i2s_trigger,
 744 +       .hw_params      = bcm2708_i2s_hw_params,
 745 +       .set_fmt        = bcm2708_i2s_set_dai_fmt,
 746 +       .set_bclk_ratio = bcm2708_i2s_set_dai_bclk_ratio
 747 +};
 748 +
 749 +static int bcm2708_i2s_dai_probe(struct snd_soc_dai *dai)
 750 +{
 751 +       struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 752 +
 753 +       dai->playback_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
 754 +       dai->capture_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_CAPTURE];
 755 +
 756 +       return 0;
 757 +}
 758 +
 759 +static struct snd_soc_dai_driver bcm2708_i2s_dai = {
 760 +       .name   = "bcm2708-i2s",
 761 +       .probe  = bcm2708_i2s_dai_probe,
 762 +       .playback = {
 763 +               .channels_min = 2,
 764 +               .channels_max = 2,
 765 +               .rates =        SNDRV_PCM_RATE_8000_192000,
 766 +               .formats =      SNDRV_PCM_FMTBIT_S16_LE
 767 +                               | SNDRV_PCM_FMTBIT_S32_LE
 768 +               },
 769 +       .capture = {
 770 +               .channels_min = 2,
 771 +               .channels_max = 2,
 772 +               .rates =        SNDRV_PCM_RATE_8000_192000,
 773 +               .formats =      SNDRV_PCM_FMTBIT_S16_LE
 774 +                               | SNDRV_PCM_FMTBIT_S32_LE
 775 +               },
 776 +       .ops = &bcm2708_i2s_dai_ops,
 777 +       .symmetric_rates = 1
 778 +};
 779 +
 780 +static bool bcm2708_i2s_volatile_reg(struct device *dev, unsigned int reg)
 781 +{
 782 +       switch (reg) {
 783 +       case BCM2708_I2S_CS_A_REG:
 784 +       case BCM2708_I2S_FIFO_A_REG:
 785 +       case BCM2708_I2S_INTSTC_A_REG:
 786 +       case BCM2708_I2S_GRAY_REG:
 787 +               return true;
 788 +       default:
 789 +               return false;
 790 +       };
 791 +}
 792 +
 793 +static bool bcm2708_i2s_precious_reg(struct device *dev, unsigned int reg)
 794 +{
 795 +       switch (reg) {
 796 +       case BCM2708_I2S_FIFO_A_REG:
 797 +               return true;
 798 +       default:
 799 +               return false;
 800 +       };
 801 +}
 802 +
 803 +static bool bcm2708_clk_volatile_reg(struct device *dev, unsigned int reg)
 804 +{
 805 +       switch (reg) {
 806 +       case BCM2708_CLK_PCMCTL_REG:
 807 +               return true;
 808 +       default:
 809 +               return false;
 810 +       };
 811 +}
 812 +
 813 +static const struct regmap_config bcm2708_regmap_config[] = {
 814 +       {
 815 +               .reg_bits = 32,
 816 +               .reg_stride = 4,
 817 +               .val_bits = 32,
 818 +               .max_register = BCM2708_I2S_GRAY_REG,
 819 +               .precious_reg = bcm2708_i2s_precious_reg,
 820 +               .volatile_reg = bcm2708_i2s_volatile_reg,
 821 +               .cache_type = REGCACHE_RBTREE,
 822 +       },
 823 +       {
 824 +               .reg_bits = 32,
 825 +               .reg_stride = 4,
 826 +               .val_bits = 32,
 827 +               .max_register = BCM2708_CLK_PCMDIV_REG,
 828 +               .volatile_reg = bcm2708_clk_volatile_reg,
 829 +               .cache_type = REGCACHE_RBTREE,
 830 +       },
 831 +};
 832 +
 833 +static const struct snd_soc_component_driver bcm2708_i2s_component = {
 834 +       .name           = "bcm2708-i2s-comp",
 835 +};
 836 +
 837 +
 838 +static void bcm2708_i2s_setup_gpio(void)
 839 +{
 840 +       /*
 841 +        * This is the common way to handle the GPIO pins for
 842 +        * the Raspberry Pi.
 843 +        * TODO Better way would be to handle
 844 +        * this in the device tree!
 845 +        */
 846 +#define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3))
 847 +#define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3))
 848 +
 849 +       unsigned int *gpio;
 850 +       int pin;
 851 +       gpio = ioremap(GPIO_BASE, SZ_16K);
 852 +
 853 +       /* SPI is on GPIO 7..11 */
 854 +       for (pin = 28; pin <= 31; pin++) {
 855 +               INP_GPIO(pin);          /* set mode to GPIO input first */
 856 +               SET_GPIO_ALT(pin, 2);   /* set mode to ALT 0 */
 857 +       }
 858 +#undef INP_GPIO
 859 +#undef SET_GPIO_ALT
 860 +}
 861 +
 862 +static const struct snd_pcm_hardware bcm2708_pcm_hardware = {
 863 +       .info                   = SNDRV_PCM_INFO_MMAP |
 864 +                                 SNDRV_PCM_INFO_MMAP_VALID |
 865 +                                 SNDRV_PCM_INFO_INTERLEAVED |
 866 +                                 SNDRV_PCM_INFO_JOINT_DUPLEX,
 867 +       .formats                = SNDRV_PCM_FMTBIT_S16_LE |
 868 +                                 SNDRV_PCM_FMTBIT_S32_LE,
 869 +       .period_bytes_min       = 32,
 870 +       .period_bytes_max       = 64 * PAGE_SIZE,
 871 +       .periods_min            = 2,
 872 +       .periods_max            = 255,
 873 +       .buffer_bytes_max       = 128 * PAGE_SIZE,
 874 +};
 875 +
 876 +static const struct snd_dmaengine_pcm_config bcm2708_dmaengine_pcm_config = {
 877 +       .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
 878 +       .pcm_hardware = &bcm2708_pcm_hardware,
 879 +       .prealloc_buffer_size = 256 * PAGE_SIZE,
 880 +};
 881 +
 882 +
 883 +static int bcm2708_i2s_probe(struct platform_device *pdev)
 884 +{
 885 +       struct bcm2708_i2s_dev *dev;
 886 +       int i;
 887 +       int ret;
 888 +       struct regmap *regmap[2];
 889 +       struct resource *mem[2];
 890 +
 891 +       /* Request both ioareas */
 892 +       for (i = 0; i <= 1; i++) {
 893 +               void __iomem *base;
 894 +
 895 +               mem[i] = platform_get_resource(pdev, IORESOURCE_MEM, i);
 896 +               base = devm_ioremap_resource(&pdev->dev, mem[i]);
 897 +               if (IS_ERR(base))
 898 +                       return PTR_ERR(base);
 899 +
 900 +               regmap[i] = devm_regmap_init_mmio(&pdev->dev, base,
 901 +                                           &bcm2708_regmap_config[i]);
 902 +               if (IS_ERR(regmap[i])) {
 903 +                       dev_err(&pdev->dev, "I2S probe: regmap init failed\n");
 904 +                       return PTR_ERR(regmap[i]);
 905 +               }
 906 +       }
 907 +
 908 +       dev = devm_kzalloc(&pdev->dev, sizeof(*dev),
 909 +                          GFP_KERNEL);
 910 +       if (IS_ERR(dev))
 911 +               return PTR_ERR(dev);
 912 +
 913 +       bcm2708_i2s_setup_gpio();
 914 +
 915 +       dev->i2s_regmap = regmap[0];
 916 +       dev->clk_regmap = regmap[1];
 917 +
 918 +       /* Set the DMA address */
 919 +       dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr =
 920 +               (dma_addr_t)BCM2708_I2S_FIFO_PHYSICAL_ADDR;
 921 +
 922 +       dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr =
 923 +               (dma_addr_t)BCM2708_I2S_FIFO_PHYSICAL_ADDR;
 924 +
 925 +       /* Set the DREQ */
 926 +       dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].slave_id =
 927 +               BCM2708_DMA_DREQ_PCM_TX;
 928 +       dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].slave_id =
 929 +               BCM2708_DMA_DREQ_PCM_RX;
 930 +
 931 +       /* Set the bus width */
 932 +       dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr_width =
 933 +               DMA_SLAVE_BUSWIDTH_4_BYTES;
 934 +       dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr_width =
 935 +               DMA_SLAVE_BUSWIDTH_4_BYTES;
 936 +
 937 +       /* Set burst */
 938 +       dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].maxburst = 2;
 939 +       dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].maxburst = 2;
 940 +
 941 +       /* BCLK ratio - use default */
 942 +       dev->bclk_ratio = 0;
 943 +
 944 +       /* Store the pdev */
 945 +       dev->dev = &pdev->dev;
 946 +       dev_set_drvdata(&pdev->dev, dev);
 947 +
 948 +       ret = snd_soc_register_component(&pdev->dev,
 949 +                       &bcm2708_i2s_component, &bcm2708_i2s_dai, 1);
 950 +
 951 +       if (ret) {
 952 +               dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
 953 +               ret = -ENOMEM;
 954 +               return ret;
 955 +       }
 956 +
 957 +       ret = snd_dmaengine_pcm_register(&pdev->dev,
 958 +                               &bcm2708_dmaengine_pcm_config,
 959 +                               SND_DMAENGINE_PCM_FLAG_COMPAT);
 960 +       if (ret) {
 961 +               dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
 962 +               snd_soc_unregister_component(&pdev->dev);
 963 +               return ret;
 964 +       }
 965 +
 966 +       return 0;
 967 +}
 968 +
 969 +static int bcm2708_i2s_remove(struct platform_device *pdev)
 970 +{
 971 +       snd_dmaengine_pcm_unregister(&pdev->dev);
 972 +       snd_soc_unregister_component(&pdev->dev);
 973 +       return 0;
 974 +}
 975 +
 976 +static struct platform_driver bcm2708_i2s_driver = {
 977 +       .probe          = bcm2708_i2s_probe,
 978 +       .remove         = bcm2708_i2s_remove,
 979 +       .driver         = {
 980 +               .name   = "bcm2708-i2s",
 981 +               .owner  = THIS_MODULE,
 982 +       },
 983 +};
 984 +
 985 +module_platform_driver(bcm2708_i2s_driver);
 986 +
 987 +MODULE_ALIAS("platform:bcm2708-i2s");
 988 +MODULE_DESCRIPTION("BCM2708 I2S interface");
 989 +MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
 990 +MODULE_LICENSE("GPL v2");