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[openwrt/openwrt.git] / target / linux / brcm2708 / patches-3.14 / 0034-ASoC-Add-support-for-BCM2708.patch
1 From 8b7d5e646f5b71b22894623419202c9e8c739b2a Mon Sep 17 00:00:00 2001
2 From: Florian Meier <florian.meier@koalo.de>
3 Date: Fri, 22 Nov 2013 14:33:38 +0100
4 Subject: [PATCH 34/54] ASoC: Add support for BCM2708
5
6 This driver adds support for digital audio (I2S)
7 for the BCM2708 SoC that is used by the
8 Raspberry Pi. External audio codecs can be
9 connected to the Raspberry Pi via P5 header.
10
11 It relies on cyclic DMA engine support for BCM2708.
12
13 Signed-off-by: Florian Meier <florian.meier@koalo.de>
14 ---
15 sound/soc/bcm/Kconfig | 11 +
16 sound/soc/bcm/Makefile | 4 +
17 sound/soc/bcm/bcm2708-i2s.c | 940 ++++++++++++++++++++++++++++++++++++++++++++
18 3 files changed, 955 insertions(+)
19 create mode 100644 sound/soc/bcm/bcm2708-i2s.c
20
21 diff --git a/sound/soc/bcm/Kconfig b/sound/soc/bcm/Kconfig
22 index 6a834e1..7e5b945 100644
23 --- a/sound/soc/bcm/Kconfig
24 +++ b/sound/soc/bcm/Kconfig
25 @@ -7,3 +7,14 @@ config SND_BCM2835_SOC_I2S
26 Say Y or M if you want to add support for codecs attached to
27 the BCM2835 I2S interface. You will also need
28 to select the audio interfaces to support below.
29 +
30 +config SND_BCM2708_SOC_I2S
31 + tristate "SoC Audio support for the Broadcom BCM2708 I2S module"
32 + depends on MACH_BCM2708
33 + select REGMAP_MMIO
34 + select SND_SOC_DMAENGINE_PCM
35 + select SND_SOC_GENERIC_DMAENGINE_PCM
36 + help
37 + Say Y or M if you want to add support for codecs attached to
38 + the BCM2708 I2S interface. You will also need
39 + to select the audio interfaces to support below.
40 diff --git a/sound/soc/bcm/Makefile b/sound/soc/bcm/Makefile
41 index bc816b7..f8bbe1f 100644
42 --- a/sound/soc/bcm/Makefile
43 +++ b/sound/soc/bcm/Makefile
44 @@ -3,3 +3,7 @@ snd-soc-bcm2835-i2s-objs := bcm2835-i2s.o
45
46 obj-$(CONFIG_SND_BCM2835_SOC_I2S) += snd-soc-bcm2835-i2s.o
47
48 +# BCM2708 Platform Support
49 +snd-soc-bcm2708-i2s-objs := bcm2708-i2s.o
50 +
51 +obj-$(CONFIG_SND_BCM2708_SOC_I2S) += snd-soc-bcm2708-i2s.o
52 diff --git a/sound/soc/bcm/bcm2708-i2s.c b/sound/soc/bcm/bcm2708-i2s.c
53 new file mode 100644
54 index 0000000..ebaf3d6
55 --- /dev/null
56 +++ b/sound/soc/bcm/bcm2708-i2s.c
57 @@ -0,0 +1,940 @@
58 +/*
59 + * ALSA SoC I2S Audio Layer for Broadcom BCM2708 SoC
60 + *
61 + * Author: Florian Meier <florian.meier@koalo.de>
62 + * Copyright 2013
63 + *
64 + * Based on
65 + * Raspberry Pi PCM I2S ALSA Driver
66 + * Copyright (c) by Phil Poole 2013
67 + *
68 + * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
69 + * Vladimir Barinov, <vbarinov@embeddedalley.com>
70 + * Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com>
71 + *
72 + * OMAP ALSA SoC DAI driver using McBSP port
73 + * Copyright (C) 2008 Nokia Corporation
74 + * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
75 + * Peter Ujfalusi <peter.ujfalusi@ti.com>
76 + *
77 + * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
78 + * Author: Timur Tabi <timur@freescale.com>
79 + * Copyright 2007-2010 Freescale Semiconductor, Inc.
80 + *
81 + * This program is free software; you can redistribute it and/or
82 + * modify it under the terms of the GNU General Public License
83 + * version 2 as published by the Free Software Foundation.
84 + *
85 + * This program is distributed in the hope that it will be useful, but
86 + * WITHOUT ANY WARRANTY; without even the implied warranty of
87 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
88 + * General Public License for more details.
89 + */
90 +
91 +#include <linux/init.h>
92 +#include <linux/module.h>
93 +#include <linux/device.h>
94 +#include <linux/slab.h>
95 +#include <linux/delay.h>
96 +#include <linux/io.h>
97 +#include <linux/clk.h>
98 +
99 +#include <sound/core.h>
100 +#include <sound/pcm.h>
101 +#include <sound/pcm_params.h>
102 +#include <sound/initval.h>
103 +#include <sound/soc.h>
104 +#include <sound/dmaengine_pcm.h>
105 +
106 +/* Clock registers */
107 +#define BCM2708_CLK_PCMCTL_REG 0x00
108 +#define BCM2708_CLK_PCMDIV_REG 0x04
109 +
110 +/* Clock register settings */
111 +#define BCM2708_CLK_PASSWD (0x5a000000)
112 +#define BCM2708_CLK_PASSWD_MASK (0xff000000)
113 +#define BCM2708_CLK_MASH(v) ((v) << 9)
114 +#define BCM2708_CLK_FLIP BIT(8)
115 +#define BCM2708_CLK_BUSY BIT(7)
116 +#define BCM2708_CLK_KILL BIT(5)
117 +#define BCM2708_CLK_ENAB BIT(4)
118 +#define BCM2708_CLK_SRC(v) (v)
119 +
120 +#define BCM2708_CLK_SHIFT (12)
121 +#define BCM2708_CLK_DIVI(v) ((v) << BCM2708_CLK_SHIFT)
122 +#define BCM2708_CLK_DIVF(v) (v)
123 +#define BCM2708_CLK_DIVF_MASK (0xFFF)
124 +
125 +enum {
126 + BCM2708_CLK_MASH_0 = 0,
127 + BCM2708_CLK_MASH_1,
128 + BCM2708_CLK_MASH_2,
129 + BCM2708_CLK_MASH_3,
130 +};
131 +
132 +enum {
133 + BCM2708_CLK_SRC_GND = 0,
134 + BCM2708_CLK_SRC_OSC,
135 + BCM2708_CLK_SRC_DBG0,
136 + BCM2708_CLK_SRC_DBG1,
137 + BCM2708_CLK_SRC_PLLA,
138 + BCM2708_CLK_SRC_PLLC,
139 + BCM2708_CLK_SRC_PLLD,
140 + BCM2708_CLK_SRC_HDMI,
141 +};
142 +
143 +/* Most clocks are not useable (freq = 0) */
144 +static const unsigned int bcm2708_clk_freq[BCM2708_CLK_SRC_HDMI+1] = {
145 + [BCM2708_CLK_SRC_GND] = 0,
146 + [BCM2708_CLK_SRC_OSC] = 19200000,
147 + [BCM2708_CLK_SRC_DBG0] = 0,
148 + [BCM2708_CLK_SRC_DBG1] = 0,
149 + [BCM2708_CLK_SRC_PLLA] = 0,
150 + [BCM2708_CLK_SRC_PLLC] = 0,
151 + [BCM2708_CLK_SRC_PLLD] = 500000000,
152 + [BCM2708_CLK_SRC_HDMI] = 0,
153 +};
154 +
155 +/* I2S registers */
156 +#define BCM2708_I2S_CS_A_REG 0x00
157 +#define BCM2708_I2S_FIFO_A_REG 0x04
158 +#define BCM2708_I2S_MODE_A_REG 0x08
159 +#define BCM2708_I2S_RXC_A_REG 0x0c
160 +#define BCM2708_I2S_TXC_A_REG 0x10
161 +#define BCM2708_I2S_DREQ_A_REG 0x14
162 +#define BCM2708_I2S_INTEN_A_REG 0x18
163 +#define BCM2708_I2S_INTSTC_A_REG 0x1c
164 +#define BCM2708_I2S_GRAY_REG 0x20
165 +
166 +/* I2S register settings */
167 +#define BCM2708_I2S_STBY BIT(25)
168 +#define BCM2708_I2S_SYNC BIT(24)
169 +#define BCM2708_I2S_RXSEX BIT(23)
170 +#define BCM2708_I2S_RXF BIT(22)
171 +#define BCM2708_I2S_TXE BIT(21)
172 +#define BCM2708_I2S_RXD BIT(20)
173 +#define BCM2708_I2S_TXD BIT(19)
174 +#define BCM2708_I2S_RXR BIT(18)
175 +#define BCM2708_I2S_TXW BIT(17)
176 +#define BCM2708_I2S_CS_RXERR BIT(16)
177 +#define BCM2708_I2S_CS_TXERR BIT(15)
178 +#define BCM2708_I2S_RXSYNC BIT(14)
179 +#define BCM2708_I2S_TXSYNC BIT(13)
180 +#define BCM2708_I2S_DMAEN BIT(9)
181 +#define BCM2708_I2S_RXTHR(v) ((v) << 7)
182 +#define BCM2708_I2S_TXTHR(v) ((v) << 5)
183 +#define BCM2708_I2S_RXCLR BIT(4)
184 +#define BCM2708_I2S_TXCLR BIT(3)
185 +#define BCM2708_I2S_TXON BIT(2)
186 +#define BCM2708_I2S_RXON BIT(1)
187 +#define BCM2708_I2S_EN (1)
188 +
189 +#define BCM2708_I2S_CLKDIS BIT(28)
190 +#define BCM2708_I2S_PDMN BIT(27)
191 +#define BCM2708_I2S_PDME BIT(26)
192 +#define BCM2708_I2S_FRXP BIT(25)
193 +#define BCM2708_I2S_FTXP BIT(24)
194 +#define BCM2708_I2S_CLKM BIT(23)
195 +#define BCM2708_I2S_CLKI BIT(22)
196 +#define BCM2708_I2S_FSM BIT(21)
197 +#define BCM2708_I2S_FSI BIT(20)
198 +#define BCM2708_I2S_FLEN(v) ((v) << 10)
199 +#define BCM2708_I2S_FSLEN(v) (v)
200 +
201 +#define BCM2708_I2S_CHWEX BIT(15)
202 +#define BCM2708_I2S_CHEN BIT(14)
203 +#define BCM2708_I2S_CHPOS(v) ((v) << 4)
204 +#define BCM2708_I2S_CHWID(v) (v)
205 +#define BCM2708_I2S_CH1(v) ((v) << 16)
206 +#define BCM2708_I2S_CH2(v) (v)
207 +
208 +#define BCM2708_I2S_TX_PANIC(v) ((v) << 24)
209 +#define BCM2708_I2S_RX_PANIC(v) ((v) << 16)
210 +#define BCM2708_I2S_TX(v) ((v) << 8)
211 +#define BCM2708_I2S_RX(v) (v)
212 +
213 +#define BCM2708_I2S_INT_RXERR BIT(3)
214 +#define BCM2708_I2S_INT_TXERR BIT(2)
215 +#define BCM2708_I2S_INT_RXR BIT(1)
216 +#define BCM2708_I2S_INT_TXW BIT(0)
217 +
218 +/* I2S DMA interface */
219 +#define BCM2708_I2S_FIFO_PHYSICAL_ADDR 0x7E203004
220 +#define BCM2708_DMA_DREQ_PCM_TX 2
221 +#define BCM2708_DMA_DREQ_PCM_RX 3
222 +
223 +/* General device struct */
224 +struct bcm2708_i2s_dev {
225 + struct device *dev;
226 + struct snd_dmaengine_dai_dma_data dma_data[2];
227 + unsigned int fmt;
228 + unsigned int bclk_ratio;
229 +
230 + struct regmap *i2s_regmap;
231 + struct regmap *clk_regmap;
232 +};
233 +
234 +static void bcm2708_i2s_start_clock(struct bcm2708_i2s_dev *dev)
235 +{
236 + /* Start the clock if in master mode */
237 + unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
238 +
239 + switch (master) {
240 + case SND_SOC_DAIFMT_CBS_CFS:
241 + case SND_SOC_DAIFMT_CBS_CFM:
242 + regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG,
243 + BCM2708_CLK_PASSWD_MASK | BCM2708_CLK_ENAB,
244 + BCM2708_CLK_PASSWD | BCM2708_CLK_ENAB);
245 + break;
246 + default:
247 + break;
248 + }
249 +}
250 +
251 +static void bcm2708_i2s_stop_clock(struct bcm2708_i2s_dev *dev)
252 +{
253 + uint32_t clkreg;
254 + int timeout = 1000;
255 +
256 + /* Stop clock */
257 + regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG,
258 + BCM2708_CLK_PASSWD_MASK | BCM2708_CLK_ENAB,
259 + BCM2708_CLK_PASSWD);
260 +
261 + /* Wait for the BUSY flag going down */
262 + while (--timeout) {
263 + regmap_read(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, &clkreg);
264 + if (!(clkreg & BCM2708_CLK_BUSY))
265 + break;
266 + }
267 +
268 + if (!timeout) {
269 + /* KILL the clock */
270 + dev_err(dev->dev, "I2S clock didn't stop. Kill the clock!\n");
271 + regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG,
272 + BCM2708_CLK_KILL | BCM2708_CLK_PASSWD_MASK,
273 + BCM2708_CLK_KILL | BCM2708_CLK_PASSWD);
274 + }
275 +}
276 +
277 +static void bcm2708_i2s_clear_fifos(struct bcm2708_i2s_dev *dev,
278 + bool tx, bool rx)
279 +{
280 + int timeout = 1000;
281 + uint32_t syncval;
282 + uint32_t csreg;
283 + uint32_t i2s_active_state;
284 + uint32_t clkreg;
285 + uint32_t clk_active_state;
286 + uint32_t off;
287 + uint32_t clr;
288 +
289 + off = tx ? BCM2708_I2S_TXON : 0;
290 + off |= rx ? BCM2708_I2S_RXON : 0;
291 +
292 + clr = tx ? BCM2708_I2S_TXCLR : 0;
293 + clr |= rx ? BCM2708_I2S_RXCLR : 0;
294 +
295 + /* Backup the current state */
296 + regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &csreg);
297 + i2s_active_state = csreg & (BCM2708_I2S_RXON | BCM2708_I2S_TXON);
298 +
299 + regmap_read(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, &clkreg);
300 + clk_active_state = clkreg & BCM2708_CLK_ENAB;
301 +
302 + /* Start clock if not running */
303 + if (!clk_active_state) {
304 + regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG,
305 + BCM2708_CLK_PASSWD_MASK | BCM2708_CLK_ENAB,
306 + BCM2708_CLK_PASSWD | BCM2708_CLK_ENAB);
307 + }
308 +
309 + /* Stop I2S module */
310 + regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, off, 0);
311 +
312 + /*
313 + * Clear the FIFOs
314 + * Requires at least 2 PCM clock cycles to take effect
315 + */
316 + regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, clr, clr);
317 +
318 + /* Wait for 2 PCM clock cycles */
319 +
320 + /*
321 + * Toggle the SYNC flag. After 2 PCM clock cycles it can be read back
322 + * FIXME: This does not seem to work for slave mode!
323 + */
324 + regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &syncval);
325 + syncval &= BCM2708_I2S_SYNC;
326 +
327 + regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
328 + BCM2708_I2S_SYNC, ~syncval);
329 +
330 + /* Wait for the SYNC flag changing it's state */
331 + while (--timeout) {
332 + regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &csreg);
333 + if ((csreg & BCM2708_I2S_SYNC) != syncval)
334 + break;
335 + }
336 +
337 + if (!timeout)
338 + dev_err(dev->dev, "I2S SYNC error!\n");
339 +
340 + /* Stop clock if it was not running before */
341 + if (!clk_active_state)
342 + bcm2708_i2s_stop_clock(dev);
343 +
344 + /* Restore I2S state */
345 + regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
346 + BCM2708_I2S_RXON | BCM2708_I2S_TXON, i2s_active_state);
347 +}
348 +
349 +static int bcm2708_i2s_set_dai_fmt(struct snd_soc_dai *dai,
350 + unsigned int fmt)
351 +{
352 + struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
353 + dev->fmt = fmt;
354 + return 0;
355 +}
356 +
357 +static int bcm2708_i2s_set_dai_bclk_ratio(struct snd_soc_dai *dai,
358 + unsigned int ratio)
359 +{
360 + struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
361 + dev->bclk_ratio = ratio;
362 + return 0;
363 +}
364 +
365 +static int bcm2708_i2s_hw_params(struct snd_pcm_substream *substream,
366 + struct snd_pcm_hw_params *params,
367 + struct snd_soc_dai *dai)
368 +{
369 + struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
370 +
371 + unsigned int sampling_rate = params_rate(params);
372 + unsigned int data_length, data_delay, bclk_ratio;
373 + unsigned int ch1pos, ch2pos, mode, format;
374 + unsigned int mash = BCM2708_CLK_MASH_1;
375 + unsigned int divi, divf, target_frequency;
376 + int clk_src = -1;
377 + unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
378 + bool bit_master = (master == SND_SOC_DAIFMT_CBS_CFS
379 + || master == SND_SOC_DAIFMT_CBS_CFM);
380 +
381 + bool frame_master = (master == SND_SOC_DAIFMT_CBS_CFS
382 + || master == SND_SOC_DAIFMT_CBM_CFS);
383 + uint32_t csreg;
384 +
385 + /*
386 + * If a stream is already enabled,
387 + * the registers are already set properly.
388 + */
389 + regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &csreg);
390 +
391 + if (csreg & (BCM2708_I2S_TXON | BCM2708_I2S_RXON))
392 + return 0;
393 +
394 + /*
395 + * Adjust the data length according to the format.
396 + * We prefill the half frame length with an integer
397 + * divider of 2400 as explained at the clock settings.
398 + * Maybe it is overwritten there, if the Integer mode
399 + * does not apply.
400 + */
401 + switch (params_format(params)) {
402 + case SNDRV_PCM_FORMAT_S16_LE:
403 + data_length = 16;
404 + bclk_ratio = 40;
405 + break;
406 + case SNDRV_PCM_FORMAT_S32_LE:
407 + data_length = 32;
408 + bclk_ratio = 80;
409 + break;
410 + default:
411 + return -EINVAL;
412 + }
413 +
414 + /* If bclk_ratio already set, use that one. */
415 + if (dev->bclk_ratio)
416 + bclk_ratio = dev->bclk_ratio;
417 +
418 + /*
419 + * Clock Settings
420 + *
421 + * The target frequency of the bit clock is
422 + * sampling rate * frame length
423 + *
424 + * Integer mode:
425 + * Sampling rates that are multiples of 8000 kHz
426 + * can be driven by the oscillator of 19.2 MHz
427 + * with an integer divider as long as the frame length
428 + * is an integer divider of 19200000/8000=2400 as set up above.
429 + * This is no longer possible if the sampling rate
430 + * is too high (e.g. 192 kHz), because the oscillator is too slow.
431 + *
432 + * MASH mode:
433 + * For all other sampling rates, it is not possible to
434 + * have an integer divider. Approximate the clock
435 + * with the MASH module that induces a slight frequency
436 + * variance. To minimize that it is best to have the fastest
437 + * clock here. That is PLLD with 500 MHz.
438 + */
439 + target_frequency = sampling_rate * bclk_ratio;
440 + clk_src = BCM2708_CLK_SRC_OSC;
441 + mash = BCM2708_CLK_MASH_0;
442 +
443 + if (bcm2708_clk_freq[clk_src] % target_frequency == 0
444 + && bit_master && frame_master) {
445 + divi = bcm2708_clk_freq[clk_src] / target_frequency;
446 + divf = 0;
447 + } else {
448 + uint64_t dividend;
449 +
450 + if (!dev->bclk_ratio) {
451 + /*
452 + * Overwrite bclk_ratio, because the
453 + * above trick is not needed or can
454 + * not be used.
455 + */
456 + bclk_ratio = 2 * data_length;
457 + }
458 +
459 + target_frequency = sampling_rate * bclk_ratio;
460 +
461 + clk_src = BCM2708_CLK_SRC_PLLD;
462 + mash = BCM2708_CLK_MASH_1;
463 +
464 + dividend = bcm2708_clk_freq[clk_src];
465 + dividend <<= BCM2708_CLK_SHIFT;
466 + do_div(dividend, target_frequency);
467 + divi = dividend >> BCM2708_CLK_SHIFT;
468 + divf = dividend & BCM2708_CLK_DIVF_MASK;
469 + }
470 +
471 + /* Set clock divider */
472 + regmap_write(dev->clk_regmap, BCM2708_CLK_PCMDIV_REG, BCM2708_CLK_PASSWD
473 + | BCM2708_CLK_DIVI(divi)
474 + | BCM2708_CLK_DIVF(divf));
475 +
476 + /* Setup clock, but don't start it yet */
477 + regmap_write(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, BCM2708_CLK_PASSWD
478 + | BCM2708_CLK_MASH(mash)
479 + | BCM2708_CLK_SRC(clk_src));
480 +
481 + /* Setup the frame format */
482 + format = BCM2708_I2S_CHEN;
483 +
484 + if (data_length > 24)
485 + format |= BCM2708_I2S_CHWEX;
486 +
487 + format |= BCM2708_I2S_CHWID((data_length-8)&0xf);
488 +
489 + switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
490 + case SND_SOC_DAIFMT_I2S:
491 + data_delay = 1;
492 + break;
493 + default:
494 + /*
495 + * TODO
496 + * Others are possible but are not implemented at the moment.
497 + */
498 + dev_err(dev->dev, "%s:bad format\n", __func__);
499 + return -EINVAL;
500 + }
501 +
502 + ch1pos = data_delay;
503 + ch2pos = bclk_ratio / 2 + data_delay;
504 +
505 + switch (params_channels(params)) {
506 + case 2:
507 + format = BCM2708_I2S_CH1(format) | BCM2708_I2S_CH2(format);
508 + format |= BCM2708_I2S_CH1(BCM2708_I2S_CHPOS(ch1pos));
509 + format |= BCM2708_I2S_CH2(BCM2708_I2S_CHPOS(ch2pos));
510 + break;
511 + default:
512 + return -EINVAL;
513 + }
514 +
515 + /*
516 + * Set format for both streams.
517 + * We cannot set another frame length
518 + * (and therefore word length) anyway,
519 + * so the format will be the same.
520 + */
521 + regmap_write(dev->i2s_regmap, BCM2708_I2S_RXC_A_REG, format);
522 + regmap_write(dev->i2s_regmap, BCM2708_I2S_TXC_A_REG, format);
523 +
524 + /* Setup the I2S mode */
525 + mode = 0;
526 +
527 + if (data_length <= 16) {
528 + /*
529 + * Use frame packed mode (2 channels per 32 bit word)
530 + * We cannot set another frame length in the second stream
531 + * (and therefore word length) anyway,
532 + * so the format will be the same.
533 + */
534 + mode |= BCM2708_I2S_FTXP | BCM2708_I2S_FRXP;
535 + }
536 +
537 + mode |= BCM2708_I2S_FLEN(bclk_ratio - 1);
538 + mode |= BCM2708_I2S_FSLEN(bclk_ratio / 2);
539 +
540 + /* Master or slave? */
541 + switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
542 + case SND_SOC_DAIFMT_CBS_CFS:
543 + /* CPU is master */
544 + break;
545 + case SND_SOC_DAIFMT_CBM_CFS:
546 + /*
547 + * CODEC is bit clock master
548 + * CPU is frame master
549 + */
550 + mode |= BCM2708_I2S_CLKM;
551 + break;
552 + case SND_SOC_DAIFMT_CBS_CFM:
553 + /*
554 + * CODEC is frame master
555 + * CPU is bit clock master
556 + */
557 + mode |= BCM2708_I2S_FSM;
558 + break;
559 + case SND_SOC_DAIFMT_CBM_CFM:
560 + /* CODEC is master */
561 + mode |= BCM2708_I2S_CLKM;
562 + mode |= BCM2708_I2S_FSM;
563 + break;
564 + default:
565 + dev_err(dev->dev, "%s:bad master\n", __func__);
566 + return -EINVAL;
567 + }
568 +
569 + /*
570 + * Invert clocks?
571 + *
572 + * The BCM approach seems to be inverted to the classical I2S approach.
573 + */
574 + switch (dev->fmt & SND_SOC_DAIFMT_INV_MASK) {
575 + case SND_SOC_DAIFMT_NB_NF:
576 + /* None. Therefore, both for BCM */
577 + mode |= BCM2708_I2S_CLKI;
578 + mode |= BCM2708_I2S_FSI;
579 + break;
580 + case SND_SOC_DAIFMT_IB_IF:
581 + /* Both. Therefore, none for BCM */
582 + break;
583 + case SND_SOC_DAIFMT_NB_IF:
584 + /*
585 + * Invert only frame sync. Therefore,
586 + * invert only bit clock for BCM
587 + */
588 + mode |= BCM2708_I2S_CLKI;
589 + break;
590 + case SND_SOC_DAIFMT_IB_NF:
591 + /*
592 + * Invert only bit clock. Therefore,
593 + * invert only frame sync for BCM
594 + */
595 + mode |= BCM2708_I2S_FSI;
596 + break;
597 + default:
598 + return -EINVAL;
599 + }
600 +
601 + regmap_write(dev->i2s_regmap, BCM2708_I2S_MODE_A_REG, mode);
602 +
603 + /* Setup the DMA parameters */
604 + regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
605 + BCM2708_I2S_RXTHR(1)
606 + | BCM2708_I2S_TXTHR(1)
607 + | BCM2708_I2S_DMAEN, 0xffffffff);
608 +
609 + regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_DREQ_A_REG,
610 + BCM2708_I2S_TX_PANIC(0x10)
611 + | BCM2708_I2S_RX_PANIC(0x30)
612 + | BCM2708_I2S_TX(0x30)
613 + | BCM2708_I2S_RX(0x20), 0xffffffff);
614 +
615 + /* Clear FIFOs */
616 + bcm2708_i2s_clear_fifos(dev, true, true);
617 +
618 + return 0;
619 +}
620 +
621 +static int bcm2708_i2s_prepare(struct snd_pcm_substream *substream,
622 + struct snd_soc_dai *dai)
623 +{
624 + struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
625 + uint32_t cs_reg;
626 +
627 + bcm2708_i2s_start_clock(dev);
628 +
629 + /*
630 + * Clear both FIFOs if the one that should be started
631 + * is not empty at the moment. This should only happen
632 + * after overrun. Otherwise, hw_params would have cleared
633 + * the FIFO.
634 + */
635 + regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &cs_reg);
636 +
637 + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK
638 + && !(cs_reg & BCM2708_I2S_TXE))
639 + bcm2708_i2s_clear_fifos(dev, true, false);
640 + else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE
641 + && (cs_reg & BCM2708_I2S_RXD))
642 + bcm2708_i2s_clear_fifos(dev, false, true);
643 +
644 + return 0;
645 +}
646 +
647 +static void bcm2708_i2s_stop(struct bcm2708_i2s_dev *dev,
648 + struct snd_pcm_substream *substream,
649 + struct snd_soc_dai *dai)
650 +{
651 + uint32_t mask;
652 +
653 + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
654 + mask = BCM2708_I2S_RXON;
655 + else
656 + mask = BCM2708_I2S_TXON;
657 +
658 + regmap_update_bits(dev->i2s_regmap,
659 + BCM2708_I2S_CS_A_REG, mask, 0);
660 +
661 + /* Stop also the clock when not SND_SOC_DAIFMT_CONT */
662 + if (!dai->active && !(dev->fmt & SND_SOC_DAIFMT_CONT))
663 + bcm2708_i2s_stop_clock(dev);
664 +}
665 +
666 +static int bcm2708_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
667 + struct snd_soc_dai *dai)
668 +{
669 + struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
670 + uint32_t mask;
671 +
672 + switch (cmd) {
673 + case SNDRV_PCM_TRIGGER_START:
674 + case SNDRV_PCM_TRIGGER_RESUME:
675 + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
676 + bcm2708_i2s_start_clock(dev);
677 +
678 + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
679 + mask = BCM2708_I2S_RXON;
680 + else
681 + mask = BCM2708_I2S_TXON;
682 +
683 + regmap_update_bits(dev->i2s_regmap,
684 + BCM2708_I2S_CS_A_REG, mask, mask);
685 + break;
686 +
687 + case SNDRV_PCM_TRIGGER_STOP:
688 + case SNDRV_PCM_TRIGGER_SUSPEND:
689 + case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
690 + bcm2708_i2s_stop(dev, substream, dai);
691 + break;
692 + default:
693 + return -EINVAL;
694 + }
695 +
696 + return 0;
697 +}
698 +
699 +static int bcm2708_i2s_startup(struct snd_pcm_substream *substream,
700 + struct snd_soc_dai *dai)
701 +{
702 + struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
703 +
704 + if (dai->active)
705 + return 0;
706 +
707 + /* Should this still be running stop it */
708 + bcm2708_i2s_stop_clock(dev);
709 +
710 + /* Enable PCM block */
711 + regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
712 + BCM2708_I2S_EN, BCM2708_I2S_EN);
713 +
714 + /*
715 + * Disable STBY.
716 + * Requires at least 4 PCM clock cycles to take effect.
717 + */
718 + regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
719 + BCM2708_I2S_STBY, BCM2708_I2S_STBY);
720 +
721 + return 0;
722 +}
723 +
724 +static void bcm2708_i2s_shutdown(struct snd_pcm_substream *substream,
725 + struct snd_soc_dai *dai)
726 +{
727 + struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
728 +
729 + bcm2708_i2s_stop(dev, substream, dai);
730 +
731 + /* If both streams are stopped, disable module and clock */
732 + if (dai->active)
733 + return;
734 +
735 + /* Disable the module */
736 + regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG,
737 + BCM2708_I2S_EN, 0);
738 +
739 + /*
740 + * Stopping clock is necessary, because stop does
741 + * not stop the clock when SND_SOC_DAIFMT_CONT
742 + */
743 + bcm2708_i2s_stop_clock(dev);
744 +}
745 +
746 +static const struct snd_soc_dai_ops bcm2708_i2s_dai_ops = {
747 + .startup = bcm2708_i2s_startup,
748 + .shutdown = bcm2708_i2s_shutdown,
749 + .prepare = bcm2708_i2s_prepare,
750 + .trigger = bcm2708_i2s_trigger,
751 + .hw_params = bcm2708_i2s_hw_params,
752 + .set_fmt = bcm2708_i2s_set_dai_fmt,
753 + .set_bclk_ratio = bcm2708_i2s_set_dai_bclk_ratio
754 +};
755 +
756 +static int bcm2708_i2s_dai_probe(struct snd_soc_dai *dai)
757 +{
758 + struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
759 +
760 + dai->playback_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
761 + dai->capture_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_CAPTURE];
762 +
763 + return 0;
764 +}
765 +
766 +static struct snd_soc_dai_driver bcm2708_i2s_dai = {
767 + .name = "bcm2708-i2s",
768 + .probe = bcm2708_i2s_dai_probe,
769 + .playback = {
770 + .channels_min = 2,
771 + .channels_max = 2,
772 + .rates = SNDRV_PCM_RATE_8000_192000,
773 + .formats = SNDRV_PCM_FMTBIT_S16_LE
774 + | SNDRV_PCM_FMTBIT_S32_LE
775 + },
776 + .capture = {
777 + .channels_min = 2,
778 + .channels_max = 2,
779 + .rates = SNDRV_PCM_RATE_8000_192000,
780 + .formats = SNDRV_PCM_FMTBIT_S16_LE
781 + | SNDRV_PCM_FMTBIT_S32_LE
782 + },
783 + .ops = &bcm2708_i2s_dai_ops,
784 + .symmetric_rates = 1
785 +};
786 +
787 +static bool bcm2708_i2s_volatile_reg(struct device *dev, unsigned int reg)
788 +{
789 + switch (reg) {
790 + case BCM2708_I2S_CS_A_REG:
791 + case BCM2708_I2S_FIFO_A_REG:
792 + case BCM2708_I2S_INTSTC_A_REG:
793 + case BCM2708_I2S_GRAY_REG:
794 + return true;
795 + default:
796 + return false;
797 + };
798 +}
799 +
800 +static bool bcm2708_i2s_precious_reg(struct device *dev, unsigned int reg)
801 +{
802 + switch (reg) {
803 + case BCM2708_I2S_FIFO_A_REG:
804 + return true;
805 + default:
806 + return false;
807 + };
808 +}
809 +
810 +static bool bcm2708_clk_volatile_reg(struct device *dev, unsigned int reg)
811 +{
812 + switch (reg) {
813 + case BCM2708_CLK_PCMCTL_REG:
814 + return true;
815 + default:
816 + return false;
817 + };
818 +}
819 +
820 +static const struct regmap_config bcm2708_regmap_config[] = {
821 + {
822 + .reg_bits = 32,
823 + .reg_stride = 4,
824 + .val_bits = 32,
825 + .max_register = BCM2708_I2S_GRAY_REG,
826 + .precious_reg = bcm2708_i2s_precious_reg,
827 + .volatile_reg = bcm2708_i2s_volatile_reg,
828 + .cache_type = REGCACHE_RBTREE,
829 + },
830 + {
831 + .reg_bits = 32,
832 + .reg_stride = 4,
833 + .val_bits = 32,
834 + .max_register = BCM2708_CLK_PCMDIV_REG,
835 + .volatile_reg = bcm2708_clk_volatile_reg,
836 + .cache_type = REGCACHE_RBTREE,
837 + },
838 +};
839 +
840 +static const struct snd_soc_component_driver bcm2708_i2s_component = {
841 + .name = "bcm2708-i2s-comp",
842 +};
843 +
844 +
845 +static void bcm2708_i2s_setup_gpio(void)
846 +{
847 + /*
848 + * This is the common way to handle the GPIO pins for
849 + * the Raspberry Pi.
850 + * TODO Better way would be to handle
851 + * this in the device tree!
852 + */
853 +#define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3))
854 +#define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3))
855 +
856 + unsigned int *gpio;
857 + int pin;
858 + gpio = ioremap(GPIO_BASE, SZ_16K);
859 +
860 + /* SPI is on GPIO 7..11 */
861 + for (pin = 28; pin <= 31; pin++) {
862 + INP_GPIO(pin); /* set mode to GPIO input first */
863 + SET_GPIO_ALT(pin, 2); /* set mode to ALT 0 */
864 + }
865 +#undef INP_GPIO
866 +#undef SET_GPIO_ALT
867 +}
868 +
869 +static const struct snd_pcm_hardware bcm2708_pcm_hardware = {
870 + .info = SNDRV_PCM_INFO_MMAP |
871 + SNDRV_PCM_INFO_MMAP_VALID |
872 + SNDRV_PCM_INFO_INTERLEAVED |
873 + SNDRV_PCM_INFO_JOINT_DUPLEX,
874 + .formats = SNDRV_PCM_FMTBIT_S16_LE |
875 + SNDRV_PCM_FMTBIT_S32_LE,
876 + .period_bytes_min = 32,
877 + .period_bytes_max = 64 * PAGE_SIZE,
878 + .periods_min = 2,
879 + .periods_max = 255,
880 + .buffer_bytes_max = 128 * PAGE_SIZE,
881 +};
882 +
883 +static const struct snd_dmaengine_pcm_config bcm2708_dmaengine_pcm_config = {
884 + .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
885 + .pcm_hardware = &bcm2708_pcm_hardware,
886 + .prealloc_buffer_size = 256 * PAGE_SIZE,
887 +};
888 +
889 +
890 +static int bcm2708_i2s_probe(struct platform_device *pdev)
891 +{
892 + struct bcm2708_i2s_dev *dev;
893 + int i;
894 + int ret;
895 + struct regmap *regmap[2];
896 + struct resource *mem[2];
897 +
898 + /* Request both ioareas */
899 + for (i = 0; i <= 1; i++) {
900 + void __iomem *base;
901 +
902 + mem[i] = platform_get_resource(pdev, IORESOURCE_MEM, i);
903 + base = devm_ioremap_resource(&pdev->dev, mem[i]);
904 + if (IS_ERR(base))
905 + return PTR_ERR(base);
906 +
907 + regmap[i] = devm_regmap_init_mmio(&pdev->dev, base,
908 + &bcm2708_regmap_config[i]);
909 + if (IS_ERR(regmap[i])) {
910 + dev_err(&pdev->dev, "I2S probe: regmap init failed\n");
911 + return PTR_ERR(regmap[i]);
912 + }
913 + }
914 +
915 + dev = devm_kzalloc(&pdev->dev, sizeof(*dev),
916 + GFP_KERNEL);
917 + if (IS_ERR(dev))
918 + return PTR_ERR(dev);
919 +
920 + bcm2708_i2s_setup_gpio();
921 +
922 + dev->i2s_regmap = regmap[0];
923 + dev->clk_regmap = regmap[1];
924 +
925 + /* Set the DMA address */
926 + dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr =
927 + (dma_addr_t)BCM2708_I2S_FIFO_PHYSICAL_ADDR;
928 +
929 + dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr =
930 + (dma_addr_t)BCM2708_I2S_FIFO_PHYSICAL_ADDR;
931 +
932 + /* Set the DREQ */
933 + dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].slave_id =
934 + BCM2708_DMA_DREQ_PCM_TX;
935 + dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].slave_id =
936 + BCM2708_DMA_DREQ_PCM_RX;
937 +
938 + /* Set the bus width */
939 + dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr_width =
940 + DMA_SLAVE_BUSWIDTH_4_BYTES;
941 + dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr_width =
942 + DMA_SLAVE_BUSWIDTH_4_BYTES;
943 +
944 + /* Set burst */
945 + dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].maxburst = 2;
946 + dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].maxburst = 2;
947 +
948 + /* BCLK ratio - use default */
949 + dev->bclk_ratio = 0;
950 +
951 + /* Store the pdev */
952 + dev->dev = &pdev->dev;
953 + dev_set_drvdata(&pdev->dev, dev);
954 +
955 + ret = snd_soc_register_component(&pdev->dev,
956 + &bcm2708_i2s_component, &bcm2708_i2s_dai, 1);
957 +
958 + if (ret) {
959 + dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
960 + ret = -ENOMEM;
961 + return ret;
962 + }
963 +
964 + ret = snd_dmaengine_pcm_register(&pdev->dev,
965 + &bcm2708_dmaengine_pcm_config,
966 + SND_DMAENGINE_PCM_FLAG_COMPAT);
967 + if (ret) {
968 + dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
969 + snd_soc_unregister_component(&pdev->dev);
970 + return ret;
971 + }
972 +
973 + return 0;
974 +}
975 +
976 +static int bcm2708_i2s_remove(struct platform_device *pdev)
977 +{
978 + snd_dmaengine_pcm_unregister(&pdev->dev);
979 + snd_soc_unregister_component(&pdev->dev);
980 + return 0;
981 +}
982 +
983 +static struct platform_driver bcm2708_i2s_driver = {
984 + .probe = bcm2708_i2s_probe,
985 + .remove = bcm2708_i2s_remove,
986 + .driver = {
987 + .name = "bcm2708-i2s",
988 + .owner = THIS_MODULE,
989 + },
990 +};
991 +
992 +module_platform_driver(bcm2708_i2s_driver);
993 +
994 +MODULE_ALIAS("platform:bcm2708-i2s");
995 +MODULE_DESCRIPTION("BCM2708 I2S interface");
996 +MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
997 +MODULE_LICENSE("GPL v2");
998 --
999 1.9.1
1000
OpenWrt Source Repository