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brcm2708: add linux 4.1 support
[openwrt/openwrt.git] / target / linux / brcm2708 / patches-4.1 / 0008-MMC-added-alternative-MMC-driver.patch
1 From 0464f674cf3e441b8651c4a5ea0131fa24a3adc4 Mon Sep 17 00:00:00 2001
2 From: gellert <gellert@raspberrypi.org>
3 Date: Fri, 15 Aug 2014 16:35:06 +0100
4 Subject: [PATCH 008/121] MMC: added alternative MMC driver
5 MIME-Version: 1.0
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
8
9 mmc: Disable CMD23 transfers on all cards
10
11 Pending wire-level investigation of these types of transfers
12 and associated errors on bcm2835-mmc, disable for now. Fallback of
13 CMD18/CMD25 transfers will be used automatically by the MMC layer.
14
15 Reported/Tested-by: Gellert Weisz <gellert@raspberrypi.org>
16
17 mmc: bcm2835-mmc: enable DT support for all architectures
18
19 Both ARCH_BCM2835 and ARCH_BCM270x are built with OF now.
20 Enable Device Tree support for all architectures.
21
22 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
23
24 mmc: bcm2835-mmc: fix probe error handling
25
26 Probe error handling is broken in several places.
27 Simplify error handling by using device managed functions.
28 Replace pr_{err,info} with dev_{err,info}.
29
30 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
31
32 bcm2835-mmc: Add locks when accessing sdhost registers
33
34 bcm2835-mmc: Add range of debug options for slowing things down
35
36 bcm2835-mmc: Add option to disable some delays
37
38 bcm2835-mmc: Add option to disable MMC_QUIRK_BLK_NO_CMD23
39
40 bcm2835-mmc: Default to disabling MMC_QUIRK_BLK_NO_CMD23
41
42 bcm2835-mmc: Adding overclocking option
43
44 Allow a different clock speed to be substitued for a requested 50MHz.
45 This option is exposed using the "overclock_50" DT parameter.
46 Note that the mmc interface is restricted to EVEN integer divisions of
47 250MHz, and the highest sensible option is 63 (250/4 = 62.5), the
48 next being 125 (250/2) which is much too high.
49
50 Use at your own risk.
51
52 bcm2835-mmc: Round up the overclock, so 62 works for 62.5Mhz
53
54 Also only warn once for each overclock setting.
55
56 mmc: bcm2835-mmc: Make available on ARCH_BCM2835
57
58 Make the bcm2835-mmc driver available for use on ARCH_BCM2835.
59
60 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
61
62 BCM270x_DT: add bcm2835-mmc entry
63
64 Add Device Tree entry for bcm2835-mmc.
65 In non-DT mode, don't add the device in the board file.
66
67 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
68 ---
69 arch/arm/mach-bcm2708/bcm2708.c | 31 +
70 arch/arm/mach-bcm2709/bcm2709.c | 35 +-
71 drivers/mmc/core/quirks.c | 6 +
72 drivers/mmc/host/Kconfig | 29 +
73 drivers/mmc/host/Makefile | 1 +
74 drivers/mmc/host/bcm2835-mmc.c | 1558 +++++++++++++++++++++++++++++++++++++++
75 6 files changed, 1658 insertions(+), 2 deletions(-)
76 create mode 100644 drivers/mmc/host/bcm2835-mmc.c
77
78 --- a/arch/arm/mach-bcm2708/bcm2708.c
79 +++ b/arch/arm/mach-bcm2708/bcm2708.c
80 @@ -401,6 +401,34 @@ static struct platform_device bcm2708_gp
81 };
82 #endif
83
84 +#ifdef CONFIG_MMC_BCM2835 /* Arasan emmc SD (new) */
85 +static struct resource bcm2835_emmc_resources[] = {
86 + [0] = {
87 + .start = EMMC_BASE,
88 + .end = EMMC_BASE + SZ_256 - 1, /* we only need this area */
89 + /* the memory map actually makes SZ_4K available */
90 + .flags = IORESOURCE_MEM,
91 + },
92 + [1] = {
93 + .start = IRQ_ARASANSDIO,
94 + .end = IRQ_ARASANSDIO,
95 + .flags = IORESOURCE_IRQ,
96 + },
97 +};
98 +
99 +static u64 bcm2835_emmc_dmamask = 0xffffffffUL;
100 +
101 +struct platform_device bcm2835_emmc_device = {
102 + .name = "mmc-bcm2835",
103 + .id = 0,
104 + .num_resources = ARRAY_SIZE(bcm2835_emmc_resources),
105 + .resource = bcm2835_emmc_resources,
106 + .dev = {
107 + .dma_mask = &bcm2835_emmc_dmamask,
108 + .coherent_dma_mask = 0xffffffffUL},
109 +};
110 +#endif /* CONFIG_MMC_BCM2835 */
111 +
112 int __init bcm_register_device(struct platform_device *pdev)
113 {
114 int ret;
115 @@ -538,6 +566,9 @@ void __init bcm2708_init(void)
116 bcm_register_device_dt(&bcm2708_fb_device);
117 bcm_register_device_dt(&bcm2708_usb_device);
118
119 +#ifdef CONFIG_MMC_BCM2835
120 + bcm_register_device_dt(&bcm2835_emmc_device);
121 +#endif
122 bcm2708_init_led();
123 bcm2708_init_uart1();
124
125 --- a/arch/arm/mach-bcm2709/bcm2709.c
126 +++ b/arch/arm/mach-bcm2709/bcm2709.c
127 @@ -421,6 +421,34 @@ static struct platform_device bcm2708_gp
128 };
129 #endif
130
131 +#ifdef CONFIG_MMC_BCM2835 /* Arasan emmc SD (new) */
132 +static struct resource bcm2835_emmc_resources[] = {
133 + [0] = {
134 + .start = EMMC_BASE,
135 + .end = EMMC_BASE + SZ_256 - 1, /* we only need this area */
136 + /* the memory map actually makes SZ_4K available */
137 + .flags = IORESOURCE_MEM,
138 + },
139 + [1] = {
140 + .start = IRQ_ARASANSDIO,
141 + .end = IRQ_ARASANSDIO,
142 + .flags = IORESOURCE_IRQ,
143 + },
144 +};
145 +
146 +static u64 bcm2835_emmc_dmamask = 0xffffffffUL;
147 +
148 +struct platform_device bcm2835_emmc_device = {
149 + .name = "mmc-bcm2835",
150 + .id = 0,
151 + .num_resources = ARRAY_SIZE(bcm2835_emmc_resources),
152 + .resource = bcm2835_emmc_resources,
153 + .dev = {
154 + .dma_mask = &bcm2835_emmc_dmamask,
155 + .coherent_dma_mask = 0xffffffffUL},
156 +};
157 +#endif /* CONFIG_MMC_BCM2835 */
158 +
159 int __init bcm_register_device(struct platform_device *pdev)
160 {
161 int ret;
162 @@ -558,8 +586,11 @@ void __init bcm2709_init(void)
163 bcm_register_device_dt(&bcm2708_fb_device);
164 bcm_register_device_dt(&bcm2708_usb_device);
165
166 - bcm2708_init_led();
167 - bcm2708_init_uart1();
168 +#ifdef CONFIG_MMC_BCM2835
169 + bcm_register_device_dt(&bcm2835_emmc_device);
170 +#endif
171 + bcm2709_init_led();
172 + bcm2709_init_uart1();
173
174 if (!use_dt) {
175 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
176 --- a/drivers/mmc/core/quirks.c
177 +++ b/drivers/mmc/core/quirks.c
178 @@ -71,6 +71,7 @@ static const struct mmc_fixup mmc_fixup_
179
180 void mmc_fixup_device(struct mmc_card *card, const struct mmc_fixup *table)
181 {
182 + extern unsigned mmc_debug;
183 const struct mmc_fixup *f;
184 u64 rev = cid_rev_card(card);
185
186 @@ -95,5 +96,10 @@ void mmc_fixup_device(struct mmc_card *c
187 f->vendor_fixup(card, f->data);
188 }
189 }
190 + /* SDHCI on BCM2708 - bug causes a certain sequence of CMD23 operations to fail.
191 + * Disable this flag for all cards (fall-back to CMD25/CMD18 multi-block transfers).
192 + */
193 + if (mmc_debug & (1<<13))
194 + card->quirks |= MMC_QUIRK_BLK_NO_CMD23;
195 }
196 EXPORT_SYMBOL(mmc_fixup_device);
197 --- a/drivers/mmc/host/Kconfig
198 +++ b/drivers/mmc/host/Kconfig
199 @@ -4,6 +4,35 @@
200
201 comment "MMC/SD/SDIO Host Controller Drivers"
202
203 +config MMC_BCM2835
204 + tristate "MMC support on BCM2835"
205 + depends on MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835
206 + help
207 + This selects the MMC Interface on BCM2835.
208 +
209 + If you have a controller with this interface, say Y or M here.
210 +
211 + If unsure, say N.
212 +
213 +config MMC_BCM2835_DMA
214 + bool "DMA support on BCM2835 Arasan controller"
215 + depends on MMC_BCM2835
216 + help
217 + Enable DMA support on the Arasan SDHCI controller in Broadcom 2708
218 + based chips.
219 +
220 + If unsure, say N.
221 +
222 +config MMC_BCM2835_PIO_DMA_BARRIER
223 + int "Block count limit for PIO transfers"
224 + depends on MMC_BCM2835 && MMC_BCM2835_DMA
225 + range 0 256
226 + default 2
227 + help
228 + The inclusive limit in bytes under which PIO will be used instead of DMA
229 +
230 + If unsure, say 2 here.
231 +
232 config MMC_ARMMMCI
233 tristate "ARM AMBA Multimedia Card Interface support"
234 depends on ARM_AMBA
235 --- a/drivers/mmc/host/Makefile
236 +++ b/drivers/mmc/host/Makefile
237 @@ -18,6 +18,7 @@ obj-$(CONFIG_MMC_SDHCI_S3C) += sdhci-s3c
238 obj-$(CONFIG_MMC_SDHCI_SIRF) += sdhci-sirf.o
239 obj-$(CONFIG_MMC_SDHCI_F_SDH30) += sdhci_f_sdh30.o
240 obj-$(CONFIG_MMC_SDHCI_SPEAR) += sdhci-spear.o
241 +obj-$(CONFIG_MMC_BCM2835) += bcm2835-mmc.o
242 obj-$(CONFIG_MMC_WBSD) += wbsd.o
243 obj-$(CONFIG_MMC_AU1X) += au1xmmc.o
244 obj-$(CONFIG_MMC_OMAP) += omap.o
245 --- /dev/null
246 +++ b/drivers/mmc/host/bcm2835-mmc.c
247 @@ -0,0 +1,1558 @@
248 +/*
249 + * BCM2835 MMC host driver.
250 + *
251 + * Author: Gellert Weisz <gellert@raspberrypi.org>
252 + * Copyright 2014
253 + *
254 + * Based on
255 + * sdhci-bcm2708.c by Broadcom
256 + * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko
257 + * sdhci.c and sdhci-pci.c by Pierre Ossman
258 + *
259 + * This program is free software; you can redistribute it and/or modify it
260 + * under the terms and conditions of the GNU General Public License,
261 + * version 2, as published by the Free Software Foundation.
262 + *
263 + * This program is distributed in the hope it will be useful, but WITHOUT
264 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
265 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
266 + * more details.
267 + *
268 + * You should have received a copy of the GNU General Public License
269 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
270 + */
271 +
272 +#include <linux/delay.h>
273 +#include <linux/module.h>
274 +#include <linux/io.h>
275 +#include <linux/mmc/mmc.h>
276 +#include <linux/mmc/host.h>
277 +#include <linux/mmc/sd.h>
278 +#include <linux/scatterlist.h>
279 +#include <linux/of_address.h>
280 +#include <linux/of_irq.h>
281 +#include <linux/clk.h>
282 +#include <linux/platform_device.h>
283 +#include <linux/err.h>
284 +#include <linux/blkdev.h>
285 +#include <linux/dmaengine.h>
286 +#include <linux/dma-mapping.h>
287 +#include <linux/of_dma.h>
288 +
289 +#include "sdhci.h"
290 +
291 +
292 +#define DRIVER_NAME "mmc-bcm2835"
293 +
294 +#define DBG(f, x...) \
295 +pr_debug(DRIVER_NAME " [%s()]: " f, __func__, ## x)
296 +
297 +#ifndef CONFIG_MMC_BCM2835_DMA
298 + #define FORCE_PIO
299 +#endif
300 +
301 +
302 +/* the inclusive limit in bytes under which PIO will be used instead of DMA */
303 +#ifdef CONFIG_MMC_BCM2835_PIO_DMA_BARRIER
304 +#define PIO_DMA_BARRIER CONFIG_MMC_BCM2835_PIO_DMA_BARRIER
305 +#else
306 +#define PIO_DMA_BARRIER 00
307 +#endif
308 +
309 +#define MIN_FREQ 400000
310 +#define TIMEOUT_VAL 0xE
311 +#define BCM2835_SDHCI_WRITE_DELAY(f) (((2 * 1000000) / f) + 1)
312 +
313 +#ifndef BCM2708_PERI_BASE
314 + #define BCM2708_PERI_BASE 0x20000000
315 +#endif
316 +
317 +/* FIXME: Needs IOMMU support */
318 +#define BCM2835_VCMMU_SHIFT (0x7E000000 - BCM2708_PERI_BASE)
319 +
320 +
321 +unsigned mmc_debug;
322 +unsigned mmc_debug2;
323 +
324 +struct bcm2835_host {
325 + spinlock_t lock;
326 +
327 + void __iomem *ioaddr;
328 + u32 phys_addr;
329 +
330 + struct mmc_host *mmc;
331 +
332 + u32 timeout;
333 +
334 + int clock; /* Current clock speed */
335 + u8 pwr; /* Current voltage */
336 +
337 + unsigned int max_clk; /* Max possible freq */
338 + unsigned int timeout_clk; /* Timeout freq (KHz) */
339 + unsigned int clk_mul; /* Clock Muliplier value */
340 +
341 + struct tasklet_struct finish_tasklet; /* Tasklet structures */
342 +
343 + struct timer_list timer; /* Timer for timeouts */
344 +
345 + struct sg_mapping_iter sg_miter; /* SG state for PIO */
346 + unsigned int blocks; /* remaining PIO blocks */
347 +
348 + int irq; /* Device IRQ */
349 +
350 +
351 + u32 ier; /* cached registers */
352 +
353 + struct mmc_request *mrq; /* Current request */
354 + struct mmc_command *cmd; /* Current command */
355 + struct mmc_data *data; /* Current data request */
356 + unsigned int data_early:1; /* Data finished before cmd */
357 +
358 + wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */
359 +
360 + u32 thread_isr;
361 +
362 + u32 shadow;
363 +
364 + /*DMA part*/
365 + struct dma_chan *dma_chan_rx; /* DMA channel for reads */
366 + struct dma_chan *dma_chan_tx; /* DMA channel for writes */
367 + struct dma_async_tx_descriptor *tx_desc; /* descriptor */
368 +
369 + bool have_dma;
370 + bool use_dma;
371 + /*end of DMA part*/
372 +
373 + int max_delay; /* maximum length of time spent waiting */
374 +
375 + int flags; /* Host attributes */
376 +#define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */
377 +#define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */
378 +#define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */
379 +#define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */
380 +#define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */
381 +
382 + u32 overclock_50; /* frequency to use when 50MHz is requested (in MHz) */
383 + u32 max_overclock; /* Highest reported */
384 +};
385 +
386 +
387 +static inline void bcm2835_mmc_writel(struct bcm2835_host *host, u32 val, int reg, int from)
388 +{
389 + unsigned delay;
390 + lockdep_assert_held_once(&host->lock);
391 + writel(val, host->ioaddr + reg);
392 + udelay(BCM2835_SDHCI_WRITE_DELAY(max(host->clock, MIN_FREQ)));
393 +
394 + delay = ((mmc_debug >> 16) & 0xf) << ((mmc_debug >> 20) & 0xf);
395 + if (delay && !((1<<from) & mmc_debug2))
396 + udelay(delay);
397 +}
398 +
399 +static inline void mmc_raw_writel(struct bcm2835_host *host, u32 val, int reg)
400 +{
401 + unsigned delay;
402 + lockdep_assert_held_once(&host->lock);
403 + writel(val, host->ioaddr + reg);
404 +
405 + delay = ((mmc_debug >> 24) & 0xf) << ((mmc_debug >> 28) & 0xf);
406 + if (delay)
407 + udelay(delay);
408 +}
409 +
410 +static inline u32 bcm2835_mmc_readl(struct bcm2835_host *host, int reg)
411 +{
412 + lockdep_assert_held_once(&host->lock);
413 + return readl(host->ioaddr + reg);
414 +}
415 +
416 +static inline void bcm2835_mmc_writew(struct bcm2835_host *host, u16 val, int reg)
417 +{
418 + u32 oldval = (reg == SDHCI_COMMAND) ? host->shadow :
419 + bcm2835_mmc_readl(host, reg & ~3);
420 + u32 word_num = (reg >> 1) & 1;
421 + u32 word_shift = word_num * 16;
422 + u32 mask = 0xffff << word_shift;
423 + u32 newval = (oldval & ~mask) | (val << word_shift);
424 +
425 + if (reg == SDHCI_TRANSFER_MODE)
426 + host->shadow = newval;
427 + else
428 + bcm2835_mmc_writel(host, newval, reg & ~3, 0);
429 +
430 +}
431 +
432 +static inline void bcm2835_mmc_writeb(struct bcm2835_host *host, u8 val, int reg)
433 +{
434 + u32 oldval = bcm2835_mmc_readl(host, reg & ~3);
435 + u32 byte_num = reg & 3;
436 + u32 byte_shift = byte_num * 8;
437 + u32 mask = 0xff << byte_shift;
438 + u32 newval = (oldval & ~mask) | (val << byte_shift);
439 +
440 + bcm2835_mmc_writel(host, newval, reg & ~3, 1);
441 +}
442 +
443 +
444 +static inline u16 bcm2835_mmc_readw(struct bcm2835_host *host, int reg)
445 +{
446 + u32 val = bcm2835_mmc_readl(host, (reg & ~3));
447 + u32 word_num = (reg >> 1) & 1;
448 + u32 word_shift = word_num * 16;
449 + u32 word = (val >> word_shift) & 0xffff;
450 +
451 + return word;
452 +}
453 +
454 +static inline u8 bcm2835_mmc_readb(struct bcm2835_host *host, int reg)
455 +{
456 + u32 val = bcm2835_mmc_readl(host, (reg & ~3));
457 + u32 byte_num = reg & 3;
458 + u32 byte_shift = byte_num * 8;
459 + u32 byte = (val >> byte_shift) & 0xff;
460 +
461 + return byte;
462 +}
463 +
464 +static void bcm2835_mmc_unsignal_irqs(struct bcm2835_host *host, u32 clear)
465 +{
466 + u32 ier;
467 +
468 + ier = bcm2835_mmc_readl(host, SDHCI_SIGNAL_ENABLE);
469 + ier &= ~clear;
470 + /* change which requests generate IRQs - makes no difference to
471 + the content of SDHCI_INT_STATUS, or the need to acknowledge IRQs */
472 + bcm2835_mmc_writel(host, ier, SDHCI_SIGNAL_ENABLE, 2);
473 +}
474 +
475 +
476 +static void bcm2835_mmc_dumpregs(struct bcm2835_host *host)
477 +{
478 + pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
479 + mmc_hostname(host->mmc));
480 +
481 + pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
482 + bcm2835_mmc_readl(host, SDHCI_DMA_ADDRESS),
483 + bcm2835_mmc_readw(host, SDHCI_HOST_VERSION));
484 + pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
485 + bcm2835_mmc_readw(host, SDHCI_BLOCK_SIZE),
486 + bcm2835_mmc_readw(host, SDHCI_BLOCK_COUNT));
487 + pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
488 + bcm2835_mmc_readl(host, SDHCI_ARGUMENT),
489 + bcm2835_mmc_readw(host, SDHCI_TRANSFER_MODE));
490 + pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
491 + bcm2835_mmc_readl(host, SDHCI_PRESENT_STATE),
492 + bcm2835_mmc_readb(host, SDHCI_HOST_CONTROL));
493 + pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
494 + bcm2835_mmc_readb(host, SDHCI_POWER_CONTROL),
495 + bcm2835_mmc_readb(host, SDHCI_BLOCK_GAP_CONTROL));
496 + pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
497 + bcm2835_mmc_readb(host, SDHCI_WAKE_UP_CONTROL),
498 + bcm2835_mmc_readw(host, SDHCI_CLOCK_CONTROL));
499 + pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
500 + bcm2835_mmc_readb(host, SDHCI_TIMEOUT_CONTROL),
501 + bcm2835_mmc_readl(host, SDHCI_INT_STATUS));
502 + pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
503 + bcm2835_mmc_readl(host, SDHCI_INT_ENABLE),
504 + bcm2835_mmc_readl(host, SDHCI_SIGNAL_ENABLE));
505 + pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
506 + bcm2835_mmc_readw(host, SDHCI_ACMD12_ERR),
507 + bcm2835_mmc_readw(host, SDHCI_SLOT_INT_STATUS));
508 + pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
509 + bcm2835_mmc_readl(host, SDHCI_CAPABILITIES),
510 + bcm2835_mmc_readl(host, SDHCI_CAPABILITIES_1));
511 + pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
512 + bcm2835_mmc_readw(host, SDHCI_COMMAND),
513 + bcm2835_mmc_readl(host, SDHCI_MAX_CURRENT));
514 + pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
515 + bcm2835_mmc_readw(host, SDHCI_HOST_CONTROL2));
516 +
517 + pr_debug(DRIVER_NAME ": ===========================================\n");
518 +}
519 +
520 +
521 +static void bcm2835_mmc_reset(struct bcm2835_host *host, u8 mask)
522 +{
523 + unsigned long timeout;
524 + unsigned long flags;
525 +
526 + spin_lock_irqsave(&host->lock, flags);
527 + bcm2835_mmc_writeb(host, mask, SDHCI_SOFTWARE_RESET);
528 +
529 + if (mask & SDHCI_RESET_ALL)
530 + host->clock = 0;
531 +
532 + /* Wait max 100 ms */
533 + timeout = 100;
534 +
535 + /* hw clears the bit when it's done */
536 + while (bcm2835_mmc_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
537 + if (timeout == 0) {
538 + pr_err("%s: Reset 0x%x never completed.\n",
539 + mmc_hostname(host->mmc), (int)mask);
540 + bcm2835_mmc_dumpregs(host);
541 + return;
542 + }
543 + timeout--;
544 + spin_unlock_irqrestore(&host->lock, flags);
545 + mdelay(1);
546 + spin_lock_irqsave(&host->lock, flags);
547 + }
548 +
549 + if (100-timeout > 10 && 100-timeout > host->max_delay) {
550 + host->max_delay = 100-timeout;
551 + pr_warning("Warning: MMC controller hung for %d ms\n", host->max_delay);
552 + }
553 + spin_unlock_irqrestore(&host->lock, flags);
554 +}
555 +
556 +static void bcm2835_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
557 +
558 +static void bcm2835_mmc_init(struct bcm2835_host *host, int soft)
559 +{
560 + unsigned long flags;
561 + if (soft)
562 + bcm2835_mmc_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
563 + else
564 + bcm2835_mmc_reset(host, SDHCI_RESET_ALL);
565 +
566 + host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
567 + SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
568 + SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
569 + SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
570 + SDHCI_INT_RESPONSE;
571 +
572 + spin_lock_irqsave(&host->lock, flags);
573 + bcm2835_mmc_writel(host, host->ier, SDHCI_INT_ENABLE, 3);
574 + bcm2835_mmc_writel(host, host->ier, SDHCI_SIGNAL_ENABLE, 3);
575 + spin_unlock_irqrestore(&host->lock, flags);
576 +
577 + if (soft) {
578 + /* force clock reconfiguration */
579 + host->clock = 0;
580 + bcm2835_mmc_set_ios(host->mmc, &host->mmc->ios);
581 + }
582 +}
583 +
584 +
585 +
586 +static void bcm2835_mmc_finish_data(struct bcm2835_host *host);
587 +
588 +static void bcm2835_mmc_dma_complete(void *param)
589 +{
590 + struct bcm2835_host *host = param;
591 + struct dma_chan *dma_chan;
592 + unsigned long flags;
593 + u32 dir_data;
594 +
595 + spin_lock_irqsave(&host->lock, flags);
596 +
597 + if (host->data && !(host->data->flags & MMC_DATA_WRITE)) {
598 + /* otherwise handled in SDHCI IRQ */
599 + dma_chan = host->dma_chan_rx;
600 + dir_data = DMA_FROM_DEVICE;
601 +
602 + dma_unmap_sg(dma_chan->device->dev,
603 + host->data->sg, host->data->sg_len,
604 + dir_data);
605 +
606 + bcm2835_mmc_finish_data(host);
607 + }
608 +
609 + spin_unlock_irqrestore(&host->lock, flags);
610 +}
611 +
612 +static void bcm2835_bcm2835_mmc_read_block_pio(struct bcm2835_host *host)
613 +{
614 + unsigned long flags;
615 + size_t blksize, len, chunk;
616 +
617 + u32 uninitialized_var(scratch);
618 + u8 *buf;
619 +
620 + blksize = host->data->blksz;
621 + chunk = 0;
622 +
623 + local_irq_save(flags);
624 +
625 + while (blksize) {
626 + if (!sg_miter_next(&host->sg_miter))
627 + BUG();
628 +
629 + len = min(host->sg_miter.length, blksize);
630 +
631 + blksize -= len;
632 + host->sg_miter.consumed = len;
633 +
634 + buf = host->sg_miter.addr;
635 +
636 + while (len) {
637 + if (chunk == 0) {
638 + scratch = bcm2835_mmc_readl(host, SDHCI_BUFFER);
639 + chunk = 4;
640 + }
641 +
642 + *buf = scratch & 0xFF;
643 +
644 + buf++;
645 + scratch >>= 8;
646 + chunk--;
647 + len--;
648 + }
649 + }
650 +
651 + sg_miter_stop(&host->sg_miter);
652 +
653 + local_irq_restore(flags);
654 +}
655 +
656 +static void bcm2835_bcm2835_mmc_write_block_pio(struct bcm2835_host *host)
657 +{
658 + unsigned long flags;
659 + size_t blksize, len, chunk;
660 + u32 scratch;
661 + u8 *buf;
662 +
663 + blksize = host->data->blksz;
664 + chunk = 0;
665 + chunk = 0;
666 + scratch = 0;
667 +
668 + local_irq_save(flags);
669 +
670 + while (blksize) {
671 + if (!sg_miter_next(&host->sg_miter))
672 + BUG();
673 +
674 + len = min(host->sg_miter.length, blksize);
675 +
676 + blksize -= len;
677 + host->sg_miter.consumed = len;
678 +
679 + buf = host->sg_miter.addr;
680 +
681 + while (len) {
682 + scratch |= (u32)*buf << (chunk * 8);
683 +
684 + buf++;
685 + chunk++;
686 + len--;
687 +
688 + if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
689 + mmc_raw_writel(host, scratch, SDHCI_BUFFER);
690 + chunk = 0;
691 + scratch = 0;
692 + }
693 + }
694 + }
695 +
696 + sg_miter_stop(&host->sg_miter);
697 +
698 + local_irq_restore(flags);
699 +}
700 +
701 +
702 +static void bcm2835_mmc_transfer_pio(struct bcm2835_host *host)
703 +{
704 + u32 mask;
705 +
706 + BUG_ON(!host->data);
707 +
708 + if (host->blocks == 0)
709 + return;
710 +
711 + if (host->data->flags & MMC_DATA_READ)
712 + mask = SDHCI_DATA_AVAILABLE;
713 + else
714 + mask = SDHCI_SPACE_AVAILABLE;
715 +
716 + while (bcm2835_mmc_readl(host, SDHCI_PRESENT_STATE) & mask) {
717 +
718 + if (host->data->flags & MMC_DATA_READ)
719 + bcm2835_bcm2835_mmc_read_block_pio(host);
720 + else
721 + bcm2835_bcm2835_mmc_write_block_pio(host);
722 +
723 + host->blocks--;
724 +
725 + /* QUIRK used in sdhci.c removes the 'if' */
726 + /* but it seems this is unnecessary */
727 + if (host->blocks == 0)
728 + break;
729 +
730 +
731 + }
732 +}
733 +
734 +
735 +static void bcm2835_mmc_transfer_dma(struct bcm2835_host *host)
736 +{
737 + u32 len, dir_data, dir_slave;
738 + struct dma_async_tx_descriptor *desc = NULL;
739 + struct dma_chan *dma_chan;
740 +
741 +
742 + WARN_ON(!host->data);
743 +
744 + if (!host->data)
745 + return;
746 +
747 + if (host->blocks == 0)
748 + return;
749 +
750 + if (host->data->flags & MMC_DATA_READ) {
751 + dma_chan = host->dma_chan_rx;
752 + dir_data = DMA_FROM_DEVICE;
753 + dir_slave = DMA_DEV_TO_MEM;
754 + } else {
755 + dma_chan = host->dma_chan_tx;
756 + dir_data = DMA_TO_DEVICE;
757 + dir_slave = DMA_MEM_TO_DEV;
758 + }
759 +
760 + BUG_ON(!dma_chan->device);
761 + BUG_ON(!dma_chan->device->dev);
762 + BUG_ON(!host->data->sg);
763 +
764 + len = dma_map_sg(dma_chan->device->dev, host->data->sg,
765 + host->data->sg_len, dir_data);
766 + if (len > 0) {
767 + desc = dmaengine_prep_slave_sg(dma_chan, host->data->sg,
768 + len, dir_slave,
769 + DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
770 + } else {
771 + dev_err(mmc_dev(host->mmc), "dma_map_sg returned zero length\n");
772 + }
773 + if (desc) {
774 + unsigned long flags;
775 + spin_lock_irqsave(&host->lock, flags);
776 + bcm2835_mmc_unsignal_irqs(host, SDHCI_INT_DATA_AVAIL |
777 + SDHCI_INT_SPACE_AVAIL);
778 + host->tx_desc = desc;
779 + desc->callback = bcm2835_mmc_dma_complete;
780 + desc->callback_param = host;
781 + spin_unlock_irqrestore(&host->lock, flags);
782 + dmaengine_submit(desc);
783 + dma_async_issue_pending(dma_chan);
784 + }
785 +
786 +}
787 +
788 +
789 +
790 +static void bcm2835_mmc_set_transfer_irqs(struct bcm2835_host *host)
791 +{
792 + u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
793 + u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
794 +
795 + if (host->use_dma)
796 + host->ier = (host->ier & ~pio_irqs) | dma_irqs;
797 + else
798 + host->ier = (host->ier & ~dma_irqs) | pio_irqs;
799 +
800 + bcm2835_mmc_writel(host, host->ier, SDHCI_INT_ENABLE, 4);
801 + bcm2835_mmc_writel(host, host->ier, SDHCI_SIGNAL_ENABLE, 4);
802 +}
803 +
804 +
805 +static void bcm2835_mmc_prepare_data(struct bcm2835_host *host, struct mmc_command *cmd)
806 +{
807 + u8 count;
808 + struct mmc_data *data = cmd->data;
809 +
810 + WARN_ON(host->data);
811 +
812 + if (data || (cmd->flags & MMC_RSP_BUSY)) {
813 + count = TIMEOUT_VAL;
814 + bcm2835_mmc_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
815 + }
816 +
817 + if (!data)
818 + return;
819 +
820 + /* Sanity checks */
821 + BUG_ON(data->blksz * data->blocks > 524288);
822 + BUG_ON(data->blksz > host->mmc->max_blk_size);
823 + BUG_ON(data->blocks > 65535);
824 +
825 + host->data = data;
826 + host->data_early = 0;
827 + host->data->bytes_xfered = 0;
828 +
829 +
830 + if (!(host->flags & SDHCI_REQ_USE_DMA)) {
831 + int flags;
832 +
833 + flags = SG_MITER_ATOMIC;
834 + if (host->data->flags & MMC_DATA_READ)
835 + flags |= SG_MITER_TO_SG;
836 + else
837 + flags |= SG_MITER_FROM_SG;
838 + sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
839 + host->blocks = data->blocks;
840 + }
841 +
842 + host->use_dma = host->have_dma && data->blocks > PIO_DMA_BARRIER;
843 +
844 + bcm2835_mmc_set_transfer_irqs(host);
845 +
846 + /* Set the DMA boundary value and block size */
847 + bcm2835_mmc_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
848 + data->blksz), SDHCI_BLOCK_SIZE);
849 + bcm2835_mmc_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
850 +
851 + BUG_ON(!host->data);
852 +}
853 +
854 +static void bcm2835_mmc_set_transfer_mode(struct bcm2835_host *host,
855 + struct mmc_command *cmd)
856 +{
857 + u16 mode;
858 + struct mmc_data *data = cmd->data;
859 +
860 + if (data == NULL) {
861 + /* clear Auto CMD settings for no data CMDs */
862 + mode = bcm2835_mmc_readw(host, SDHCI_TRANSFER_MODE);
863 + bcm2835_mmc_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
864 + SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
865 + return;
866 + }
867 +
868 + WARN_ON(!host->data);
869 +
870 + mode = SDHCI_TRNS_BLK_CNT_EN;
871 +
872 + if ((mmc_op_multi(cmd->opcode) || data->blocks > 1)) {
873 + mode |= SDHCI_TRNS_MULTI;
874 +
875 + /*
876 + * If we are sending CMD23, CMD12 never gets sent
877 + * on successful completion (so no Auto-CMD12).
878 + */
879 + if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
880 + mode |= SDHCI_TRNS_AUTO_CMD12;
881 + else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
882 + mode |= SDHCI_TRNS_AUTO_CMD23;
883 + bcm2835_mmc_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2, 5);
884 + }
885 + }
886 +
887 + if (data->flags & MMC_DATA_READ)
888 + mode |= SDHCI_TRNS_READ;
889 + if (host->flags & SDHCI_REQ_USE_DMA)
890 + mode |= SDHCI_TRNS_DMA;
891 +
892 + bcm2835_mmc_writew(host, mode, SDHCI_TRANSFER_MODE);
893 +}
894 +
895 +void bcm2835_mmc_send_command(struct bcm2835_host *host, struct mmc_command *cmd)
896 +{
897 + int flags;
898 + u32 mask;
899 + unsigned long timeout;
900 +
901 + WARN_ON(host->cmd);
902 +
903 + /* Wait max 10 ms */
904 + timeout = 1000;
905 +
906 + mask = SDHCI_CMD_INHIBIT;
907 + if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
908 + mask |= SDHCI_DATA_INHIBIT;
909 +
910 + /* We shouldn't wait for data inihibit for stop commands, even
911 + though they might use busy signaling */
912 + if (host->mrq->data && (cmd == host->mrq->data->stop))
913 + mask &= ~SDHCI_DATA_INHIBIT;
914 +
915 + while (bcm2835_mmc_readl(host, SDHCI_PRESENT_STATE) & mask) {
916 + if (timeout == 0) {
917 + pr_err("%s: Controller never released inhibit bit(s).\n",
918 + mmc_hostname(host->mmc));
919 + bcm2835_mmc_dumpregs(host);
920 + cmd->error = -EIO;
921 + tasklet_schedule(&host->finish_tasklet);
922 + return;
923 + }
924 + timeout--;
925 + udelay(10);
926 + }
927 +
928 + if ((1000-timeout)/100 > 1 && (1000-timeout)/100 > host->max_delay) {
929 + host->max_delay = (1000-timeout)/100;
930 + pr_warning("Warning: MMC controller hung for %d ms\n", host->max_delay);
931 + }
932 +
933 + timeout = jiffies;
934 +#ifdef CONFIG_ARCH_BCM2835
935 + if (!cmd->data && cmd->busy_timeout > 9000)
936 + timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
937 + else
938 +#endif
939 + timeout += 10 * HZ;
940 + mod_timer(&host->timer, timeout);
941 +
942 + host->cmd = cmd;
943 +
944 + bcm2835_mmc_prepare_data(host, cmd);
945 +
946 + bcm2835_mmc_writel(host, cmd->arg, SDHCI_ARGUMENT, 6);
947 +
948 + bcm2835_mmc_set_transfer_mode(host, cmd);
949 +
950 + if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
951 + pr_err("%s: Unsupported response type!\n",
952 + mmc_hostname(host->mmc));
953 + cmd->error = -EINVAL;
954 + tasklet_schedule(&host->finish_tasklet);
955 + return;
956 + }
957 +
958 + if (!(cmd->flags & MMC_RSP_PRESENT))
959 + flags = SDHCI_CMD_RESP_NONE;
960 + else if (cmd->flags & MMC_RSP_136)
961 + flags = SDHCI_CMD_RESP_LONG;
962 + else if (cmd->flags & MMC_RSP_BUSY)
963 + flags = SDHCI_CMD_RESP_SHORT_BUSY;
964 + else
965 + flags = SDHCI_CMD_RESP_SHORT;
966 +
967 + if (cmd->flags & MMC_RSP_CRC)
968 + flags |= SDHCI_CMD_CRC;
969 + if (cmd->flags & MMC_RSP_OPCODE)
970 + flags |= SDHCI_CMD_INDEX;
971 +
972 + if (cmd->data)
973 + flags |= SDHCI_CMD_DATA;
974 +
975 + bcm2835_mmc_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
976 +}
977 +
978 +
979 +static void bcm2835_mmc_finish_data(struct bcm2835_host *host)
980 +{
981 + struct mmc_data *data;
982 +
983 + BUG_ON(!host->data);
984 +
985 + data = host->data;
986 + host->data = NULL;
987 +
988 + if (data->error)
989 + data->bytes_xfered = 0;
990 + else
991 + data->bytes_xfered = data->blksz * data->blocks;
992 +
993 + /*
994 + * Need to send CMD12 if -
995 + * a) open-ended multiblock transfer (no CMD23)
996 + * b) error in multiblock transfer
997 + */
998 + if (data->stop &&
999 + (data->error ||
1000 + !host->mrq->sbc)) {
1001 +
1002 + /*
1003 + * The controller needs a reset of internal state machines
1004 + * upon error conditions.
1005 + */
1006 + if (data->error) {
1007 + bcm2835_mmc_reset(host, SDHCI_RESET_CMD);
1008 + bcm2835_mmc_reset(host, SDHCI_RESET_DATA);
1009 + }
1010 +
1011 + bcm2835_mmc_send_command(host, data->stop);
1012 + } else
1013 + tasklet_schedule(&host->finish_tasklet);
1014 +}
1015 +
1016 +static void bcm2835_mmc_finish_command(struct bcm2835_host *host)
1017 +{
1018 + int i;
1019 +
1020 + BUG_ON(host->cmd == NULL);
1021 +
1022 + if (host->cmd->flags & MMC_RSP_PRESENT) {
1023 + if (host->cmd->flags & MMC_RSP_136) {
1024 + /* CRC is stripped so we need to do some shifting. */
1025 + for (i = 0; i < 4; i++) {
1026 + host->cmd->resp[i] = bcm2835_mmc_readl(host,
1027 + SDHCI_RESPONSE + (3-i)*4) << 8;
1028 + if (i != 3)
1029 + host->cmd->resp[i] |=
1030 + bcm2835_mmc_readb(host,
1031 + SDHCI_RESPONSE + (3-i)*4-1);
1032 + }
1033 + } else {
1034 + host->cmd->resp[0] = bcm2835_mmc_readl(host, SDHCI_RESPONSE);
1035 + }
1036 + }
1037 +
1038 + host->cmd->error = 0;
1039 +
1040 + /* Finished CMD23, now send actual command. */
1041 + if (host->cmd == host->mrq->sbc) {
1042 + host->cmd = NULL;
1043 + bcm2835_mmc_send_command(host, host->mrq->cmd);
1044 +
1045 + if (host->mrq->cmd->data && host->use_dma) {
1046 + /* DMA transfer starts now, PIO starts after interrupt */
1047 + bcm2835_mmc_transfer_dma(host);
1048 + }
1049 + } else {
1050 +
1051 + /* Processed actual command. */
1052 + if (host->data && host->data_early)
1053 + bcm2835_mmc_finish_data(host);
1054 +
1055 + if (!host->cmd->data)
1056 + tasklet_schedule(&host->finish_tasklet);
1057 +
1058 + host->cmd = NULL;
1059 + }
1060 +}
1061 +
1062 +
1063 +static void bcm2835_mmc_timeout_timer(unsigned long data)
1064 +{
1065 + struct bcm2835_host *host;
1066 + unsigned long flags;
1067 +
1068 + host = (struct bcm2835_host *)data;
1069 +
1070 + spin_lock_irqsave(&host->lock, flags);
1071 +
1072 + if (host->mrq) {
1073 + pr_err("%s: Timeout waiting for hardware interrupt.\n",
1074 + mmc_hostname(host->mmc));
1075 + bcm2835_mmc_dumpregs(host);
1076 +
1077 + if (host->data) {
1078 + host->data->error = -ETIMEDOUT;
1079 + bcm2835_mmc_finish_data(host);
1080 + } else {
1081 + if (host->cmd)
1082 + host->cmd->error = -ETIMEDOUT;
1083 + else
1084 + host->mrq->cmd->error = -ETIMEDOUT;
1085 +
1086 + tasklet_schedule(&host->finish_tasklet);
1087 + }
1088 + }
1089 +
1090 + mmiowb();
1091 + spin_unlock_irqrestore(&host->lock, flags);
1092 +}
1093 +
1094 +
1095 +static void bcm2835_mmc_enable_sdio_irq_nolock(struct bcm2835_host *host, int enable)
1096 +{
1097 + if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1098 + if (enable)
1099 + host->ier |= SDHCI_INT_CARD_INT;
1100 + else
1101 + host->ier &= ~SDHCI_INT_CARD_INT;
1102 +
1103 + bcm2835_mmc_writel(host, host->ier, SDHCI_INT_ENABLE, 7);
1104 + bcm2835_mmc_writel(host, host->ier, SDHCI_SIGNAL_ENABLE, 7);
1105 + mmiowb();
1106 + }
1107 +}
1108 +
1109 +static void bcm2835_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1110 +{
1111 + struct bcm2835_host *host = mmc_priv(mmc);
1112 + unsigned long flags;
1113 +
1114 + spin_lock_irqsave(&host->lock, flags);
1115 + if (enable)
1116 + host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1117 + else
1118 + host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1119 +
1120 + bcm2835_mmc_enable_sdio_irq_nolock(host, enable);
1121 + spin_unlock_irqrestore(&host->lock, flags);
1122 +}
1123 +
1124 +static void bcm2835_mmc_cmd_irq(struct bcm2835_host *host, u32 intmask)
1125 +{
1126 +
1127 + BUG_ON(intmask == 0);
1128 +
1129 + if (!host->cmd) {
1130 + pr_err("%s: Got command interrupt 0x%08x even "
1131 + "though no command operation was in progress.\n",
1132 + mmc_hostname(host->mmc), (unsigned)intmask);
1133 + bcm2835_mmc_dumpregs(host);
1134 + return;
1135 + }
1136 +
1137 + if (intmask & SDHCI_INT_TIMEOUT)
1138 + host->cmd->error = -ETIMEDOUT;
1139 + else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1140 + SDHCI_INT_INDEX)) {
1141 + host->cmd->error = -EILSEQ;
1142 + }
1143 +
1144 + if (host->cmd->error) {
1145 + tasklet_schedule(&host->finish_tasklet);
1146 + return;
1147 + }
1148 +
1149 + if (intmask & SDHCI_INT_RESPONSE)
1150 + bcm2835_mmc_finish_command(host);
1151 +
1152 +}
1153 +
1154 +static void bcm2835_mmc_data_irq(struct bcm2835_host *host, u32 intmask)
1155 +{
1156 + struct dma_chan *dma_chan;
1157 + u32 dir_data;
1158 +
1159 + BUG_ON(intmask == 0);
1160 +
1161 + if (!host->data) {
1162 + /*
1163 + * The "data complete" interrupt is also used to
1164 + * indicate that a busy state has ended. See comment
1165 + * above in sdhci_cmd_irq().
1166 + */
1167 + if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
1168 + if (intmask & SDHCI_INT_DATA_END) {
1169 + bcm2835_mmc_finish_command(host);
1170 + return;
1171 + }
1172 + }
1173 +
1174 + pr_debug("%s: Got data interrupt 0x%08x even "
1175 + "though no data operation was in progress.\n",
1176 + mmc_hostname(host->mmc), (unsigned)intmask);
1177 + bcm2835_mmc_dumpregs(host);
1178 +
1179 + return;
1180 + }
1181 +
1182 + if (intmask & SDHCI_INT_DATA_TIMEOUT)
1183 + host->data->error = -ETIMEDOUT;
1184 + else if (intmask & SDHCI_INT_DATA_END_BIT)
1185 + host->data->error = -EILSEQ;
1186 + else if ((intmask & SDHCI_INT_DATA_CRC) &&
1187 + SDHCI_GET_CMD(bcm2835_mmc_readw(host, SDHCI_COMMAND))
1188 + != MMC_BUS_TEST_R)
1189 + host->data->error = -EILSEQ;
1190 +
1191 + if (host->use_dma) {
1192 + if (host->data->flags & MMC_DATA_WRITE) {
1193 + /* IRQ handled here */
1194 +
1195 + dma_chan = host->dma_chan_tx;
1196 + dir_data = DMA_TO_DEVICE;
1197 + dma_unmap_sg(dma_chan->device->dev,
1198 + host->data->sg, host->data->sg_len,
1199 + dir_data);
1200 +
1201 + bcm2835_mmc_finish_data(host);
1202 + }
1203 +
1204 + } else {
1205 + if (host->data->error)
1206 + bcm2835_mmc_finish_data(host);
1207 + else {
1208 + if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
1209 + bcm2835_mmc_transfer_pio(host);
1210 +
1211 + if (intmask & SDHCI_INT_DATA_END) {
1212 + if (host->cmd) {
1213 + /*
1214 + * Data managed to finish before the
1215 + * command completed. Make sure we do
1216 + * things in the proper order.
1217 + */
1218 + host->data_early = 1;
1219 + } else {
1220 + bcm2835_mmc_finish_data(host);
1221 + }
1222 + }
1223 + }
1224 + }
1225 +}
1226 +
1227 +
1228 +static irqreturn_t bcm2835_mmc_irq(int irq, void *dev_id)
1229 +{
1230 + irqreturn_t result = IRQ_NONE;
1231 + struct bcm2835_host *host = dev_id;
1232 + u32 intmask, mask, unexpected = 0;
1233 + int max_loops = 16;
1234 +#ifndef CONFIG_ARCH_BCM2835
1235 + int cardint = 0;
1236 +#endif
1237 +
1238 + spin_lock(&host->lock);
1239 +
1240 + intmask = bcm2835_mmc_readl(host, SDHCI_INT_STATUS);
1241 +
1242 + if (!intmask || intmask == 0xffffffff) {
1243 + result = IRQ_NONE;
1244 + goto out;
1245 + }
1246 +
1247 + do {
1248 + /* Clear selected interrupts. */
1249 + mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
1250 + SDHCI_INT_BUS_POWER);
1251 + bcm2835_mmc_writel(host, mask, SDHCI_INT_STATUS, 8);
1252 +
1253 +
1254 + if (intmask & SDHCI_INT_CMD_MASK)
1255 + bcm2835_mmc_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1256 +
1257 + if (intmask & SDHCI_INT_DATA_MASK)
1258 + bcm2835_mmc_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1259 +
1260 + if (intmask & SDHCI_INT_BUS_POWER)
1261 + pr_err("%s: Card is consuming too much power!\n",
1262 + mmc_hostname(host->mmc));
1263 +
1264 + if (intmask & SDHCI_INT_CARD_INT) {
1265 +#ifndef CONFIG_ARCH_BCM2835
1266 + cardint = 1;
1267 +#else
1268 + bcm2835_mmc_enable_sdio_irq_nolock(host, false);
1269 + host->thread_isr |= SDHCI_INT_CARD_INT;
1270 + result = IRQ_WAKE_THREAD;
1271 +#endif
1272 + }
1273 +
1274 + intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
1275 + SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
1276 + SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
1277 + SDHCI_INT_CARD_INT);
1278 +
1279 + if (intmask) {
1280 + unexpected |= intmask;
1281 + bcm2835_mmc_writel(host, intmask, SDHCI_INT_STATUS, 9);
1282 + }
1283 +
1284 + if (result == IRQ_NONE)
1285 + result = IRQ_HANDLED;
1286 +
1287 + intmask = bcm2835_mmc_readl(host, SDHCI_INT_STATUS);
1288 + } while (intmask && --max_loops);
1289 +out:
1290 + spin_unlock(&host->lock);
1291 +
1292 + if (unexpected) {
1293 + pr_err("%s: Unexpected interrupt 0x%08x.\n",
1294 + mmc_hostname(host->mmc), unexpected);
1295 + bcm2835_mmc_dumpregs(host);
1296 + }
1297 +
1298 +#ifndef CONFIG_ARCH_BCM2835
1299 + if (cardint)
1300 + mmc_signal_sdio_irq(host->mmc);
1301 +#endif
1302 +
1303 + return result;
1304 +}
1305 +
1306 +#ifdef CONFIG_ARCH_BCM2835
1307 +static irqreturn_t bcm2835_mmc_thread_irq(int irq, void *dev_id)
1308 +{
1309 + struct bcm2835_host *host = dev_id;
1310 + unsigned long flags;
1311 + u32 isr;
1312 +
1313 + spin_lock_irqsave(&host->lock, flags);
1314 + isr = host->thread_isr;
1315 + host->thread_isr = 0;
1316 + spin_unlock_irqrestore(&host->lock, flags);
1317 +
1318 + if (isr & SDHCI_INT_CARD_INT) {
1319 + sdio_run_irqs(host->mmc);
1320 +
1321 + spin_lock_irqsave(&host->lock, flags);
1322 + if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
1323 + bcm2835_mmc_enable_sdio_irq_nolock(host, true);
1324 + spin_unlock_irqrestore(&host->lock, flags);
1325 + }
1326 +
1327 + return isr ? IRQ_HANDLED : IRQ_NONE;
1328 +}
1329 +#endif
1330 +
1331 +
1332 +
1333 +void bcm2835_mmc_set_clock(struct bcm2835_host *host, unsigned int clock)
1334 +{
1335 + int div = 0; /* Initialized for compiler warning */
1336 + int real_div = div, clk_mul = 1;
1337 + u16 clk = 0;
1338 + unsigned long timeout;
1339 + unsigned int input_clock = clock;
1340 +
1341 + if (host->overclock_50 && (clock == 50000000))
1342 + clock = host->overclock_50 * 1000000 + 999999;
1343 +
1344 + host->mmc->actual_clock = 0;
1345 +
1346 + bcm2835_mmc_writew(host, 0, SDHCI_CLOCK_CONTROL);
1347 +
1348 + if (clock == 0)
1349 + return;
1350 +
1351 + /* Version 3.00 divisors must be a multiple of 2. */
1352 + if (host->max_clk <= clock)
1353 + div = 1;
1354 + else {
1355 + for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1356 + div += 2) {
1357 + if ((host->max_clk / div) <= clock)
1358 + break;
1359 + }
1360 + }
1361 +
1362 + real_div = div;
1363 + div >>= 1;
1364 +
1365 + if (real_div)
1366 + clock = (host->max_clk * clk_mul) / real_div;
1367 + host->mmc->actual_clock = clock;
1368 +
1369 + if ((clock > input_clock) && (clock > host->max_overclock)) {
1370 + pr_warn("%s: Overclocking to %dHz\n",
1371 + mmc_hostname(host->mmc), clock);
1372 + host->max_overclock = clock;
1373 + }
1374 +
1375 + clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1376 + clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1377 + << SDHCI_DIVIDER_HI_SHIFT;
1378 + clk |= SDHCI_CLOCK_INT_EN;
1379 + bcm2835_mmc_writew(host, clk, SDHCI_CLOCK_CONTROL);
1380 +
1381 + /* Wait max 20 ms */
1382 + timeout = 20;
1383 + while (!((clk = bcm2835_mmc_readw(host, SDHCI_CLOCK_CONTROL))
1384 + & SDHCI_CLOCK_INT_STABLE)) {
1385 + if (timeout == 0) {
1386 + pr_err("%s: Internal clock never "
1387 + "stabilised.\n", mmc_hostname(host->mmc));
1388 + bcm2835_mmc_dumpregs(host);
1389 + return;
1390 + }
1391 + timeout--;
1392 + mdelay(1);
1393 + }
1394 +
1395 + if (20-timeout > 10 && 20-timeout > host->max_delay) {
1396 + host->max_delay = 20-timeout;
1397 + pr_warning("Warning: MMC controller hung for %d ms\n", host->max_delay);
1398 + }
1399 +
1400 + clk |= SDHCI_CLOCK_CARD_EN;
1401 + bcm2835_mmc_writew(host, clk, SDHCI_CLOCK_CONTROL);
1402 +}
1403 +
1404 +static void bcm2835_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
1405 +{
1406 + struct bcm2835_host *host;
1407 + unsigned long flags;
1408 +
1409 + host = mmc_priv(mmc);
1410 +
1411 + spin_lock_irqsave(&host->lock, flags);
1412 +
1413 + WARN_ON(host->mrq != NULL);
1414 +
1415 + host->mrq = mrq;
1416 +
1417 + if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1418 + bcm2835_mmc_send_command(host, mrq->sbc);
1419 + else
1420 + bcm2835_mmc_send_command(host, mrq->cmd);
1421 +
1422 + mmiowb();
1423 + spin_unlock_irqrestore(&host->lock, flags);
1424 +
1425 + if (!(mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) && mrq->cmd->data && host->use_dma) {
1426 + /* DMA transfer starts now, PIO starts after interrupt */
1427 + bcm2835_mmc_transfer_dma(host);
1428 + }
1429 +}
1430 +
1431 +
1432 +static void bcm2835_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1433 +{
1434 +
1435 + struct bcm2835_host *host = mmc_priv(mmc);
1436 + unsigned long flags;
1437 + u8 ctrl;
1438 + u16 clk, ctrl_2;
1439 +
1440 + pr_debug("bcm2835_mmc_set_ios: clock %d, pwr %d, bus_width %d, timing %d, vdd %d, drv_type %d\n",
1441 + ios->clock, ios->power_mode, ios->bus_width,
1442 + ios->timing, ios->signal_voltage, ios->drv_type);
1443 +
1444 + spin_lock_irqsave(&host->lock, flags);
1445 +
1446 + if (!ios->clock || ios->clock != host->clock) {
1447 + bcm2835_mmc_set_clock(host, ios->clock);
1448 + host->clock = ios->clock;
1449 + }
1450 +
1451 + if (host->pwr != SDHCI_POWER_330) {
1452 + host->pwr = SDHCI_POWER_330;
1453 + bcm2835_mmc_writeb(host, SDHCI_POWER_330 | SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1454 + }
1455 +
1456 + ctrl = bcm2835_mmc_readb(host, SDHCI_HOST_CONTROL);
1457 +
1458 + /* set bus width */
1459 + ctrl &= ~SDHCI_CTRL_8BITBUS;
1460 + if (ios->bus_width == MMC_BUS_WIDTH_4)
1461 + ctrl |= SDHCI_CTRL_4BITBUS;
1462 + else
1463 + ctrl &= ~SDHCI_CTRL_4BITBUS;
1464 +
1465 + ctrl &= ~SDHCI_CTRL_HISPD; /* NO_HISPD_BIT */
1466 +
1467 +
1468 + bcm2835_mmc_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1469 + /*
1470 + * We only need to set Driver Strength if the
1471 + * preset value enable is not set.
1472 + */
1473 + ctrl_2 = bcm2835_mmc_readw(host, SDHCI_HOST_CONTROL2);
1474 + ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1475 + if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1476 + ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1477 + else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1478 + ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1479 +
1480 + bcm2835_mmc_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1481 +
1482 + /* Reset SD Clock Enable */
1483 + clk = bcm2835_mmc_readw(host, SDHCI_CLOCK_CONTROL);
1484 + clk &= ~SDHCI_CLOCK_CARD_EN;
1485 + bcm2835_mmc_writew(host, clk, SDHCI_CLOCK_CONTROL);
1486 +
1487 + /* Re-enable SD Clock */
1488 + bcm2835_mmc_set_clock(host, host->clock);
1489 + bcm2835_mmc_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1490 +
1491 + mmiowb();
1492 +
1493 + spin_unlock_irqrestore(&host->lock, flags);
1494 +}
1495 +
1496 +
1497 +static struct mmc_host_ops bcm2835_ops = {
1498 + .request = bcm2835_mmc_request,
1499 + .set_ios = bcm2835_mmc_set_ios,
1500 + .enable_sdio_irq = bcm2835_mmc_enable_sdio_irq,
1501 +};
1502 +
1503 +
1504 +static void bcm2835_mmc_tasklet_finish(unsigned long param)
1505 +{
1506 + struct bcm2835_host *host;
1507 + unsigned long flags;
1508 + struct mmc_request *mrq;
1509 +
1510 + host = (struct bcm2835_host *)param;
1511 +
1512 + spin_lock_irqsave(&host->lock, flags);
1513 +
1514 + /*
1515 + * If this tasklet gets rescheduled while running, it will
1516 + * be run again afterwards but without any active request.
1517 + */
1518 + if (!host->mrq) {
1519 + spin_unlock_irqrestore(&host->lock, flags);
1520 + return;
1521 + }
1522 +
1523 + del_timer(&host->timer);
1524 +
1525 + mrq = host->mrq;
1526 +
1527 + /*
1528 + * The controller needs a reset of internal state machines
1529 + * upon error conditions.
1530 + */
1531 + if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1532 + ((mrq->cmd && mrq->cmd->error) ||
1533 + (mrq->data && (mrq->data->error ||
1534 + (mrq->data->stop && mrq->data->stop->error))))) {
1535 +
1536 + spin_unlock_irqrestore(&host->lock, flags);
1537 + bcm2835_mmc_reset(host, SDHCI_RESET_CMD);
1538 + bcm2835_mmc_reset(host, SDHCI_RESET_DATA);
1539 + spin_lock_irqsave(&host->lock, flags);
1540 + }
1541 +
1542 + host->mrq = NULL;
1543 + host->cmd = NULL;
1544 + host->data = NULL;
1545 +
1546 + mmiowb();
1547 +
1548 + spin_unlock_irqrestore(&host->lock, flags);
1549 + mmc_request_done(host->mmc, mrq);
1550 +}
1551 +
1552 +
1553 +
1554 +static int bcm2835_mmc_add_host(struct bcm2835_host *host)
1555 +{
1556 + struct mmc_host *mmc = host->mmc;
1557 + struct device *dev = mmc->parent;
1558 +#ifndef FORCE_PIO
1559 + struct dma_slave_config cfg;
1560 +#endif
1561 + int ret;
1562 +
1563 + bcm2835_mmc_reset(host, SDHCI_RESET_ALL);
1564 +
1565 + host->clk_mul = 0;
1566 +
1567 + mmc->f_max = host->max_clk;
1568 + mmc->f_max = host->max_clk;
1569 + mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
1570 +
1571 + /* SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK */
1572 + host->timeout_clk = mmc->f_max / 1000;
1573 +#ifdef CONFIG_ARCH_BCM2835
1574 + mmc->max_busy_timeout = (1 << 27) / host->timeout_clk;
1575 +#endif
1576 + /* host controller capabilities */
1577 + mmc->caps = MMC_CAP_CMD23 | MMC_CAP_ERASE | MMC_CAP_NEEDS_POLL | MMC_CAP_SDIO_IRQ |
1578 + MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_4_BIT_DATA;
1579 +
1580 + host->flags = SDHCI_AUTO_CMD23;
1581 +
1582 + dev_info(dev, "mmc_debug:%x mmc_debug2:%x\n", mmc_debug, mmc_debug2);
1583 +#ifdef FORCE_PIO
1584 + dev_info(dev, "Forcing PIO mode\n");
1585 + host->have_dma = false;
1586 +#else
1587 + if (IS_ERR_OR_NULL(host->dma_chan_tx) ||
1588 + IS_ERR_OR_NULL(host->dma_chan_rx)) {
1589 + dev_err(dev, "%s: Unable to initialise DMA channels. Falling back to PIO\n",
1590 + DRIVER_NAME);
1591 + host->have_dma = false;
1592 + } else {
1593 + dev_info(dev, "DMA channels allocated");
1594 + host->have_dma = true;
1595 +
1596 + cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1597 + cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1598 + cfg.slave_id = 11; /* DREQ channel */
1599 +
1600 + cfg.direction = DMA_MEM_TO_DEV;
1601 + cfg.src_addr = 0;
1602 + cfg.dst_addr = host->phys_addr + SDHCI_BUFFER;
1603 + ret = dmaengine_slave_config(host->dma_chan_tx, &cfg);
1604 +
1605 + cfg.direction = DMA_DEV_TO_MEM;
1606 + cfg.src_addr = host->phys_addr + SDHCI_BUFFER;
1607 + cfg.dst_addr = 0;
1608 + ret = dmaengine_slave_config(host->dma_chan_rx, &cfg);
1609 + }
1610 +#endif
1611 + mmc->max_segs = 128;
1612 + mmc->max_req_size = 524288;
1613 + mmc->max_seg_size = mmc->max_req_size;
1614 + mmc->max_blk_size = 512;
1615 + mmc->max_blk_count = 65535;
1616 +
1617 + /* report supported voltage ranges */
1618 + mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1619 +
1620 + tasklet_init(&host->finish_tasklet,
1621 + bcm2835_mmc_tasklet_finish, (unsigned long)host);
1622 +
1623 + setup_timer(&host->timer, bcm2835_mmc_timeout_timer, (unsigned long)host);
1624 + init_waitqueue_head(&host->buf_ready_int);
1625 +
1626 + bcm2835_mmc_init(host, 0);
1627 +#ifndef CONFIG_ARCH_BCM2835
1628 + ret = devm_request_irq(dev, host->irq, bcm2835_mmc_irq, 0,
1629 + mmc_hostname(mmc), host);
1630 +#else
1631 + ret = devm_request_threaded_irq(dev, host->irq, bcm2835_mmc_irq,
1632 + bcm2835_mmc_thread_irq, IRQF_SHARED,
1633 + mmc_hostname(mmc), host);
1634 +#endif
1635 + if (ret) {
1636 + dev_err(dev, "Failed to request IRQ %d: %d\n", host->irq, ret);
1637 + goto untasklet;
1638 + }
1639 +
1640 + mmiowb();
1641 + mmc_add_host(mmc);
1642 +
1643 + return 0;
1644 +
1645 +untasklet:
1646 + tasklet_kill(&host->finish_tasklet);
1647 +
1648 + return ret;
1649 +}
1650 +
1651 +static int bcm2835_mmc_probe(struct platform_device *pdev)
1652 +{
1653 + struct device *dev = &pdev->dev;
1654 + struct device_node *node = dev->of_node;
1655 + struct clk *clk;
1656 + struct resource *iomem;
1657 + struct bcm2835_host *host;
1658 + struct mmc_host *mmc;
1659 + int ret;
1660 +
1661 + mmc = mmc_alloc_host(sizeof(*host), dev);
1662 + if (!mmc)
1663 + return -ENOMEM;
1664 +
1665 + mmc->ops = &bcm2835_ops;
1666 + host = mmc_priv(mmc);
1667 + host->mmc = mmc;
1668 + host->timeout = msecs_to_jiffies(1000);
1669 + spin_lock_init(&host->lock);
1670 +
1671 + iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1672 + host->ioaddr = devm_ioremap_resource(dev, iomem);
1673 + if (IS_ERR(host->ioaddr)) {
1674 + ret = PTR_ERR(host->ioaddr);
1675 + goto err;
1676 + }
1677 +
1678 + host->phys_addr = iomem->start + BCM2835_VCMMU_SHIFT;
1679 +
1680 +#ifndef FORCE_PIO
1681 + if (node) {
1682 + host->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1683 + host->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1684 + } else {
1685 + dma_cap_mask_t mask;
1686 +
1687 + dma_cap_zero(mask);
1688 + /* we don't care about the channel, any would work */
1689 + dma_cap_set(DMA_SLAVE, mask);
1690 + host->dma_chan_tx = dma_request_channel(mask, NULL, NULL);
1691 + host->dma_chan_rx = dma_request_channel(mask, NULL, NULL);
1692 + }
1693 +#endif
1694 + clk = devm_clk_get(dev, NULL);
1695 + if (IS_ERR(clk)) {
1696 + dev_err(dev, "could not get clk\n");
1697 + ret = PTR_ERR(clk);
1698 + goto err;
1699 + }
1700 +
1701 + host->max_clk = clk_get_rate(clk);
1702 +
1703 + host->irq = platform_get_irq(pdev, 0);
1704 + if (host->irq <= 0) {
1705 + dev_err(dev, "get IRQ failed\n");
1706 + ret = -EINVAL;
1707 + goto err;
1708 + }
1709 +
1710 + if (node) {
1711 + mmc_of_parse(mmc);
1712 +
1713 + /* Read any custom properties */
1714 + of_property_read_u32(node,
1715 + "brcm,overclock-50",
1716 + &host->overclock_50);
1717 + } else {
1718 + mmc->caps |= MMC_CAP_4_BIT_DATA;
1719 + }
1720 +
1721 + ret = bcm2835_mmc_add_host(host);
1722 + if (ret)
1723 + goto err;
1724 +
1725 + platform_set_drvdata(pdev, host);
1726 +
1727 + return 0;
1728 +err:
1729 + mmc_free_host(mmc);
1730 +
1731 + return ret;
1732 +}
1733 +
1734 +static int bcm2835_mmc_remove(struct platform_device *pdev)
1735 +{
1736 + struct bcm2835_host *host = platform_get_drvdata(pdev);
1737 + unsigned long flags;
1738 + int dead;
1739 + u32 scratch;
1740 +
1741 + dead = 0;
1742 + scratch = bcm2835_mmc_readl(host, SDHCI_INT_STATUS);
1743 + if (scratch == (u32)-1)
1744 + dead = 1;
1745 +
1746 +
1747 + if (dead) {
1748 + spin_lock_irqsave(&host->lock, flags);
1749 +
1750 + host->flags |= SDHCI_DEVICE_DEAD;
1751 +
1752 + if (host->mrq) {
1753 + pr_err("%s: Controller removed during "
1754 + " transfer!\n", mmc_hostname(host->mmc));
1755 +
1756 + host->mrq->cmd->error = -ENOMEDIUM;
1757 + tasklet_schedule(&host->finish_tasklet);
1758 + }
1759 +
1760 + spin_unlock_irqrestore(&host->lock, flags);
1761 + }
1762 +
1763 + mmc_remove_host(host->mmc);
1764 +
1765 + if (!dead)
1766 + bcm2835_mmc_reset(host, SDHCI_RESET_ALL);
1767 +
1768 + free_irq(host->irq, host);
1769 +
1770 + del_timer_sync(&host->timer);
1771 +
1772 + tasklet_kill(&host->finish_tasklet);
1773 +
1774 + mmc_free_host(host->mmc);
1775 + platform_set_drvdata(pdev, NULL);
1776 +
1777 + return 0;
1778 +}
1779 +
1780 +
1781 +static const struct of_device_id bcm2835_mmc_match[] = {
1782 + { .compatible = "brcm,bcm2835-mmc" },
1783 + { }
1784 +};
1785 +MODULE_DEVICE_TABLE(of, bcm2835_mmc_match);
1786 +
1787 +
1788 +
1789 +static struct platform_driver bcm2835_mmc_driver = {
1790 + .probe = bcm2835_mmc_probe,
1791 + .remove = bcm2835_mmc_remove,
1792 + .driver = {
1793 + .name = DRIVER_NAME,
1794 + .owner = THIS_MODULE,
1795 + .of_match_table = bcm2835_mmc_match,
1796 + },
1797 +};
1798 +module_platform_driver(bcm2835_mmc_driver);
1799 +
1800 +module_param(mmc_debug, uint, 0644);
1801 +module_param(mmc_debug2, uint, 0644);
1802 +MODULE_ALIAS("platform:mmc-bcm2835");
1803 +MODULE_DESCRIPTION("BCM2835 SDHCI driver");
1804 +MODULE_LICENSE("GPL v2");
1805 +MODULE_AUTHOR("Gellert Weisz");
OpenWrt Source Repository