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brcm2708: update 4.1 patches
[openwrt/openwrt.git] / target / linux / brcm2708 / patches-4.1 / 0054-bcm2709-Simplify-and-strip-down-IRQ-handler.patch
1 From 39a6ff9b1ecb74c734606429647a9d783c7504f1 Mon Sep 17 00:00:00 2001
2 From: popcornmix <popcornmix@gmail.com>
3 Date: Fri, 20 Jun 2014 17:19:27 +0100
4 Subject: [PATCH 054/148] bcm2709: Simplify and strip down IRQ handler
5
6 ---
7 arch/arm/include/asm/entry-macro-multi.S | 2 +
8 arch/arm/mach-bcm2709/include/mach/entry-macro.S | 173 +++++++++++------------
9 2 files changed, 87 insertions(+), 88 deletions(-)
10
11 --- a/arch/arm/include/asm/entry-macro-multi.S
12 +++ b/arch/arm/include/asm/entry-macro-multi.S
13 @@ -1,5 +1,6 @@
14 #include <asm/assembler.h>
15
16 +#ifndef CONFIG_ARCH_BCM2709
17 /*
18 * Interrupt handling. Preserves r7, r8, r9
19 */
20 @@ -28,6 +29,7 @@
21 #endif
22 9997:
23 .endm
24 +#endif
25
26 .macro arch_irq_handler, symbol_name
27 .align 5
28 --- a/arch/arm/mach-bcm2709/include/mach/entry-macro.S
29 +++ b/arch/arm/mach-bcm2709/include/mach/entry-macro.S
30 @@ -22,102 +22,99 @@
31 #include <mach/hardware.h>
32 #include <mach/irqs.h>
33
34 - .macro disable_fiq
35 - .endm
36 + .macro arch_ret_to_user, tmp1, tmp2
37 + .endm
38
39 - .macro get_irqnr_preamble, base, tmp
40 - ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE)
41 - .endm
42 -
43 - .macro arch_ret_to_user, tmp1, tmp2
44 - .endm
45 -
46 - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
47 - /* get core number */
48 - mrc p15, 0, \tmp, c0, c0, 5
49 - ubfx \tmp, \tmp, #0, #2
50 -
51 - /* get core's local interrupt controller */
52 - ldr \irqstat, = __io_address(ARM_LOCAL_IRQ_PENDING0) @ local interrupt source
53 - add \irqstat, \irqstat, \tmp, lsl #2
54 - ldr \tmp, [\irqstat]
55 - /* ignore gpu interrupt */
56 - bic \tmp, #0x100
57 - /* ignore mailbox interrupts */
58 - bics \tmp, #0xf0
59 - beq 1005f
60 -
61 - @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
62 - @ N.B. CLZ is an ARM5 instruction.
63 - mov \irqnr, #(ARM_IRQ_LOCAL_BASE + 31)
64 - sub \irqstat, \tmp, #1
65 - eor \irqstat, \irqstat, \tmp
66 - clz \tmp, \irqstat
67 - sub \irqnr, \tmp
68 - b 1020f
69 -1005:
70 - /* get core number */
71 - mrc p15, 0, \tmp, c0, c0, 5
72 - ubfx \tmp, \tmp, #0, #2
73 -
74 - cmp \tmp, #1
75 - beq 1020f
76 - cmp \tmp, #2
77 - beq 1020f
78 - cmp \tmp, #3
79 - beq 1020f
80 -
81 - /* get masked status */
82 - ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)]
83 - mov \irqnr, #(ARM_IRQ0_BASE + 31)
84 - and \tmp, \irqstat, #0x300 @ save bits 8 and 9
85 - /* clear bits 8 and 9, and test */
86 - bics \irqstat, \irqstat, #0x300
87 - bne 1010f
88 -
89 - tst \tmp, #0x100
90 - ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)]
91 - movne \irqnr, #(ARM_IRQ1_BASE + 31)
92 - @ Mask out the interrupts also present in PEND0 - see SW-5809
93 - bicne \irqstat, #((1<<7) | (1<<9) | (1<<10))
94 - bicne \irqstat, #((1<<18) | (1<<19))
95 - bne 1010f
96 -
97 - tst \tmp, #0x200
98 - ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)]
99 - movne \irqnr, #(ARM_IRQ2_BASE + 31)
100 - @ Mask out the interrupts also present in PEND0 - see SW-5809
101 - bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25))
102 - bicne \irqstat, #((1<<30))
103 - beq 1020f
104 + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
105
106 + /* get core number */
107 + mrc p15, 0, \base, c0, c0, 5
108 + ubfx \base, \base, #0, #2
109 +
110 + /* get core's local interrupt controller */
111 + ldr \irqstat, = __io_address(ARM_LOCAL_IRQ_PENDING0) @ local interrupt source
112 + add \irqstat, \irqstat, \base, lsl #2
113 + ldr \tmp, [\irqstat]
114 +#ifdef CONFIG_SMP
115 + /* test for mailbox0 (IPI) interrupt */
116 + tst \tmp, #0x10
117 + beq 1030f
118 +
119 + /* get core's mailbox interrupt control */
120 + ldr \irqstat, = __io_address(ARM_LOCAL_MAILBOX0_CLR0) @ mbox_clr
121 + add \irqstat, \irqstat, \base, lsl #4
122 + ldr \tmp, [\irqstat]
123 + clz \tmp, \tmp
124 + rsb \irqnr, \tmp, #31
125 + mov \tmp, #1
126 + lsl \tmp, \irqnr
127 + str \tmp, [\irqstat] @ clear interrupt source
128 + dsb
129 + mov r1, sp
130 + adr lr, BSYM(1b)
131 + b do_IPI
132 +#endif
133 +1030:
134 + /* check gpu interrupt */
135 + tst \tmp, #0x100
136 + beq 1040f
137 +
138 + ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE)
139 + /* get masked status */
140 + ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)]
141 + mov \irqnr, #(ARM_IRQ0_BASE + 31)
142 + and \tmp, \irqstat, #0x300 @ save bits 8 and 9
143 + /* clear bits 8 and 9, and test */
144 + bics \irqstat, \irqstat, #0x300
145 + bne 1010f
146 +
147 + tst \tmp, #0x100
148 + ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)]
149 + movne \irqnr, #(ARM_IRQ1_BASE + 31)
150 + @ Mask out the interrupts also present in PEND0 - see SW-5809
151 + bicne \irqstat, #((1<<7) | (1<<9) | (1<<10))
152 + bicne \irqstat, #((1<<18) | (1<<19))
153 + bne 1010f
154 +
155 + tst \tmp, #0x200
156 + ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)]
157 + movne \irqnr, #(ARM_IRQ2_BASE + 31)
158 + @ Mask out the interrupts also present in PEND0 - see SW-5809
159 + bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25))
160 + bicne \irqstat, #((1<<30))
161 + beq 1020f
162 1010:
163 - @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
164 - @ N.B. CLZ is an ARM5 instruction.
165 - sub \tmp, \irqstat, #1
166 - eor \irqstat, \irqstat, \tmp
167 - clz \tmp, \irqstat
168 - sub \irqnr, \tmp
169 + @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
170 + sub \tmp, \irqstat, #1
171 + eor \irqstat, \irqstat, \tmp
172 + clz \tmp, \irqstat
173 + sub \irqnr, \tmp
174 + b 1050f
175 +1040:
176 + cmp \tmp, #0
177 + beq 1020f
178 +
179 + /* handle local (e.g. timer) interrupts */
180 + @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
181 + mov \irqnr, #(ARM_IRQ_LOCAL_BASE + 31)
182 + sub \irqstat, \tmp, #1
183 + eor \irqstat, \irqstat, \tmp
184 + clz \tmp, \irqstat
185 + sub \irqnr, \tmp
186 +1050:
187 + mov r1, sp
188 + @
189 + @ routine called with r0 = irq number, r1 = struct pt_regs *
190 + @
191 + adr lr, BSYM(1b)
192 + b asm_do_IRQ
193
194 1020: @ EQ will be set if no irqs pending
195 + .endm
196
197 - .endm
198 -
199 - .macro test_for_ipi, irqnr, irqstat, base, tmp
200 - /* get core number */
201 - mrc p15, 0, \tmp, c0, c0, 5
202 - ubfx \tmp, \tmp, #0, #2
203 - /* get core's mailbox interrupt control */
204 - ldr \irqstat, = __io_address(ARM_LOCAL_MAILBOX0_CLR0) @ mbox_clr
205 - add \irqstat, \irqstat, \tmp, lsl #4
206 - ldr \tmp, [\irqstat]
207 - cmp \tmp, #0
208 - beq 1030f
209 - clz \tmp, \tmp
210 - rsb \irqnr, \tmp, #31
211 - mov \tmp, #1
212 - lsl \tmp, \irqnr
213 - str \tmp, [\irqstat] @ clear interrupt source
214 - dsb
215 -1030: @ EQ will be set if no irqs pending
216 - .endm
217 +/*
218 + * Interrupt handling. Preserves r7, r8, r9
219 + */
220 + .macro arch_irq_handler_default
221 +1: get_irqnr_and_base r0, r2, r6, lr
222 + .endm
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