target/linux/brcm2708/patches-4.19/950-0402-ASoC-tlv320aic32x4-Model-PLL-in-CCF.patch

   1 From 721de503c943a8c9f0b957e27099c7b2ec38a37a Mon Sep 17 00:00:00 2001
   2 From: Annaliese McDermond <nh6z@nh6z.net>
   3 Date: Thu, 21 Mar 2019 17:58:45 -0700
   4 Subject: [PATCH 402/725] ASoC: tlv320aic32x4: Model PLL in CCF
   5
   6 commit 514b044cba667e4b7c383ec79b42b997e624b91d upstream.
   7
   8 Model and manage the on-board PLL as a component in the Core
   9 Clock Framework.  This should allow us to do some more complex
  10 clock management and power control.  Also, some of the
  11 on-board chip clocks can be exposed to the outside, and this
  12 change will make those clocks easier to consume by other
  13 parts of the kernel.
  14
  15 Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
  16 Signed-off-by: Mark Brown <broonie@kernel.org>
  17 ---
  18  sound/soc/codecs/Kconfig             |   1 +
  19  sound/soc/codecs/Makefile            |   2 +-
  20  sound/soc/codecs/tlv320aic32x4-clk.c | 323 +++++++++++++++++++++++++++
  21  sound/soc/codecs/tlv320aic32x4.c     | 195 ++++++++--------
  22  sound/soc/codecs/tlv320aic32x4.h     |   5 +
  23  5 files changed, 431 insertions(+), 95 deletions(-)
  24  create mode 100644 sound/soc/codecs/tlv320aic32x4-clk.c
  25
  26 --- a/sound/soc/codecs/Kconfig
  27 +++ b/sound/soc/codecs/Kconfig
  28 @@ -1025,6 +1025,7 @@ config SND_SOC_TLV320AIC31XX
  29
  30  config SND_SOC_TLV320AIC32X4
  31         tristate
  32 +       depends on COMMON_CLK
  33
  34  config SND_SOC_TLV320AIC32X4_I2C
  35         tristate "Texas Instruments TLV320AIC32x4 audio CODECs - I2C"
  36 --- a/sound/soc/codecs/Makefile
  37 +++ b/sound/soc/codecs/Makefile
  38 @@ -182,7 +182,7 @@ snd-soc-tlv320aic23-i2c-objs := tlv320ai
  39  snd-soc-tlv320aic23-spi-objs := tlv320aic23-spi.o
  40  snd-soc-tlv320aic26-objs := tlv320aic26.o
  41  snd-soc-tlv320aic31xx-objs := tlv320aic31xx.o
  42 -snd-soc-tlv320aic32x4-objs := tlv320aic32x4.o
  43 +snd-soc-tlv320aic32x4-objs := tlv320aic32x4.o tlv320aic32x4-clk.o
  44  snd-soc-tlv320aic32x4-i2c-objs := tlv320aic32x4-i2c.o
  45  snd-soc-tlv320aic32x4-spi-objs := tlv320aic32x4-spi.o
  46  snd-soc-tlv320aic3x-objs := tlv320aic3x.o
  47 --- /dev/null
  48 +++ b/sound/soc/codecs/tlv320aic32x4-clk.c
  49 @@ -0,0 +1,323 @@
  50 +/* SPDX-License-Identifier: GPL-2.0
  51 + *
  52 + * Clock Tree for the Texas Instruments TLV320AIC32x4
  53 + *
  54 + * Copyright 2019 Annaliese McDermond
  55 + *
  56 + * Author: Annaliese McDermond <nh6z@nh6z.net>
  57 + */
  58 +
  59 +#include <linux/clk-provider.h>
  60 +#include <linux/clkdev.h>
  61 +#include <linux/regmap.h>
  62 +#include <linux/device.h>
  63 +
  64 +#include "tlv320aic32x4.h"
  65 +
  66 +#define to_clk_aic32x4(_hw) container_of(_hw, struct clk_aic32x4, hw)
  67 +struct clk_aic32x4 {
  68 +       struct clk_hw hw;
  69 +       struct device *dev;
  70 +       struct regmap *regmap;
  71 +       unsigned int reg;
  72 +};
  73 +
  74 +/*
  75 + * struct clk_aic32x4_pll_muldiv - Multiplier/divider settings
  76 + * @p:         Divider
  77 + * @r:         first multiplier
  78 + * @j:         integer part of second multiplier
  79 + * @d:         decimal part of second multiplier
  80 + */
  81 +struct clk_aic32x4_pll_muldiv {
  82 +       u8 p;
  83 +       u16 r;
  84 +       u8 j;
  85 +       u16 d;
  86 +};
  87 +
  88 +struct aic32x4_clkdesc {
  89 +       const char *name;
  90 +       const char * const *parent_names;
  91 +       unsigned int num_parents;
  92 +       const struct clk_ops *ops;
  93 +       unsigned int reg;
  94 +};
  95 +
  96 +static int clk_aic32x4_pll_prepare(struct clk_hw *hw)
  97 +{
  98 +       struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
  99 +
 100 +       return regmap_update_bits(pll->regmap, AIC32X4_PLLPR,
 101 +                               AIC32X4_PLLEN, AIC32X4_PLLEN);
 102 +}
 103 +
 104 +static void clk_aic32x4_pll_unprepare(struct clk_hw *hw)
 105 +{
 106 +       struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
 107 +
 108 +       regmap_update_bits(pll->regmap, AIC32X4_PLLPR,
 109 +                               AIC32X4_PLLEN, 0);
 110 +}
 111 +
 112 +static int clk_aic32x4_pll_is_prepared(struct clk_hw *hw)
 113 +{
 114 +       struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
 115 +
 116 +       unsigned int val;
 117 +       int ret;
 118 +
 119 +       ret = regmap_read(pll->regmap, AIC32X4_PLLPR, &val);
 120 +       if (ret < 0)
 121 +               return ret;
 122 +
 123 +       return !!(val & AIC32X4_PLLEN);
 124 +}
 125 +
 126 +static int clk_aic32x4_pll_get_muldiv(struct clk_aic32x4 *pll,
 127 +                       struct clk_aic32x4_pll_muldiv *settings)
 128 +{
 129 +       /*      Change to use regmap_bulk_read? */
 130 +       unsigned int val;
 131 +       int ret;
 132 +
 133 +       ret = regmap_read(pll->regmap, AIC32X4_PLLPR, &val);
 134 +       if (ret)
 135 +               return ret;
 136 +       settings->r = val & AIC32X4_PLL_R_MASK;
 137 +       settings->p = (val & AIC32X4_PLL_P_MASK) >> AIC32X4_PLL_P_SHIFT;
 138 +
 139 +       ret = regmap_read(pll->regmap, AIC32X4_PLLJ, &val);
 140 +       if (ret < 0)
 141 +               return ret;
 142 +       settings->j = val;
 143 +
 144 +       ret = regmap_read(pll->regmap, AIC32X4_PLLDMSB, &val);
 145 +       if (ret < 0)
 146 +               return ret;
 147 +       settings->d = val << 8;
 148 +
 149 +       ret = regmap_read(pll->regmap, AIC32X4_PLLDLSB,  &val);
 150 +       if (ret < 0)
 151 +               return ret;
 152 +       settings->d |= val;
 153 +
 154 +       return 0;
 155 +}
 156 +
 157 +static int clk_aic32x4_pll_set_muldiv(struct clk_aic32x4 *pll,
 158 +                       struct clk_aic32x4_pll_muldiv *settings)
 159 +{
 160 +       int ret;
 161 +       /*      Change to use regmap_bulk_write for some if not all? */
 162 +
 163 +       ret = regmap_update_bits(pll->regmap, AIC32X4_PLLPR,
 164 +                               AIC32X4_PLL_R_MASK, settings->r);
 165 +       if (ret < 0)
 166 +               return ret;
 167 +
 168 +       ret = regmap_update_bits(pll->regmap, AIC32X4_PLLPR,
 169 +                               AIC32X4_PLL_P_MASK,
 170 +                               settings->p << AIC32X4_PLL_P_SHIFT);
 171 +       if (ret < 0)
 172 +               return ret;
 173 +
 174 +       ret = regmap_write(pll->regmap, AIC32X4_PLLJ, settings->j);
 175 +       if (ret < 0)
 176 +               return ret;
 177 +
 178 +       ret = regmap_write(pll->regmap, AIC32X4_PLLDMSB, (settings->d >> 8));
 179 +       if (ret < 0)
 180 +               return ret;
 181 +       ret = regmap_write(pll->regmap, AIC32X4_PLLDLSB, (settings->d & 0xff));
 182 +       if (ret < 0)
 183 +               return ret;
 184 +
 185 +       return 0;
 186 +}
 187 +
 188 +static unsigned long clk_aic32x4_pll_calc_rate(
 189 +                       struct clk_aic32x4_pll_muldiv *settings,
 190 +                       unsigned long parent_rate)
 191 +{
 192 +       u64 rate;
 193 +       /*
 194 +        * We scale j by 10000 to account for the decimal part of P and divide
 195 +        * it back out later.
 196 +        */
 197 +       rate = (u64) parent_rate * settings->r *
 198 +                               ((settings->j * 10000) + settings->d);
 199 +
 200 +       return (unsigned long) DIV_ROUND_UP_ULL(rate, settings->p * 10000);
 201 +}
 202 +
 203 +static int clk_aic32x4_pll_calc_muldiv(struct clk_aic32x4_pll_muldiv *settings,
 204 +                       unsigned long rate, unsigned long parent_rate)
 205 +{
 206 +       u64 multiplier;
 207 +
 208 +       settings->p = parent_rate / AIC32X4_MAX_PLL_CLKIN + 1;
 209 +       if (settings->p > 8)
 210 +               return -1;
 211 +
 212 +       /*
 213 +        * We scale this figure by 10000 so that we can get the decimal part
 214 +        * of the multiplier.   This is because we can't do floating point
 215 +        * math in the kernel.
 216 +        */
 217 +        multiplier = (u64) rate * settings->p * 10000;
 218 +        do_div(multiplier, parent_rate);
 219 +
 220 +       /*
 221 +        * J can't be over 64, so R can scale this.
 222 +        * R can't be greater than 4.
 223 +        */
 224 +       settings->r = ((u32) multiplier / 640000) + 1;
 225 +       if (settings->r > 4)
 226 +               return -1;
 227 +       do_div(multiplier, settings->r);
 228 +
 229 +       /*
 230 +        * J can't be < 1.
 231 +        */
 232 +       if (multiplier < 10000)
 233 +               return -1;
 234 +
 235 +       /* Figure out the integer part, J, and the fractional part, D. */
 236 +       settings->j = (u32) multiplier / 10000;
 237 +       settings->d = (u32) multiplier % 10000;
 238 +
 239 +       return 0;
 240 +}
 241 +
 242 +static unsigned long clk_aic32x4_pll_recalc_rate(struct clk_hw *hw,
 243 +                       unsigned long parent_rate)
 244 +{
 245 +       struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
 246 +       struct clk_aic32x4_pll_muldiv settings;
 247 +       int ret;
 248 +
 249 +       ret =  clk_aic32x4_pll_get_muldiv(pll, &settings);
 250 +       if (ret < 0)
 251 +               return 0;
 252 +
 253 +       return clk_aic32x4_pll_calc_rate(&settings, parent_rate);
 254 +}
 255 +
 256 +static long clk_aic32x4_pll_round_rate(struct clk_hw *hw,
 257 +                       unsigned long rate,
 258 +                       unsigned long *parent_rate)
 259 +{
 260 +       struct clk_aic32x4_pll_muldiv settings;
 261 +       int ret;
 262 +
 263 +       ret = clk_aic32x4_pll_calc_muldiv(&settings, rate, *parent_rate);
 264 +       if (ret < 0)
 265 +               return 0;
 266 +
 267 +       return clk_aic32x4_pll_calc_rate(&settings, *parent_rate);
 268 +}
 269 +
 270 +static int clk_aic32x4_pll_set_rate(struct clk_hw *hw,
 271 +                       unsigned long rate,
 272 +                       unsigned long parent_rate)
 273 +{
 274 +       struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
 275 +       struct clk_aic32x4_pll_muldiv settings;
 276 +       int ret;
 277 +
 278 +       ret = clk_aic32x4_pll_calc_muldiv(&settings, rate, parent_rate);
 279 +       if (ret < 0)
 280 +               return -EINVAL;
 281 +
 282 +       return clk_aic32x4_pll_set_muldiv(pll, &settings);
 283 +}
 284 +
 285 +static int clk_aic32x4_pll_set_parent(struct clk_hw *hw, u8 index)
 286 +{
 287 +       struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
 288 +
 289 +       return regmap_update_bits(pll->regmap,
 290 +                               AIC32X4_CLKMUX,
 291 +                               AIC32X4_PLL_CLKIN_MASK,
 292 +                               index << AIC32X4_PLL_CLKIN_SHIFT);
 293 +}
 294 +
 295 +static u8 clk_aic32x4_pll_get_parent(struct clk_hw *hw)
 296 +{
 297 +       struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
 298 +       unsigned int val;
 299 +
 300 +       regmap_read(pll->regmap, AIC32X4_PLLPR, &val);
 301 +
 302 +       return (val & AIC32X4_PLL_CLKIN_MASK) >> AIC32X4_PLL_CLKIN_SHIFT;
 303 +}
 304 +
 305 +
 306 +static const struct clk_ops aic32x4_pll_ops = {
 307 +       .prepare = clk_aic32x4_pll_prepare,
 308 +       .unprepare = clk_aic32x4_pll_unprepare,
 309 +       .is_prepared = clk_aic32x4_pll_is_prepared,
 310 +       .recalc_rate = clk_aic32x4_pll_recalc_rate,
 311 +       .round_rate = clk_aic32x4_pll_round_rate,
 312 +       .set_rate = clk_aic32x4_pll_set_rate,
 313 +       .set_parent = clk_aic32x4_pll_set_parent,
 314 +       .get_parent = clk_aic32x4_pll_get_parent,
 315 +};
 316 +
 317 +static struct aic32x4_clkdesc aic32x4_clkdesc_array[] = {
 318 +       {
 319 +               .name = "pll",
 320 +               .parent_names =
 321 +                       (const char* []) { "mclk", "bclk", "gpio", "din" },
 322 +               .num_parents = 4,
 323 +               .ops = &aic32x4_pll_ops,
 324 +               .reg = 0,
 325 +       },
 326 +};
 327 +
 328 +static struct clk *aic32x4_register_clk(struct device *dev,
 329 +                       struct aic32x4_clkdesc *desc)
 330 +{
 331 +       struct clk_init_data init;
 332 +       struct clk_aic32x4 *priv;
 333 +       const char *devname = dev_name(dev);
 334 +
 335 +       init.ops = desc->ops;
 336 +       init.name = desc->name;
 337 +       init.parent_names = desc->parent_names;
 338 +       init.num_parents = desc->num_parents;
 339 +       init.flags = 0;
 340 +
 341 +       priv = devm_kzalloc(dev, sizeof(struct clk_aic32x4), GFP_KERNEL);
 342 +       if (priv == NULL)
 343 +               return (struct clk *) -ENOMEM;
 344 +
 345 +       priv->dev = dev;
 346 +       priv->hw.init = &init;
 347 +       priv->regmap = dev_get_regmap(dev, NULL);
 348 +       priv->reg = desc->reg;
 349 +
 350 +       clk_hw_register_clkdev(&priv->hw, desc->name, devname);
 351 +       return devm_clk_register(dev, &priv->hw);
 352 +}
 353 +
 354 +int aic32x4_register_clocks(struct device *dev, const char *mclk_name)
 355 +{
 356 +       int i;
 357 +
 358 +       /*
 359 +        * These lines are here to preserve the current functionality of
 360 +        * the driver with regard to the DT.  These should eventually be set
 361 +        * by DT nodes so that the connections can be set up in configuration
 362 +        * rather than code.
 363 +        */
 364 +       aic32x4_clkdesc_array[0].parent_names =
 365 +                       (const char* []) { mclk_name, "bclk", "gpio", "din" };
 366 +
 367 +       for (i = 0; i < ARRAY_SIZE(aic32x4_clkdesc_array); ++i)
 368 +               aic32x4_register_clk(dev, &aic32x4_clkdesc_array[i]);
 369 +
 370 +       return 0;
 371 +}
 372 +EXPORT_SYMBOL_GPL(aic32x4_register_clocks);
 373 --- a/sound/soc/codecs/tlv320aic32x4.c
 374 +++ b/sound/soc/codecs/tlv320aic32x4.c
 375 @@ -14,7 +14,7 @@
 376   *
 377   * This program is distributed in the hope that it will be useful,
 378   * but WITHOUT ANY WARRANTY; without even the implied warranty of
 379 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 380 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
 381   * GNU General Public License for more details.
 382   *
 383   * You should have received a copy of the GNU General Public License
 384 @@ -33,6 +33,7 @@
 385  #include <linux/cdev.h>
 386  #include <linux/slab.h>
 387  #include <linux/clk.h>
 388 +#include <linux/of_clk.h>
 389  #include <linux/regulator/consumer.h>
 390
 391  #include <sound/tlv320aic32x4.h>
 392 @@ -49,9 +50,7 @@
 393  struct aic32x4_rate_divs {
 394         u32 mclk;
 395         u32 rate;
 396 -       u8 p_val;
 397 -       u8 pll_j;
 398 -       u16 pll_d;
 399 +       unsigned long pll_rate;
 400         u16 dosr;
 401         u8 ndac;
 402         u8 mdac;
 403 @@ -71,6 +70,7 @@ struct aic32x4_priv {
 404         bool swapdacs;
 405         int rstn_gpio;
 406         struct clk *mclk;
 407 +       const char *mclk_name;
 408
 409         struct regulator *supply_ldo;
 410         struct regulator *supply_iov;
 411 @@ -309,34 +309,34 @@ static const struct snd_kcontrol_new aic
 412
 413  static const struct aic32x4_rate_divs aic32x4_divs[] = {
 414         /* 8k rate */
 415 -       {12000000, 8000, 1, 7, 6800, 768, 5, 3, 128, 5, 18, 24, 1, 1},
 416 -       {24000000, 8000, 2, 7, 6800, 768, 15, 1, 64, 45, 4, 24, 1, 1},
 417 -       {25000000, 8000, 2, 7, 3728, 768, 15, 1, 64, 45, 4, 24, 1, 1},
 418 +       { 12000000, 8000, 57120000, 768, 5, 3, 128, 5, 18, 24, 1, 1 },
 419 +       { 24000000, 8000, 57120000, 768, 15, 1, 64, 45, 4, 24, 1, 1 },
 420 +       { 25000000, 8000, 32620000, 768, 15, 1, 64, 45, 4, 24, 1, 1 },
 421         /* 11.025k rate */
 422 -       {12000000, 11025, 1, 7, 5264, 512, 8, 2, 128, 8, 8, 16, 1, 1},
 423 -       {24000000, 11025, 2, 7, 5264, 512, 16, 1, 64, 32, 4, 16, 1, 1},
 424 +       { 12000000, 11025, 44217600, 512, 8, 2, 128, 8, 8, 16, 1, 1 },
 425 +       { 24000000, 11025, 44217600, 512, 16, 1, 64, 32, 4, 16, 1, 1 },
 426         /* 16k rate */
 427 -       {12000000, 16000, 1, 7, 6800, 384, 5, 3, 128, 5, 9, 12, 1, 1},
 428 -       {24000000, 16000, 2, 7, 6800, 384, 15, 1, 64, 18, 5, 12, 1, 1},
 429 -       {25000000, 16000, 2, 7, 3728, 384, 15, 1, 64, 18, 5, 12, 1, 1},
 430 +       { 12000000, 16000, 57120000, 384, 5, 3, 128, 5, 9, 12, 1, 1 },
 431 +       { 24000000, 16000, 57120000, 384, 15, 1, 64, 18, 5, 12, 1, 1 },
 432 +       { 25000000, 16000, 32620000, 384, 15, 1, 64, 18, 5, 12, 1, 1 },
 433         /* 22.05k rate */
 434 -       {12000000, 22050, 1, 7, 5264, 256, 4, 4, 128, 4, 8, 8, 1, 1},
 435 -       {24000000, 22050, 2, 7, 5264, 256, 16, 1, 64, 16, 4, 8, 1, 1},
 436 -       {25000000, 22050, 2, 7, 2253, 256, 16, 1, 64, 16, 4, 8, 1, 1},
 437 +       { 12000000, 22050, 44217600, 256, 4, 4, 128, 4, 8, 8, 1, 1 },
 438 +       { 24000000, 22050, 44217600, 256, 16, 1, 64, 16, 4, 8, 1, 1 },
 439 +       { 25000000, 22050, 19713750, 256, 16, 1, 64, 16, 4, 8, 1, 1 },
 440         /* 32k rate */
 441 -       {12000000, 32000, 1, 7, 1680, 192, 2, 7, 64, 2, 21, 6, 1, 1},
 442 -       {24000000, 32000, 2, 7, 1680, 192, 7, 2, 64, 7, 6, 6, 1, 1},
 443 +       { 12000000, 32000, 14112000, 192, 2, 7, 64, 2, 21, 6, 1, 1 },
 444 +       { 24000000, 32000, 14112000, 192, 7, 2, 64, 7, 6, 6, 1, 1 },
 445         /* 44.1k rate */
 446 -       {12000000, 44100, 1, 7, 5264, 128, 2, 8, 128, 2, 8, 4, 1, 1},
 447 -       {24000000, 44100, 2, 7, 5264, 128, 8, 2, 64, 8, 4, 4, 1, 1},
 448 -       {25000000, 44100, 2, 7, 2253, 128, 8, 2, 64, 8, 4, 4, 1, 1},
 449 +       { 12000000, 44100, 44217600, 128, 2, 8, 128, 2, 8, 4, 1, 1 },
 450 +       { 24000000, 44100, 44217600, 128, 8, 2, 64, 8, 4, 4, 1, 1 },
 451 +       { 25000000, 44100, 19713750, 128, 8, 2, 64, 8, 4, 4, 1, 1 },
 452         /* 48k rate */
 453 -       {12000000, 48000, 1, 8, 1920, 128, 2, 8, 128, 2, 8, 4, 1, 1},
 454 -       {24000000, 48000, 2, 8, 1920, 128, 8, 2, 64, 8, 4, 4, 1, 1},
 455 -       {25000000, 48000, 2, 7, 8643, 128, 8, 2, 64, 8, 4, 4, 1, 1},
 456 +       { 12000000, 48000, 18432000, 128, 2, 8, 128, 2, 8, 4, 1, 1 },
 457 +       { 24000000, 48000, 18432000, 128, 8, 2, 64, 8, 4, 4, 1, 1 },
 458 +       { 25000000, 48000, 75626250, 128, 8, 2, 64, 8, 4, 4, 1, 1 },
 459
 460         /* 96k rate */
 461 -       {25000000, 96000, 2, 7, 8643, 64, 4, 4, 64, 4, 4, 1, 1, 9},
 462 +       { 25000000, 96000, 75626250, 64, 4, 4, 64, 4, 4, 1, 1, 9 },
 463  };
 464
 465  static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
 466 @@ -393,7 +393,7 @@ static const struct snd_kcontrol_new in3
 467         SOC_DAPM_ENUM("IN3_R L- Switch", in3r_lpga_n_enum),
 468  };
 469
 470 -/*  Right mixer pins */
 471 +/*     Right mixer pins */
 472  static SOC_ENUM_SINGLE_DECL(in1r_rpga_p_enum, AIC32X4_RMICPGAPIN, 6, resistor_text);
 473  static SOC_ENUM_SINGLE_DECL(in2r_rpga_p_enum, AIC32X4_RMICPGAPIN, 4, resistor_text);
 474  static SOC_ENUM_SINGLE_DECL(in3r_rpga_p_enum, AIC32X4_RMICPGAPIN, 2, resistor_text);
 475 @@ -597,7 +597,7 @@ static const struct snd_soc_dapm_route a
 476  static const struct regmap_range_cfg aic32x4_regmap_pages[] = {
 477         {
 478                 .selector_reg = 0,
 479 -               .selector_mask  = 0xff,
 480 +               .selector_mask  = 0xff,
 481                 .window_start = 0,
 482                 .window_len = 128,
 483                 .range_min = 0,
 484 @@ -618,7 +618,7 @@ static inline int aic32x4_get_divs(int m
 485
 486         for (i = 0; i < ARRAY_SIZE(aic32x4_divs); i++) {
 487                 if ((aic32x4_divs[i].rate == rate)
 488 -                   && (aic32x4_divs[i].mclk == mclk)) {
 489 +                       && (aic32x4_divs[i].mclk == mclk)) {
 490                         return i;
 491                 }
 492         }
 493 @@ -690,12 +690,12 @@ static int aic32x4_set_dai_fmt(struct sn
 494         }
 495
 496         snd_soc_component_update_bits(component, AIC32X4_IFACE1,
 497 -                           AIC32X4_IFACE1_DATATYPE_MASK |
 498 -                           AIC32X4_IFACE1_MASTER_MASK, iface_reg_1);
 499 +                               AIC32X4_IFACE1_DATATYPE_MASK |
 500 +                               AIC32X4_IFACE1_MASTER_MASK, iface_reg_1);
 501         snd_soc_component_update_bits(component, AIC32X4_IFACE2,
 502 -                           AIC32X4_DATA_OFFSET_MASK, iface_reg_2);
 503 +                               AIC32X4_DATA_OFFSET_MASK, iface_reg_2);
 504         snd_soc_component_update_bits(component, AIC32X4_IFACE3,
 505 -                           AIC32X4_BCLKINV_MASK, iface_reg_3);
 506 +                               AIC32X4_BCLKINV_MASK, iface_reg_3);
 507
 508         return 0;
 509  }
 510 @@ -717,6 +717,11 @@ static int aic32x4_setup_clocks(struct s
 511                                 unsigned int parent_rate)
 512  {
 513         int i;
 514 +       int ret;
 515 +
 516 +       struct clk_bulk_data clocks[] = {
 517 +               { .id = "pll" },
 518 +       };
 519
 520         i = aic32x4_get_divs(parent_rate, sample_rate);
 521         if (i < 0) {
 522 @@ -724,39 +729,29 @@ static int aic32x4_setup_clocks(struct s
 523                 return i;
 524         }
 525
 526 +       ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
 527 +       if (ret)
 528 +               return ret;
 529 +
 530 +       clk_set_rate(clocks[0].clk, sample_rate);
 531 +
 532         aic32x4_set_processing_blocks(component, aic32x4_divs[i].r_block, aic32x4_divs[i].p_block);
 533
 534 -       /* MCLK as PLL_CLKIN */
 535 -       snd_soc_component_update_bits(component, AIC32X4_CLKMUX, AIC32X4_PLL_CLKIN_MASK,
 536 -                           AIC32X4_PLL_CLKIN_MCLK << AIC32X4_PLL_CLKIN_SHIFT);
 537         /* PLL as CODEC_CLKIN */
 538 -       snd_soc_component_update_bits(component, AIC32X4_CLKMUX, AIC32X4_CODEC_CLKIN_MASK,
 539 -                           AIC32X4_CODEC_CLKIN_PLL << AIC32X4_CODEC_CLKIN_SHIFT);
 540 +       snd_soc_component_update_bits(component, AIC32X4_CLKMUX,
 541 +                       AIC32X4_CODEC_CLKIN_MASK,
 542 +                       AIC32X4_CODEC_CLKIN_PLL << AIC32X4_CODEC_CLKIN_SHIFT);
 543         /* DAC_MOD_CLK as BDIV_CLKIN */
 544         snd_soc_component_update_bits(component, AIC32X4_IFACE3, AIC32X4_BDIVCLK_MASK,
 545 -                           AIC32X4_DACMOD2BCLK << AIC32X4_BDIVCLK_SHIFT);
 546 -
 547 -       /* We will fix R value to 1 and will make P & J=K.D as variable */
 548 -       snd_soc_component_update_bits(component, AIC32X4_PLLPR, AIC32X4_PLL_R_MASK, 0x01);
 549 -
 550 -       /* PLL P value */
 551 -       snd_soc_component_update_bits(component, AIC32X4_PLLPR, AIC32X4_PLL_P_MASK,
 552 -                           aic32x4_divs[i].p_val << AIC32X4_PLL_P_SHIFT);
 553 -
 554 -       /* PLL J value */
 555 -       snd_soc_component_write(component, AIC32X4_PLLJ, aic32x4_divs[i].pll_j);
 556 -
 557 -       /* PLL D value */
 558 -       snd_soc_component_write(component, AIC32X4_PLLDMSB, (aic32x4_divs[i].pll_d >> 8));
 559 -       snd_soc_component_write(component, AIC32X4_PLLDLSB, (aic32x4_divs[i].pll_d & 0xff));
 560 +                               AIC32X4_DACMOD2BCLK << AIC32X4_BDIVCLK_SHIFT);
 561
 562         /* NDAC divider value */
 563         snd_soc_component_update_bits(component, AIC32X4_NDAC,
 564 -                           AIC32X4_NDAC_MASK, aic32x4_divs[i].ndac);
 565 +                               AIC32X4_NDAC_MASK, aic32x4_divs[i].ndac);
 566
 567         /* MDAC divider value */
 568         snd_soc_component_update_bits(component, AIC32X4_MDAC,
 569 -                           AIC32X4_MDAC_MASK, aic32x4_divs[i].mdac);
 570 +                               AIC32X4_MDAC_MASK, aic32x4_divs[i].mdac);
 571
 572         /* DOSR MSB & LSB values */
 573         snd_soc_component_write(component, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8);
 574 @@ -764,18 +759,18 @@ static int aic32x4_setup_clocks(struct s
 575
 576         /* NADC divider value */
 577         snd_soc_component_update_bits(component, AIC32X4_NADC,
 578 -                           AIC32X4_NADC_MASK, aic32x4_divs[i].nadc);
 579 +                               AIC32X4_NADC_MASK, aic32x4_divs[i].nadc);
 580
 581         /* MADC divider value */
 582         snd_soc_component_update_bits(component, AIC32X4_MADC,
 583 -                           AIC32X4_MADC_MASK, aic32x4_divs[i].madc);
 584 +                               AIC32X4_MADC_MASK, aic32x4_divs[i].madc);
 585
 586         /* AOSR value */
 587         snd_soc_component_write(component, AIC32X4_AOSR, aic32x4_divs[i].aosr);
 588
 589         /* BCLK N divider */
 590         snd_soc_component_update_bits(component, AIC32X4_BCLKN,
 591 -                           AIC32X4_BCLK_MASK, aic32x4_divs[i].blck_N);
 592 +                               AIC32X4_BCLK_MASK, aic32x4_divs[i].blck_N);
 593
 594         return 0;
 595  }
 596 @@ -794,23 +789,23 @@ static int aic32x4_hw_params(struct snd_
 597         switch (params_width(params)) {
 598         case 16:
 599                 iface1_reg |= (AIC32X4_WORD_LEN_16BITS <<
 600 -                              AIC32X4_IFACE1_DATALEN_SHIFT);
 601 +                                  AIC32X4_IFACE1_DATALEN_SHIFT);
 602                 break;
 603         case 20:
 604                 iface1_reg |= (AIC32X4_WORD_LEN_20BITS <<
 605 -                              AIC32X4_IFACE1_DATALEN_SHIFT);
 606 +                                  AIC32X4_IFACE1_DATALEN_SHIFT);
 607                 break;
 608         case 24:
 609                 iface1_reg |= (AIC32X4_WORD_LEN_24BITS <<
 610 -                              AIC32X4_IFACE1_DATALEN_SHIFT);
 611 +                                  AIC32X4_IFACE1_DATALEN_SHIFT);
 612                 break;
 613         case 32:
 614                 iface1_reg |= (AIC32X4_WORD_LEN_32BITS <<
 615 -                              AIC32X4_IFACE1_DATALEN_SHIFT);
 616 +                                  AIC32X4_IFACE1_DATALEN_SHIFT);
 617                 break;
 618         }
 619         snd_soc_component_update_bits(component, AIC32X4_IFACE1,
 620 -                           AIC32X4_IFACE1_DATALEN_MASK, iface1_reg);
 621 +                               AIC32X4_IFACE1_DATALEN_MASK, iface1_reg);
 622
 623         if (params_channels(params) == 1) {
 624                 dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN;
 625 @@ -821,7 +816,7 @@ static int aic32x4_hw_params(struct snd_
 626                         dacsetup_reg = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN;
 627         }
 628         snd_soc_component_update_bits(component, AIC32X4_DACSETUP,
 629 -                           AIC32X4_DAC_CHAN_MASK, dacsetup_reg);
 630 +                               AIC32X4_DAC_CHAN_MASK, dacsetup_reg);
 631
 632         return 0;
 633  }
 634 @@ -831,7 +826,7 @@ static int aic32x4_mute(struct snd_soc_d
 635         struct snd_soc_component *component = dai->component;
 636
 637         snd_soc_component_update_bits(component, AIC32X4_DACMUTE,
 638 -                           AIC32X4_MUTEON, mute ? AIC32X4_MUTEON : 0);
 639 +                               AIC32X4_MUTEON, mute ? AIC32X4_MUTEON : 0);
 640
 641         return 0;
 642  }
 643 @@ -853,27 +848,27 @@ static int aic32x4_set_bias_level(struct
 644
 645                 /* Switch on PLL */
 646                 snd_soc_component_update_bits(component, AIC32X4_PLLPR,
 647 -                                   AIC32X4_PLLEN, AIC32X4_PLLEN);
 648 +                                       AIC32X4_PLLEN, AIC32X4_PLLEN);
 649
 650                 /* Switch on NDAC Divider */
 651                 snd_soc_component_update_bits(component, AIC32X4_NDAC,
 652 -                                   AIC32X4_NDACEN, AIC32X4_NDACEN);
 653 +                                       AIC32X4_NDACEN, AIC32X4_NDACEN);
 654
 655                 /* Switch on MDAC Divider */
 656                 snd_soc_component_update_bits(component, AIC32X4_MDAC,
 657 -                                   AIC32X4_MDACEN, AIC32X4_MDACEN);
 658 +                                       AIC32X4_MDACEN, AIC32X4_MDACEN);
 659
 660                 /* Switch on NADC Divider */
 661                 snd_soc_component_update_bits(component, AIC32X4_NADC,
 662 -                                   AIC32X4_NADCEN, AIC32X4_NADCEN);
 663 +                                       AIC32X4_NADCEN, AIC32X4_NADCEN);
 664
 665                 /* Switch on MADC Divider */
 666                 snd_soc_component_update_bits(component, AIC32X4_MADC,
 667 -                                   AIC32X4_MADCEN, AIC32X4_MADCEN);
 668 +                                       AIC32X4_MADCEN, AIC32X4_MADCEN);
 669
 670                 /* Switch on BCLK_N Divider */
 671                 snd_soc_component_update_bits(component, AIC32X4_BCLKN,
 672 -                                   AIC32X4_BCLKEN, AIC32X4_BCLKEN);
 673 +                                       AIC32X4_BCLKEN, AIC32X4_BCLKEN);
 674                 break;
 675         case SND_SOC_BIAS_PREPARE:
 676                 break;
 677 @@ -884,27 +879,27 @@ static int aic32x4_set_bias_level(struct
 678
 679                 /* Switch off BCLK_N Divider */
 680                 snd_soc_component_update_bits(component, AIC32X4_BCLKN,
 681 -                                   AIC32X4_BCLKEN, 0);
 682 +                                       AIC32X4_BCLKEN, 0);
 683
 684                 /* Switch off MADC Divider */
 685                 snd_soc_component_update_bits(component, AIC32X4_MADC,
 686 -                                   AIC32X4_MADCEN, 0);
 687 +                                       AIC32X4_MADCEN, 0);
 688
 689                 /* Switch off NADC Divider */
 690                 snd_soc_component_update_bits(component, AIC32X4_NADC,
 691 -                                   AIC32X4_NADCEN, 0);
 692 +                                       AIC32X4_NADCEN, 0);
 693
 694                 /* Switch off MDAC Divider */
 695                 snd_soc_component_update_bits(component, AIC32X4_MDAC,
 696 -                                   AIC32X4_MDACEN, 0);
 697 +                                       AIC32X4_MDACEN, 0);
 698
 699                 /* Switch off NDAC Divider */
 700                 snd_soc_component_update_bits(component, AIC32X4_NDAC,
 701 -                                   AIC32X4_NDACEN, 0);
 702 +                                       AIC32X4_NDACEN, 0);
 703
 704                 /* Switch off PLL */
 705                 snd_soc_component_update_bits(component, AIC32X4_PLLPR,
 706 -                                   AIC32X4_PLLEN, 0);
 707 +                                       AIC32X4_PLLEN, 0);
 708
 709                 /* Switch off master clock */
 710                 clk_disable_unprepare(aic32x4->mclk);
 711 @@ -916,7 +911,7 @@ static int aic32x4_set_bias_level(struct
 712  }
 713
 714  #define AIC32X4_RATES  SNDRV_PCM_RATE_8000_96000
 715 -#define AIC32X4_FORMATS        (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
 716 +#define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
 717                          | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
 718
 719  static const struct snd_soc_dai_ops aic32x4_ops = {
 720 @@ -929,17 +924,17 @@ static const struct snd_soc_dai_ops aic3
 721  static struct snd_soc_dai_driver aic32x4_dai = {
 722         .name = "tlv320aic32x4-hifi",
 723         .playback = {
 724 -                    .stream_name = "Playback",
 725 -                    .channels_min = 1,
 726 -                    .channels_max = 2,
 727 -                    .rates = AIC32X4_RATES,
 728 -                    .formats = AIC32X4_FORMATS,},
 729 +                        .stream_name = "Playback",
 730 +                        .channels_min = 1,
 731 +                        .channels_max = 2,
 732 +                        .rates = AIC32X4_RATES,
 733 +                        .formats = AIC32X4_FORMATS,},
 734         .capture = {
 735 -                   .stream_name = "Capture",
 736 -                   .channels_min = 1,
 737 -                   .channels_max = 2,
 738 -                   .rates = AIC32X4_RATES,
 739 -                   .formats = AIC32X4_FORMATS,},
 740 +                       .stream_name = "Capture",
 741 +                       .channels_min = 1,
 742 +                       .channels_max = 2,
 743 +                       .rates = AIC32X4_RATES,
 744 +                       .formats = AIC32X4_FORMATS,},
 745         .ops = &aic32x4_ops,
 746         .symmetric_rates = 1,
 747  };
 748 @@ -952,7 +947,7 @@ static void aic32x4_setup_gpios(struct s
 749         /* MFP1 */
 750         if (aic32x4->setup->gpio_func[0] != AIC32X4_MFPX_DEFAULT_VALUE) {
 751                 snd_soc_component_write(component, AIC32X4_DINCTL,
 752 -                     aic32x4->setup->gpio_func[0]);
 753 +                         aic32x4->setup->gpio_func[0]);
 754                 snd_soc_add_component_controls(component, aic32x4_mfp1,
 755                         ARRAY_SIZE(aic32x4_mfp1));
 756         }
 757 @@ -960,7 +955,7 @@ static void aic32x4_setup_gpios(struct s
 758         /* MFP2 */
 759         if (aic32x4->setup->gpio_func[1] != AIC32X4_MFPX_DEFAULT_VALUE) {
 760                 snd_soc_component_write(component, AIC32X4_DOUTCTL,
 761 -                     aic32x4->setup->gpio_func[1]);
 762 +                         aic32x4->setup->gpio_func[1]);
 763                 snd_soc_add_component_controls(component, aic32x4_mfp2,
 764                         ARRAY_SIZE(aic32x4_mfp2));
 765         }
 766 @@ -968,7 +963,7 @@ static void aic32x4_setup_gpios(struct s
 767         /* MFP3 */
 768         if (aic32x4->setup->gpio_func[2] != AIC32X4_MFPX_DEFAULT_VALUE) {
 769                 snd_soc_component_write(component, AIC32X4_SCLKCTL,
 770 -                     aic32x4->setup->gpio_func[2]);
 771 +                         aic32x4->setup->gpio_func[2]);
 772                 snd_soc_add_component_controls(component, aic32x4_mfp3,
 773                         ARRAY_SIZE(aic32x4_mfp3));
 774         }
 775 @@ -976,7 +971,7 @@ static void aic32x4_setup_gpios(struct s
 776         /* MFP4 */
 777         if (aic32x4->setup->gpio_func[3] != AIC32X4_MFPX_DEFAULT_VALUE) {
 778                 snd_soc_component_write(component, AIC32X4_MISOCTL,
 779 -                     aic32x4->setup->gpio_func[3]);
 780 +                         aic32x4->setup->gpio_func[3]);
 781                 snd_soc_add_component_controls(component, aic32x4_mfp4,
 782                         ARRAY_SIZE(aic32x4_mfp4));
 783         }
 784 @@ -984,7 +979,7 @@ static void aic32x4_setup_gpios(struct s
 785         /* MFP5 */
 786         if (aic32x4->setup->gpio_func[4] != AIC32X4_MFPX_DEFAULT_VALUE) {
 787                 snd_soc_component_write(component, AIC32X4_GPIOCTL,
 788 -                     aic32x4->setup->gpio_func[4]);
 789 +                         aic32x4->setup->gpio_func[4]);
 790                 snd_soc_add_component_controls(component, aic32x4_mfp5,
 791                         ARRAY_SIZE(aic32x4_mfp5));
 792         }
 793 @@ -1007,8 +1002,8 @@ static int aic32x4_component_probe(struc
 794
 795         /* Power platform configuration */
 796         if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
 797 -               snd_soc_component_write(component, AIC32X4_MICBIAS, AIC32X4_MICBIAS_LDOIN |
 798 -                                                     AIC32X4_MICBIAS_2075V);
 799 +               snd_soc_component_write(component, AIC32X4_MICBIAS,
 800 +                               AIC32X4_MICBIAS_LDOIN | AIC32X4_MICBIAS_2075V);
 801         }
 802         if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE)
 803                 snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
 804 @@ -1071,12 +1066,18 @@ static int aic32x4_parse_dt(struct aic32
 805                 struct device_node *np)
 806  {
 807         struct aic32x4_setup_data *aic32x4_setup;
 808 +       int ret;
 809
 810         aic32x4_setup = devm_kzalloc(aic32x4->dev, sizeof(*aic32x4_setup),
 811                                                         GFP_KERNEL);
 812         if (!aic32x4_setup)
 813                 return -ENOMEM;
 814
 815 +       ret = of_property_match_string(np, "clock-names", "mclk");
 816 +       if (ret < 0)
 817 +               return -EINVAL;
 818 +       aic32x4->mclk_name = of_clk_get_parent_name(np, ret);
 819 +
 820         aic32x4->swapdacs = false;
 821         aic32x4->micpga_routing = 0;
 822         aic32x4->rstn_gpio = of_get_named_gpio(np, "reset-gpios", 0);
 823 @@ -1198,7 +1199,7 @@ int aic32x4_probe(struct device *dev, st
 824                 return PTR_ERR(regmap);
 825
 826         aic32x4 = devm_kzalloc(dev, sizeof(struct aic32x4_priv),
 827 -                              GFP_KERNEL);
 828 +                                  GFP_KERNEL);
 829         if (aic32x4 == NULL)
 830                 return -ENOMEM;
 831
 832 @@ -1210,6 +1211,7 @@ int aic32x4_probe(struct device *dev, st
 833                 aic32x4->swapdacs = pdata->swapdacs;
 834                 aic32x4->micpga_routing = pdata->micpga_routing;
 835                 aic32x4->rstn_gpio = pdata->rstn_gpio;
 836 +               aic32x4->mclk_name = "mclk";
 837         } else if (np) {
 838                 ret = aic32x4_parse_dt(aic32x4, np);
 839                 if (ret) {
 840 @@ -1221,6 +1223,7 @@ int aic32x4_probe(struct device *dev, st
 841                 aic32x4->swapdacs = false;
 842                 aic32x4->micpga_routing = 0;
 843                 aic32x4->rstn_gpio = -1;
 844 +               aic32x4->mclk_name = "mclk";
 845         }
 846
 847         aic32x4->mclk = devm_clk_get(dev, "mclk");
 848 @@ -1229,6 +1232,10 @@ int aic32x4_probe(struct device *dev, st
 849                 return PTR_ERR(aic32x4->mclk);
 850         }
 851
 852 +       ret = aic32x4_register_clocks(dev, aic32x4->mclk_name);
 853 +       if (ret)
 854 +               return ret;
 855 +
 856         if (gpio_is_valid(aic32x4->rstn_gpio)) {
 857                 ret = devm_gpio_request_one(dev, aic32x4->rstn_gpio,
 858                                 GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn");
 859 --- a/sound/soc/codecs/tlv320aic32x4.h
 860 +++ b/sound/soc/codecs/tlv320aic32x4.h
 861 @@ -16,6 +16,7 @@ struct regmap_config;
 862  extern const struct regmap_config aic32x4_regmap_config;
 863  int aic32x4_probe(struct device *dev, struct regmap *regmap);
 864  int aic32x4_remove(struct device *dev);
 865 +int aic32x4_register_clocks(struct device *dev, const char *mclk_name);
 866
 867  /* tlv320aic32x4 register space (in decimal to match datasheet) */
 868
 869 @@ -205,4 +206,8 @@ int aic32x4_remove(struct device *dev);
 870  #define AIC32X4_RMICPGANIN_IN1L_10K    0x10
 871  #define AIC32X4_RMICPGANIN_CM1R_10K    0x40
 872
 873 +/* Clock Limits */
 874 +#define AIC32X4_MAX_PLL_CLKIN          20000000
 875 +
 876 +
 877  #endif                         /* _TLV320AIC32X4_H */