target/linux/brcm2708/patches-4.19/950-0404-ASoC-tlv320aic32x4-Control-clock-gating-with-CCF.patch

   1 From 0d5aca18bd8a4ad3fa82f1f7f82cc0b95575a492 Mon Sep 17 00:00:00 2001
   2 From: Annaliese McDermond <nh6z@nh6z.net>
   3 Date: Thu, 21 Mar 2019 17:58:49 -0700
   4 Subject: [PATCH 404/773] ASoC: tlv320aic32x4: Control clock gating with CCF
   5
   6 commit d25970b5fd51e9fcf0afbe190908ea4049454da4 upstream.
   7
   8 Control the clock gating to the various clock components to use
   9 the CCF.  This allows us to prepare_enalbe only 3 clocks and the
  10 relationships assigned to them will cause upstream clockss to
  11 enable automatically.  Additionally we can do this in a single
  12 call to the CCF.
  13
  14 Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
  15 Signed-off-by: Mark Brown <broonie@kernel.org>
  16 ---
  17  sound/soc/codecs/tlv320aic32x4.c | 67 +++++++-------------------------
  18  1 file changed, 13 insertions(+), 54 deletions(-)
  19
  20 --- a/sound/soc/codecs/tlv320aic32x4.c
  21 +++ b/sound/soc/codecs/tlv320aic32x4.c
  22 @@ -836,41 +836,25 @@ static int aic32x4_mute(struct snd_soc_d
  23  static int aic32x4_set_bias_level(struct snd_soc_component *component,
  24                                   enum snd_soc_bias_level level)
  25  {
  26 -       struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
  27         int ret;
  28
  29 +       struct clk_bulk_data clocks[] = {
  30 +               { .id = "madc" },
  31 +               { .id = "mdac" },
  32 +               { .id = "bdiv" },
  33 +       };
  34 +
  35 +       ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
  36 +       if (ret)
  37 +               return ret;
  38 +
  39         switch (level) {
  40         case SND_SOC_BIAS_ON:
  41 -               /* Switch on master clock */
  42 -               ret = clk_prepare_enable(aic32x4->mclk);
  43 +               ret = clk_bulk_prepare_enable(ARRAY_SIZE(clocks), clocks);
  44                 if (ret) {
  45 -                       dev_err(component->dev, "Failed to enable master clock\n");
  46 +                       dev_err(component->dev, "Failed to enable clocks\n");
  47                         return ret;
  48                 }
  49 -
  50 -               /* Switch on PLL */
  51 -               snd_soc_component_update_bits(component, AIC32X4_PLLPR,
  52 -                                       AIC32X4_PLLEN, AIC32X4_PLLEN);
  53 -
  54 -               /* Switch on NDAC Divider */
  55 -               snd_soc_component_update_bits(component, AIC32X4_NDAC,
  56 -                                       AIC32X4_NDACEN, AIC32X4_NDACEN);
  57 -
  58 -               /* Switch on MDAC Divider */
  59 -               snd_soc_component_update_bits(component, AIC32X4_MDAC,
  60 -                                       AIC32X4_MDACEN, AIC32X4_MDACEN);
  61 -
  62 -               /* Switch on NADC Divider */
  63 -               snd_soc_component_update_bits(component, AIC32X4_NADC,
  64 -                                       AIC32X4_NADCEN, AIC32X4_NADCEN);
  65 -
  66 -               /* Switch on MADC Divider */
  67 -               snd_soc_component_update_bits(component, AIC32X4_MADC,
  68 -                                       AIC32X4_MADCEN, AIC32X4_MADCEN);
  69 -
  70 -               /* Switch on BCLK_N Divider */
  71 -               snd_soc_component_update_bits(component, AIC32X4_BCLKN,
  72 -                                       AIC32X4_BCLKEN, AIC32X4_BCLKEN);
  73                 break;
  74         case SND_SOC_BIAS_PREPARE:
  75                 break;
  76 @@ -879,32 +863,7 @@ static int aic32x4_set_bias_level(struct
  77                 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
  78                         break;
  79
  80 -               /* Switch off BCLK_N Divider */
  81 -               snd_soc_component_update_bits(component, AIC32X4_BCLKN,
  82 -                                       AIC32X4_BCLKEN, 0);
  83 -
  84 -               /* Switch off MADC Divider */
  85 -               snd_soc_component_update_bits(component, AIC32X4_MADC,
  86 -                                       AIC32X4_MADCEN, 0);
  87 -
  88 -               /* Switch off NADC Divider */
  89 -               snd_soc_component_update_bits(component, AIC32X4_NADC,
  90 -                                       AIC32X4_NADCEN, 0);
  91 -
  92 -               /* Switch off MDAC Divider */
  93 -               snd_soc_component_update_bits(component, AIC32X4_MDAC,
  94 -                                       AIC32X4_MDACEN, 0);
  95 -
  96 -               /* Switch off NDAC Divider */
  97 -               snd_soc_component_update_bits(component, AIC32X4_NDAC,
  98 -                                       AIC32X4_NDACEN, 0);
  99 -
 100 -               /* Switch off PLL */
 101 -               snd_soc_component_update_bits(component, AIC32X4_PLLPR,
 102 -                                       AIC32X4_PLLEN, 0);
 103 -
 104 -               /* Switch off master clock */
 105 -               clk_disable_unprepare(aic32x4->mclk);
 106 +               clk_bulk_disable_unprepare(ARRAY_SIZE(clocks), clocks);
 107                 break;
 108         case SND_SOC_BIAS_OFF:
 109                 break;