target/linux/brcm2708/patches-4.19/950-0408-ASoC-tlv320aic32x4-Model-BDIV-divider-in-CCF.patch

   1 From f057c2ccc9c5fddca55fb42032395cf355f918e8 Mon Sep 17 00:00:00 2001
   2 From: Annaliese McDermond <nh6z@nh6z.net>
   3 Date: Thu, 21 Mar 2019 17:58:48 -0700
   4 Subject: [PATCH 408/703] ASoC: tlv320aic32x4: Model BDIV divider in CCF
   5
   6 commit 9b484124ebd906c4d6bc826cc0d417e80cc1105c upstream.
   7
   8 Model and manage BDIV divider as components in the Core
   9 Clock Framework.  This should allow us to do some more complex
  10 clock management and power control.  Also, some of the
  11 on-board chip clocks can be exposed to the outside, and this
  12 change will make those clocks easier to consume by other
  13 parts of the kernel.
  14
  15 Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
  16 Signed-off-by: Mark Brown <broonie@kernel.org>
  17 ---
  18  sound/soc/codecs/tlv320aic32x4-clk.c | 36 ++++++++++++++++++
  19  sound/soc/codecs/tlv320aic32x4.c     | 56 +++++++++++++---------------
  20  2 files changed, 62 insertions(+), 30 deletions(-)
  21
  22 --- a/sound/soc/codecs/tlv320aic32x4-clk.c
  23 +++ b/sound/soc/codecs/tlv320aic32x4-clk.c
  24 @@ -351,6 +351,34 @@ static const struct clk_ops aic32x4_div_
  25         .recalc_rate = clk_aic32x4_div_recalc_rate,
  26  };
  27
  28 +static int clk_aic32x4_bdiv_set_parent(struct clk_hw *hw, u8 index)
  29 +{
  30 +       struct clk_aic32x4 *mux = to_clk_aic32x4(hw);
  31 +
  32 +       return regmap_update_bits(mux->regmap, AIC32X4_IFACE3,
  33 +                               AIC32X4_BDIVCLK_MASK, index);
  34 +}
  35 +
  36 +static u8 clk_aic32x4_bdiv_get_parent(struct clk_hw *hw)
  37 +{
  38 +       struct clk_aic32x4 *mux = to_clk_aic32x4(hw);
  39 +       unsigned int val;
  40 +
  41 +       regmap_read(mux->regmap, AIC32X4_IFACE3, &val);
  42 +
  43 +       return val & AIC32X4_BDIVCLK_MASK;
  44 +}
  45 +
  46 +static const struct clk_ops aic32x4_bdiv_ops = {
  47 +       .prepare = clk_aic32x4_div_prepare,
  48 +       .unprepare = clk_aic32x4_div_unprepare,
  49 +       .set_parent = clk_aic32x4_bdiv_set_parent,
  50 +       .get_parent = clk_aic32x4_bdiv_get_parent,
  51 +       .set_rate = clk_aic32x4_div_set_rate,
  52 +       .round_rate = clk_aic32x4_div_round_rate,
  53 +       .recalc_rate = clk_aic32x4_div_recalc_rate,
  54 +};
  55 +
  56  static struct aic32x4_clkdesc aic32x4_clkdesc_array[] = {
  57         {
  58                 .name = "pll",
  59 @@ -396,6 +424,14 @@ static struct aic32x4_clkdesc aic32x4_cl
  60                 .ops = &aic32x4_div_ops,
  61                 .reg = AIC32X4_MADC,
  62         },
  63 +       {
  64 +               .name = "bdiv",
  65 +               .parent_names =
  66 +                       (const char *[]) { "ndac", "mdac", "nadc", "madc" },
  67 +               .num_parents = 4,
  68 +               .ops = &aic32x4_bdiv_ops,
  69 +               .reg = AIC32X4_BCLKN,
  70 +       },
  71  };
  72
  73  static struct clk *aic32x4_register_clk(struct device *dev,
  74 --- a/sound/soc/codecs/tlv320aic32x4.c
  75 +++ b/sound/soc/codecs/tlv320aic32x4.c
  76 @@ -57,7 +57,7 @@ struct aic32x4_rate_divs {
  77         u8 aosr;
  78         unsigned long nadc_rate;
  79         unsigned long madc_rate;
  80 -       u8 blck_N;
  81 +       unsigned long bdiv_rate;
  82         u8 r_block;
  83         u8 p_block;
  84  };
  85 @@ -310,53 +310,53 @@ static const struct snd_kcontrol_new aic
  86  static const struct aic32x4_rate_divs aic32x4_divs[] = {
  87         /* 8k rate */
  88         { 12000000, 8000, 57120000, 768, 18432000, 6144000, 128, 18432000,
  89 -               1024000, 24, 1, 1 },
  90 +               1024000, 256000, 1, 1 },
  91         { 24000000, 8000, 57120000, 768, 6144000, 6144000, 64, 2048000,
  92 -               512000, 24, 1, 1 },
  93 +               512000, 256000, 1, 1 },
  94         { 25000000, 8000, 32620000, 768, 6144000, 6144000, 64, 2048000,
  95 -               512000, 24, 1, 1 },
  96 +               512000, 256000, 1, 1 },
  97         /* 11.025k rate */
  98         { 12000000, 11025, 44217600, 512, 11289600, 5644800, 128, 11289600,
  99 -               1411200, 16, 1, 1 },
 100 +               1411200, 352800, 1, 1 },
 101         { 24000000, 11025, 44217600, 512, 5644800, 5644800, 64, 2822400,
 102 -               705600, 16, 1, 1 },
 103 +               705600, 352800, 1, 1 },
 104         /* 16k rate */
 105         { 12000000, 16000, 57120000, 384, 18432000, 6144000, 128, 18432000,
 106 -               2048000, 12, 1, 1 },
 107 +               2048000, 512000, 1, 1 },
 108         { 24000000, 16000, 57120000, 384, 6144000, 6144000, 64, 5120000,
 109 -               1024000, 12, 1, 1 },
 110 +               1024000, 512000, 1, 1 },
 111         { 25000000, 16000, 32620000, 384, 6144000, 6144000, 64, 5120000,
 112 -               1024000, 12, 1, 1 },
 113 +               1024000, 512000, 1, 1 },
 114         /* 22.05k rate */
 115         { 12000000, 22050, 44217600, 256, 22579200, 5644800, 128, 22579200,
 116 -               2822400, 8, 1, 1 },
 117 +               2822400, 705600, 1, 1 },
 118         { 24000000, 22050, 44217600, 256, 5644800, 5644800, 64, 5644800,
 119 -               1411200, 8, 1, 1 },
 120 +               1411200, 705600, 1, 1 },
 121         { 25000000, 22050, 19713750, 256, 5644800, 5644800, 64, 5644800,
 122 -               1411200, 8, 1, 1 },
 123 +               1411200, 705600, 1, 1 },
 124         /* 32k rate */
 125         { 12000000, 32000, 14112000, 192, 43008000, 6144000, 64, 43008000,
 126 -               2048000, 6, 1, 1 },
 127 +               2048000, 1024000, 1, 1 },
 128         { 24000000, 32000, 14112000, 192, 12288000, 6144000, 64, 12288000,
 129 -               2048000, 6, 1, 1 },
 130 +               2048000, 1024000, 1, 1 },
 131         /* 44.1k rate */
 132         { 12000000, 44100, 44217600, 128, 45158400, 5644800, 128, 45158400,
 133 -               5644800, 4, 1, 1 },
 134 +               5644800, 1411200, 1, 1 },
 135         { 24000000, 44100, 44217600, 128, 11289600, 5644800, 64, 11289600,
 136 -               2822400, 4, 1, 1 },
 137 +               2822400, 1411200, 1, 1 },
 138         { 25000000, 44100, 19713750, 128, 11289600, 5644800, 64, 11289600,
 139 -               2822400, 4, 1, 1 },
 140 +               2822400, 1411200, 1, 1 },
 141         /* 48k rate */
 142         { 12000000, 48000, 18432000, 128, 49152000, 6144000, 128, 49152000,
 143 -               6144000, 4, 1, 1 },
 144 +               6144000, 1536000, 1, 1 },
 145         { 24000000, 48000, 18432000, 128, 12288000, 6144000, 64, 12288000,
 146 -               3072000, 4, 1, 1 },
 147 +               3072000, 1536000, 1, 1 },
 148         { 25000000, 48000, 75626250, 128, 12288000, 6144000, 64, 12288000,
 149 -               3072000, 4, 1, 1 },
 150 +               3072000, 1536000, 1, 1 },
 151
 152         /* 96k rate */
 153         { 25000000, 96000, 75626250, 64, 24576000, 6144000, 64, 24576000,
 154 -               6144000, 1, 1, 9 },
 155 +               6144000, 3072000, 1, 9 },
 156  };
 157
 158  static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
 159 @@ -745,6 +745,7 @@ static int aic32x4_setup_clocks(struct s
 160                 { .id = "madc" },
 161                 { .id = "ndac" },
 162                 { .id = "mdac" },
 163 +               { .id = "bdiv" },
 164         };
 165
 166         i = aic32x4_get_divs(parent_rate, sample_rate);
 167 @@ -762,14 +763,10 @@ static int aic32x4_setup_clocks(struct s
 168         clk_set_rate(clocks[2].clk, aic32x4_divs[i].madc_rate);
 169         clk_set_rate(clocks[3].clk, aic32x4_divs[i].ndac_rate);
 170         clk_set_rate(clocks[4].clk, aic32x4_divs[i].mdac_rate);
 171 +       clk_set_rate(clocks[5].clk, aic32x4_divs[i].bdiv_rate);
 172
 173         aic32x4_set_processing_blocks(component, aic32x4_divs[i].r_block, aic32x4_divs[i].p_block);
 174
 175 -       /* DAC_MOD_CLK as BDIV_CLKIN */
 176 -       snd_soc_component_update_bits(component, AIC32X4_IFACE3,
 177 -                               AIC32X4_BDIVCLK_MASK,
 178 -                               AIC32X4_DACMOD2BCLK << AIC32X4_BDIVCLK_SHIFT);
 179 -
 180         /* DOSR MSB & LSB values */
 181         snd_soc_component_write(component, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8);
 182         snd_soc_component_write(component, AIC32X4_DOSRLSB, (aic32x4_divs[i].dosr & 0xff));
 183 @@ -777,10 +774,6 @@ static int aic32x4_setup_clocks(struct s
 184         /* AOSR value */
 185         snd_soc_component_write(component, AIC32X4_AOSR, aic32x4_divs[i].aosr);
 186
 187 -       /* BCLK N divider */
 188 -       snd_soc_component_update_bits(component, AIC32X4_BCLKN,
 189 -                               AIC32X4_BCLK_MASK, aic32x4_divs[i].blck_N);
 190 -
 191         return 0;
 192  }
 193
 194 @@ -1003,6 +996,8 @@ static int aic32x4_component_probe(struc
 195         struct clk_bulk_data clocks[] = {
 196                 { .id = "codec_clkin" },
 197                 { .id = "pll" },
 198 +               { .id = "bdiv" },
 199 +               { .id = "mdac" },
 200         };
 201
 202         ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
 203 @@ -1020,6 +1015,7 @@ static int aic32x4_component_probe(struc
 204                 aic32x4_setup_gpios(component);
 205
 206         clk_set_parent(clocks[0].clk, clocks[1].clk);
 207 +       clk_set_parent(clocks[2].clk, clocks[3].clk);
 208
 209         /* Power platform configuration */
 210         if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {