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kernel: bump 4.9 to 4.9.137
[openwrt/openwrt.git] / target / linux / brcm2708 / patches-4.9 / 031-v4.10-0001-ARM-dts-bcm283x-Define-standard-pinctrl-groups-in-th.patch
1 From 21ff843931b2e5a9b628ac56fd0f2e4355890096 Mon Sep 17 00:00:00 2001
2 From: Eric Anholt <eric@anholt.net>
3 Date: Mon, 19 Sep 2016 10:43:18 +0200
4 Subject: [PATCH] ARM: dts: bcm283x: Define standard pinctrl groups in the gpio
5 node.
6
7 The BCM2835-ARM-Peripherals.pdf documentation specifies what the
8 function selects do for the pins, and there are a bunch of obvious
9 groupings to be made. With these created, we'll be able to replace
10 bcm2835-rpi.dtsi's main "set all of these pins to alt0" with
11 references to specific groups we want enabled.
12
13 Also add pinctrl groups for emmc and sdhost.
14
15 Based on patches by Eric Anholt, with fixups by Gerd Hoffmann.
16
17 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
18 Signed-off-by: Eric Anholt <eric@anholt.net>
19 Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
20 ---
21 arch/arm/boot/dts/bcm283x.dtsi | 203 +++++++++++++++++++++++++++++++++++++++++
22 1 file changed, 203 insertions(+)
23
24 --- a/arch/arm/boot/dts/bcm283x.dtsi
25 +++ b/arch/arm/boot/dts/bcm283x.dtsi
26 @@ -137,6 +137,209 @@
27
28 interrupt-controller;
29 #interrupt-cells = <2>;
30 +
31 + /* Defines pin muxing groups according to
32 + * BCM2835-ARM-Peripherals.pdf page 102.
33 + *
34 + * While each pin can have its mux selected
35 + * for various functions individually, some
36 + * groups only make sense to switch to a
37 + * particular function together.
38 + */
39 + dpi_gpio0: dpi_gpio0 {
40 + brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
41 + 12 13 14 15 16 17 18 19
42 + 20 21 22 23 24 25 26 27>;
43 + brcm,function = <BCM2835_FSEL_ALT2>;
44 + };
45 + emmc_gpio22: emmc_gpio22 {
46 + brcm,pins = <22 23 24 25 26 27>;
47 + brcm,function = <BCM2835_FSEL_ALT3>;
48 + };
49 + emmc_gpio34: emmc_gpio34 {
50 + brcm,pins = <34 35 36 37 38 39>;
51 + brcm,function = <BCM2835_FSEL_ALT3>;
52 + brcm,pull = <BCM2835_PUD_OFF
53 + BCM2835_PUD_UP
54 + BCM2835_PUD_UP
55 + BCM2835_PUD_UP
56 + BCM2835_PUD_UP
57 + BCM2835_PUD_UP>;
58 + };
59 + emmc_gpio48: emmc_gpio48 {
60 + brcm,pins = <48 49 50 51 52 53>;
61 + brcm,function = <BCM2835_FSEL_ALT3>;
62 + };
63 +
64 + gpclk0_gpio4: gpclk0_gpio4 {
65 + brcm,pins = <4>;
66 + brcm,function = <BCM2835_FSEL_ALT0>;
67 + };
68 + gpclk1_gpio5: gpclk1_gpio5 {
69 + brcm,pins = <5>;
70 + brcm,function = <BCM2835_FSEL_ALT0>;
71 + };
72 + gpclk1_gpio42: gpclk1_gpio42 {
73 + brcm,pins = <42>;
74 + brcm,function = <BCM2835_FSEL_ALT0>;
75 + };
76 + gpclk1_gpio44: gpclk1_gpio44 {
77 + brcm,pins = <44>;
78 + brcm,function = <BCM2835_FSEL_ALT0>;
79 + };
80 + gpclk2_gpio6: gpclk2_gpio6 {
81 + brcm,pins = <6>;
82 + brcm,function = <BCM2835_FSEL_ALT0>;
83 + };
84 + gpclk2_gpio43: gpclk2_gpio43 {
85 + brcm,pins = <43>;
86 + brcm,function = <BCM2835_FSEL_ALT0>;
87 + };
88 +
89 + i2c0_gpio0: i2c0_gpio0 {
90 + brcm,pins = <0 1>;
91 + brcm,function = <BCM2835_FSEL_ALT0>;
92 + };
93 + i2c0_gpio32: i2c0_gpio32 {
94 + brcm,pins = <32 34>;
95 + brcm,function = <BCM2835_FSEL_ALT0>;
96 + };
97 + i2c0_gpio44: i2c0_gpio44 {
98 + brcm,pins = <44 45>;
99 + brcm,function = <BCM2835_FSEL_ALT1>;
100 + };
101 + i2c1_gpio2: i2c1_gpio2 {
102 + brcm,pins = <2 3>;
103 + brcm,function = <BCM2835_FSEL_ALT0>;
104 + };
105 + i2c1_gpio44: i2c1_gpio44 {
106 + brcm,pins = <44 45>;
107 + brcm,function = <BCM2835_FSEL_ALT2>;
108 + };
109 + i2c_slave_gpio18: i2c_slave_gpio18 {
110 + brcm,pins = <18 19 20 21>;
111 + brcm,function = <BCM2835_FSEL_ALT3>;
112 + };
113 +
114 + jtag_gpio4: jtag_gpio4 {
115 + brcm,pins = <4 5 6 12 13>;
116 + brcm,function = <BCM2835_FSEL_ALT4>;
117 + };
118 + jtag_gpio22: jtag_gpio22 {
119 + brcm,pins = <22 23 24 25 26 27>;
120 + brcm,function = <BCM2835_FSEL_ALT4>;
121 + };
122 +
123 + pcm_gpio18: pcm_gpio18 {
124 + brcm,pins = <18 19 20 21>;
125 + brcm,function = <BCM2835_FSEL_ALT0>;
126 + };
127 + pcm_gpio28: pcm_gpio28 {
128 + brcm,pins = <28 29 30 31>;
129 + brcm,function = <BCM2835_FSEL_ALT2>;
130 + };
131 +
132 + pwm0_gpio12: pwm0_gpio12 {
133 + brcm,pins = <12>;
134 + brcm,function = <BCM2835_FSEL_ALT0>;
135 + };
136 + pwm0_gpio18: pwm0_gpio18 {
137 + brcm,pins = <18>;
138 + brcm,function = <BCM2835_FSEL_ALT5>;
139 + };
140 + pwm0_gpio40: pwm0_gpio40 {
141 + brcm,pins = <40>;
142 + brcm,function = <BCM2835_FSEL_ALT0>;
143 + };
144 + pwm1_gpio13: pwm1_gpio13 {
145 + brcm,pins = <13>;
146 + brcm,function = <BCM2835_FSEL_ALT0>;
147 + };
148 + pwm1_gpio19: pwm1_gpio19 {
149 + brcm,pins = <19>;
150 + brcm,function = <BCM2835_FSEL_ALT5>;
151 + };
152 + pwm1_gpio41: pwm1_gpio41 {
153 + brcm,pins = <41>;
154 + brcm,function = <BCM2835_FSEL_ALT0>;
155 + };
156 + pwm1_gpio45: pwm1_gpio45 {
157 + brcm,pins = <45>;
158 + brcm,function = <BCM2835_FSEL_ALT0>;
159 + };
160 +
161 + sdhost_gpio48: sdhost_gpio48 {
162 + brcm,pins = <48 49 50 51 52 53>;
163 + brcm,function = <BCM2835_FSEL_ALT0>;
164 + };
165 +
166 + spi0_gpio7: spi0_gpio7 {
167 + brcm,pins = <7 8 9 10 11>;
168 + brcm,function = <BCM2835_FSEL_ALT0>;
169 + };
170 + spi0_gpio35: spi0_gpio35 {
171 + brcm,pins = <35 36 37 38 39>;
172 + brcm,function = <BCM2835_FSEL_ALT0>;
173 + };
174 + spi1_gpio16: spi1_gpio16 {
175 + brcm,pins = <16 17 18 19 20 21>;
176 + brcm,function = <BCM2835_FSEL_ALT4>;
177 + };
178 + spi2_gpio40: spi2_gpio40 {
179 + brcm,pins = <40 41 42 43 44 45>;
180 + brcm,function = <BCM2835_FSEL_ALT4>;
181 + };
182 +
183 + uart0_gpio14: uart0_gpio14 {
184 + brcm,pins = <14 15>;
185 + brcm,function = <BCM2835_FSEL_ALT0>;
186 + };
187 + /* Separate from the uart0_gpio14 group
188 + * because it conflicts with spi1_gpio16, and
189 + * people often run uart0 on the two pins
190 + * without flow contrl.
191 + */
192 + uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
193 + brcm,pins = <16 17>;
194 + brcm,function = <BCM2835_FSEL_ALT3>;
195 + };
196 + uart0_gpio30: uart0_gpio30 {
197 + brcm,pins = <30 31>;
198 + brcm,function = <BCM2835_FSEL_ALT3>;
199 + };
200 + uart0_ctsrts_gpio32: uart0_ctsrts_gpio32 {
201 + brcm,pins = <32 33>;
202 + brcm,function = <BCM2835_FSEL_ALT3>;
203 + };
204 +
205 + uart1_gpio14: uart1_gpio14 {
206 + brcm,pins = <14 15>;
207 + brcm,function = <BCM2835_FSEL_ALT5>;
208 + };
209 + uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
210 + brcm,pins = <16 17>;
211 + brcm,function = <BCM2835_FSEL_ALT5>;
212 + };
213 + uart1_gpio32: uart1_gpio32 {
214 + brcm,pins = <32 33>;
215 + brcm,function = <BCM2835_FSEL_ALT5>;
216 + };
217 + uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
218 + brcm,pins = <30 31>;
219 + brcm,function = <BCM2835_FSEL_ALT5>;
220 + };
221 + uart1_gpio36: uart1_gpio36 {
222 + brcm,pins = <36 37 38 39>;
223 + brcm,function = <BCM2835_FSEL_ALT2>;
224 + };
225 + uart1_gpio40: uart1_gpio40 {
226 + brcm,pins = <40 41>;
227 + brcm,function = <BCM2835_FSEL_ALT5>;
228 + };
229 + uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
230 + brcm,pins = <42 43>;
231 + brcm,function = <BCM2835_FSEL_ALT5>;
232 + };
233 };
234
235 uart0: serial@7e201000 {
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