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dev-spi.c checks for running CPU, not board code
[openwrt/openwrt.git] / target / linux / brcm63xx / patches-2.6.39 / 240-spi.patch
1 --- a/arch/mips/bcm63xx/cpu.c
2 +++ b/arch/mips/bcm63xx/cpu.c
3 @@ -58,6 +58,7 @@ static const unsigned long bcm96338_regs
4
5 static const int bcm96338_irqs[] = {
6 [IRQ_TIMER] = BCM_6338_TIMER_IRQ,
7 + [IRQ_SPI] = BCM_6338_SPI_IRQ,
8 [IRQ_UART0] = BCM_6338_UART0_IRQ,
9 [IRQ_DSL] = BCM_6338_DSL_IRQ,
10 [IRQ_ENET0] = BCM_6338_ENET0_IRQ,
11 @@ -132,6 +133,7 @@ static const unsigned long bcm96348_regs
12
13 static const int bcm96348_irqs[] = {
14 [IRQ_TIMER] = BCM_6348_TIMER_IRQ,
15 + [IRQ_SPI] = BCM_6348_SPI_IRQ,
16 [IRQ_UART0] = BCM_6348_UART0_IRQ,
17 [IRQ_DSL] = BCM_6348_DSL_IRQ,
18 [IRQ_ENET0] = BCM_6348_ENET0_IRQ,
19 @@ -175,6 +177,7 @@ static const unsigned long bcm96358_regs
20
21 static const int bcm96358_irqs[] = {
22 [IRQ_TIMER] = BCM_6358_TIMER_IRQ,
23 + [IRQ_SPI] = BCM_6358_SPI_IRQ,
24 [IRQ_UART0] = BCM_6358_UART0_IRQ,
25 [IRQ_UART1] = BCM_6358_UART1_IRQ,
26 [IRQ_DSL] = BCM_6358_DSL_IRQ,
27 --- /dev/null
28 +++ b/arch/mips/bcm63xx/dev-spi.c
29 @@ -0,0 +1,131 @@
30 +/*
31 + * This file is subject to the terms and conditions of the GNU General Public
32 + * License. See the file "COPYING" in the main directory of this archive
33 + * for more details.
34 + *
35 + * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
36 + * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
37 + */
38 +
39 +#include <linux/init.h>
40 +#include <linux/kernel.h>
41 +#include <linux/platform_device.h>
42 +
43 +#include <bcm63xx_cpu.h>
44 +#include <bcm63xx_dev_spi.h>
45 +#include <bcm63xx_regs.h>
46 +
47 +#ifdef BCMCPU_RUNTIME_DETECT
48 +/*
49 + * register offsets
50 + */
51 +static const unsigned long bcm96338_regs_spi[] = {
52 + [SPI_CMD] = SPI_BCM_6338_SPI_CMD,
53 + [SPI_INT_STATUS] = SPI_BCM_6338_SPI_INT_STATUS,
54 + [SPI_INT_MASK_ST] = SPI_BCM_6338_SPI_MASK_INT_ST,
55 + [SPI_INT_MASK] = SPI_BCM_6338_SPI_INT_MASK,
56 + [SPI_ST] = SPI_BCM_6338_SPI_ST,
57 + [SPI_CLK_CFG] = SPI_BCM_6338_SPI_CLK_CFG,
58 + [SPI_FILL_BYTE] = SPI_BCM_6338_SPI_FILL_BYTE,
59 + [SPI_MSG_TAIL] = SPI_BCM_6338_SPI_MSG_TAIL,
60 + [SPI_RX_TAIL] = SPI_BCM_6338_SPI_RX_TAIL,
61 + [SPI_MSG_CTL] = SPI_BCM_6338_SPI_MSG_CTL,
62 + [SPI_MSG_DATA] = SPI_BCM_6338_SPI_MSG_DATA,
63 + [SPI_RX_DATA] = SPI_BCM_6338_SPI_RX_DATA,
64 +};
65 +
66 +static const unsigned long bcm96348_regs_spi[] = {
67 + [SPI_CMD] = SPI_BCM_6348_SPI_CMD,
68 + [SPI_INT_STATUS] = SPI_BCM_6348_SPI_INT_STATUS,
69 + [SPI_INT_MASK_ST] = SPI_BCM_6348_SPI_MASK_INT_ST,
70 + [SPI_INT_MASK] = SPI_BCM_6348_SPI_INT_MASK,
71 + [SPI_ST] = SPI_BCM_6348_SPI_ST,
72 + [SPI_CLK_CFG] = SPI_BCM_6348_SPI_CLK_CFG,
73 + [SPI_FILL_BYTE] = SPI_BCM_6348_SPI_FILL_BYTE,
74 + [SPI_MSG_TAIL] = SPI_BCM_6348_SPI_MSG_TAIL,
75 + [SPI_RX_TAIL] = SPI_BCM_6348_SPI_RX_TAIL,
76 + [SPI_MSG_CTL] = SPI_BCM_6348_SPI_MSG_CTL,
77 + [SPI_MSG_DATA] = SPI_BCM_6348_SPI_MSG_DATA,
78 + [SPI_RX_DATA] = SPI_BCM_6348_SPI_RX_DATA,
79 +};
80 +
81 +static const unsigned long bcm96358_regs_spi[] = {
82 + [SPI_CMD] = SPI_BCM_6358_SPI_CMD,
83 + [SPI_INT_STATUS] = SPI_BCM_6358_SPI_INT_STATUS,
84 + [SPI_INT_MASK_ST] = SPI_BCM_6358_SPI_MASK_INT_ST,
85 + [SPI_INT_MASK] = SPI_BCM_6358_SPI_INT_MASK,
86 + [SPI_ST] = SPI_BCM_6358_SPI_STATUS,
87 + [SPI_CLK_CFG] = SPI_BCM_6358_SPI_CLK_CFG,
88 + [SPI_FILL_BYTE] = SPI_BCM_6358_SPI_FILL_BYTE,
89 + [SPI_MSG_TAIL] = SPI_BCM_6358_SPI_MSG_TAIL,
90 + [SPI_RX_TAIL] = SPI_BCM_6358_SPI_RX_TAIL,
91 + [SPI_MSG_CTL] = SPI_BCM_6358_MSG_CTL,
92 + [SPI_MSG_DATA] = SPI_BCM_6358_SPI_MSG_DATA,
93 + [SPI_RX_DATA] = SPI_BCM_6358_SPI_RX_DATA,
94 +};
95 +
96 +const unsigned long *bcm63xx_regs_spi;
97 +EXPORT_SYMBOL(bcm63xx_regs_spi);
98 +
99 +static __init void bcm63xx_spi_regs_init(void)
100 +{
101 + if (BCMCPU_IS_6338())
102 + bcm63xx_regs_spi = bcm96338_regs_spi;
103 + if (BCMCPU_IS_6348())
104 + bcm63xx_regs_spi = bcm96348_regs_spi;
105 + if (BCMCPU_IS_6358())
106 + bcm63xx_regs_spi = bcm96358_regs_spi;
107 +}
108 +#else
109 +static __init void bcm63xx_spi_regs_init(void) { }
110 +#endif
111 +
112 +static struct resource spi_resources[] = {
113 + {
114 + .start = -1, /* filled at runtime */
115 + .end = -1, /* filled at runtime */
116 + .flags = IORESOURCE_MEM,
117 + },
118 + {
119 + .start = -1, /* filled at runtime */
120 + .flags = IORESOURCE_IRQ,
121 + },
122 +};
123 +
124 +static struct bcm63xx_spi_pdata spi_pdata = {
125 + .bus_num = 0,
126 + .num_chipselect = 8,
127 + .speed_hz = 50000000, /* Fclk */
128 +};
129 +
130 +static struct platform_device bcm63xx_spi_device = {
131 + .name = "bcm63xx-spi",
132 + .id = 0,
133 + .num_resources = ARRAY_SIZE(spi_resources),
134 + .resource = spi_resources,
135 + .dev = {
136 + .platform_data = &spi_pdata,
137 + },
138 +};
139 +
140 +int __init bcm63xx_spi_register(void)
141 +{
142 + spi_resources[0].start = bcm63xx_regset_address(RSET_SPI);
143 + spi_resources[0].end = spi_resources[0].start;
144 + spi_resources[0].end += RSET_SPI_SIZE - 1;
145 + spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI);
146 +
147 + if (BCMCPU_IS_6345())
148 + return -ENODEV;
149 +
150 + /* Fill in platform data */
151 + if (BCMCPU_IS_6338() || BCMCPU_IS_6348())
152 + spi_pdata.fifo_size = SPI_BCM_6338_SPI_MSG_DATA_SIZE;
153 +
154 + if (BCMCPU_IS_6358())
155 + spi_pdata.fifo_size = SPI_BCM_6358_SPI_MSG_DATA_SIZE;
156 +
157 + bcm63xx_spi_regs_init();
158 +
159 + return platform_device_register(&bcm63xx_spi_device);
160 +}
161 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
162 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
163 @@ -109,6 +109,7 @@ enum bcm63xx_regs_set {
164 #define RSET_WDT_SIZE 12
165 #define RSET_ENET_SIZE 2048
166 #define RSET_ENETDMA_SIZE 2048
167 +#define RSET_SPI_SIZE 256
168 #define RSET_UART_SIZE 24
169 #define RSET_UDC_SIZE 256
170 #define RSET_OHCI_SIZE 256
171 @@ -214,7 +215,7 @@ enum bcm63xx_regs_set {
172 #define BCM_6358_UART0_BASE (0xfffe0100)
173 #define BCM_6358_UART1_BASE (0xfffe0120)
174 #define BCM_6358_GPIO_BASE (0xfffe0080)
175 -#define BCM_6358_SPI_BASE (0xdeadbeef)
176 +#define BCM_6358_SPI_BASE (0xfffe0800)
177 #define BCM_6358_UDC0_BASE (0xfffe0400)
178 #define BCM_6358_OHCI0_BASE (0xfffe1400)
179 #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
180 @@ -441,6 +442,7 @@ static inline unsigned long bcm63xx_regs
181 */
182 enum bcm63xx_irq {
183 IRQ_TIMER = 0,
184 + IRQ_SPI,
185 IRQ_UART0,
186 IRQ_UART1,
187 IRQ_DSL,
188 @@ -507,6 +509,7 @@ enum bcm63xx_irq {
189 * 6348 irqs
190 */
191 #define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
192 +#define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
193 #define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
194 #define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
195 #define BCM_6348_UDC0_IRQ (IRQ_INTERNAL_BASE + 6)
196 @@ -531,6 +534,7 @@ enum bcm63xx_irq {
197 * 6358 irqs
198 */
199 #define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
200 +#define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
201 #define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
202 #define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
203 #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
204 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
205 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
206 @@ -771,4 +771,116 @@
207 #define DMIPSPLLCFG_N2_SHIFT 29
208 #define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
209
210 +/*************************************************************************
211 + * _REG relative to RSET_SPI
212 + *************************************************************************/
213 +
214 +/* BCM 6338 SPI core */
215 +#define SPI_BCM_6338_SPI_CMD 0x00 /* 16-bits register */
216 +#define SPI_BCM_6338_SPI_INT_STATUS 0x02
217 +#define SPI_BCM_6338_SPI_MASK_INT_ST 0x03
218 +#define SPI_BCM_6338_SPI_INT_MASK 0x04
219 +#define SPI_BCM_6338_SPI_ST 0x05
220 +#define SPI_BCM_6338_SPI_CLK_CFG 0x06
221 +#define SPI_BCM_6338_SPI_FILL_BYTE 0x07
222 +#define SPI_BCM_6338_SPI_MSG_TAIL 0x09
223 +#define SPI_BCM_6338_SPI_RX_TAIL 0x0b
224 +#define SPI_BCM_6338_SPI_MSG_CTL 0x40
225 +#define SPI_BCM_6338_SPI_MSG_DATA 0x41
226 +#define SPI_BCM_6338_SPI_MSG_DATA_SIZE 0x3f
227 +#define SPI_BCM_6338_SPI_RX_DATA 0x80
228 +#define SPI_BCM_6338_SPI_RX_DATA_SIZE 0x3f
229 +
230 +/* BCM 6348 SPI core */
231 +#define SPI_BCM_6348_SPI_MASK_INT_ST 0x00
232 +#define SPI_BCM_6348_SPI_INT_STATUS 0x01
233 +#define SPI_BCM_6348_SPI_CMD 0x02 /* 16-bits register */
234 +#define SPI_BCM_6348_SPI_FILL_BYTE 0x04
235 +#define SPI_BCM_6348_SPI_CLK_CFG 0x05
236 +#define SPI_BCM_6348_SPI_ST 0x06
237 +#define SPI_BCM_6348_SPI_INT_MASK 0x07
238 +#define SPI_BCM_6348_SPI_RX_TAIL 0x08
239 +#define SPI_BCM_6348_SPI_MSG_TAIL 0x10
240 +#define SPI_BCM_6348_SPI_MSG_DATA 0x40
241 +#define SPI_BCM_6348_SPI_MSG_CTL 0x42
242 +#define SPI_BCM_6348_SPI_MSG_DATA_SIZE 0x3f
243 +#define SPI_BCM_6348_SPI_RX_DATA 0x80
244 +#define SPI_BCM_6348_SPI_RX_DATA_SIZE 0x3f
245 +
246 +/* BCM 6358 SPI core */
247 +#define SPI_BCM_6358_MSG_CTL 0x00 /* 16-bits register */
248 +
249 +#define SPI_BCM_6358_SPI_MSG_DATA 0x02
250 +#define SPI_BCM_6358_SPI_MSG_DATA_SIZE 0x21e
251 +
252 +#define SPI_BCM_6358_SPI_RX_DATA 0x400
253 +#define SPI_BCM_6358_SPI_RX_DATA_SIZE 0x220
254 +
255 +#define SPI_BCM_6358_SPI_CMD 0x700 /* 16-bits register */
256 +
257 +#define SPI_BCM_6358_SPI_INT_STATUS 0x702
258 +#define SPI_BCM_6358_SPI_MASK_INT_ST 0x703
259 +
260 +#define SPI_BCM_6358_SPI_INT_MASK 0x704
261 +
262 +#define SPI_BCM_6358_SPI_STATUS 0x705
263 +
264 +#define SPI_BCM_6358_SPI_CLK_CFG 0x706
265 +
266 +#define SPI_BCM_6358_SPI_FILL_BYTE 0x707
267 +#define SPI_BCM_6358_SPI_MSG_TAIL 0x709
268 +#define SPI_BCM_6358_SPI_RX_TAIL 0x70B
269 +
270 +/* Shared SPI definitions */
271 +
272 +/* Message configuration */
273 +#define SPI_FD_RW 0x00
274 +#define SPI_HD_W 0x01
275 +#define SPI_HD_R 0x02
276 +#define SPI_BYTE_CNT_SHIFT 0
277 +#define SPI_MSG_TYPE_SHIFT 14
278 +
279 +/* Command */
280 +#define SPI_CMD_NOOP 0x01
281 +#define SPI_CMD_SOFT_RESET 0x02
282 +#define SPI_CMD_HARD_RESET 0x04
283 +#define SPI_CMD_START_IMMEDIATE 0x08
284 +#define SPI_CMD_COMMAND_SHIFT 0
285 +#define SPI_CMD_COMMAND_MASK 0x000f
286 +#define SPI_CMD_DEVICE_ID_SHIFT 4
287 +#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
288 +#define SPI_CMD_ONE_BYTE_SHIFT 11
289 +#define SPI_CMD_ONE_WIRE_SHIFT 12
290 +#define SPI_DEV_ID_0 0
291 +#define SPI_DEV_ID_1 1
292 +#define SPI_DEV_ID_2 2
293 +#define SPI_DEV_ID_3 3
294 +
295 +/* Interrupt mask */
296 +#define SPI_INTR_CMD_DONE 0x01
297 +#define SPI_INTR_RX_OVERFLOW 0x02
298 +#define SPI_INTR_TX_UNDERFLOW 0x04
299 +#define SPI_INTR_TX_OVERFLOW 0x08
300 +#define SPI_INTR_RX_UNDERFLOW 0x10
301 +#define SPI_INTR_CLEAR_ALL 0x1f
302 +
303 +/* Status */
304 +#define SPI_RX_EMPTY 0x02
305 +#define SPI_CMD_BUSY 0x04
306 +#define SPI_SERIAL_BUSY 0x08
307 +
308 +/* Clock configuration */
309 +#define SPI_CLK_20MHZ 0x00
310 +#define SPI_CLK_0_391MHZ 0x01
311 +#define SPI_CLK_0_781MHZ 0x02 /* default */
312 +#define SPI_CLK_1_563MHZ 0x03
313 +#define SPI_CLK_3_125MHZ 0x04
314 +#define SPI_CLK_6_250MHZ 0x05
315 +#define SPI_CLK_12_50MHZ 0x06
316 +#define SPI_CLK_25MHZ 0x07
317 +#define SPI_CLK_MASK 0x07
318 +#define SPI_SSOFFTIME_MASK 0x38
319 +#define SPI_SSOFFTIME_SHIFT 3
320 +#define SPI_BYTE_SWAP 0x80
321 +
322 #endif /* BCM63XX_REGS_H_ */
323 --- /dev/null
324 +++ b/drivers/spi/bcm63xx_spi.c
325 @@ -0,0 +1,496 @@
326 +/*
327 + * Broadcom BCM63xx SPI controller support
328 + *
329 + * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
330 + * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
331 + *
332 + * This program is free software; you can redistribute it and/or
333 + * modify it under the terms of the GNU General Public License
334 + * as published by the Free Software Foundation; either version 2
335 + * of the License, or (at your option) any later version.
336 + *
337 + * This program is distributed in the hope that it will be useful,
338 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
339 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
340 + * GNU General Public License for more details.
341 + *
342 + * You should have received a copy of the GNU General Public License
343 + * along with this program; if not, write to the
344 + * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
345 + */
346 +
347 +#include <linux/kernel.h>
348 +#include <linux/init.h>
349 +#include <linux/clk.h>
350 +#include <linux/module.h>
351 +#include <linux/platform_device.h>
352 +#include <linux/delay.h>
353 +#include <linux/interrupt.h>
354 +#include <linux/spi/spi.h>
355 +#include <linux/completion.h>
356 +#include <linux/err.h>
357 +
358 +#include <bcm63xx_dev_spi.h>
359 +
360 +#define PFX KBUILD_MODNAME
361 +#define DRV_VER "0.1.2"
362 +
363 +struct bcm63xx_spi {
364 + spinlock_t lock;
365 + int stopping;
366 + struct completion done;
367 +
368 + void __iomem *regs;
369 + int irq;
370 +
371 + /* Platform data */
372 + u32 speed_hz;
373 + unsigned fifo_size;
374 +
375 + /* Data buffers */
376 + const unsigned char *tx_ptr;
377 + unsigned char *rx_ptr;
378 +
379 + /* data iomem */
380 + u8 __iomem *tx_io;
381 + const u8 __iomem *rx_io;
382 +
383 + int remaining_bytes;
384 +
385 + struct clk *clk;
386 + struct platform_device *pdev;
387 +};
388 +
389 +static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
390 + unsigned int offset)
391 +{
392 + return bcm_readw(bs->regs + bcm63xx_spireg(offset));
393 +}
394 +
395 +static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
396 + unsigned int offset)
397 +{
398 + return bcm_readw(bs->regs + bcm63xx_spireg(offset));
399 +}
400 +
401 +static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
402 + u8 value, unsigned int offset)
403 +{
404 + bcm_writeb(value, bs->regs + bcm63xx_spireg(offset));
405 +}
406 +
407 +static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
408 + u16 value, unsigned int offset)
409 +{
410 + bcm_writew(value, bs->regs + bcm63xx_spireg(offset));
411 +}
412 +
413 +static int bcm63xx_spi_setup_transfer(struct spi_device *spi,
414 + struct spi_transfer *t)
415 +{
416 + u8 bits_per_word;
417 + u8 clk_cfg;
418 + u32 hz;
419 + unsigned int div;
420 +
421 + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
422 +
423 + bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
424 + hz = (t) ? t->speed_hz : spi->max_speed_hz;
425 + if (bits_per_word != 8) {
426 + dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
427 + __func__, bits_per_word);
428 + return -EINVAL;
429 + }
430 +
431 + if (spi->chip_select > spi->master->num_chipselect) {
432 + dev_err(&spi->dev, "%s, unsupported slave %d\n",
433 + __func__, spi->chip_select);
434 + return -EINVAL;
435 + }
436 +
437 + /* Check clock setting */
438 + div = (bs->speed_hz / hz);
439 + switch (div) {
440 + case 2:
441 + clk_cfg = SPI_CLK_25MHZ;
442 + break;
443 + case 4:
444 + clk_cfg = SPI_CLK_12_50MHZ;
445 + break;
446 + case 8:
447 + clk_cfg = SPI_CLK_6_250MHZ;
448 + break;
449 + case 16:
450 + clk_cfg = SPI_CLK_3_125MHZ;
451 + break;
452 + case 32:
453 + clk_cfg = SPI_CLK_1_563MHZ;
454 + break;
455 + case 64:
456 + clk_cfg = SPI_CLK_0_781MHZ;
457 + break;
458 + case 128:
459 + default:
460 + /* Set to slowest mode for compatibility */
461 + clk_cfg = SPI_CLK_0_391MHZ;
462 + break;
463 + }
464 +
465 + bcm_spi_writeb(bs, clk_cfg, SPI_CLK_CFG);
466 + dev_dbg(&spi->dev, "Setting clock register to %d (hz %d, cmd %02x)\n",
467 + div, hz, clk_cfg);
468 +
469 + return 0;
470 +}
471 +
472 +/* the spi->mode bits understood by this driver: */
473 +#define MODEBITS (SPI_CPOL | SPI_CPHA)
474 +
475 +static int bcm63xx_spi_setup(struct spi_device *spi)
476 +{
477 + struct bcm63xx_spi *bs;
478 + int ret;
479 +
480 + bs = spi_master_get_devdata(spi->master);
481 +
482 + if (bs->stopping)
483 + return -ESHUTDOWN;
484 +
485 + if (!spi->bits_per_word)
486 + spi->bits_per_word = 8;
487 +
488 + if (spi->mode & ~MODEBITS) {
489 + dev_err(&spi->dev, "%s, unsupported mode bits %x\n",
490 + __func__, spi->mode & ~MODEBITS);
491 + return -EINVAL;
492 + }
493 +
494 + ret = bcm63xx_spi_setup_transfer(spi, NULL);
495 + if (ret < 0) {
496 + dev_err(&spi->dev, "setup: unsupported mode bits %x\n",
497 + spi->mode & ~MODEBITS);
498 + return ret;
499 + }
500 +
501 + dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
502 + __func__, spi->mode & MODEBITS, spi->bits_per_word, 0);
503 +
504 + return 0;
505 +}
506 +
507 +/* Fill the TX FIFO with as many bytes as possible */
508 +static void bcm63xx_spi_fill_tx_fifo(struct bcm63xx_spi *bs)
509 +{
510 + u8 size;
511 +
512 + /* Fill the Tx FIFO with as many bytes as possible */
513 + size = bs->remaining_bytes < bs->fifo_size ? bs->remaining_bytes :
514 + bs->fifo_size;
515 + memcpy_toio(bs->tx_io, bs->tx_ptr, size);
516 + bs->remaining_bytes -= size;
517 +}
518 +
519 +static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
520 +{
521 + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
522 + u16 msg_ctl;
523 + u16 cmd;
524 +
525 + dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
526 + t->tx_buf, t->rx_buf, t->len);
527 +
528 + /* Transmitter is inhibited */
529 + bs->tx_ptr = t->tx_buf;
530 + bs->rx_ptr = t->rx_buf;
531 + init_completion(&bs->done);
532 +
533 + if (t->tx_buf) {
534 + bs->remaining_bytes = t->len;
535 + bcm63xx_spi_fill_tx_fifo(bs);
536 + }
537 +
538 + /* Enable the command done interrupt which
539 + * we use to determine completion of a command */
540 + bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
541 +
542 + /* Fill in the Message control register */
543 + msg_ctl = (t->len << SPI_BYTE_CNT_SHIFT);
544 +
545 + if (t->rx_buf && t->tx_buf)
546 + msg_ctl |= (SPI_FD_RW << SPI_MSG_TYPE_SHIFT);
547 + else if (t->rx_buf)
548 + msg_ctl |= (SPI_HD_R << SPI_MSG_TYPE_SHIFT);
549 + else if (t->tx_buf)
550 + msg_ctl |= (SPI_HD_W << SPI_MSG_TYPE_SHIFT);
551 +
552 + bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
553 +
554 + /* Issue the transfer */
555 + cmd = SPI_CMD_START_IMMEDIATE;
556 + cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
557 + cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
558 + bcm_spi_writew(bs, cmd, SPI_CMD);
559 + wait_for_completion(&bs->done);
560 +
561 + /* Disable the CMD_DONE interrupt */
562 + bcm_spi_writeb(bs, 0, SPI_INT_MASK);
563 +
564 + return t->len - bs->remaining_bytes;
565 +}
566 +
567 +static int bcm63xx_transfer(struct spi_device *spi, struct spi_message *m)
568 +{
569 + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
570 + struct spi_transfer *t;
571 + int ret = 0;
572 +
573 + if (unlikely(list_empty(&m->transfers)))
574 + return -EINVAL;
575 +
576 + if (bs->stopping)
577 + return -ESHUTDOWN;
578 +
579 + list_for_each_entry(t, &m->transfers, transfer_list) {
580 + ret += bcm63xx_txrx_bufs(spi, t);
581 + }
582 +
583 + m->complete(m->context);
584 +
585 + return ret;
586 +}
587 +
588 +/* This driver supports single master mode only. Hence
589 + * CMD_DONE is the only interrupt we care about
590 + */
591 +static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
592 +{
593 + struct spi_master *master = (struct spi_master *)dev_id;
594 + struct bcm63xx_spi *bs = spi_master_get_devdata(master);
595 + u8 intr;
596 + u16 cmd;
597 +
598 + /* Read interupts and clear them immediately */
599 + intr = bcm_spi_readb(bs, SPI_INT_STATUS);
600 + bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
601 + bcm_spi_writeb(bs, 0, SPI_INT_MASK);
602 +
603 + /* A tansfer completed */
604 + if (intr & SPI_INTR_CMD_DONE) {
605 + u8 rx_tail;
606 +
607 + rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL);
608 +
609 + /* Read out all the data */
610 + if (rx_tail)
611 + memcpy_fromio(bs->rx_ptr, bs->rx_io, rx_tail);
612 +
613 + /* See if there is more data to send */
614 + if (bs->remaining_bytes > 0) {
615 + bcm63xx_spi_fill_tx_fifo(bs);
616 +
617 + /* Start the transfer */
618 + bcm_spi_writew(bs, SPI_HD_W << SPI_MSG_TYPE_SHIFT,
619 + SPI_MSG_CTL);
620 + cmd = bcm_spi_readw(bs, SPI_CMD);
621 + cmd |= SPI_CMD_START_IMMEDIATE;
622 + cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
623 + bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
624 + bcm_spi_writew(bs, cmd, SPI_CMD);
625 + } else {
626 + complete(&bs->done);
627 + }
628 + }
629 +
630 + return IRQ_HANDLED;
631 +}
632 +
633 +
634 +static int __init bcm63xx_spi_probe(struct platform_device *pdev)
635 +{
636 + struct resource *r;
637 + struct device *dev = &pdev->dev;
638 + struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data;
639 + int irq;
640 + struct spi_master *master;
641 + struct clk *clk;
642 + struct bcm63xx_spi *bs;
643 + int ret;
644 +
645 + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
646 + if (!r) {
647 + dev_err(dev, "no iomem\n");
648 + ret = -ENXIO;
649 + goto out;
650 + }
651 +
652 + irq = platform_get_irq(pdev, 0);
653 + if (irq < 0) {
654 + dev_err(dev, "no irq\n");
655 + ret = -ENXIO;
656 + goto out;
657 + }
658 +
659 + clk = clk_get(dev, "spi");
660 + if (IS_ERR(clk)) {
661 + dev_err(dev, "no clock for device\n");
662 + ret = -ENODEV;
663 + goto out;
664 + }
665 +
666 + master = spi_alloc_master(dev, sizeof(*bs));
667 + if (!master) {
668 + dev_err(dev, "out of memory\n");
669 + ret = -ENOMEM;
670 + goto out_free;
671 + }
672 +
673 + bs = spi_master_get_devdata(master);
674 + init_completion(&bs->done);
675 +
676 + platform_set_drvdata(pdev, master);
677 + bs->pdev = pdev;
678 +
679 + if (!request_mem_region(r->start, r->end - r->start, PFX)) {
680 + dev_err(dev, "iomem request failed\n");
681 + ret = -ENXIO;
682 + goto out_put_master;
683 + }
684 +
685 + bs->regs = ioremap_nocache(r->start, r->end - r->start);
686 + if (!bs->regs) {
687 + dev_err(dev, "unable to ioremap regs\n");
688 + ret = -ENOMEM;
689 + goto out_put_master;
690 + }
691 + bs->irq = irq;
692 + bs->clk = clk;
693 + bs->fifo_size = pdata->fifo_size;
694 +
695 + ret = request_irq(irq, bcm63xx_spi_interrupt, 0, pdev->name, master);
696 + if (ret) {
697 + dev_err(dev, "unable to request irq\n");
698 + goto out_unmap;
699 + }
700 +
701 + master->bus_num = pdata->bus_num;
702 + master->num_chipselect = pdata->num_chipselect;
703 + master->setup = bcm63xx_spi_setup;
704 + master->transfer = bcm63xx_transfer;
705 + bs->speed_hz = pdata->speed_hz;
706 + bs->stopping = 0;
707 + bs->tx_io = (u8*)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
708 + bs->rx_io = (const u8*)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));
709 + spin_lock_init(&bs->lock);
710 +
711 + /* Initialize hardware */
712 + clk_enable(bs->clk);
713 + bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
714 +
715 + /* register and we are done */
716 + ret = spi_register_master(master);
717 + if (ret) {
718 + dev_err(dev, "spi register failed\n");
719 + goto out_reset_hw;
720 + }
721 +
722 + dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d) v%s\n",
723 + r->start, irq, bs->fifo_size, DRV_VER);
724 +
725 + return 0;
726 +
727 +out_reset_hw:
728 + clk_disable(clk);
729 + free_irq(irq, master);
730 +out_unmap:
731 + iounmap(bs->regs);
732 +out_put_master:
733 + spi_master_put(master);
734 +out_free:
735 + clk_put(clk);
736 +out:
737 + return ret;
738 +}
739 +
740 +static int __exit bcm63xx_spi_remove(struct platform_device *pdev)
741 +{
742 + struct spi_master *master = platform_get_drvdata(pdev);
743 + struct bcm63xx_spi *bs = spi_master_get_devdata(master);
744 + struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
745 +
746 + /* reset spi block */
747 + bcm_spi_writeb(bs, 0, SPI_INT_MASK);
748 + spin_lock(&bs->lock);
749 + bs->stopping = 1;
750 +
751 + /* HW shutdown */
752 + clk_disable(bs->clk);
753 + clk_put(bs->clk);
754 +
755 + spin_unlock(&bs->lock);
756 +
757 + free_irq(bs->irq, master);
758 + iounmap(bs->regs);
759 + release_mem_region(r->start, r->end - r->start);
760 + platform_set_drvdata(pdev, 0);
761 + spi_unregister_master(master);
762 +
763 + return 0;
764 +}
765 +
766 +#ifdef CONFIG_PM
767 +static int bcm63xx_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
768 +{
769 + struct spi_master *master = platform_get_drvdata(pdev);
770 + struct bcm63xx_spi *bs = spi_master_get_devdata(master);
771 +
772 + clk_disable(bs->clk);
773 +
774 + return 0;
775 +}
776 +
777 +static int bcm63xx_spi_resume(struct platform_device *pdev)
778 +{
779 + struct spi_master *master = platform_get_drvdata(pdev);
780 + struct bcm63xx_spi *bs = spi_master_get_devdata(master);
781 +
782 + clk_enable(bs->clk);
783 +
784 + return 0;
785 +}
786 +#else
787 +#define bcm63xx_spi_suspend NULL
788 +#define bcm63xx_spi_resume NULL
789 +#endif
790 +
791 +static struct platform_driver bcm63xx_spi_driver = {
792 + .driver = {
793 + .name = "bcm63xx-spi",
794 + .owner = THIS_MODULE,
795 + },
796 + .probe = bcm63xx_spi_probe,
797 + .remove = __exit_p(bcm63xx_spi_remove),
798 + .suspend = bcm63xx_spi_suspend,
799 + .resume = bcm63xx_spi_resume,
800 +};
801 +
802 +
803 +static int __init bcm63xx_spi_init(void)
804 +{
805 + return platform_driver_register(&bcm63xx_spi_driver);
806 +}
807 +
808 +static void __exit bcm63xx_spi_exit(void)
809 +{
810 + platform_driver_unregister(&bcm63xx_spi_driver);
811 +}
812 +
813 +module_init(bcm63xx_spi_init);
814 +module_exit(bcm63xx_spi_exit);
815 +
816 +MODULE_ALIAS("platform:bcm63xx_spi");
817 +MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
818 +MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
819 +MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
820 +MODULE_LICENSE("GPL");
821 +MODULE_VERSION(DRV_VER);
822 --- a/drivers/spi/Kconfig
823 +++ b/drivers/spi/Kconfig
824 @@ -74,6 +74,12 @@ config SPI_ATMEL
825 This selects a driver for the Atmel SPI Controller, present on
826 many AT32 (AVR32) and AT91 (ARM) chips.
827
828 +config SPI_BCM63XX
829 + tristate "Broadcom BCM63xx SPI controller"
830 + depends on BCM63XX
831 + help
832 + This is the SPI controller master driver for Broadcom BCM63xx SoC.
833 +
834 config SPI_BFIN
835 tristate "SPI controller driver for ADI Blackfin5xx"
836 depends on BLACKFIN
837 --- a/drivers/spi/Makefile
838 +++ b/drivers/spi/Makefile
839 @@ -55,6 +55,7 @@ obj-$(CONFIG_SPI_SH_SCI) += spi_sh_sci.
840 obj-$(CONFIG_SPI_SH_MSIOF) += spi_sh_msiof.o
841 obj-$(CONFIG_SPI_STMP3XXX) += spi_stmp.o
842 obj-$(CONFIG_SPI_NUC900) += spi_nuc900.o
843 +obj-$(CONFIG_SPI_BCM63XX) += bcm63xx_spi.o
844
845 # special build for s3c24xx spi driver with fiq support
846 spi_s3c24xx_hw-y := spi_s3c24xx.o
847 --- /dev/null
848 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
849 @@ -0,0 +1,126 @@
850 +#ifndef BCM63XX_DEV_SPI_H
851 +#define BCM63XX_DEV_SPI_H
852 +
853 +#include <linux/types.h>
854 +#include <bcm63xx_io.h>
855 +#include <bcm63xx_regs.h>
856 +
857 +int __init bcm63xx_spi_register(void);
858 +
859 +struct bcm63xx_spi_pdata {
860 + unsigned int fifo_size;
861 + int bus_num;
862 + int num_chipselect;
863 + u32 speed_hz;
864 +};
865 +
866 +enum bcm63xx_regs_spi {
867 + SPI_CMD,
868 + SPI_INT_STATUS,
869 + SPI_INT_MASK_ST,
870 + SPI_INT_MASK,
871 + SPI_ST,
872 + SPI_CLK_CFG,
873 + SPI_FILL_BYTE,
874 + SPI_MSG_TAIL,
875 + SPI_RX_TAIL,
876 + SPI_MSG_CTL,
877 + SPI_MSG_DATA,
878 + SPI_RX_DATA,
879 +};
880 +
881 +static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
882 +{
883 +#ifdef BCMCPU_RUNTIME_DETECT
884 + extern const unsigned long *bcm63xx_regs_spi;
885 + return bcm63xx_regs_spi[reg];
886 +#else
887 +#ifdef CONFIG_BCM63XX_CPU_6338
888 +switch (reg) {
889 + case SPI_CMD:
890 + return SPI_BCM_6338_SPI_CMD;
891 + case SPI_INT_STATUS:
892 + return SPI_BCM_6338_SPI_INT_STATUS;
893 + case SPI_INT_MASK_ST:
894 + return SPI_BCM_6338_SPI_MASK_INT_ST;
895 + case SPI_INT_MASK:
896 + return SPI_BCM_6338_SPI_INT_MASK;
897 + case SPI_ST:
898 + return SPI_BCM_6338_SPI_ST;
899 + case SPI_CLK_CFG:
900 + return SPI_BCM_6338_SPI_CLK_CFG;
901 + case SPI_FILL_BYTE:
902 + return SPI_BCM_6338_SPI_FILL_BYTE;
903 + case SPI_MSG_TAIL:
904 + return SPI_BCM_6338_SPI_MSG_TAIL;
905 + case SPI_RX_TAIL:
906 + return SPI_BCM_6338_SPI_RX_TAIL;
907 + case SPI_MSG_CTL:
908 + return SPI_BCM_6338_SPI_MSG_CTL;
909 + case SPI_MSG_DATA:
910 + return SPI_BCM_6338_SPI_MSG_DATA;
911 + case SPI_RX_DATA:
912 + return SPI_BCM_6338_SPI_RX_DATA;
913 +}
914 +#endif
915 +#ifdef CONFIG_BCM63XX_CPU_6348
916 +switch (reg) {
917 + case SPI_CMD:
918 + return SPI_BCM_6348_SPI_CMD;
919 + case SPI_INT_MASK_ST:
920 + return SPI_BCM_6348_SPI_MASK_INT_ST;
921 + case SPI_INT_MASK:
922 + return SPI_BCM_6348_SPI_INT_MASK;
923 + case SPI_INT_STATUS:
924 + return SPI_BCM_6348_SPI_INT_STATUS;
925 + case SPI_ST:
926 + return SPI_BCM_6348_SPI_ST;
927 + case SPI_CLK_CFG:
928 + return SPI_BCM_6348_SPI_CLK_CFG;
929 + case SPI_FILL_BYTE:
930 + return SPI_BCM_6348_SPI_FILL_BYTE;
931 + case SPI_MSG_TAIL:
932 + return SPI_BCM_6348_SPI_MSG_TAIL;
933 + case SPI_RX_TAIL:
934 + return SPI_BCM_6348_SPI_RX_TAIL;
935 + case SPI_MSG_CTL:
936 + return SPI_BCM_6348_SPI_MSG_CTL;
937 + case SPI_MSG_DATA:
938 + return SPI_BCM_6348_SPI_MSG_DATA;
939 + case SPI_RX_DATA:
940 + return SPI_BCM_6348_SPI_RX_DATA;
941 +}
942 +#endif
943 +#ifdef CONFIG_BCM63XX_CPU_6358
944 +switch (reg) {
945 + case SPI_CMD:
946 + return SPI_BCM_6358_SPI_CMD;
947 + case SPI_INT_STATUS:
948 + return SPI_BCM_6358_SPI_INT_STATUS;
949 + case SPI_INT_MASK_ST:
950 + return SPI_BCM_6358_SPI_MASK_INT_ST;
951 + case SPI_INT_MASK:
952 + return SPI_BCM_6358_SPI_INT_MASK;
953 + case SPI_ST:
954 + return SPI_BCM_6358_SPI_STATUS;
955 + case SPI_CLK_CFG:
956 + return SPI_BCM_6358_SPI_CLK_CFG;
957 + case SPI_FILL_BYTE:
958 + return SPI_BCM_6358_SPI_FILL_BYTE;
959 + case SPI_MSG_TAIL:
960 + return SPI_BCM_6358_SPI_MSG_TAIL;
961 + case SPI_RX_TAIL:
962 + return SPI_BCM_6358_SPI_RX_TAIL;
963 + case SPI_MSG_CTL:
964 + return SPI_BCM_6358_MSG_CTL;
965 + case SPI_MSG_DATA:
966 + return SPI_BCM_6358_SPI_MSG_DATA;
967 + case SPI_RX_DATA:
968 + return SPI_BCM_6358_SPI_RX_DATA;
969 +}
970 +#endif
971 +#endif
972 + return 0;
973 +}
974 +
975 +#endif /* BCM63XX_DEV_SPI_H */
976 --- a/arch/mips/bcm63xx/Makefile
977 +++ b/arch/mips/bcm63xx/Makefile
978 @@ -1,6 +1,6 @@
979 obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
980 dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o dev-wdt.o \
981 - dev-usb-ohci.o dev-usb-ehci.o dev-usb-udc.o
982 + dev-usb-ohci.o dev-usb-ehci.o dev-usb-udc.o dev-spi.o
983 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
984
985 obj-y += boards/
986 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
987 +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
988 @@ -30,6 +30,7 @@
989 #include <bcm63xx_dev_usb_ohci.h>
990 #include <bcm63xx_dev_usb_ehci.h>
991 #include <bcm63xx_dev_usb_udc.h>
992 +#include <bcm63xx_dev_spi.h>
993 #include <board_bcm963xx.h>
994
995 #define PFX "board_bcm963xx: "
996 @@ -931,6 +932,8 @@ int __init board_register_devices(void)
997 if (board.num_spis)
998 spi_register_board_info(board.spis, board.num_spis);
999
1000 + bcm63xx_spi_register();
1001 +
1002 /* read base address of boot chip select (0) */
1003 if (BCMCPU_IS_6345())
1004 val = 0x1fc00000;
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