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brcm63xx: Add profile and build image for Sagemcom F@ST2704V2 ADSL router
[openwrt/openwrt.git] / target / linux / brcm63xx / patches-3.10 / 052-MIPS-BCM63XX-add-HSSPI-IRQ-and-register-offsets.patch
1 From 33a6acbe47636adcd9062a0e0af7985c0df9faa5 Mon Sep 17 00:00:00 2001
2 From: Jonas Gorski <jogo@openwrt.org>
3 Date: Sat, 12 Nov 2011 12:19:55 +0100
4 Subject: [PATCH 3/5] MIPS: BCM63XX: add HSSPI IRQ and register offsets
5
6 Signed-off-by: Jonas Gorski <jogo@openwrt.org>
7 ---
8 arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 18 ++++++++++++++++++
9 1 file changed, 18 insertions(+)
10
11 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
12 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
13 @@ -145,6 +145,7 @@ enum bcm63xx_regs_set {
14 RSET_UART1,
15 RSET_GPIO,
16 RSET_SPI,
17 + RSET_HSSPI,
18 RSET_UDC0,
19 RSET_OHCI0,
20 RSET_OHCI_PRIV,
21 @@ -193,6 +194,7 @@ enum bcm63xx_regs_set {
22 #define RSET_ENETDMAS_SIZE(chans) (16 * (chans))
23 #define RSET_ENETSW_SIZE 65536
24 #define RSET_UART_SIZE 24
25 +#define RSET_HSSPI_SIZE 1536
26 #define RSET_UDC_SIZE 256
27 #define RSET_OHCI_SIZE 256
28 #define RSET_EHCI_SIZE 256
29 @@ -265,6 +267,7 @@ enum bcm63xx_regs_set {
30 #define BCM_6328_UART1_BASE (0xb0000120)
31 #define BCM_6328_GPIO_BASE (0xb0000080)
32 #define BCM_6328_SPI_BASE (0xdeadbeef)
33 +#define BCM_6328_HSSPI_BASE (0xb0001000)
34 #define BCM_6328_UDC0_BASE (0xdeadbeef)
35 #define BCM_6328_USBDMA_BASE (0xb000c000)
36 #define BCM_6328_OHCI0_BASE (0xb0002600)
37 @@ -313,6 +316,7 @@ enum bcm63xx_regs_set {
38 #define BCM_6338_UART1_BASE (0xdeadbeef)
39 #define BCM_6338_GPIO_BASE (0xfffe0400)
40 #define BCM_6338_SPI_BASE (0xfffe0c00)
41 +#define BCM_6338_HSSPI_BASE (0xdeadbeef)
42 #define BCM_6338_UDC0_BASE (0xdeadbeef)
43 #define BCM_6338_USBDMA_BASE (0xfffe2400)
44 #define BCM_6338_OHCI0_BASE (0xdeadbeef)
45 @@ -360,6 +364,7 @@ enum bcm63xx_regs_set {
46 #define BCM_6345_UART1_BASE (0xdeadbeef)
47 #define BCM_6345_GPIO_BASE (0xfffe0400)
48 #define BCM_6345_SPI_BASE (0xdeadbeef)
49 +#define BCM_6345_HSSPI_BASE (0xdeadbeef)
50 #define BCM_6345_UDC0_BASE (0xdeadbeef)
51 #define BCM_6345_USBDMA_BASE (0xfffe2800)
52 #define BCM_6345_ENET0_BASE (0xfffe1800)
53 @@ -406,6 +411,7 @@ enum bcm63xx_regs_set {
54 #define BCM_6348_UART1_BASE (0xdeadbeef)
55 #define BCM_6348_GPIO_BASE (0xfffe0400)
56 #define BCM_6348_SPI_BASE (0xfffe0c00)
57 +#define BCM_6348_HSSPI_BASE (0xdeadbeef)
58 #define BCM_6348_UDC0_BASE (0xfffe1000)
59 #define BCM_6348_USBDMA_BASE (0xdeadbeef)
60 #define BCM_6348_OHCI0_BASE (0xfffe1b00)
61 @@ -451,6 +457,7 @@ enum bcm63xx_regs_set {
62 #define BCM_6358_UART1_BASE (0xfffe0120)
63 #define BCM_6358_GPIO_BASE (0xfffe0080)
64 #define BCM_6358_SPI_BASE (0xfffe0800)
65 +#define BCM_6358_HSSPI_BASE (0xdeadbeef)
66 #define BCM_6358_UDC0_BASE (0xfffe0800)
67 #define BCM_6358_USBDMA_BASE (0xdeadbeef)
68 #define BCM_6358_OHCI0_BASE (0xfffe1400)
69 @@ -553,6 +560,7 @@ enum bcm63xx_regs_set {
70 #define BCM_6368_UART1_BASE (0xb0000120)
71 #define BCM_6368_GPIO_BASE (0xb0000080)
72 #define BCM_6368_SPI_BASE (0xb0000800)
73 +#define BCM_6368_HSSPI_BASE (0xdeadbeef)
74 #define BCM_6368_UDC0_BASE (0xdeadbeef)
75 #define BCM_6368_USBDMA_BASE (0xb0004800)
76 #define BCM_6368_OHCI0_BASE (0xb0001600)
77 @@ -604,6 +612,7 @@ extern const unsigned long *bcm63xx_regs
78 __GEN_RSET_BASE(__cpu, UART1) \
79 __GEN_RSET_BASE(__cpu, GPIO) \
80 __GEN_RSET_BASE(__cpu, SPI) \
81 + __GEN_RSET_BASE(__cpu, HSSPI) \
82 __GEN_RSET_BASE(__cpu, UDC0) \
83 __GEN_RSET_BASE(__cpu, OHCI0) \
84 __GEN_RSET_BASE(__cpu, OHCI_PRIV) \
85 @@ -647,6 +656,7 @@ extern const unsigned long *bcm63xx_regs
86 [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \
87 [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \
88 [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \
89 + [RSET_HSSPI] = BCM_## __cpu ##_HSSPI_BASE, \
90 [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \
91 [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \
92 [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \
93 @@ -727,6 +737,7 @@ enum bcm63xx_irq {
94 IRQ_ENET0,
95 IRQ_ENET1,
96 IRQ_ENET_PHY,
97 + IRQ_HSSPI,
98 IRQ_OHCI0,
99 IRQ_EHCI0,
100 IRQ_USBD,
101 @@ -815,6 +826,7 @@ enum bcm63xx_irq {
102 #define BCM_6328_ENET0_IRQ 0
103 #define BCM_6328_ENET1_IRQ 0
104 #define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
105 +#define BCM_6328_HSSPI_IRQ (IRQ_INTERNAL_BASE + 29)
106 #define BCM_6328_OHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 9)
107 #define BCM_6328_EHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 10)
108 #define BCM_6328_USBD_IRQ (IRQ_INTERNAL_BASE + 4)
109 @@ -860,6 +872,7 @@ enum bcm63xx_irq {
110 #define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
111 #define BCM_6338_ENET1_IRQ 0
112 #define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
113 +#define BCM_6338_HSSPI_IRQ 0
114 #define BCM_6338_OHCI0_IRQ 0
115 #define BCM_6338_EHCI0_IRQ 0
116 #define BCM_6338_USBD_IRQ 0
117 @@ -898,6 +911,7 @@ enum bcm63xx_irq {
118 #define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
119 #define BCM_6345_ENET1_IRQ 0
120 #define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
121 +#define BCM_6345_HSSPI_IRQ 0
122 #define BCM_6345_OHCI0_IRQ 0
123 #define BCM_6345_EHCI0_IRQ 0
124 #define BCM_6345_USBD_IRQ 0
125 @@ -936,6 +950,7 @@ enum bcm63xx_irq {
126 #define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
127 #define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
128 #define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
129 +#define BCM_6348_HSSPI_IRQ 0
130 #define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
131 #define BCM_6348_EHCI0_IRQ 0
132 #define BCM_6348_USBD_IRQ 0
133 @@ -974,6 +989,7 @@ enum bcm63xx_irq {
134 #define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
135 #define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
136 #define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
137 +#define BCM_6358_HSSPI_IRQ 0
138 #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
139 #define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
140 #define BCM_6358_USBD_IRQ 0
141 @@ -1086,6 +1102,7 @@ enum bcm63xx_irq {
142 #define BCM_6368_ENET0_IRQ 0
143 #define BCM_6368_ENET1_IRQ 0
144 #define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15)
145 +#define BCM_6368_HSSPI_IRQ 0
146 #define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
147 #define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7)
148 #define BCM_6368_USBD_IRQ (IRQ_INTERNAL_BASE + 8)
149 @@ -1133,6 +1150,7 @@ extern const int *bcm63xx_irqs;
150 [IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \
151 [IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \
152 [IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \
153 + [IRQ_HSSPI] = BCM_## __cpu ##_HSSPI_IRQ, \
154 [IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \
155 [IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \
156 [IRQ_USBD] = BCM_## __cpu ##_USBD_IRQ, \
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