target/linux/brcm63xx/patches-3.10/057-MIPS-BMIPS-do-not-change-interrupt-routing-depending.patch

   1 From c4091d3fbbed922a3641e5e749655e49cc0d4dee Mon Sep 17 00:00:00 2001
   2 From: Florian Fainelli <florian@openwrt.org>
   3 Date: Wed, 24 Jul 2013 17:12:10 +0100
   4 Subject: [PATCH] MIPS: BMIPS: do not change interrupt routing depending on
   5  boot CPU
   6
   7 Commit 4df715aa ("MIPS: BMIPS: support booting from physical CPU other
   8 than 0") changed the interupt routing when we are booting from physical
   9 CPU 0, but the settings are actually correct if we are booting from
  10 physical CPU 0 or CPU 1. Revert that specific change.
  11
  12 Signed-off-by: Florian Fainelli <florian@openwrt.org>
  13 Cc: linux-mips@linux-mips.org
  14 Cc: cernekee@gmail.com
  15 Cc: jogo@openwrt.org
  16 Cc: blogic@openwrt.org
  17 Patchwork: https://patchwork.linux-mips.org/patch/5622/
  18 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
  19 ---
  20  arch/mips/kernel/smp-bmips.c | 8 +-------
  21  1 file changed, 1 insertion(+), 7 deletions(-)
  22
  23 --- a/arch/mips/kernel/smp-bmips.c
  24 +++ b/arch/mips/kernel/smp-bmips.c
  25 @@ -79,15 +79,9 @@ static void __init bmips_smp_setup(void)
  26          * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other thread
  27          * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
  28          * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
  29 -        *
  30 -        * If booting from TP1, leave the existing CMT interrupt routing
  31 -        * such that TP0 responds to SW1 and TP1 responds to SW0.
  32          */
  33 -       if (boot_cpu == 0)
  34 -               change_c0_brcm_cmt_intr(0xf8018000,
  35 +       change_c0_brcm_cmt_intr(0xf8018000,
  36                                         (0x02 << 27) | (0x03 << 15));
  37 -       else
  38 -               change_c0_brcm_cmt_intr(0xf8018000, (0x1d << 27));
  39
  40         /* single core, 2 threads (2 pipelines) */
  41         max_cpus = 2;